JP2005275054A - Liquid crystal display and its manufacturing method - Google Patents

Liquid crystal display and its manufacturing method Download PDF

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JP2005275054A
JP2005275054A JP2004089053A JP2004089053A JP2005275054A JP 2005275054 A JP2005275054 A JP 2005275054A JP 2004089053 A JP2004089053 A JP 2004089053A JP 2004089053 A JP2004089053 A JP 2004089053A JP 2005275054 A JP2005275054 A JP 2005275054A
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gate
film
tapered
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JP4011557B2 (en
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Yuichi Masutani
雄一 升谷
Shingo Nagano
慎吾 永野
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display which will not produce voids in the viewing area near the gate terminals, by shielding the electric fields generated by the lead conductors and preventing potential fluctuation of the facing substrates, in an in-plane switching liquid crystal display. <P>SOLUTION: The liquid crystal display is provided with gate terminals 16 for applying a voltage to the gate wiring 4 and a tapered gate wiring 14 to connect with it, and a conductor layer 18 is provided on the upper layer of the tapered gate wiring 14 via a gate insulating film 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、面内応答型液晶表示装置(以下、IPS(in plane switching)パネルと称す)に関する。さらに詳しくは、表示領域のゲート端子近傍の白抜けをなくし表示特性を向上した構造の液晶表示装置およびその製造方法に関する。   The present invention relates to an in-plane response type liquid crystal display device (hereinafter referred to as an IPS (in plane switching) panel). More particularly, the present invention relates to a liquid crystal display device having a structure in which white spots in the vicinity of a gate terminal in a display region are eliminated and display characteristics are improved, and a manufacturing method thereof.

従来のIPSパネルにおいては、画素電極PXは、対向電圧信号線CLと接続された対向電極CTとの間に電界を発生させ、この電界によって液晶の光透過率を制御させるようになっている(例えば、特許文献1参照)。 In the conventional IPS panel, the pixel electrode PX generates an electric field between the pixel electrode PX and the counter electrode CT connected to the counter voltage signal line CL, and the light transmittance of the liquid crystal is controlled by this electric field ( For example, see Patent Document 1).

特開2003−295210号公報(第4−5頁、第2図)JP 2003-295210 A (page 4-5, FIG. 2)

従来のIPSパネルでは、透明基板SUB1上のゲート信号線GLとゲート端子とを結ぶ引き出し配線、詳しくは、表示領域外の隣接するゲート端子間の間隔が隣接するゲート配線間の間隔より狭いためにゲート端子に近いほど配線ピッチが狭くなる引き出し配線群(以下、テーパーゲート配線部と称す)から発生する電界により、対向基板である透明基板SUB2の電位変動を誘発し、ゲート端子近傍の液晶表示部ARに白抜けが生じるという問題点があった。 In the conventional IPS panel, the lead line connecting the gate signal line GL and the gate terminal on the transparent substrate SUB1, more specifically, the distance between adjacent gate terminals outside the display area is narrower than the distance between adjacent gate lines. A liquid crystal display near the gate terminal is induced by an electric field generated from a lead wiring group (hereinafter referred to as a tapered gate wiring portion) in which the wiring pitch becomes narrower as it is closer to the gate terminal. There was a problem that white spots occurred in AR.

この発明は、上述のような課題を解決するためになされたもので、IPSパネルを用いた場合において、テーパーゲート配線部から発生する電界を遮蔽し、対向基板の電位変動を防止することで、ゲート端子近傍の表示領域に白抜けを生じない液晶表示装置を得るものである。 The present invention has been made to solve the above-described problems. When an IPS panel is used, the electric field generated from the tapered gate wiring portion is shielded, and the potential fluctuation of the counter substrate is prevented. A liquid crystal display device that does not cause white spots in the display region near the gate terminal is obtained.

この発明に係る液晶表示装置においては、ゲート配線に電圧を印加するためのゲート端子およびこれに接続するため設置されたテーパーゲート配線部が設けられ、テーパーゲート配線部の上層に絶縁膜を介して導電層を配設したものである。 In the liquid crystal display device according to the present invention, a gate terminal for applying a voltage to the gate wiring and a tapered gate wiring portion installed to connect to the gate terminal are provided, and an insulating film is provided above the tapered gate wiring portion. A conductive layer is provided.

この発明は、テーパーゲート配線部の上層に絶縁膜を介して導電層を配設したことにより、テーパーゲート配線部から発生する電界を導電層が遮蔽し、対向基板の電位変動を防止することで、ゲート端子近傍の表示領域に白抜けを生じず表示品位を向上することが可能となる。 According to the present invention, the conductive layer is disposed on the upper layer of the tapered gate wiring portion with an insulating film interposed therebetween, so that the conductive layer shields the electric field generated from the tapered gate wiring portion and prevents the potential fluctuation of the counter substrate. Thus, it is possible to improve the display quality without causing white spots in the display area near the gate terminal.

実施の形態1.
図1はこの発明を実施するための実施の形態1における液晶表示装置の薄膜トランジスタ(以下、TFTと称す)近傍を拡大した平面図、図2は図1に示すTFT近傍の矢視A−A線からみた部分断面の製造工程を示した説明図、図3はこの発明を実施するための実施の形態1における液晶表示装置のゲート端子側の端部を示した平面図、図4は図3に示すテーパーゲート配線部近傍の矢視B−B線からみた部分断面の製造工程を示した説明図、図5はこの発明を実施するための実施の形態1における液晶表示装置のテーパーゲート配線部近傍を拡大した平面図、図6は図5に示すテーパーゲート配線部近傍の矢視C−C線からみた部分断面の製造工程を示した説明図である。
Embodiment 1 FIG.
1 is an enlarged plan view of the vicinity of a thin film transistor (hereinafter referred to as TFT) of a liquid crystal display device according to Embodiment 1 for carrying out the present invention, and FIG. 2 is an arrow AA line in the vicinity of the TFT shown in FIG. FIG. 3 is a plan view showing an end portion on the gate terminal side of the liquid crystal display device according to the first embodiment for carrying out the present invention, and FIG. 4 is a plan view showing FIG. FIG. 5 is an explanatory view showing a manufacturing process of a partial cross section seen from the line BB in the vicinity of the tapered gate wiring portion shown in FIG. 5, and FIG. FIG. 6 is an explanatory view showing a manufacturing process of a partial cross section as seen from the CC line in the vicinity of the tapered gate wiring portion shown in FIG.

図1〜図6において、透明な絶縁性基板である第1の基板1a上に表示領域2を形成する画素が配設され、各画素はTFT3を具備している。ゲート配線4はゲート絶縁膜5を介してソース配線6と交差しており、TFT3は複数のゲート配線4と複数のソース配線6の各交差部に対応して形成されている。TFT3のゲート電極4aはゲート配線4の一部であり、ソース電極6aはソース配線6の一部であり、ドレイン電極6bは第1のコンタクトホール7を介して画素電極8に接続されている。 1 to 6, pixels for forming a display region 2 are disposed on a first substrate 1 a which is a transparent insulating substrate, and each pixel includes a TFT 3. The gate line 4 intersects with the source line 6 through the gate insulating film 5, and the TFT 3 is formed corresponding to each intersection of the plurality of gate lines 4 and the plurality of source lines 6. The gate electrode 4 a of the TFT 3 is a part of the gate wiring 4, the source electrode 6 a is a part of the source wiring 6, and the drain electrode 6 b is connected to the pixel electrode 8 through the first contact hole 7.

TFT3に接続された櫛歯状の画素電極8と、画素電極8の櫛歯とほぼ並行かつ交互に対応して形成され、共通信号線11に第2のコンタクトホール9を介して接続された櫛歯状の対向電極10との間に電圧を印加することによって、第1の基板1a面にほぼ平行な電界を発生させる。画素電極8は、クロム(Cr)等の金属やITO(Indium Tin Oxide)等の透明性導電膜により形成されている。 Comb-like pixel electrodes 8 connected to the TFTs 3 and combs formed in parallel and alternately corresponding to the comb teeth of the pixel electrodes 8 and connected to the common signal line 11 through the second contact holes 9 By applying a voltage between the toothed counter electrode 10, an electric field substantially parallel to the surface of the first substrate 1 a is generated. The pixel electrode 8 is formed of a metal such as chromium (Cr) or a transparent conductive film such as ITO (Indium Tin Oxide).

共通信号線11は、一般的に、表示装置全体として同一の電圧が印加されるため、表示領域2の外側に配設された接続線12に変換部13を介して複数の共通信号線11を共通に接続する。共通信号線11は、クロム(Cr)等の金属からなる。
この例では、ソース配線6、画素電極8、対向電極10は、中央部において1回屈曲している。そして、この屈曲点は、共通信号線11に対応する位置に設けられている。このように、屈曲した電極構成により、2方向の液晶の駆動方向を得ることができ、IPSパネルで特定方向におこる視角特性の悪化を改善することができる。
Since the common voltage is generally applied to the common signal line 11 as a whole display device, a plurality of common signal lines 11 are connected to the connection line 12 arranged outside the display area 2 via the conversion unit 13. Connect in common. The common signal line 11 is made of a metal such as chromium (Cr).
In this example, the source wiring 6, the pixel electrode 8, and the counter electrode 10 are bent once at the center. The bending point is provided at a position corresponding to the common signal line 11. In this way, the bent electrode configuration can provide two directions of liquid crystal driving directions, and can improve the deterioration of viewing angle characteristics that occur in a specific direction in the IPS panel.

各ゲート配線4およびソース配線6は、表示領域2からテーパーゲート配線部14およびテーパーソース配線部15によりそれぞれ引き出され、第1の基板1aの端部近傍に形成されたゲート端子16とソース端子17にそれぞれ接続されている。また、接続線12は、ゲート端子16またはソース端子17と並行に形成された共通信号線端子23に接続されている。
ゲート端子16、ソース端子17および共通信号線端子23に、例えば、ACF(Anisotropic Conductive Film:異方性導電膜)などの導電性材料により、フィルム基板に実装された駆動回路などが接続されている。
以下、第1の基板1a上にTFT3を形成した基板をアレイ基板と称す。
Each gate line 4 and source line 6 are drawn from the display region 2 by a tapered gate line part 14 and a tapered source line part 15, respectively, and are formed near the end of the first substrate 1a. Are connected to each. The connection line 12 is connected to a common signal line terminal 23 formed in parallel with the gate terminal 16 or the source terminal 17.
A drive circuit or the like mounted on a film substrate is connected to the gate terminal 16, the source terminal 17, and the common signal line terminal 23 by a conductive material such as ACF (Anisotropic Conductive Film). .
Hereinafter, a substrate in which the TFT 3 is formed on the first substrate 1a is referred to as an array substrate.

第1の基板1aに対向する第2の基板1bと第1の基板1aとの間隙に複数のスペーサを配置し、二枚の基板を等間隔に保持している。また、第1の基板1aと第2の基板1bの周辺部に配置され両基板を貼り合わせるシール材と封止材により液晶を封入させる。第2の基板1b上には、着色層、遮光層、液晶に初期配向をもたせる配向膜および光を偏光させる偏光板などが形成され、アレイ基板に対向することで対向基板と称す。 A plurality of spacers are arranged in the gap between the second substrate 1b and the first substrate 1a facing the first substrate 1a, and the two substrates are held at equal intervals. In addition, liquid crystal is sealed with a sealing material and a sealing material which are arranged around the first substrate 1a and the second substrate 1b and are bonded to each other. On the second substrate 1b, a colored layer, a light-shielding layer, an alignment film for imparting initial alignment to the liquid crystal, a polarizing plate for polarizing light, and the like are formed and referred to as a counter substrate by facing the array substrate.

第1の基板1a上のテーパーゲート配線部14の上層には絶縁膜を介して導電層18を形成するが、この実施の形態1においては、絶縁膜はゲート配線4およびソース配線6を絶縁するゲート絶縁膜5と後述する保護膜21であり、導電層18は画素電極8と同一の製造工程で形成された、すなわち、同一層の導電膜により形成している。
なお、この導電層18のパターンは、第2の基板1b側から見てテーパーゲート配線部14をすべて覆うような領域に配設することがテーパーゲート配線部14から発生する電界を漏れなく遮蔽することができ好ましいが、ゲート端子16近傍の表示領域2に白抜けを生じない範囲で導電層18のパターンをゲート端子16から表示領域側に狭めてもよい。
A conductive layer 18 is formed over the tapered gate wiring portion 14 on the first substrate 1a via an insulating film. In the first embodiment, the insulating film insulates the gate wiring 4 and the source wiring 6 from each other. The gate insulating film 5 and a protective film 21 to be described later, and the conductive layer 18 is formed by the same manufacturing process as the pixel electrode 8, that is, is formed by a conductive film of the same layer.
Note that the pattern of the conductive layer 18 is disposed in a region that covers the entire tapered gate wiring portion 14 when viewed from the second substrate 1b side, thereby shielding the electric field generated from the tapered gate wiring portion 14 without leakage. However, the pattern of the conductive layer 18 may be narrowed from the gate terminal 16 toward the display region as long as no white spots occur in the display region 2 near the gate terminal 16.

つぎに、本発明の実施の形態1にかかる液晶表示装置の製造方法を図2、図4および図6を用いて説明する。
まず、図2(a)、図4(a)および図6(a)に示すように、絶縁性基板上にCr、Al、Ti、Ta、Mo、W、Ni、Cu、Au、Ag等やそれらを主成分とする合金、またはITO等の透光性を有する導電膜、またはそれらの多層膜等をスパッタ法や蒸着法等により成膜し、写真製版・加工により、ゲート配線4、ゲート電極4a、共通信号線11およびテーパーゲート配線部14を形成する。
Next, a method for manufacturing the liquid crystal display device according to the first embodiment of the present invention will be described with reference to FIGS.
First, as shown in FIGS. 2 (a), 4 (a) and 6 (a), Cr, Al, Ti, Ta, Mo, W, Ni, Cu, Au, Ag, etc. are formed on an insulating substrate. An alloy containing them as a main component, a light-transmitting conductive film such as ITO, or a multilayer film thereof is formed by a sputtering method, a vapor deposition method, etc. 4a, the common signal line 11 and the tapered gate wiring portion 14 are formed.

次に、図2(b)、図4(b)および図6(b)に示すように、窒化シリコン等よりなるゲート絶縁膜5を形成し、さらに非晶質Si、多結晶poly−Si等よりなる半導体膜19、n型のTFTの場合はP等の不純物を高濃度にドーピングしたn非晶質Si、n多結晶poly−Si等よりなるコンタクト膜20を、連続的に例えばプラズマCVD、常圧CVD、減圧CVD法で成膜する。
次いで、半導体膜19およびコンタクト膜20を島状に加工する。
Next, as shown in FIGS. 2B, 4B, and 6B, a gate insulating film 5 made of silicon nitride or the like is formed, and further, amorphous Si, polycrystalline poly-Si, or the like is formed. In the case of an n-type TFT, a contact film 20 made of n + amorphous Si, n + polycrystalline poly-Si or the like doped with an impurity such as P in a high concentration is continuously formed, for example, by plasma. The film is formed by CVD, atmospheric pressure CVD, or reduced pressure CVD.
Next, the semiconductor film 19 and the contact film 20 are processed into an island shape.

次に、図2(c)、図4(c)および図6(c)に示すように、Cr、Al、Ti、Ta、Mo、W、Ni、Cu、Au、Ag等やそれらを主成分とする合金、またはITO等の透光性を有する導電膜、またはそれらの多層膜等をスパッタ法や蒸着法で成膜後、写真製版と微細加工技術により、ソース配線6、ソース電極6a、ドレイン電極6b、テーパーソース配線部15、接続線12および保持容量電極等を形成する。
さらに、ソース電極6aおよびドレイン電極6bあるいはそれらを形成したホトレジストをマスクとしてコンタクト膜20をエッチングし、チャネル領域から取り除く。
Next, as shown in FIG. 2 (c), FIG. 4 (c) and FIG. 6 (c), Cr, Al, Ti, Ta, Mo, W, Ni, Cu, Au, Ag, etc. and their main components After forming a light-transmitting conductive film such as an alloy or ITO, or a multilayer film thereof by sputtering or vapor deposition, the source wiring 6, the source electrode 6a, and the drain are formed by photolithography and microfabrication technology. An electrode 6b, a tapered source wiring portion 15, a connection line 12, a storage capacitor electrode, and the like are formed.
Further, the contact film 20 is etched using the source electrode 6a and the drain electrode 6b or the photoresist on which they are formed as a mask, and removed from the channel region.

次いで、図2(d)、図4(d)および図6(d)に示すように、窒化シリコンや酸化シリコン、無機絶縁膜または有機樹脂等からなる保護膜21を成膜する。
その後、写真製版とそれに続くエッチングにより、第1のコンタクトホール7、第2のコンタクトホール9、テーパーゲート配線部14とゲート端子16および共通信号線11と変換部13とを接続する第3のコンタクトホール22、ならびにテーパーソース配線部15とソース端子17および接続線12と共通信号線端子23または変換部13とを接続する第4のコンタクトホール24を形成する。
Next, as shown in FIGS. 2D, 4D, and 6D, a protective film 21 made of silicon nitride, silicon oxide, an inorganic insulating film, an organic resin, or the like is formed.
Thereafter, a third contact for connecting the first contact hole 7, the second contact hole 9, the tapered gate wiring portion 14 and the gate terminal 16, and the common signal line 11 and the conversion portion 13 by photolithography and subsequent etching. A hole 22 and a fourth contact hole 24 that connects the tapered source wiring portion 15, the source terminal 17, the connection line 12, and the common signal line terminal 23 or the conversion portion 13 are formed.

最後に、図2(e)、図4(e)および図6(e)に示すように、Cr、Al、Ti、Ta、Mo、W、Ni、Cu、Au、Ag等やそれらを主成分とする合金、またはITO等の透光性を有する導電膜、またはそれらの多層膜等を成膜後、パターニングすることで、画素電極8、対向電極10、ゲート端子16、ソース端子17、変換部13、導電層18および共通信号線端子23を形成する。 Finally, as shown in FIG. 2 (e), FIG. 4 (e) and FIG. 6 (e), Cr, Al, Ti, Ta, Mo, W, Ni, Cu, Au, Ag, etc. and their main components The pixel electrode 8, the counter electrode 10, the gate terminal 16, the source terminal 17, and the conversion unit are formed by patterning after forming a transparent conductive film such as ITO, a transparent conductive film such as ITO, or a multilayer film thereof. 13. Conductive layer 18 and common signal line terminal 23 are formed.

以上の工程により、本実施の形態におけるIPSパネルを構成するアレイ基板を作製することができる。さらに、このアレイ基板と対向基板の間に液晶を挟持し、シール材にて接合する。このときラビング、光配向等の方法により液晶分子を所定の角度で配向させる。なお、液晶を配向させる方法は、既知のどのような方法を用いてもよい。さらに、ゲート配線4、ソース配線6、共通信号線11にそれぞれゲート線駆動回路、ソース線駆動回路、共通信号線用電源を接続することにより液晶表示装置を作製する。 Through the above steps, the array substrate constituting the IPS panel in this embodiment can be manufactured. Further, a liquid crystal is sandwiched between the array substrate and the counter substrate and bonded with a sealing material. At this time, liquid crystal molecules are aligned at a predetermined angle by a method such as rubbing or photo-alignment. Any known method may be used for aligning the liquid crystal. Furthermore, a liquid crystal display device is manufactured by connecting a gate line driving circuit, a source line driving circuit, and a common signal line power source to the gate line 4, the source line 6, and the common signal line 11, respectively.

以上のように、この実施の形態1においては、導電層18をゲート絶縁膜5および保護膜21を介してテーパーゲート配線部14の上層に配設することで、テーパーゲート配線部14から発生する電界を導電層18によって遮蔽し、対向基板の電位変動を防止することで、ゲート端子16近傍の表示領域2に白抜けを生じさせない液晶表示装置を得ることができる。 As described above, in the first embodiment, the conductive layer 18 is disposed on the upper layer of the tapered gate wiring portion 14 via the gate insulating film 5 and the protective film 21, and is generated from the tapered gate wiring portion 14. By shielding the electric field with the conductive layer 18 and preventing the potential fluctuation of the counter substrate, a liquid crystal display device that does not cause white spots in the display region 2 in the vicinity of the gate terminal 16 can be obtained.

また、導電層18を画素電極8と同一工程で形成することで、導電層18を形成するための写真製版におけるマスク数の増加による製造工程数の増加や、導電層18の材料を新たに追加することなく、液晶表示装置を得ることができる。 Further, by forming the conductive layer 18 in the same process as the pixel electrode 8, an increase in the number of manufacturing steps due to an increase in the number of masks in the photoengraving for forming the conductive layer 18, and a new material for the conductive layer 18 is added. Thus, a liquid crystal display device can be obtained.

なお、この実施の形態1では、導電層18と変換部13とを離間して形成しているが、図7に示すように、変換部13をゲート端子16側に延在させ導電層18を兼用することで、導電層18を共通信号線11と電気的に接続し、固定電位によってシールドさせることができるので好ましい。図7はこの発明を実施するための実施の形態1における他の液晶表示装置のテーパーゲート配線部近傍を拡大した平面図である。 In the first embodiment, the conductive layer 18 and the conversion part 13 are formed apart from each other. However, as shown in FIG. 7, the conversion part 13 is extended to the gate terminal 16 side so that the conductive layer 18 is formed. The dual use is preferable because the conductive layer 18 can be electrically connected to the common signal line 11 and shielded by a fixed potential. FIG. 7 is an enlarged plan view of the vicinity of a tapered gate wiring portion of another liquid crystal display device according to the first embodiment for carrying out the present invention.

また、この実施の形態1では、導電層18を画素電極8と同一工程で形成しているが、図8に示すように、ソース配線6、ソース電極6a、ドレイン電極6b、テーパーソース配線部15、接続線12および保持容量電極等と同一工程で形成しても、導電層18がテーパーゲート配線部14から発生する電界を遮蔽することができるので、同様の効果が得られる。図8は図3に示すテーパーゲート配線部近傍の矢視B−B線からみた部分断面の他の製造工程を示した説明図である。 In the first embodiment, the conductive layer 18 is formed in the same process as the pixel electrode 8, but as shown in FIG. 8, the source wiring 6, the source electrode 6a, the drain electrode 6b, and the tapered source wiring section 15 are formed. Even when the connection line 12 and the storage capacitor electrode are formed in the same process, the conductive layer 18 can shield the electric field generated from the tapered gate wiring portion 14, and the same effect can be obtained. FIG. 8 is an explanatory view showing another manufacturing process of the partial cross section viewed along the line BB in the vicinity of the tapered gate wiring portion shown in FIG.

また、この実施の形態1では、導電層18と接続線12とを離間して形成しているが、図9に示すように、接続線12をゲート端子16側に延在させ導電層18を兼用することで、導電層18を共通信号線11と電気的に接続し、固定電位によってシールドさせることができるので好ましい。図9はこの発明を実施するための実施の形態1における他の液晶表示装置のテーパーゲート配線部近傍を拡大した平面図である。 In the first embodiment, the conductive layer 18 and the connection line 12 are formed apart from each other. However, as shown in FIG. 9, the connection line 12 extends to the gate terminal 16 side so that the conductive layer 18 is formed. The dual use is preferable because the conductive layer 18 can be electrically connected to the common signal line 11 and shielded by a fixed potential. FIG. 9 is an enlarged plan view of the vicinity of a tapered gate wiring portion of another liquid crystal display device according to the first embodiment for carrying out the present invention.

また、この実施の形態1では、導電層18をアレイ基板上に形成しているが、対向基板上のテーパーゲート配線部14に対応する領域に導電層18を形成しても、導電層18がテーパーゲート配線部14から発生する電界を遮蔽することができるので、同様の効果が得られる。 In the first embodiment, the conductive layer 18 is formed on the array substrate. However, even if the conductive layer 18 is formed in the region corresponding to the tapered gate wiring portion 14 on the counter substrate, the conductive layer 18 is not formed. Since the electric field generated from the tapered gate wiring portion 14 can be shielded, the same effect can be obtained.

この発明を実施するための実施の形態1における液晶表示装置のTFT近傍を拡大した平面図である。It is the top view to which TFT vicinity of the liquid crystal display device in Embodiment 1 for implementing this invention was expanded. 図1に示すTFT近傍の矢視A−A線からみた部分断面の製造工程を示した説明図である。It is explanatory drawing which showed the manufacturing process of the partial cross section seen from the arrow AA line of TFT vicinity shown in FIG. この発明を実施するための実施の形態1における液晶表示装置のゲート端子側の端部を示した平面図である。It is the top view which showed the edge part by the side of the gate terminal of the liquid crystal display device in Embodiment 1 for implementing this invention. 図3に示すテーパーゲート配線部近傍の矢視B−B線からみた部分断面の製造工程を示した説明図である。It is explanatory drawing which showed the manufacturing process of the partial cross section seen from the arrow BB line of the taper gate wiring part vicinity shown in FIG. この発明を実施するための実施の形態1における液晶表示装置のテーパーゲート配線部近傍を拡大した平面図である。It is the top view to which the taper gate wiring part vicinity of the liquid crystal display device in Embodiment 1 for implementing this invention was expanded. 図5に示すテーパーゲート配線部近傍の矢視C−C線からみた部分断面の製造工程を示した説明図である。It is explanatory drawing which showed the manufacturing process of the partial cross section seen from the arrow CC line vicinity of the taper gate wiring part shown in FIG. この発明を実施するための実施の形態1における他の液晶表示装置のテーパーゲート配線部近傍を拡大した平面図である。It is the top view to which the taper gate wiring part vicinity of the other liquid crystal display device in Embodiment 1 for implementing this invention was expanded. 図3に示すテーパーゲート配線部近傍の矢視B−B線からみた部分断面の他の製造工程を示した説明図である。It is explanatory drawing which showed the other manufacturing process of the partial cross section seen from the arrow BB line of the taper gate wiring part vicinity shown in FIG. この発明を実施するための実施の形態1における他の液晶表示装置のテーパーゲート配線部近傍を拡大した平面図である。It is the top view to which the taper gate wiring part vicinity of the other liquid crystal display device in Embodiment 1 for implementing this invention was expanded.

符号の説明Explanation of symbols

1a 第1の基板、1b 第2の基板、2 表示領域、3 TFT、4 ゲート配線、4aゲート電極、5 ゲート絶縁膜、6 ソース配線、6a ソース電極、6b ドレイン電極、7 第1のコンタクトホール、8 画素電極、9 第2のコンタクトホール、10 対向電極、11 共通信号線、12 接続線、13 変換部、14 テーパーゲート配線部、15 テーパーソース配線部、16 ゲート端子、17 ソース端子、18 導電層、19 半導体層、20 コンタクト膜、21 保護膜、22 第3のコンタクトホール、23 共通信号線、24 第4のコンタクトホール DESCRIPTION OF SYMBOLS 1a 1st board | substrate, 1b 2nd board | substrate, 2 Display area, 3 TFT, 4 Gate wiring, 4a gate electrode, 5 Gate insulating film, 6 Source wiring, 6a Source electrode, 6b Drain electrode, 7 1st contact hole , 8 Pixel electrode, 9 Second contact hole, 10 Counter electrode, 11 Common signal line, 12 Connection line, 13 Conversion part, 14 Tapered gate wiring part, 15 Tapered source wiring part, 16 Gate terminal, 17 Source terminal, 18 Conductive layer, 19 semiconductor layer, 20 contact film, 21 protective film, 22 third contact hole, 23 common signal line, 24 fourth contact hole

Claims (10)

複数のゲート配線と複数のソース配線の各交差部に対応して形成された薄膜トランジスタ、
前記薄膜トランジスタに接続された画素電極、
前記画素電極に対応して形成され、共通信号線に接続された対向電極、
複数の前記共通信号線を変換部によって共通に接続する接続線、
を有するアレイ基板と、
前記アレイ基板に対向する対向基板とを備え、
前記ゲート配線に電圧を印加するためのゲート端子およびこれに接続するため設置されたテーパーゲート配線部が設けられ、
前記テーパーゲート配線部の上層に絶縁膜を介して導電層を配設したことを特徴とする液晶表示装置。
A thin film transistor formed corresponding to each intersection of a plurality of gate lines and a plurality of source lines;
A pixel electrode connected to the thin film transistor;
A counter electrode formed corresponding to the pixel electrode and connected to a common signal line;
A plurality of common signal lines connected in common by the converter,
An array substrate having
A counter substrate facing the array substrate,
A gate terminal for applying a voltage to the gate wiring and a tapered gate wiring portion installed to connect to the gate terminal;
A liquid crystal display device, wherein a conductive layer is disposed above the tapered gate wiring portion with an insulating film interposed therebetween.
前記絶縁膜は前記ゲート配線およびソース配線を絶縁するゲート絶縁膜と
保護膜であり、前記導電層は前記画素電極と同一層であることを特徴とする請求項1記載の液晶表示装置。
2. The liquid crystal display device according to claim 1, wherein the insulating film is a gate insulating film and a protective film for insulating the gate wiring and the source wiring, and the conductive layer is the same layer as the pixel electrode.
前記導電層は、前記変換部をゲート端子側に延在させ形成したことを特徴とする請求項2記載の液晶表示装置。 The liquid crystal display device according to claim 2, wherein the conductive layer is formed by extending the conversion portion to a gate terminal side. 前記絶縁膜は前記ゲート配線およびソース配線を絶縁するゲート絶縁膜であり、前記導電層は前記接続線と同一層であることを特徴とする請求項1記載の液晶表示装置。 2. The liquid crystal display device according to claim 1, wherein the insulating film is a gate insulating film that insulates the gate wiring and the source wiring, and the conductive layer is the same layer as the connection line. 前記導電層は、前記接続線をゲート端子側に延在させ形成したことを特徴とする請求項4記載の液晶表示装置。 5. The liquid crystal display device according to claim 4, wherein the conductive layer is formed by extending the connection line to the gate terminal side. 複数のゲート配線と複数のソース配線の各交差部に対応して形成された薄膜トランジスタ、
前記薄膜トランジスタに接続された画素電極、
前記画素電極に対応して形成され、共通信号線に接続された対向電極、
複数の前記共通信号線を変換部によって共通に接続する接続線、
を有するアレイ基板と、
前記アレイ基板に対向する対向基板とを備え、
前記ゲート配線に電圧を印加するためのゲート端子およびこれに接続するため設置されたテーパーゲート配線部が設けられ、
前記対向基板上の前記テーパーゲート配線部に対応する領域に導電層を形成したことを特徴とする液晶表示装置。
A thin film transistor formed corresponding to each intersection of a plurality of gate lines and a plurality of source lines;
A pixel electrode connected to the thin film transistor;
A counter electrode formed corresponding to the pixel electrode and connected to a common signal line;
A plurality of common signal lines connected in common by the converter,
An array substrate having
A counter substrate facing the array substrate,
A gate terminal for applying a voltage to the gate wiring and a tapered gate wiring portion installed to connect to the gate terminal;
A liquid crystal display device, wherein a conductive layer is formed in a region corresponding to the tapered gate wiring portion on the counter substrate.
絶縁性基板上に、導電膜からなるゲート配線、ゲート電極、共通信号線およびテーパーゲート配線部を形成する工程と、
前記ゲート配線とソース配線を絶縁するための絶縁膜からなるゲート絶縁膜、半導体膜およびコンタクト膜を連続的に成膜し、前記半導体膜およびコンタクト膜を島状に形成する工程と、
導電膜からなるソース配線、ソース電極、ドレイン電極、テーパーソース配線部および接続線を形成する工程と、
絶縁膜からなる保護膜を成膜し、前記ドレイン電極と画素電極とを接続する第1のコンタクトホール、前記共通信号線と対向電極とを接続する第2のコンタクトホール、前記テーパーゲート配線部と前記ゲート端子および前記共通信号線と変換部とを接続する第3のコンタクトホール、ならびに前記テーパーソース配線部と前記ソース端子および前記接続線と共通信号線端子または変換部を接続する第4のコンタクトホールを形成する工程と、
導電膜からなる画素電極、対向電極、ゲート端子、ソース端子、変換部、導電層および共通信号線端子を形成する工程とを備えた液晶表示装置の製造方法。
Forming a gate wiring made of a conductive film, a gate electrode, a common signal line, and a tapered gate wiring portion on an insulating substrate;
A step of continuously forming a gate insulating film, a semiconductor film and a contact film made of an insulating film for insulating the gate wiring and the source wiring, and forming the semiconductor film and the contact film in an island shape;
Forming a source wiring made of a conductive film, a source electrode, a drain electrode, a tapered source wiring portion and a connection line;
A protective film made of an insulating film; a first contact hole connecting the drain electrode and the pixel electrode; a second contact hole connecting the common signal line and the counter electrode; and the tapered gate wiring portion; A third contact hole connecting the gate terminal and the common signal line and the conversion unit; and a fourth contact connecting the tapered source wiring unit and the source terminal and the connection line to the common signal line terminal or the conversion unit. Forming a hole;
Forming a pixel electrode made of a conductive film, a counter electrode, a gate terminal, a source terminal, a conversion unit, a conductive layer, and a common signal line terminal.
前記導電層は、前記変換部をゲート端子側に延在させ形成したことを特徴とする請求項7記載の液晶表示装置の製造方法。 8. The method of manufacturing a liquid crystal display device according to claim 7, wherein the conductive layer is formed by extending the conversion portion toward the gate terminal. 絶縁性基板上に、導電膜からなるゲート配線、ゲート電極、共通信号線およびテーパーゲート配線部を形成する工程と、
前記ゲート配線とソース配線を絶縁するための絶縁膜からなるゲート絶縁膜、半導体膜およびコンタクト膜を連続的に成膜し、前記半導体膜およびコンタクト膜を島状に形成する工程と、
導電膜からなるソース配線、ソース電極、ドレイン電極、テーパーソース配線部、導電層および接続線を形成する工程と、
絶縁膜からなる保護膜を成膜し、前記ドレイン電極と画素電極とを接続する第1のコンタクトホール、前記共通信号線と対向電極とを接続する第2のコンタクトホール、前記テーパーゲート配線部と前記ゲート端子および共通信号線と変換部とを接続する第3のコンタクトホール、ならびに前記テーパーソース配線部と前記ソース端子および前記接続線と共通信号線端子または変換部とを接続する第4のコンタクトホールを形成する工程と、
導電膜からなる画素電極、対向電極、ゲート端子、ソース端子、共通信号線端子および変換部を形成する工程とを備えた液晶表示装置の製造方法。
Forming a gate wiring made of a conductive film, a gate electrode, a common signal line, and a tapered gate wiring portion on an insulating substrate;
A step of continuously forming a gate insulating film, a semiconductor film and a contact film made of an insulating film for insulating the gate wiring and the source wiring, and forming the semiconductor film and the contact film in an island shape;
Forming a source wiring, a source electrode, a drain electrode, a tapered source wiring portion, a conductive layer and a connection line made of a conductive film;
A protective film made of an insulating film; a first contact hole connecting the drain electrode and the pixel electrode; a second contact hole connecting the common signal line and the counter electrode; and the tapered gate wiring portion; A third contact hole connecting the gate terminal and the common signal line and the conversion unit; and a fourth contact connecting the tapered source wiring unit and the source terminal and the connection line and the common signal line terminal or the conversion unit. Forming a hole;
Forming a pixel electrode made of a conductive film, a counter electrode, a gate terminal, a source terminal, a common signal line terminal, and a conversion unit.
前記導電層は、前記接続線をゲート端子側に延在させ形成したことを特徴とする請求項9記載の液晶表示装置の製造方法。
10. The method of manufacturing a liquid crystal display device according to claim 9, wherein the conductive layer is formed by extending the connection line to the gate terminal side.
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