JP2010123680A - Semiconductor device, connection conductor, and method of manufacturing semiconductor device - Google Patents

Semiconductor device, connection conductor, and method of manufacturing semiconductor device Download PDF

Info

Publication number
JP2010123680A
JP2010123680A JP2008294673A JP2008294673A JP2010123680A JP 2010123680 A JP2010123680 A JP 2010123680A JP 2008294673 A JP2008294673 A JP 2008294673A JP 2008294673 A JP2008294673 A JP 2008294673A JP 2010123680 A JP2010123680 A JP 2010123680A
Authority
JP
Japan
Prior art keywords
electrode
terminal
lead frame
conductive
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008294673A
Other languages
Japanese (ja)
Inventor
Hideo Nishiuchi
秀夫 西内
Tomoyuki Kitani
智之 木谷
Tomohiro Iguchi
知洋 井口
Takahiro Aizawa
隆博 相澤
Masako Oishi
昌子 大石
Hiroshi Tojo
啓 東條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2008294673A priority Critical patent/JP2010123680A/en
Publication of JP2010123680A publication Critical patent/JP2010123680A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/35—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/77—Apparatus for connecting with strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/35—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/35—Manufacturing methods
    • H01L2224/35001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H01L2224/3769—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/77—Apparatus for connecting with strap connectors
    • H01L2224/7725—Means for applying energy, e.g. heating means
    • H01L2224/773—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/77313—Wedge
    • H01L2224/77314—Shape
    • H01L2224/77315—Shape of the pressing surface, e.g. tip or head
    • H01L2224/77316—Shape of the pressing surface, e.g. tip or head comprising protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/77—Apparatus for connecting with strap connectors
    • H01L2224/777—Means for aligning
    • H01L2224/77743—Suction holding means
    • H01L2224/77745—Suction holding means in the upper part of the bonding apparatus, e.g. in the wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842—Applying energy for connecting
    • H01L2224/84201—Compression bonding
    • H01L2224/84205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device reducing package loss by reducing electric resistance in a conduction state and reducing manufacturing man-hours, to provide a connection conductor, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: This semiconductor device 1 includes: a lead frame 20 having drain terminals 12, a source terminal 13 and a gate terminal 14; a semiconductor chip 10 arranged on the lead frame 20, having a drain electrode 15c on one surface on the lead frame 20 side, and having a source electrode 15a and a gate electrode 15b on the other surface; and a plate-like connection conductor 16 where a conductive strip-like conduction part 16a for a source extending in a first direction, and having one end side connected to the source terminal 13 and the other end side connected to the source electrode 15a, and a strip-like conductive conduction part 16b for a gate extending in the first direction, and having one end side connected to the gate terminal 14, and the other end side connected to the gate electrode 15b are integrally formed by being arranged side by side in a second direction intersecting the first direction while interposing an insulation part 16c therebetween. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置、接続導体及び半導体装置の製造方法に係り、特に、半導体チップの電極とリードフレームのリード端子とに跨って板または帯状の接続導体を接合させる際に用いられるものに関する。   The present invention relates to a semiconductor device, a connection conductor, and a method for manufacturing the semiconductor device, and more particularly to a device used when a plate or strip-shaped connection conductor is joined across an electrode of a semiconductor chip and a lead terminal of a lead frame.

携帯電話、デジタルカメラ、ビデオカメラ、ポータブルオーディオ、ＩＣレコーダ等の電源部（ＤＣ−ＤＣコンバータや中電流スイッチ用途）に適用される半導体装置に関し、上面にソース電極とゲート電極、下面にドレイン電極を有するＭＯＳＦＥＴチップが知られている。このような半導体チップを、リードフレームに搭載し、ソース電極とリードフレームのリード端子間を電気的に接続させる半導体装置において、その接続にワイヤボンディングが多く用いられている（例えば、特許文献１参照）。   In connection with semiconductor devices applied to power supply units (for DC-DC converters and medium current switches) for mobile phones, digital cameras, video cameras, portable audio, IC recorders, etc., source and gate electrodes are provided on the upper surface and drain electrodes on the lower surface. A MOSFET chip having the same is known. In a semiconductor device in which such a semiconductor chip is mounted on a lead frame and the source electrode and the lead terminal of the lead frame are electrically connected, wire bonding is often used for the connection (see, for example, Patent Document 1). ).

また、携帯電話等のバッテリー駆動で動作する電気機器に搭載される場合には低消費電力型・小型の半導体装置が求められることから、パッケージとしての抵抗値を小さくするために、半導体チップの上面電極とリード端子とが、ワイヤよりも断面積の大きな金属板で板または帯状に構成された接続導体で接続される構造が用いられる（例えば、特許文献２参照）。   In addition, when mounted on battery-driven electric devices such as mobile phones, low power consumption and small semiconductor devices are required. Therefore, in order to reduce the resistance value as a package, the upper surface of a semiconductor chip is used. A structure is used in which the electrode and the lead terminal are connected to each other by a connection conductor configured in a plate or strip shape with a metal plate having a cross-sectional area larger than that of the wire (see, for example, Patent Document 2).

接続導体は、リードフレームに搭載された半導体チップの上面電極と、リードフレームに形成されたリード端子とに跨って載置され、上面電極とリード端子に対して超音波接合して接続される。この種の半導体装置を接合する際には、例えば、半導体チップの上面電極と前記接続導体との接合部を押圧する第１押圧部と、前記リードフレームのリード端子と前記接続導体との接合部を押圧する第２押圧部と、前記第１および第２押圧部に形成された複数の突起とを有する超音波接合装置が用いられる。このツール部により、第１及び第２押圧部で接続導体を上方から上面電極及びリード端子に対して押し付けて圧接させた状態で、接続導体を超音波周波数で機械的に微小振動させる（超音波振動させる）ことにより、接続導体と上面電極及びリード端子との界面が摩擦により固相接合される。   The connection conductor is placed across the upper surface electrode of the semiconductor chip mounted on the lead frame and the lead terminal formed on the lead frame, and is connected to the upper surface electrode and the lead terminal by ultrasonic bonding. When bonding this type of semiconductor device, for example, a first pressing portion that presses the bonding portion between the upper surface electrode of the semiconductor chip and the connection conductor, and a bonding portion between the lead terminal of the lead frame and the connection conductor. An ultrasonic bonding apparatus having a second pressing portion that presses and a plurality of protrusions formed on the first and second pressing portions is used. With this tool portion, the connection conductor is mechanically microvibrated at an ultrasonic frequency in a state where the connection conductor is pressed against the upper surface electrode and the lead terminal from above by the first and second pressing portions (ultrasonic wave). By vibrating), the interface between the connection conductor, the upper surface electrode, and the lead terminal is solid-phase bonded by friction.

通常、このような接合の際には、まずソース電極とソース端子を超音波接合で接続した後に、ゲート電極とゲート端子を接続する。
特開２００２−３１３８５１号公報 特開２００４−２２１２９４号公報 Usually, in such bonding, the source electrode and the source terminal are first connected by ultrasonic bonding, and then the gate electrode and the gate terminal are connected.
JP 2002-313851 A JP 2004-221294 A

しかしながら、上述した技術では、次のような問題があった。すなわち、ソース電極とソース端子１３を接続した後に、ゲート電極とゲート端子を接続するため、ワイヤボンディングのような別の工法を用いて接合しており、半導体チップと電極を接続する工程に複数の異なる装置と工程を要している。   However, the above-described technique has the following problems. That is, after the source electrode and the source terminal 13 are connected, in order to connect the gate electrode and the gate terminal, bonding is performed using another method such as wire bonding, and a plurality of processes are performed in the step of connecting the semiconductor chip and the electrode. Different equipment and processes are required.

そこで、本発明は、導通状態の電気抵抗を小さくしてパッケージ損失を低減し、かつ製造工数を削減する半導体装置、接続導体及び半導体装置の製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device, a connection conductor, and a method for manufacturing a semiconductor device in which the electrical resistance in a conductive state is reduced to reduce package loss and the number of manufacturing steps.

本発明の一形態にかかる半導体装置は、ドレイン端子、ソース端子及び、ゲート端子を有するリードフレームと、前記リードフレーム上に設けられ、前記リードフレーム側の一方の面にドレイン電極を有し、前記リードフレームと反対側の他方の面にソース電極とゲート電極を有する半導体チップと、第１方向に延び一端側が前記ソース端子に接続されるとともに他端側が前記ソース電極に接続される導電性の帯状のソース用導電部と、前記第１方向に延び一端側が前記ゲート端子に接続されるとともに他端側が前記ゲート電極に接続される帯状の導電性のゲート用導電部とが、間に絶縁部を介して前記第１方向と交差する第２方向において並列して一体に形成された、板状の接続導体と、を備えたことを特徴とする。   A semiconductor device according to an aspect of the present invention includes a lead frame having a drain terminal, a source terminal, and a gate terminal, a lead frame provided on the lead frame, and having a drain electrode on one surface on the lead frame side, A semiconductor chip having a source electrode and a gate electrode on the other surface opposite to the lead frame, and a conductive strip extending in the first direction and having one end connected to the source terminal and the other end connected to the source electrode An insulating portion between the source conductive portion and a strip-like conductive gate conductive portion extending in the first direction and having one end connected to the gate terminal and the other end connected to the gate electrode. And a plate-like connection conductor integrally formed in parallel in a second direction intersecting the first direction.

本発明の他の一形態にかかる半導体装置は、第１端子、第２端子、及び第３端子を有するリードフレームと、前記リードフレームに設けられ、一方の面に第１電極を、他方の面に第２電極と第３電極を有する半導体チップと、前記第２端子と前記第２電極を接続する第１の導電部と、前記第３端子と前記第３電極とを接続する第２の導電部とが、絶縁部を介して一体に形成された、板状の接続導体と、を備えたことを特徴とする。   A semiconductor device according to another aspect of the present invention is provided with a lead frame having a first terminal, a second terminal, and a third terminal, the lead frame, the first electrode on one surface, and the other surface A semiconductor chip having a second electrode and a third electrode, a first conductive portion connecting the second terminal and the second electrode, and a second conductive connecting the third terminal and the third electrode. And a plate-like connecting conductor formed integrally with the insulating portion.

本発明の他の一形態にかかる半導体装置の製造方法は、リードフレームに形成された複数の端子と、前記リードフレームに設けられた半導体チップに設けられた複数の電極とを、板状または帯状の接続導体に超音波接合して接続する半導体装置の製造方法であって、前記リードフレームに形成されたソース端子と前記半導体チップに設けられたソース電極を接続するソース用導電部と、前記リードフレームに形成されたゲート端子と前記半導体チップに設けられたゲート電極とを接続するゲート用導電部とを、絶縁部を介して一体に形成する工程と、前記接続導体における前記ソース用導電部の一端側を前記ソース端子に、他端側を前記ソース電極に、前記ゲート用導電部の一端側を前記ゲート端子に、他端側を前記ゲート電極に接するように押圧して超音波振動を前記接続導体に付与する工程と、を備えたことを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a plurality of terminals formed on a lead frame; and a plurality of electrodes provided on a semiconductor chip provided on the lead frame. A method of manufacturing a semiconductor device to be connected by ultrasonic bonding to a connection conductor of a source, a source conductive portion connecting a source terminal formed on the lead frame and a source electrode provided on the semiconductor chip, and the lead A step of integrally forming a gate conductive portion connecting a gate terminal formed on the frame and a gate electrode provided on the semiconductor chip via an insulating portion; and a step of forming the source conductive portion in the connection conductor. One end side is in contact with the source terminal, the other end side is in contact with the source electrode, one end side of the gate conductive portion is in contact with the gate terminal, and the other end side is in contact with the gate electrode. Pressing to ultrasonic vibrations, characterized in that and a step of applying to said connection conductor.

本発明の他の一形態にかかる半導体装置の製造方法は、前記接続導体は、接合状態において前記半導体チップの接合面から離間する方向に湾曲するアーチ部を有する導電板をベースシートに貼り付ける工程と、それぞれ前記アーチ部を有する複数の帯状の導電部が互いに所定の間隔を開けて並列するように前記導電板を個片化する工程と、２つの前記導電部の間を含む所定箇所に絶縁シートを貼り付ける工程と、パターニングにより、前記アーチ部上の所定部位を残して前記絶縁シートを除去し、残された絶縁シートにより前記導電部同士が絶縁される接続導体を前記ベースシート上に複数並列して形成する工程と、前記接続導体毎に前記ベースシートを切り分ける工程と、を備えることを特徴とする。   In the method of manufacturing a semiconductor device according to another aspect of the present invention, the connection conductor includes a step of attaching a conductive plate having an arch portion that curves in a direction away from the bonding surface of the semiconductor chip to the base sheet in the bonded state. And a step of separating the conductive plates so that a plurality of strip-shaped conductive portions each having the arch portion are arranged in parallel at predetermined intervals, and insulated at a predetermined location including between the two conductive portions. A plurality of connection conductors are formed on the base sheet by attaching the sheet and patterning to remove the insulating sheet while leaving a predetermined portion on the arch part, and to insulate the conductive parts from each other by the remaining insulating sheet. A step of forming the base sheet in parallel; and a step of cutting the base sheet for each of the connection conductors.

本発明の他の一形態にかかる半導体装置の製造方法は、前記接続導体の製造方法は、絶縁材で構成されるフレキシブル基板の主面上の所定位置に２本の導電配線を形成する工程と、接合時に前記半導体チップの側面に近接する前記導電配線における所定の部位に、絶縁層を形成する工程と、を備えることを特徴とする。   According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method of manufacturing the connection conductor includes a step of forming two conductive wirings at predetermined positions on a main surface of a flexible substrate made of an insulating material. And a step of forming an insulating layer at a predetermined portion of the conductive wiring adjacent to the side surface of the semiconductor chip at the time of bonding.

本発明によれば、導通状態の電気抵抗を小さくしてパッケージ損失を低減し、かつ製造工数を削減することが可能となる。   According to the present invention, it is possible to reduce the electrical resistance in the conductive state, reduce the package loss, and reduce the number of manufacturing steps.

以下に本発明の一実施形態にかかる半導体装置１及び超音波接合装置３０について、図１乃至図４を参照して説明する。なお、各図において適宜構成を拡大・縮小・省略して示している。図中矢印Ｘ、Ｙ、及びＺは互いに直交する３方向を示している。Ｘ軸は第１方向、Ｙ軸は第２方向、Ｚは上下方向に沿っている。   Hereinafter, a semiconductor device 1 and an ultrasonic bonding apparatus 30 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4. In each figure, the configuration is appropriately enlarged, reduced, or omitted. In the figure, arrows X, Y, and Z indicate three directions orthogonal to each other. The X axis is in the first direction, the Y axis is in the second direction, and Z is in the vertical direction.

図１は本実施形態に係る半導体装置１の斜視図、図２はリードフレーム２０の平面図である。本実施形態の半導体装置１は、例えば、数ミリ角で構成され、小型、薄型であるとともに低Ｒｏｎ、低容量、低消費電力、低電圧駆動等の特徴を有し、携帯電話、デジタルカメラ、ビデオカメラ、ポータブルオーディオ、ＩＣレコーダ等の電源部等（ＤＣ−ＤＣコンバータや中電流スイッチ用途）に適用される小信号トランジスタ、または、小信号半導体装置である。   FIG. 1 is a perspective view of a semiconductor device 1 according to this embodiment, and FIG. 2 is a plan view of a lead frame 20. The semiconductor device 1 of the present embodiment is, for example, configured with several millimeters of squares, and is small and thin, and has characteristics such as low Ron, low capacity, low power consumption, low voltage driving, and the like. It is a small signal transistor or a small signal semiconductor device applied to a power supply unit (for a DC-DC converter or a medium current switch) such as a video camera, a portable audio, and an IC recorder.

図１に示す半導体装置１は、半導体チップ１０と、この半導体チップ１０が搭載されたアイランド部１１と、アイランド部１１から一体に延びる第１端子としてのドレイン端子１２と、アイランド部１１近傍に独立して形成された第２端子としてのソース端子１３と、アイランド部近傍に独立して形成された第３端子としてのゲート端子１４と、を備え、ゲート端子１４に所定の電圧を掛けるとソース端子１３からドレイン端子１２に所定の電流が流れるスイッチとして機能する。   A semiconductor device 1 shown in FIG. 1 includes a semiconductor chip 10, an island portion 11 on which the semiconductor chip 10 is mounted, a drain terminal 12 as a first terminal integrally extending from the island portion 11, and an island portion 11. A source terminal 13 as a second terminal formed in this manner, and a gate terminal 14 as a third terminal formed independently in the vicinity of the island portion. When a predetermined voltage is applied to the gate terminal 14, the source terminal It functions as a switch in which a predetermined current flows from 13 to the drain terminal 12.

半導体装置１の大きさは、例えば数ミリ角であって、その端子１２〜１４の幅や端子同士の間隔は例えば数百μｍ程度に構成されている。   The size of the semiconductor device 1 is, for example, several millimeters square, and the width of the terminals 12 to 14 and the interval between the terminals are, for example, about several hundred μm.

半導体チップ１０の上面１５には、第２電極としてのソース電極１５ａ及び第３電極としてのゲート電極１５ｂ（図１７に示す）が形成されている。これらソース電極１５ａとゲート電極１５ｂがそれぞれ半導体チップ１０の上面とリードフレームとに跨って配置された接続導体としての接続導体１６を介してソース端子１３及びゲート端子１４に接続されている。また、半導体チップ１０の下方側にはドレイン端子１２に接続される第１電極としてのドレイン電極１５ｃが形成されている。   On the upper surface 15 of the semiconductor chip 10, a source electrode 15a as a second electrode and a gate electrode 15b (shown in FIG. 17) as a third electrode are formed. The source electrode 15a and the gate electrode 15b are connected to the source terminal 13 and the gate terminal 14 via connection conductors 16 as connection conductors arranged across the upper surface of the semiconductor chip 10 and the lead frame, respectively. A drain electrode 15 c as a first electrode connected to the drain terminal 12 is formed on the lower side of the semiconductor chip 10.

図２に本実施形態のリードフレーム２０を示す。リードフレーム２０は、例えば銅等の金属性の板状部材が所定の帯形状に形成されている。リードフレーム２０は、複数の半導体装置１に対応するものであり、正方形状のアイランド部１１及び矢印Ｙで示す第２方向に延びる細長形状の端子１２〜１４が、それぞれ矢印Ｘで示す搬送方向に沿って複数個（図２では７個）並列されているとともに、第２方向に沿って２個並列して配置されている。   FIG. 2 shows the lead frame 20 of the present embodiment. The lead frame 20 is formed of a metal plate member such as copper in a predetermined band shape. The lead frame 20 corresponds to the plurality of semiconductor devices 1, and the rectangular island portion 11 and the elongated terminals 12 to 14 extending in the second direction indicated by the arrow Y are respectively provided in the transport direction indicated by the arrow X. A plurality (seven in FIG. 2) are arranged in parallel along the line, and two are arranged in parallel along the second direction.

これら複数のアイランド部１１及び端子１２〜１４が、枠状のフレーム部２１と一体に形成されてなる。フレーム部２１の外縁、すなわち第２方向の両端部の縁には、第１方向に沿って、搬送の際の位置決め用の係合孔２３が複数並列形成されている。   The plurality of island portions 11 and the terminals 12 to 14 are formed integrally with the frame-shaped frame portion 21. On the outer edge of the frame portion 21, that is, at the edges of both end portions in the second direction, a plurality of engaging holes 23 for positioning during transport are formed in parallel along the first direction.

ステージブロック（ステージ）３１の所定位置に並列形成された位置決めピン（不図示）が、この係合孔２３に挿入されて係合することにより、図示しない搬送手段によりリードフレーム２０が第１方向に沿って搬送される。この結果、第１方向に並列された複数の単位リードフレーム２２の一端側から他端側に、順次各種処理装置を通り、これらに対して順次各種処理が施される。   A positioning pin (not shown) formed in parallel at a predetermined position of the stage block (stage) 31 is inserted into the engagement hole 23 and engaged therewith, so that the lead frame 20 is moved in the first direction by a conveying means (not shown). Conveyed along. As a result, the plurality of unit lead frames 22 arranged in parallel in the first direction are sequentially passed through various processing devices from one end side to the other end side, and various processes are sequentially performed on these.

図２中破線で囲む部分が１つの半導体装置１に対応する単位リードフレーム２２であり、複数の半導体装置１を一括製造し、樹脂２４でモールドした後、これらの単位リードフレーム２２毎に分割される。   A portion surrounded by a broken line in FIG. 2 is a unit lead frame 22 corresponding to one semiconductor device 1. After a plurality of semiconductor devices 1 are manufactured at once and molded with resin 24, the unit lead frame 22 is divided for each unit lead frame 22. The

なお、図１は分割された後の半導体装置１を示しているが、モールド樹脂２４を省略して示している。なお、モールドした状態の断面図を図１８に示す。   Although FIG. 1 shows the semiconductor device 1 after being divided, the mold resin 24 is omitted. A sectional view of the molded state is shown in FIG.

複数のアイランド部１１はそれぞれ正方形状の板状に構成されている。アイランド部１１の４隅すなわち左右前後端部分から、細長い矩形状のドレイン端子１２がアイランド部１１に一体に形成されて第２方向に延び、フレーム部２１に接続されている。   Each of the plurality of island portions 11 is formed in a square plate shape. From the four corners of the island portion 11, that is, from the left and right front and rear end portions, elongated rectangular drain terminals 12 are formed integrally with the island portion 11 and extend in the second direction, and are connected to the frame portion 21.

アイランド部１１の、第１方向における隣に、それぞれＹ方向を長手方向として延びる細長い矩形の板状を成すソース端子１３及びゲート端子１４が形成されている。このソース端子１３及びゲート端子１４の上面が超音波接合される被接合界面となる。このソース端子１３及びゲート端子１４は、そのＹ方向における外側の一端部である基端部のみがフレーム部２１に支持されて一体形成されている。他端側の先端部は開放されている。   Next to the island part 11 in the first direction, there are formed a source terminal 13 and a gate terminal 14 each having an elongated rectangular plate shape extending in the Y direction as a longitudinal direction. The upper surfaces of the source terminal 13 and the gate terminal 14 become a bonded interface to be ultrasonically bonded. The source terminal 13 and the gate terminal 14 are integrally formed with only the base end portion, which is the outer end portion in the Y direction, supported by the frame portion 21. The tip on the other end side is open.

半導体チップ１０は、リードフレーム２０のアイランド部１１に搭載されている。半導体チップ１０の上面には、アルミニウム材からなる上面電極１５として、ソース電極１５ａ及びゲート電極１５ｂが形成されている。この上面電極１５の上面が超音波接合される被接合界面となり、接続導体１６を介してソース端子１３に接続されている。     The semiconductor chip 10 is mounted on the island portion 11 of the lead frame 20. On the upper surface of the semiconductor chip 10, a source electrode 15a and a gate electrode 15b are formed as an upper surface electrode 15 made of an aluminum material. The upper surface of the upper surface electrode 15 becomes a bonded interface to be ultrasonically bonded, and is connected to the source terminal 13 via the connection conductor 16.

接続導体１６は、例えばアルミニウム材製の板状または帯状の部材であり、上面電極１５とソース端子１３とに跨って配置されている。接続導体１６の中央部分は湾曲形成されアーチ部１７を構成する、アーチ部１７の両側の下面がそれぞれ接合される被接合界面を構成する。   The connection conductor 16 is, for example, a plate-like or strip-like member made of an aluminum material, and is disposed across the upper surface electrode 15 and the source terminal 13. A central portion of the connection conductor 16 is curved to form an arch portion 17 and constitutes a joined interface to which the lower surfaces on both sides of the arch portion 17 are joined.

接続導体１６は、ソース電極１５ａとソース端子１３を接続するための第１の導電部としてのソース用導電部１６ａと、ゲート電極１５ｂとゲート端子１４とを接続するための第２の導電部としてのゲート用導電部１６ｂとの間に絶縁部１６ｃを設け、それらが板状に一体に形成されてなる。ソース用導電部１６ａとゲート用導電部１６ｂはそれぞれ図中Ｘ方向に伸びる帯状に形成されている。   The connection conductor 16 serves as a source conductive portion 16a as a first conductive portion for connecting the source electrode 15a and the source terminal 13, and as a second conductive portion for connecting the gate electrode 15b and the gate terminal 14. An insulating portion 16c is provided between the gate conductive portion 16b and these are integrally formed in a plate shape. The source conductive portion 16a and the gate conductive portion 16b are each formed in a strip shape extending in the X direction in the drawing.

接続導体１６は、ソースとゲートが絶縁されるようソースの導電経路となるソース用導電部１６ａとゲートの導電経路となるゲート用導電部１６ｂの間に絶縁部１６ｃが設けられている。   In the connection conductor 16, an insulating portion 16c is provided between a source conductive portion 16a serving as a source conductive path and a gate conductive portion 16b serving as a gate conductive path so that the source and the gate are insulated.

すなわち、接続導体１６のＸ方向両端部をそれぞれリードフレーム２０、半導体チップ１０に接合することにより、ソース電極１５ａとソース端子１３間、ゲート電極１５ｂとゲート端子１４間を超音波接合により接合する。   That is, the X direction both ends of the connection conductor 16 are joined to the lead frame 20 and the semiconductor chip 10 respectively, thereby joining the source electrode 15a and the source terminal 13 and the gate electrode 15b and the gate terminal 14 by ultrasonic joining.

これにより、ソース電極１５ａとソース端子１３間は導通し、ゲート電極１５ｂとゲート端子１４間は導通するがソース電極１５ａとゲート電極１５ｂ間は絶縁される。   Thereby, the source electrode 15a and the source terminal 13 are electrically connected, and the gate electrode 15b and the gate terminal 14 are electrically connected, but the source electrode 15a and the gate electrode 15b are insulated.

半導体チップ１０の電極の材質、接続導体１６のソース用導電部１６ａ、及びゲート用導電部１６ｂの材質はいずれもアルミニウム材である。なお、この明細書で言うアルミニウム材とは、アルミニウムまたはアルミニウム合金からなるものを言う。絶縁部１６ｃの材質は樹脂製の絶縁体、例えばポリイミドであり、リードフレーム２０の材質は銅である。   The material of the electrode of the semiconductor chip 10 and the material of the source conductive portion 16a and the gate conductive portion 16b of the connection conductor 16 are all aluminum. In addition, the aluminum material said in this specification means what consists of aluminum or an aluminum alloy. The material of the insulating part 16c is a resin insulator, for example, polyimide, and the material of the lead frame 20 is copper.

接続導体１６は、第１方向に沿って延び、その中央部分が上方向に湾曲して下方に開くアーチ部１７を構成する。このアーチ部１７において接続導体１６は半導体チップ１０から上方に離間している。このため、接続導体１６は、半導体チップ１０及び上面電極１５との間に第２方向に貫通する間隙を呈する。したがって、接続導体１６は、半導体チップ１０の側面の電極と絶縁されている。   The connection conductor 16 extends along the first direction, and constitutes an arch portion 17 whose central portion curves upward and opens downward. In the arch portion 17, the connection conductor 16 is spaced upward from the semiconductor chip 10. For this reason, the connection conductor 16 exhibits a gap penetrating in the second direction between the semiconductor chip 10 and the upper surface electrode 15. Therefore, the connection conductor 16 is insulated from the electrode on the side surface of the semiconductor chip 10.

接続導体１６の一端側の下面（一部分）がソース端子１３及びゲート端子１４に、他端側の下面（他の部分）が半導体チップ１０の上面のソース電極１５ａ及びゲート電極１５ｂに、接続される。ソース端子１３よりも上面電極１５の方が上方に位置しているため、接続導体１６は、一端側よりも他端側の下面が高い位置となるように構成されている。この接続導体１６の両端の下面が超音波接合される被接合界面となる。   The lower surface (part) of one end side of the connection conductor 16 is connected to the source terminal 13 and the gate terminal 14, and the lower surface (other part) of the other end side is connected to the source electrode 15 a and the gate electrode 15 b on the upper surface of the semiconductor chip 10. . Since the upper electrode 15 is positioned above the source terminal 13, the connection conductor 16 is configured such that the lower surface on the other end side is higher than the one end side. The lower surfaces of both ends of the connection conductor 16 are bonded interfaces to be ultrasonically bonded.

接続導体１６を電極１５ａ，ｂ及び端子１３，１４に接合するための超音波接合装置３０について、図３及び図４を参照して説明する。図３は半導体装置が設置された超音波接合装置３０の斜視図であり、図４はツール部３４の底面を示す斜視図である。   An ultrasonic bonding apparatus 30 for bonding the connection conductor 16 to the electrodes 15a and 15b and the terminals 13 and 14 will be described with reference to FIGS. FIG. 3 is a perspective view of the ultrasonic bonding apparatus 30 in which the semiconductor device is installed, and FIG. 4 is a perspective view showing the bottom surface of the tool portion 34.

超音波接合装置３０は、接続導体に圧力と強力な超音波振動を与えることにより、被接合界面を摩擦することで固相接合するものである。超音波接合装置３０は、リードフレーム２０が載置されるステージブロック３１と、このステージブロック３１にリードフレーム２０を固定するための固定治具３２、３３と、ステージブロック３１の上方に位置し、超音波ホーン（図示せず）の先端に取り付けられるツール部３４とを有する。   The ultrasonic bonding apparatus 30 performs solid-phase bonding by rubbing the interface to be bonded by applying pressure and strong ultrasonic vibration to the connection conductor. The ultrasonic bonding apparatus 30 is positioned above the stage block 31, a stage block 31 on which the lead frame 20 is placed, fixing jigs 32 and 33 for fixing the lead frame 20 to the stage block 31, And a tool part 34 attached to the tip of an ultrasonic horn (not shown).

ツール部３４は例えば図中矢印Ｚに沿う上下方向及び第２方向において移動可能であり、第２方向において２列並列された処理対象としての半導体装置１に対して順次処理を施すことが可能である。ツール部３４は超音波振動を発生させる超音波ホーンの先端に取り付けられている。   For example, the tool part 34 is movable in the vertical direction and the second direction along the arrow Z in the figure, and can sequentially perform processing on the semiconductor device 1 as a processing target arranged in two rows in the second direction. is there. The tool part 34 is attached to the tip of an ultrasonic horn that generates ultrasonic vibrations.

ツール部３４の底面は図４に示すように、アーチ部１７に対応する凹み形状の凹部３４ａと、ソース電極１５ａを接続導体１６に接合させる第１押圧部３５と、ソース端子１３を接続導体１６と接合させる第２押圧部３６と、ゲート電極１５ｂを接続導体１６に接合させる第３押圧部３７と、ゲート端子１４を接続導体１６に接合させる第４押圧部３８とからなり、各押圧部３５，３６，３７，３８の先端面には全面には、それぞれ同じ大きさの複数の四角錘台状の突起３９が格子状に並列して形成されている。突起３９は、０．３ｍｍ程度のピッチで第１及び第２方向において並列形成されている。この突起３９により、接合面を均一に押圧することができる。   As shown in FIG. 4, the bottom surface of the tool portion 34 has a concave recess 34 a corresponding to the arch portion 17, a first pressing portion 35 that joins the source electrode 15 a to the connection conductor 16, and the source terminal 13 as the connection conductor 16. Each pressing portion 35 includes a second pressing portion 36 to be joined to the connecting conductor 16, a third pressing portion 37 to join the gate electrode 15b to the connecting conductor 16, and a fourth pressing portion 38 to join the gate terminal 14 to the connecting conductor 16. , 36, 37, 38 are formed with a plurality of square frustum-shaped projections 39 of the same size in parallel on the entire front end surface thereof in a grid pattern. The protrusions 39 are formed in parallel in the first and second directions with a pitch of about 0.3 mm. The projection 39 can press the bonding surface uniformly.

そして、第１押圧部３５と第２押圧部３６とは、半導体チップ１０の上面電極１５の平面と端子１３、１４の平面との距離、すなわち高さの差に相当する段差が形成されている。   The first pressing portion 35 and the second pressing portion 36 are formed with a step corresponding to the distance between the plane of the upper surface electrode 15 of the semiconductor chip 10 and the plane of the terminals 13, 14, that is, the difference in height. .

次に、本実施形態にかかる半導体装置１の製造方法について、図５乃至図１３を参照して説明する。   Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS.

まず、接続導体１６の製造方法について説明する。まず図５及び図６に示すように、アーチ部１７を成型したアルミ板４０を、ＵＶダイシングテープで構成されたダイシングシート（ベースシート）４１に貼り付ける。アルミ板４０は矩形の板状であり、複数箇所において厚み方向に湾曲したアーチ部１７が形成されている。   First, a method for manufacturing the connection conductor 16 will be described. First, as shown in FIGS. 5 and 6, the aluminum plate 40 on which the arch portion 17 is molded is attached to a dicing sheet (base sheet) 41 composed of a UV dicing tape. The aluminum plate 40 has a rectangular plate shape, and is formed with arch portions 17 curved in the thickness direction at a plurality of locations.

図７及び図８に示すように、接続の対象となるリードフレーム２０と半導体チップ１０の大きさ及び配置に対応した所定形状にアルミ板４０を個片化する。   As shown in FIGS. 7 and 8, the aluminum plate 40 is separated into a predetermined shape corresponding to the size and arrangement of the lead frame 20 and the semiconductor chip 10 to be connected.

ここで、Ｙ方向に伸びソース用導電部１６ａとなる帯状のアルミ板部４０ａ（導電部）と、ゲート用導電部１６ｂとなる帯状のアルミ板部４０ｂ（導電部）とがＸ方向に所定の間隔を開けて並列するように個片化する。   Here, a strip-shaped aluminum plate portion 40a (conductive portion) extending in the Y direction and serving as the source conductive portion 16a and a strip-shaped aluminum plate portion 40b (conductive portion) serving as the gate conductive portion 16b are predetermined in the X direction. Divide into pieces so as to be parallel with a gap.

個片化されたアルミ板４０ａ、４０ｂの上に、図９及び図１０に示すように、矩形状の絶縁シート４２を貼り付ける。複数の個片化されたアルミ板４０ａ、４０ｂが並列した状態で、これら及びその間を覆うように矩形状のポリイミド粘着テープで構成された絶縁シート４２を貼り付ける。   As shown in FIGS. 9 and 10, a rectangular insulating sheet 42 is pasted on the separated aluminum plates 40 a and 40 b. In a state where a plurality of separated aluminum plates 40a and 40b are arranged in parallel, an insulating sheet 42 made of a rectangular polyimide adhesive tape is attached so as to cover these and the space between them.

さらに図１１及び図１２に示すように、パターニングにより、アーチ部１７上においてＸ方向に伸びる矩形の所定部位を残して絶縁シート４２を除去する。絶縁シート４２の残された部分が絶縁部１６ｃとなり、アルミ材で形成されたソース用導電部１６ａ、絶縁部１６ｃ、アルミ材で形成されたゲート用導電部１６ｂがＸ方向に並列して形成され、ゲートとソースが絶縁された接続導体１６が完成する。接続導体１６はツールによって図１３に示すように一つずつピックアップされて接合の際に用いられる。   Further, as shown in FIGS. 11 and 12, the insulating sheet 42 is removed by patterning, leaving a predetermined rectangular portion extending in the X direction on the arch portion 17. The remaining portion of the insulating sheet 42 becomes the insulating portion 16c, and the source conductive portion 16a formed of aluminum material, the insulating portion 16c, and the gate conductive portion 16b formed of aluminum material are formed in parallel in the X direction. Then, the connection conductor 16 in which the gate and the source are insulated is completed. The connecting conductors 16 are picked up one by one by a tool as shown in FIG. 13 and used for joining.

接合の際には、まず、接続導体１６、リードフレーム２０および半導体チップ１０が用意され、超音波接合機３０の収納部に接続導体１６がセットされる。また、リードフレーム２０をステージ上に搭載する。   When joining, first, the connection conductor 16, the lead frame 20, and the semiconductor chip 10 are prepared, and the connection conductor 16 is set in the housing portion of the ultrasonic bonding machine 30. The lead frame 20 is mounted on the stage.

図１４に示すように、アイランド部１１に半導体チップ１０が、例えば高温はんだを介して固着される。高温はんだの種類としては、例えばＰｂリッチはんだ、ＡｕＧｅはんだ、ＡｕＳｎはんだ等が適用される。   As shown in FIG. 14, the semiconductor chip 10 is fixed to the island part 11 via, for example, high-temperature solder. For example, Pb-rich solder, AuGe solder, AuSn solder, or the like is applied as the type of high-temperature solder.

次に、図１５に示すように、リードフレーム２０がステージブロック３１に移載され、ツール部３４により、接続導体１６が吸着され、リードフレーム２０および半導体チップ１０上に載置されて接続導体１６の一端部とソース端子１３、および接続導体１６の他端部と上面電極１５が重ね合わされる。   Next, as shown in FIG. 15, the lead frame 20 is transferred to the stage block 31, the connection conductor 16 is attracted by the tool portion 34, and placed on the lead frame 20 and the semiconductor chip 10 to be connected to the connection conductor 16. The one end of the source electrode 13 and the source terminal 13, and the other end of the connection conductor 16 and the upper surface electrode 15 are superimposed.

次に、ツール部３４を用いて接合工程が行われる。リードフレーム２０のリード端子１２〜１４が、第１方向に延びる固定治具３２、３３により固定された状態で、ツール部３４をＺ方向に沿って降下させ、ツール部の第１、第３押圧部３５、３７により接続導体１６の一端部とソース端子１３及びゲート端子１４を、第２押圧部３６、第４押圧部３８により接続導体１６の他端部と上面のソース電極１５ａ，ゲート電極１５ｂを同時に下方に押圧するとともに、超音波を加えて水平方向に超音波振動させることにより、接続導体１６を端子１３，１４と電極１５ａ，１５ｂに接合する。   Next, a joining process is performed using the tool part 34. In a state where the lead terminals 12 to 14 of the lead frame 20 are fixed by the fixing jigs 32 and 33 extending in the first direction, the tool part 34 is lowered along the Z direction, and the first and third pressings of the tool part are performed. One end of the connection conductor 16 and the source terminal 13 and the gate terminal 14 are connected by the portions 35 and 37, and the other end of the connection conductor 16 and the source electrode 15a and the gate electrode 15b on the upper surface are connected by the second pressing portion 36 and the fourth pressing portion 38. Are simultaneously pressed downward, and an ultrasonic wave is applied to cause ultrasonic vibration in the horizontal direction, thereby joining the connection conductor 16 to the terminals 13 and 14 and the electrodes 15a and 15b.

半導体チップ１０のソース電極１５ａと接続導体１６、ソース端子１３と接続導体１６、半導体チップ１０のゲート電極１５ｂと接続導体１６、ゲート端子１４と接続導体１６が同時に超音波接合される。   The source electrode 15a and the connection conductor 16 of the semiconductor chip 10, the source terminal 13 and the connection conductor 16, the gate electrode 15b and the connection conductor 16 of the semiconductor chip 10, and the gate terminal 14 and the connection conductor 16 are ultrasonically bonded simultaneously.

この超音波接合によって、２つの金属が極めて短時間で接合される。すなわち、接合される対象となる金属表面、ここでは接続導体１６の両端の下面、電極１５ａ、１５ｂ及びソース端子１３、ゲート端子１４の上面には、吸着物や酸化皮膜があり、またミクロにみれば平滑ではなく、超音波振動を付与することによって接合対象の２つの金属同士を摩擦させる。この摩擦により、対象となる金属表面の吸着物や酸化皮膜が破壊され、接触面が機械的にクリーニングされるとともに平滑化されて、金属同士間において凝着が起こる。次に、電極１５ａ，１５ｂ、端子１３，１４の上面と接合の対象となる接続導体１６との間で相対運動が起こり、急激な塑性流動によって接合面積が拡大される。   By this ultrasonic bonding, two metals are bonded in an extremely short time. That is, there are adsorbates and oxide films on the metal surfaces to be joined, here the lower surfaces of both ends of the connecting conductor 16, the electrodes 15a and 15b, the source terminal 13, and the gate terminal 14, and they are seen microscopically. The two metals to be joined are rubbed with each other by applying ultrasonic vibration instead of being smooth. By this friction, the adsorbate and oxide film on the target metal surface are destroyed, the contact surface is mechanically cleaned and smoothed, and adhesion occurs between the metals. Next, relative movement occurs between the upper surfaces of the electrodes 15a and 15b and the terminals 13 and 14 and the connection conductor 16 to be joined, and the joining area is expanded by a rapid plastic flow.

この後、リードフレーム２０の第１方向に搬送し、モールド装置に移送して、図１８に示すように、樹脂２４でモールドする。この樹脂モールド工程において、樹モールド金型によって、リードフレーム２０が搬送される第１方向に交差する第２方向に向かって樹脂２４の充填処理がなされる。このため、接続導体１６の湾曲したアーチ部１７の内側に樹脂２４を良好に充填することができる。すなわち、ソース端子１３と上面電極１５とが第１方向に並んでいるため、搬送方向と直行する方向で処理することで良好にアーチ部１７の内側まで樹脂２４を充填させることができる。したがって、搬送方向と直交する方向で動作する装置を、搬送方向に沿って配置することができるので設置が容易となる。   Thereafter, the lead frame 20 is conveyed in the first direction, transferred to a molding device, and molded with a resin 24 as shown in FIG. In this resin molding process, the resin 24 is filled with a resin mold in a second direction that intersects the first direction in which the lead frame 20 is conveyed. For this reason, the resin 24 can be satisfactorily filled inside the curved arch portion 17 of the connection conductor 16. That is, since the source terminal 13 and the upper surface electrode 15 are arranged in the first direction, the resin 24 can be satisfactorily filled to the inside of the arch portion 17 by processing in the direction orthogonal to the transport direction. Therefore, the apparatus that operates in the direction orthogonal to the transport direction can be arranged along the transport direction, so that installation is facilitated.

この後、ホーニング、マーク、メッキ、セパレーション、テスト、テーピング、などの各種処理を経て、半導体装置１が完成する。   Thereafter, the semiconductor device 1 is completed through various processes such as honing, marking, plating, separation, testing, and taping.

本実施形態において、複数のアイランド部１１やドレイン端子１２〜１４を多数並列するリードフレーム２０が、係合孔２３により位置決めされて第１方向に搬送され、超音波接合、樹脂モールド、等の各種処理具の処理対象となる部分を順次第１方向に沿って通る際に、各種処理が順次行われ、多数の半導体装置１が一括製造される。   In the present embodiment, a lead frame 20 in which a plurality of island portions 11 and drain terminals 12 to 14 are arranged in parallel is positioned by the engagement hole 23 and conveyed in the first direction, and various types such as ultrasonic bonding, resin molding, and the like. Various processes are sequentially performed when a portion to be processed of the processing tool is sequentially passed along the first direction, and a large number of semiconductor devices 1 are manufactured at once.

すなわち、図示しない搬送手段において係合孔２３に係合させてリードフレーム２０を第１方向すなわちＸ方向に沿って搬送し、リードフレーム２０を移動させながらツール部３４により上記の処理を順次複数の単位リードフレーム２２に対して繰り返し、多数の半導体装置１を一括製造することができる。例えば本実施形態では単位リードフレーム２２は第２方向に２列形成されているので、第２方向に移動可能なツール部３４を用いて２列ずつ処理を行うことができる。あるいはこれに代えて、第２方向において同様のツール部３４を二つ並列して同時に作動させることにより２列ずつ処理することも可能である。   In other words, the lead frame 20 is transported along the first direction, that is, the X direction by being engaged with the engagement hole 23 by a transport means (not shown), and the above-described processing is sequentially performed by the tool portion 34 while moving the lead frame 20. A large number of semiconductor devices 1 can be manufactured at once by repeating the unit lead frame 22. For example, in this embodiment, the unit lead frames 22 are formed in two rows in the second direction, so that the processing can be performed in two rows using the tool part 34 that can move in the second direction. Alternatively, it is also possible to process two rows at a time by simultaneously operating two similar tool portions 34 in parallel in the second direction.

本実施形態にかかる半導体装置、接続導体及び半導体装置の製造方法は以下に掲げる効果を奏する。すなわち、ソース電極１５ａとソース端子１３の接続、ゲート電極１５ｂとゲート端子１４の接続を一括で行うことにより、ワイヤボンディング工程及び装置が不要となり、半導体装置の製造コストを低減することができる。   The semiconductor device, the connection conductor, and the manufacturing method of the semiconductor device according to the present embodiment have the following effects. That is, the connection between the source electrode 15a and the source terminal 13 and the connection between the gate electrode 15b and the gate terminal 14 are collectively performed, so that a wire bonding process and an apparatus are not necessary, and the manufacturing cost of the semiconductor device can be reduced.

［第２実施形態］
本発明の第２実施形態にかかる半導体装置、接続導体及び半導体装置の製造方法について図１９及び図２２を参照して説明する。なお、本実施形態の半導体装置、接続導体及び半導体装置の製造方法は、接続導体５０の構成及び製造工程以外の点は上記第１実施形態と同様である。 [Second Embodiment]
A semiconductor device, a connection conductor, and a method for manufacturing the semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. The semiconductor device, the connection conductor, and the method for manufacturing the semiconductor device of the present embodiment are the same as those of the first embodiment except for the configuration of the connection conductor 50 and the manufacturing process.

本実施形態にかかる接続導体５０は、図２０に示すように、絶縁材からなるフレキシブル基板で形成されるベース部５１と、ベース部５１上に形成された第１の銅配線５２と、第１の銅配線と離間して形成された第２の銅配線５３と、これらの銅配線の両端にそれぞれアルミニウム材がめっきされた接合端部５２ａ，５２ｂ、５３ａ，５３ｂと、銅配線上（下面）を横切るように形成された電極絶縁部５４と、を備えて構成されている。この接続導体５０は、中央部分が湾曲した状態で、その一端側が半導体チップの上面のソース電極１５ａ及びゲート電極１５ｂに接合され、多端側がリードフレーム２０の端子１３，１４に接合されている。図１９に示すように、接続導体５０にはアーチ部は形成されておらず、平板状に構成されている。   As shown in FIG. 20, the connection conductor 50 according to the present embodiment includes a base portion 51 formed of a flexible substrate made of an insulating material, a first copper wiring 52 formed on the base portion 51, and a first Second copper wiring 53 formed apart from the copper wiring, joint ends 52a, 52b, 53a, 53b each plated with an aluminum material, and above the copper wiring (lower surface) And an electrode insulating part 54 formed so as to cross the line. The connecting conductor 50 is bent at the center portion, one end thereof is joined to the source electrode 15a and the gate electrode 15b on the upper surface of the semiconductor chip, and the other end is joined to the terminals 13 and 14 of the lead frame 20. As shown in FIG. 19, the connecting conductor 50 is not formed with an arch portion, and is configured in a flat plate shape.

すなわち、この接続導体５０によって、ゲート用の電極と端子が接合されると同時にソース用の電極と端子とが接続されている。   That is, the connection conductor 50 joins the gate electrode and the terminal and simultaneously connects the source electrode and the terminal.

ベース部５１は、矩形の板状のフレキシブル基板からなり、ポリイミド等で形成されている。このベース部は厚み方向（図中Ｚ方向）における少なくとも一方側に撓み変形可能である。   The base 51 is made of a rectangular plate-like flexible substrate and is made of polyimide or the like. This base portion can be bent and deformed to at least one side in the thickness direction (Z direction in the figure).

このベース部５１の接合側の面上、すなわち、図１９における下側であって、図２０における上面側、にＸ方向に伸びる細長い２本の銅配線５２，５３が形成されている。すなわち、この銅配線５２，５３がそれぞれ第２及び第３の接続部を構成するとともにこの銅配線５２，５３の間のベース部５１が絶縁部を構成する。   Two elongated copper wirings 52 and 53 extending in the X direction are formed on the surface of the base portion 51 on the bonding side, that is, the lower side in FIG. 19 and the upper surface side in FIG. That is, the copper wirings 52 and 53 constitute second and third connection parts, respectively, and the base part 51 between the copper wirings 52 and 53 constitutes an insulating part.

この銅配線５２，５３の長手方向の両端部の接合側の面に、アルミによるめっきが施され、接合端部５２ａ，５２ｂ，５３ａ，５３ｂ，が形成されている。   The copper-side wirings 52 and 53 are plated with aluminum on the joint-side surfaces at both ends in the longitudinal direction to form joint end portions 52a, 52b, 53a, and 53b.

さらに、接続導体５０の接合側の面であって図１９において接続導体５０が上面電極に接触する部位には、銅配線５２，５３を横切ってポリイミドがコーティングされることにより電極絶縁部５４が形成されている。この電極絶縁部５４は、接続導体５０が半導体チップ１０の側面に形成されている電極との絶縁を確保する機能を有する。   Further, in the surface of the connecting conductor 50 on the bonding side where the connecting conductor 50 contacts the upper surface electrode in FIG. 19, an electrode insulating portion 54 is formed by coating polyimide across the copper wirings 52 and 53. Has been. The electrode insulating portion 54 has a function of ensuring insulation between the connection conductor 50 and the electrode formed on the side surface of the semiconductor chip 10.

本実施形態にかかる接続導体の製造方法においては、図２２に示すように、ポリイミド等で構成されるフレキシブル基板の主面上の所定位置に２本の銅配線５２，５３をパターニング形成する。導電体である銅配線５２，５３は、第２導電体及び第３導電体となる部分に形成する。銅配線５２，５３の両端部にアルミめっきを施し、円形の接合端部５２ａ，５２ｂ，５３ａ，５３ｂを形成する。さらに、銅配線５２，５３を横切るように、半導体チップ１０の側面電極に近接する所定の部位にポリイミド等で絶縁層を形成し、電極絶縁部５４を構成する。以上により接続導体５０が完成する。   In the manufacturing method of the connection conductor according to this embodiment, as shown in FIG. 22, two copper wirings 52 and 53 are formed by patterning at predetermined positions on the main surface of a flexible substrate made of polyimide or the like. Copper wirings 52 and 53, which are conductors, are formed in portions that become the second conductor and the third conductor. Aluminum plating is applied to both ends of the copper wirings 52 and 53 to form circular joining end portions 52a, 52b, 53a and 53b. Further, an insulating layer is formed of polyimide or the like at a predetermined portion close to the side electrode of the semiconductor chip 10 so as to cross the copper wirings 52 and 53, thereby constituting the electrode insulating portion 54. Thus, the connection conductor 50 is completed.

完成した接続導体５０は、上記第１実施形態の接続導体１６と同様に、超音波接合装置によって、一端側の接合端部５２ａ，５３ａが半導体チップ１０の上面の電極１５ａ，１５ｂに接合されるとともに、他端側の接合端部５２ｂ、５３ｂがリードフレームの第２端子１３、及び第３端子１４にそれぞれ位置あわせされて押圧され、超音波接合される。   The completed connection conductor 50 is bonded to the electrodes 15a and 15b on the upper surface of the semiconductor chip 10 by the ultrasonic bonding apparatus, similarly to the connection conductor 16 of the first embodiment. At the same time, the joining end portions 52b and 53b on the other end side are aligned and pressed to the second terminal 13 and the third terminal 14 of the lead frame, respectively, and are ultrasonically joined.

本実施形態にかかる半導体装置、接続導体及び半導体装置の製造方法によれば、フレキシブル基板を用いたことによりアーチ部分を形成する必要がない。したがって、接続導体に要するＺ方向の厚み方向の寸法を比較的小さくすることができる。このため断面積を大きくとることができるので、導通経路を用意に確保することが可能となる。またアルミニウム材よりも導通のよい銅を適用することができる。   According to the semiconductor device, the connection conductor, and the semiconductor device manufacturing method according to the present embodiment, it is not necessary to form an arch portion by using the flexible substrate. Therefore, the dimension in the thickness direction in the Z direction required for the connection conductor can be made relatively small. For this reason, since a cross-sectional area can be taken large, it becomes possible to ensure a conduction path easily. Further, copper that is more conductive than an aluminum material can be used.

また、本実施形態の接続導体５０は、大きなフレキシブル基板上に多数の銅配線、アルミめっきを施した後に個片化することで、一度に多数の接続導体を製造することが可能であるため、製造時間の短縮及び費用の削減が可能となる。   In addition, since the connection conductor 50 of the present embodiment can be manufactured in pieces after performing a large number of copper wirings and aluminum plating on a large flexible substrate, a large number of connection conductors can be manufactured at one time. Manufacturing time can be reduced and costs can be reduced.

なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。例えば、リードフレーム２０のドレイン端子１２〜１４や上面電極１５の形状及び材質もこれに限定されるものではなく、種々変更して適用することができる。上記実施形態では、上面電極１５及び接続導体１６がアルミ材からなり、端子が銅からなる場合について説明したが、これに限られるものではなく、例えば他に、上面電極１５の材質が金でソース端子１３の材質がアルミニウムの場合や、ソース端子１３の材質が銅で接続導体１６の材質がアルミニウムである場合などが考えられる。また、接続される金属同士が異なる材質であっても同じ材質であっても同様の効果が得られる。   Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. For example, the shapes and materials of the drain terminals 12 to 14 and the upper surface electrode 15 of the lead frame 20 are not limited to this, and various changes can be applied. In the above embodiment, the case where the upper surface electrode 15 and the connection conductor 16 are made of an aluminum material and the terminal is made of copper has been described. However, the present invention is not limited to this. For example, the material of the upper surface electrode 15 is a gold source. A case where the material of the terminal 13 is aluminum or a case where the material of the source terminal 13 is copper and the material of the connecting conductor 16 is aluminum is conceivable. The same effect can be obtained regardless of whether the metals to be connected are different materials or the same materials.

上述の実施の形態では、突起３９は四角錘台形状に限定されるものではなく、例えば多角錐台形状突起、円錐台形状突起、または半球状突起としても構わない。   In the above-described embodiment, the projection 39 is not limited to a square frustum shape, and may be a polygonal frustum-shaped projection, a truncated cone-shaped projection, or a hemispherical projection, for example.

また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。   In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

本発明の第１実施形態にかかる半導体装置を示す斜視図。1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention. 同実施形態にかかるリードフレームを示す平面図。The top view which shows the lead frame concerning the embodiment. 同実施形態にかかる超音波接合装置を示す斜視図。The perspective view which shows the ultrasonic bonding apparatus concerning the embodiment. 同超音波接合装置のツール部を示す斜視図。The perspective view which shows the tool part of the ultrasonic bonding apparatus. 同実施形態にかかる半導体装置の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the semiconductor device concerning the embodiment. 同半導体装置の製造方法を示す平面図。FIG. 7 is a plan view showing the method for manufacturing the semiconductor device. 同半導体装置の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the same semiconductor device. 同半導体装置の製造方法を示す平面図。FIG. 7 is a plan view showing the method for manufacturing the semiconductor device. 同半導体装置の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the same semiconductor device. 同半導体装置の製造方法を示す平面図。FIG. 7 is a plan view showing the method for manufacturing the semiconductor device. 同半導体装置の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the same semiconductor device. 同半導体装置の製造方法を示す平面図。FIG. 7 is a plan view showing the method for manufacturing the semiconductor device. 同半導体装置の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the same semiconductor device. 同半導体装置の製造方法を示す側面図。The side view which shows the manufacturing method of the same semiconductor device. 同半導体装置の製造方法を示す側面図。The side view which shows the manufacturing method of the same semiconductor device. 同半導体装置の製造方法を示す側面図。The side view which shows the manufacturing method of the same semiconductor device. 同半導体装置の製造方法を示す平面図。FIG. 7 is a plan view showing the method for manufacturing the semiconductor device. 同半導体装置の製造方法を示す側面図。The side view which shows the manufacturing method of the same semiconductor device. 本発明の第２実施形態にかかる半導体装置を示す側面図。The side view which shows the semiconductor device concerning 2nd Embodiment of this invention. 同半導体装置の製造方法を示す平面図。FIG. 9 is a plan view showing the method for manufacturing the semiconductor device. 同半導体装置の図２０のＡ−Ａ断面における断面図。Sectional drawing in the AA cross section of FIG. 20 of the semiconductor device. 同半導体装置の製造方法を示す平面図。FIG. 7 is a plan view showing the method for manufacturing the semiconductor device. 同半導体装置の図２０のＢ−Ｂ断面における断面図。Sectional drawing in the BB cross section of FIG. 20 of the semiconductor device.

符号の説明Explanation of symbols

１…半導体装置、１０…半導体チップ、１１…アイランド部、１２…ドレイン端子、
１３…ソース端子、１４…ゲート端子、１５…上面電極、１５ａ…ソース電極、
１５ｂ…ゲート電極、ドレイン電極…１５ｃ、１６…接続導体、１６ａ…ソース用導電部、
１６ｂ…ゲート用導電部、１６ｃ…絶縁部、１６ｃ…絶縁体、１７…アーチ部、
２０…リードフレーム、２１…フレーム部、２２…単位リードフレーム、２３…係合孔、
３０…超音波接合装置、３０…超音波接合機、３１…ステージブロック、
３２．３３…固定治具、３４…ツール部、３４ａ…凹部、３５…第１押圧部、３６…第２押圧部、３７…第３押圧部、３８…第４押圧部、３９…突起、４０…アルミ板、
４０ａ…アルミ板部、４０ｂ…アルミ板部、４１…ダイシングシート（ベースシート）、４２…絶縁シート、５０…接続導体、５１…ベース部、５２…第１の銅配線、５３…第２の銅配線、５２ａ．５２ｂ．５３ａ．５３ｂ…接合端部、５４…電極絶縁部。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Semiconductor chip, 11 ... Island part, 12 ... Drain terminal,
13 ... Source terminal, 14 ... Gate terminal, 15 ... Top electrode, 15a ... Source electrode,
15b ... gate electrode, drain electrode ... 15c, 16 ... connection conductor, 16a ... conductive portion for source,
16b ... conductive portion for gate, 16c ... insulating portion, 16c ... insulator, 17 ... arch portion,
20 ... lead frame, 21 ... frame portion, 22 ... unit lead frame, 23 ... engagement hole,
30 ... Ultrasonic bonding apparatus, 30 ... Ultrasonic bonding machine, 31 ... Stage block,
32.33 ... Fixing jig, 34 ... Tool part, 34a ... Recess, 35 ... First pressing part, 36 ... Second pressing part, 37 ... Third pressing part, 38 ... Fourth pressing part, 39 ... Projection, 40 …an alminium board,
40a ... Aluminum plate part, 40b ... Aluminum plate part, 41 ... Dicing sheet (base sheet), 42 ... Insulating sheet, 50 ... Connection conductor, 51 ... Base part, 52 ... First copper wiring, 53 ... Second copper Wiring, 52a. 52b. 53a. 53b ... Joining end, 54 ... Electrode insulating part.

Claims (5)

ドレイン端子、ソース端子及び、ゲート端子を有するリードフレームと、
前記リードフレーム上に設けられ、前記リードフレーム側の一方の面にドレイン電極を有し、前記リードフレームと反対側の他方の面にソース電極とゲート電極を有する半導体チップと、
第１方向に延び一端側が前記ソース端子に接続されるとともに他端側が前記ソース電極に接続される導電性の帯状のソース用導電部と、前記第１方向に延び一端側が前記ゲート端子に接続されるとともに他端側が前記ゲート電極に接続される帯状の導電性のゲート用導電部とが、間に絶縁部を介して前記第１方向と交差する第２方向において並列して一体に形成された、板状の接続導体と、
を備えたことを特徴とする半導体装置。 A lead frame having a drain terminal, a source terminal, and a gate terminal;
A semiconductor chip provided on the lead frame, having a drain electrode on one surface on the lead frame side, and having a source electrode and a gate electrode on the other surface opposite to the lead frame;
A conductive band-shaped source conductive portion extending in the first direction and having one end connected to the source terminal and the other end connected to the source electrode, and one end connected to the gate terminal extending in the first direction. In addition, a strip-shaped conductive gate conductive portion whose other end is connected to the gate electrode is integrally formed in parallel in the second direction intersecting the first direction with an insulating portion therebetween. A plate-like connecting conductor;
A semiconductor device comprising: 第１端子、第２端子、及び第３端子を有するリードフレームと、
前記リードフレームに設けられ、一方の面に第１電極を、他方の面に第２電極と第３電極を有する半導体チップと、
前記第２端子と前記第２電極を接続する第１の導電部と、前記第３端子と前記第３電極とを接続する第２の導電部とが、絶縁部を介して一体に形成された、板状の接続導体と、を備えたことを特徴とする半導体装置。 A lead frame having a first terminal, a second terminal, and a third terminal;
A semiconductor chip provided on the lead frame, having a first electrode on one side and a second electrode and a third electrode on the other side;
The first conductive part that connects the second terminal and the second electrode and the second conductive part that connects the third terminal and the third electrode are integrally formed via an insulating part. And a plate-like connection conductor. リードフレームに形成された複数の端子と、前記リードフレームに設けられた半導体チップに設けられた複数の電極とを、板状または帯状の接続導体に超音波接合して接続する半導体装置の製造方法であって、
前記リードフレームに形成されたソース端子と前記半導体チップに設けられたソース電極を接続するソース用導電部と、前記リードフレームに形成されたゲート端子と前記半導体チップに設けられたゲート電極とを接続するゲート用導電部とを、絶縁部を介して一体に形成する工程と、
前記接続導体における前記ソース用導電部の一端側を前記ソース端子に、他端側を前記ソース電極に、前記ゲート用導電部の一端側を前記ゲート端子に、他端側を前記ゲート電極に接するように押圧して超音波振動を前記接続導体に付与する工程と、
を備えたことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device, wherein a plurality of terminals formed on a lead frame and a plurality of electrodes provided on a semiconductor chip provided on the lead frame are ultrasonically joined to a plate-like or strip-like connection conductor. Because
A source conductive portion for connecting a source terminal formed on the lead frame and a source electrode provided on the semiconductor chip, and a gate terminal formed on the lead frame and a gate electrode provided on the semiconductor chip are connected. Forming a gate conductive portion to be integrally formed through an insulating portion;
One end side of the source conductive portion in the connection conductor is in contact with the source terminal, the other end side is in contact with the source electrode, one end side of the gate conductive portion is in contact with the gate terminal, and the other end side is in contact with the gate electrode. Applying the ultrasonic vibration to the connecting conductor by pressing so that,
A method for manufacturing a semiconductor device, comprising: 前記接続導体は、接合状態において前記半導体チップの接合面から離間する方向に湾曲するアーチ部を有する導電板をベースシートに貼り付ける工程と、
それぞれ前記アーチ部を有する複数の帯状の導電部が互いに所定の間隔を開けて並列するように前記導電板を個片化する工程と、
２つの前記導電部の間を含む所定箇所に絶縁シートを貼り付ける工程と、
パターニングにより、前記アーチ部上の所定部位を残して前記絶縁シートを除去し、残された絶縁シートにより前記導電部同士が絶縁される接続導体を前記ベースシート上に複数並列して形成する工程と、
前記接続導体毎に前記ベースシートを切り分ける工程と、
を備えることを特徴とする請求項３記載の半導体装置の製造方法。 The connecting conductor is a step of attaching a conductive plate having an arch portion curved in a direction away from the bonding surface of the semiconductor chip in a bonded state to a base sheet;
A step of separating the conductive plates so that a plurality of strip-shaped conductive portions each having the arch portion are parallel to each other with a predetermined interval;
A step of attaching an insulating sheet to a predetermined portion including between the two conductive portions;
Forming a plurality of connecting conductors in parallel on the base sheet by patterning to remove the insulating sheet leaving a predetermined portion on the arch, and to insulate the conductive parts from each other by the remaining insulating sheet; ,
Cutting the base sheet for each connection conductor;
The method of manufacturing a semiconductor device according to claim 3, comprising: 前記接続導体の製造方法は、絶縁材で構成されるフレキシブル基板の主面上の所定位置に２本の導電配線を形成する工程と、
接合時に前記半導体チップの側面に近接する前記導電配線における所定の部位に、絶縁層を形成する工程と、
を備えることを特徴とする請求項３記載の半導体装置の製造方法。 The method for manufacturing the connection conductor includes a step of forming two conductive wirings at predetermined positions on a main surface of a flexible substrate made of an insulating material;
Forming an insulating layer at a predetermined site in the conductive wiring adjacent to the side surface of the semiconductor chip at the time of bonding;
The method of manufacturing a semiconductor device according to claim 3, comprising:
JP2008294673A 2008-11-18 2008-11-18 Semiconductor device, connection conductor, and method of manufacturing semiconductor device Withdrawn JP2010123680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008294673A JP2010123680A (en) 2008-11-18 2008-11-18 Semiconductor device, connection conductor, and method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008294673A JP2010123680A (en) 2008-11-18 2008-11-18 Semiconductor device, connection conductor, and method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2010123680A true JP2010123680A (en) 2010-06-03

Family

ID=42324782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008294673A Withdrawn JP2010123680A (en) 2008-11-18 2008-11-18 Semiconductor device, connection conductor, and method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2010123680A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013038359A (en) * 2011-08-11 2013-02-21 Denso Corp Semiconductor device and semiconductor device manufacturing method
JP2014090170A (en) * 2012-10-29 2014-05-15 Lsi Corp Low inductance flex bond with low thermal resistance
JP2019021827A (en) * 2017-07-20 2019-02-07 ローム株式会社 Semiconductor device
WO2022172767A1 (en) * 2021-02-12 2022-08-18 日本発條株式会社 Circuit board and manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013038359A (en) * 2011-08-11 2013-02-21 Denso Corp Semiconductor device and semiconductor device manufacturing method
JP2014090170A (en) * 2012-10-29 2014-05-15 Lsi Corp Low inductance flex bond with low thermal resistance
JP2019021827A (en) * 2017-07-20 2019-02-07 ローム株式会社 Semiconductor device
JP7017202B2 (en) 2017-07-20 2022-02-08 ローム株式会社 Semiconductor device
WO2022172767A1 (en) * 2021-02-12 2022-08-18 日本発條株式会社 Circuit board and manufacturing method
JP7375229B2 (en) 2021-02-12 2023-11-07 日本発條株式会社 Circuit board and manufacturing method

Similar Documents

Publication Publication Date Title
CN107615464B (en) Method for manufacturing power semiconductor device and power semiconductor device
JP5819052B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP5930980B2 (en) Semiconductor device and manufacturing method thereof
JPWO2020129195A1 (en) Semiconductor devices and methods for manufacturing semiconductor devices
JP2010123680A (en) Semiconductor device, connection conductor, and method of manufacturing semiconductor device
JP4159348B2 (en) Circuit device manufacturing method
JP2009267054A (en) Semiconductor device and manufacturing method thereof
JP2009194153A (en) Method of manufacturing semiconductor device and ultrasonic joining apparatus
US10115699B2 (en) Method for manufacturing wire bonding structure, wire bonding structure, and electronic device
JP2008294219A (en) Semiconductor device, and manufacturing method thereof
JP4736850B2 (en) Semiconductor device and method for joining external connection terminal and external electrode of semiconductor device
US20170288564A1 (en) Power conversion apparatus and method for manufacturing the same
JP2006237503A (en) Semiconductor device and its manufacturing process
JP6653235B2 (en) Semiconductor device manufacturing method and semiconductor device
JP4901669B2 (en) Semiconductor package and semiconductor package manufacturing method
JP2011082383A (en) Power semiconductor device, and method and apparatus for manufacturing the same
US7601560B2 (en) Method for producing an electronic circuit
JP5482536B2 (en) Semiconductor manufacturing method
JP5674537B2 (en) Electrical component module
JP2008034602A (en) Semiconductor device and manufacturing method thereof
JP6808849B2 (en) Semiconductor device
JPWO2007088631A1 (en) Circuit board connection part and circuit board connection structure
JP2009194154A (en) Ultrasonic joining apparatus and method of manufacturing semiconductor device
JP2002026540A (en) Manufacturing method of electronic component and electronic component manufactured by the manufacturing method
JP2009164239A (en) Manufacturing method of semiconductor device, and semiconductor device

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20120207