JP5482536B2 - Semiconductor manufacturing method - Google Patents
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- JP5482536B2 JP5482536B2 JP2010166322A JP2010166322A JP5482536B2 JP 5482536 B2 JP5482536 B2 JP 5482536B2 JP 2010166322 A JP2010166322 A JP 2010166322A JP 2010166322 A JP2010166322 A JP 2010166322A JP 5482536 B2 JP5482536 B2 JP 5482536B2
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Description
本発明は、インバータ等に用いられる半導体装置に関する。 The present invention relates to a semiconductor device used for an inverter or the like.
特許文献１は、基盤の上にはんだ材を塗布し、これに半導体素子を載置し、はんだ付け実装することによって、半導体素子と基盤とを接合する技術を開示している。 Patent Document 1 discloses a technique for joining a semiconductor element and a base by applying a solder material on the base, placing a semiconductor element on the base, and soldering and mounting the semiconductor element.
特許文献１に開示される方法によって基盤に接合された半導体素子の上面に、小型化、抜熱性能向上を目的として、さらに電極を接合する場合がある。この場合、上記手順と同様の手順で半導体素子の上面に電極をはんだ付け実装が行われる。 In some cases, an electrode is further bonded to the upper surface of the semiconductor element bonded to the substrate by the method disclosed in Patent Document 1 for the purpose of reducing the size and improving the heat removal performance. In this case, the electrodes are soldered and mounted on the upper surface of the semiconductor element in the same procedure as described above.
しかしながら、このような実装方法において、電極が固定されていないと、電極が動いて半導体素子に捻り応力が作用し、半導体素子が損傷する可能性がある。 However, in such a mounting method, if the electrode is not fixed, the electrode may move and a torsional stress may act on the semiconductor element, possibly damaging the semiconductor element.
本発明は、このような技術的課題に鑑みてなされたもので、半導体素子に電極を接合するにあたって、半導体素子に捻り応力が作用するのを抑え、半導体素子の損傷を防止することを目的とする。 The present invention has been made in view of such a technical problem, and an object of the present invention is to prevent the twisting stress from acting on the semiconductor element and prevent the semiconductor element from being damaged when bonding the electrode to the semiconductor element. To do.
本発明のある態様によれば、半導体装置の製造方法が、半導体素子を膜に接着・固定する工程と、前記半導体素子の少なくとも一方の面にはんだ材を塗布する工程と、前記膜に熱硬化性の接着剤を塗布する工程と、前記はんだ材及び前記接着剤の塗布位置を加熱することによって、前記接着剤を硬化させて前記膜に金属電極を接着・固定するとともに前記はんだ材を溶融させて前記半導体素子の前記少なくとも一方の面に前記金属電極を実装する工程と、を含む。 According to an aspect of the present invention, a method of manufacturing a semiconductor device includes a step of bonding and fixing a semiconductor element to a film, a step of applying a solder material to at least one surface of the semiconductor element, and thermosetting the film A step of applying a functional adhesive, and heating the solder material and the application position of the adhesive to cure the adhesive and to bond and fix the metal electrode to the film and to melt the solder material Te and a step of mounting the metal electrode on the at least one surface of the semiconductor element.
この態様によれば、半導体素子と金属電極との位置関係が膜によって規定され、かつ、金属電極が膜に固定される。これにより、金属電極が半導体素子に対して動くことによって金属電極から半導体素子に捻り応力が作用するのが抑制され、半導体素子の損傷を防止することができる。 According to this aspect, the positional relationship between the semiconductor element and the metal electrode is defined by the film, and the metal electrode is fixed to the film. Thereby, it is suppressed that a torsional stress acts on a semiconductor element from a metal electrode by moving a metal electrode with respect to a semiconductor element, and damage to a semiconductor element can be prevented.
以下、添付図面を参照しながら本発明の実施形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
第１実施形態
図１Ａ〜図１Ｃは第１実施形態に係る半導体装置の製造方法を示している。半導体装置は、半導体素子としてＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）１１とダイオード１２とを含み、図１Ａ〜図１Ｃに示される工程（ａ）〜（ｅ）を経て製造される。各図の左側の図は半導体装置を上面側から見た図、右側の図は対応する左側の図のＸ−Ｘ断面を示した図である。これらを参照しながら、以下、各工程について説明する。
First Embodiment FIGS. 1A to 1C show a method of manufacturing a semiconductor device according to a first embodiment. The semiconductor device includes an IGBT (insulated gate bipolar transistor) 11 and a diode 12 as semiconductor elements, and is manufactured through steps (a) to (e) shown in FIGS. 1A to 1C. The left-hand side of each figure is a view of the semiconductor device as viewed from the upper surface side, and the right-hand side view is a cross-sectional view taken along the line XX of the corresponding left-side view. Hereinafter, each process will be described with reference to these.
まず、工程（ａ）では、フィルム状膜２０が用意される。フィルム状膜２０は、セラミックス板又は金属板、若しくは、膜内部にセラミックス板又は金属板を含んだ膜である。フィルム状膜２０には、ＩＧＢＴ１１、ダイオード１２よりも僅かに大きな矩形の開口３１、３２が形成される。また、フィルム状膜２０の上面には、配線パターンが配置される配線パターン領域４０が形成される。 First, in the step (a), a film-like film 20 is prepared. The film-like film 20 is a ceramic plate or a metal plate, or a film containing a ceramic plate or a metal plate inside the film. The film-like film 20 is formed with rectangular openings 31 and 32 that are slightly larger than the IGBT 11 and the diode 12. In addition, a wiring pattern region 40 in which a wiring pattern is arranged is formed on the upper surface of the film-like film 20.
開口３１内にはＩＧＢＴ１１が配置され、開口３２内にはダイオード１２が配置される。ＩＧＢＴ１１及びダイオード１２の上面にはそれぞれ、主電極及び制御端子電極を含む金属薄膜電極が形成される。フィルム状膜２０の厚さは、ＩＧＢＴ１１及びダイオード１２の金属薄膜電極を含んだ厚さと略同じである。 The IGBT 11 is disposed in the opening 31, and the diode 12 is disposed in the opening 32. Metal thin film electrodes including a main electrode and a control terminal electrode are formed on the upper surfaces of the IGBT 11 and the diode 12, respectively. The thickness of the film-like film 20 is substantially the same as the thickness including the metal thin film electrodes of the IGBT 11 and the diode 12.
工程（ｂ）では、フィルム状膜２０とＩＧＢＴ１１との間の隙間、及び、フィルム状膜２０とダイオード１２との間の隙間に、それぞれ絶縁材５０が充填される。これにより、ＩＧＢＴ１１及びダイオード１２がフィルム状膜２０に接着・固定される。 In the step (b), the gap between the film-like film 20 and the IGBT 11 and the gap between the film-like film 20 and the diode 12 are filled with the insulating material 50, respectively. As a result, the IGBT 11 and the diode 12 are bonded and fixed to the film-like film 20.
工程（ｃ）では、ＩＧＢＴ１１及びダイオード１２の上面にはんだ材７１が塗布され、フィルム状膜２０の上面に熱硬化性の接着剤７２が塗布される。そして、ＩＧＢＴ１１及びダイオード１２の上面に上側金属電極８１が載置される。上側金属電極８１は一部に切欠き８１ｃを有しており、切欠き８１ｃからは、配線パターン領域４０とＩＧＢＴ１１の一部とが露出する。 In the step (c), the solder material 71 is applied to the upper surfaces of the IGBT 11 and the diode 12, and the thermosetting adhesive 72 is applied to the upper surface of the film-like film 20. Then, the upper metal electrode 81 is placed on the upper surfaces of the IGBT 11 and the diode 12. The upper metal electrode 81 has a notch 81c in part, and the wiring pattern region 40 and a part of the IGBT 11 are exposed from the notch 81c.
この状態ではんだ材７１及び接着剤７２の塗布位置を加熱すると、接着剤７２が硬化して上側金属電極８１がフィルム状膜２０に接着・固定されると同時に、はんだ材７１が溶融して上側金属電極８１がＩＧＢＴ１１及びダイオード１２に実装される。このとき、上側金属電極８１はフィルム状膜２０の上に載置されているので、上側金属電極８１の自重によってはんだ材７１が潰れることはない。 When the application position of the solder material 71 and the adhesive 72 is heated in this state, the adhesive 72 is cured and the upper metal electrode 81 is bonded and fixed to the film-like film 20, and at the same time, the solder material 71 is melted and the upper side is melted. A metal electrode 81 is mounted on the IGBT 11 and the diode 12. At this time, since the upper metal electrode 81 is placed on the film-like film 20, the solder material 71 is not crushed by the weight of the upper metal electrode 81.
同様にして、フィルム状膜２０への下側金属電極８２の接着・固定、及び、ＩＧＢＴ１１及びダイオード１２への下側金属電極８２の実装が行われる。 Similarly, the lower metal electrode 82 is bonded and fixed to the film-like film 20, and the lower metal electrode 82 is mounted on the IGBT 11 and the diode 12.
工程（ｄ）では、ＩＧＢＴ１１の上面に配置される制御端子電極がワイヤ６０（信号線）によって配線パターン領域４０内の配線パターンと電気的に接続される。ワイヤ６０は上側金属電極８１の上面よりもフィルム状膜２０側、かつ、切欠き８１ｃ内（上側金属電極８１の側方空間内）に配置される。
工程（ｅ）では、上側金属電極８１及び下側金属電極８２にそれぞれ絶縁材７３を介してヒートシンク９０が取り付けられる。
In the step (d), the control terminal electrode disposed on the upper surface of the IGBT 11 is electrically connected to the wiring pattern in the wiring pattern region 40 by the wire 60 (signal line). The wire 60 is arranged on the film-like film 20 side of the upper surface of the upper metal electrode 81 and in the notch 81c (in the side space of the upper metal electrode 81).
In the step (e), the heat sink 90 is attached to the upper metal electrode 81 and the lower metal electrode 82 via the insulating material 73, respectively.
図１Ｄは、以上の工程（ａ）〜（ｅ）を経て製造される半導体装置の回路図である。半導体装置においては、ＩＧＢＴ１１とダイオード１２が逆並列接続され、電動機の制御に用いられるインバータ回路のスイッチの一つを構成する。 FIG. 1D is a circuit diagram of a semiconductor device manufactured through the above steps (a) to (e). In the semiconductor device, the IGBT 11 and the diode 12 are connected in reverse parallel to constitute one of the switches of the inverter circuit used for controlling the electric motor.
続いて、第１実施形態の作用効果について説明する。 Then, the effect of 1st Embodiment is demonstrated.
上記製造方法によれば、ＩＧＢＴ１１及びダイオード１２と金属電極８１、８２との位置関係がフィルム状膜２０によって規定され、かつ、金属電極８１、８２がフィルム状膜２０に固定される。これにより、金属電極８１、８２がＩＧＢＴ１１及びダイオード１２に対して動くことによってＩＧＢＴ１１及びダイオード１２に捻り応力が作用するのが抑制され、ＩＧＢＴ１１及びダイオード１２の損傷を防止することができる。 According to the manufacturing method, the positional relationship between the IGBT 11 and the diode 12 and the metal electrodes 81 and 82 is defined by the film-like film 20, and the metal electrodes 81 and 82 are fixed to the film-like film 20. Thereby, it is suppressed that the torsional stress acts on IGBT11 and the diode 12 by the metal electrodes 81 and 82 moving with respect to IGBT11 and the diode 12, and damage to IGBT11 and the diode 12 can be prevented.
仮に、金属電極８１、８２からＩＧＢＴ１１及びダイオード１２に捻り応力が作用したとしても、フィルム状膜２０が撓み変形するので、かかる捻り応力は吸収され、ＩＧＢＴ１１及びダイオード１２の損傷に至ることはない。 Even if a torsional stress acts on the IGBT 11 and the diode 12 from the metal electrodes 81 and 82, the film-like film 20 is bent and deformed, so that the torsional stress is absorbed and the IGBT 11 and the diode 12 are not damaged.
さらに、金属電極８１、８２に両者を近接するような力が作用しても、フィルム状膜２０が間に配置されており、かつ、金属電極８１、８２がフィルム状膜２０に固定されているので、金属電極８１、８２が接触して短絡することもない。 Furthermore, even if a force that causes both of them to approach the metal electrodes 81 and 82 acts, the film-like film 20 is disposed between them, and the metal electrodes 81 and 82 are fixed to the film-like film 20. Therefore, the metal electrodes 81 and 82 do not contact and short-circuit.
また、開口３１、３２を利用してＩＧＢＴ１１及びダイオード１２を配置することにより、ＩＧＢＴ１１及びダイオード１２が面方向に位置決めされるので、ＩＧＢＴ１１及びダイオード１２への金属電極８１、８２の実装が容易になる。 Further, by arranging the IGBT 11 and the diode 12 using the openings 31 and 32, the IGBT 11 and the diode 12 are positioned in the surface direction, so that the metal electrodes 81 and 82 can be easily mounted on the IGBT 11 and the diode 12. .
上記製造方法は、ＩＧＢＴ１１及びダイオード１２を並列接続する場合に限らず、電気的な容量を増やすために半導体素子の並列数を増やす場合、インバータ回路において多相化する場合等、複数の半導体素子に電極を実装する必要がある場合に有効である。 The above manufacturing method is not limited to the case where the IGBT 11 and the diode 12 are connected in parallel, but when the number of parallel semiconductor elements is increased in order to increase the electric capacity, the case where the inverter circuit is multiphased, etc. This is effective when it is necessary to mount electrodes.
ＩＧＢＴ１１及びダイオード１２の一方の高さが他方よりも低い場合は、低い方の上面にスペーサを載置して高さを揃える必要がある。上記製造方法によれば、フィルム状膜２０によってこのようなスペーサの移動も制限されるので、スペーサの位置ずれも防止することができる。なお、スペーサを用いることにより、フィルム状膜２０への金属電極８１、８２の接着位置とＩＧＢＴ１１及びダイオード１２への金属電極８１、８２の実装位置とで高さに差がなくなり、接着と実装を同時に行うのが容易になる。スペーサは載置される半導体素子に絶縁性の接着剤で固定するようにしてもよい。 When the height of one of the IGBT 11 and the diode 12 is lower than that of the other, it is necessary to place a spacer on the lower upper surface so as to align the height. According to the manufacturing method described above, since the movement of the spacer is restricted by the film-like film 20, the displacement of the spacer can also be prevented. In addition, by using the spacer, there is no difference in height between the bonding position of the metal electrodes 81 and 82 to the film-like film 20 and the mounting position of the metal electrodes 81 and 82 to the IGBT 11 and the diode 12. Easy to do at the same time. The spacer may be fixed to the semiconductor element to be placed with an insulating adhesive.
また、金属電極８１、８２の間にフィルム状膜２０を介在させ、かつ、フィルム状膜２０とＩＧＢＴ１１及びダイオード１２との間の隙間に絶縁材５０を充填しているので、仮に実装時にはんだ材７１が流れ落ちたとしても、はんだ材７１が原因となって短絡が起きることはない。 In addition, since the film-like film 20 is interposed between the metal electrodes 81 and 82 and the insulating material 50 is filled in the gap between the film-like film 20 and the IGBT 11 and the diode 12, it is assumed that the solder material is used at the time of mounting. Even if 71 flows down, a short circuit does not occur due to the solder material 71.
なお、半導体装置の薄型化を図る場合であっても、ＩＧＢＴ１１及びダイオード１２とフィルム状膜２０との間の隙間への絶縁材５０の充填は、当該部位を露出させた状態で行われるので簡単に行うことができる。 Even when the thickness of the semiconductor device is reduced, the filling of the insulating material 50 into the gaps between the IGBT 11 and the diode 12 and the film-like film 20 is performed in a state where the portions are exposed. Can be done.
また、フィルム状膜２０として、セラミックス板又は金属板、若しくは、膜内部にセラミックス板又は金属板を含んだ膜を用いたことにより、フィルム状膜２０の熱伝導率が高くなり、ＩＧＢＴ１１及びダイオード１２の放熱性を向上させることができる。 In addition, by using a ceramic plate or a metal plate or a film containing a ceramic plate or a metal plate inside the film as the film-like film 20, the thermal conductivity of the film-like film 20 is increased, and the IGBT 11 and the diode 12 The heat dissipation can be improved.
また、ＩＧＢＴ１１及びダイオード１２に実装される金属電極８１、８２がＩＧＢＴ１１及びダイオード１２の熱を逃がすヒートスプレッダとしても機能する。したがって、金属電極８１、８２に絶縁材７３を介してヒートシンク９０を取り付けることによって、ＩＧＢＴ１１及びダイオード１２からの放熱をより一層促進することができる。 Further, the metal electrodes 81 and 82 mounted on the IGBT 11 and the diode 12 also function as a heat spreader that releases the heat of the IGBT 11 and the diode 12. Therefore, the heat radiation from the IGBT 11 and the diode 12 can be further promoted by attaching the heat sink 90 to the metal electrodes 81 and 82 via the insulating material 73.
また、ワイヤ６０を金属電極８１、８２の上面よりもフィルム状膜２０側、かつ、切欠き８１ｃ内に配置したことにより、ヒートシンク９０との干渉が避けられ、また、ワイヤ６０を配置するための空間をわざわざ設ける必要がなくなるので、半導体装置を小型化することができる。 Further, since the wire 60 is arranged on the film-like film 20 side of the upper surfaces of the metal electrodes 81 and 82 and in the notch 81c, interference with the heat sink 90 can be avoided, and the wire 60 can be arranged. Since it is not necessary to provide a space, the size of the semiconductor device can be reduced.
なお、変形例として、上記製造方法では、上側金属電極８１をＩＧＢＴ１１及びダイオード１２に実装した後に、下側金属電極８２をＩＧＢＴ１１及びダイオード１２に実装しているが、金属電極８１、８２を一括して実装するようにしてもよい。これにより、工程数を削減することができる。 As a modification, in the manufacturing method described above, the upper metal electrode 81 is mounted on the IGBT 11 and the diode 12 and then the lower metal electrode 82 is mounted on the IGBT 11 and the diode 12. However, the metal electrodes 81 and 82 are bundled together. May be implemented. Thereby, the number of processes can be reduced.
また、フィルム状膜２０への上側金属電極８１の接着・固定とＩＧＢＴ１１及びダイオード１２への上側金属電極８１の実装を同時に行っているが、フィルム状膜２０への上側金属電極８１の接着・固定をＩＧＢＴ１１及びダイオード１２への上側金属電極８１の実装よりも先に行うようにしてもよい。 In addition, the upper metal electrode 81 is bonded and fixed to the film-like film 20 and the upper metal electrode 81 is mounted to the IGBT 11 and the diode 12 at the same time, but the upper metal electrode 81 is bonded and fixed to the film-like film 20. May be performed before the upper metal electrode 81 is mounted on the IGBT 11 and the diode 12.
また、ＩＧＢＴ１１及びダイオード１２への金属電極８１、８２の実装にはんだ材を用いているが、他の導電性材料、例えば、銀ペーストを用いるようにしてもよい。 Moreover, although the solder material is used for mounting the metal electrodes 81 and 82 on the IGBT 11 and the diode 12, other conductive materials such as silver paste may be used.
また、ＩＧＢＴ１１及びダイオード１２への金属電極８１、８２の実装を、超音波接合又は摩擦攪拌接合によって行ってもよい。この場合、金属電極８１、８２をフィルム状膜に予め接着・固定しておき、この状態で超音波又は摩擦を金属電極８１、８２に印可する。金属電極８１、８２のＩＧＢＴ１１及びダイオード１２に接触する部分がＩＧＢＴ１１及びダイオード１２に対して僅かに変位する必要があるが、かかる変位はフィルム状膜２０が撓むことで実現することができる。 Further, the metal electrodes 81 and 82 may be mounted on the IGBT 11 and the diode 12 by ultrasonic bonding or friction stir welding. In this case, the metal electrodes 81 and 82 are bonded and fixed in advance to the film-like film, and ultrasonic waves or friction is applied to the metal electrodes 81 and 82 in this state. The portions of the metal electrodes 81 and 82 that are in contact with the IGBT 11 and the diode 12 need to be slightly displaced with respect to the IGBT 11 and the diode 12, but such displacement can be realized by bending the film-like film 20.
第２実施形態
続いて、本発明の第２実施形態について説明する。
Second Embodiment Subsequently, a second embodiment of the present invention will be described.
図２Ａ〜図２Ｃは第２実施形態に係る半導体装置の製造方法を示している。半導体装置は、半導体素子としてＩＧＢＴ１１ａ、１１ｂとダイオード１２ａ、１２ｂとを含み、図２Ａ〜図２Ｃに示される工程（ａ）〜（ｅ）を経て製造される。各図の左側の図は半導体装置を上面側から見た図、右側の図は対応する左側の図のＸ−Ｘ断面及びＹ−Ｙ断面を示した図である。これらを参照しながら、以下、各工程について第１実施形態との相違点を中心に説明する。 2A to 2C show a method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device includes IGBTs 11a and 11b and diodes 12a and 12b as semiconductor elements, and is manufactured through steps (a) to (e) shown in FIGS. 2A to 2C. The left side of each figure is a view of the semiconductor device as viewed from the upper surface side, and the right side figure is a view showing the XX cross section and the YY cross section of the corresponding left side figure. Hereinafter, each process will be described with a focus on differences from the first embodiment.
工程（ａ）では、フィルム状膜２０が用意される。フィルム状膜２０には、半導体素子１１ａ〜１２ｂよりも僅かに大きな矩形の開口３１〜３４が形成される。なお、以下の説明では、適宜、ＩＧＢＴ１１ａ及びダイオード１２ａの全体を「半導体素子群１０ａ」、ＩＧＢＴ１１ｂ及びダイオード１２ｂの全体を「半導体素子群１０ｂ」と称する。また、フィルム状膜２０の上面には配線パターン領域４０ａが形成され、下面には配線パターン領域４０ｂが形成される。 In the step (a), a film-like film 20 is prepared. In the film-like film 20, rectangular openings 31 to 34 that are slightly larger than the semiconductor elements 11a to 12b are formed. In the following description, the entire IGBT 11a and the diode 12a are appropriately referred to as “semiconductor element group 10a”, and the entire IGBT 11b and the diode 12b are referred to as “semiconductor element group 10b”. In addition, a wiring pattern region 40a is formed on the upper surface of the film-like film 20, and a wiring pattern region 40b is formed on the lower surface.
開口３１、３２にはそれぞれ、ＩＧＢＴ１１ａ、ダイオード１２ａが配置され、開口３３、３４にはそれぞれ、ＩＧＢＴ１１ｂ、ダイオード１２ｂが配置される。ＩＧＢＴ１１ａ、ダイオード１２ａは上面がフィルム状膜２０の上面側に露出するように、逆に、ＩＧＢＴ１１ｂ、ダイオード１２ｂは上面がフィルム状膜２０の下面側に露出するようにそれぞれ配置される。 An IGBT 11a and a diode 12a are disposed in the openings 31 and 32, respectively, and an IGBT 11b and a diode 12b are disposed in the openings 33 and 34, respectively. The IGBT 11a and the diode 12a are arranged so that the upper surface is exposed on the upper surface side of the film-like film 20, and conversely, the IGBT 11b and the diode 12b are respectively arranged so that the upper surface is exposed on the lower surface side of the film-like film 20.
工程（ｂ）では、フィルム状膜２０と半導体素子１１ａ〜１２ｂとの間の隙間に絶縁材５０が充填される。これにより、半導体素子１１ａ〜１２ｂがフィルム状膜２０に接着・固定される。 In the step (b), the insulating material 50 is filled in the gap between the film-like film 20 and the semiconductor elements 11a to 12b. Thereby, the semiconductor elements 11 a to 12 b are bonded and fixed to the film-like film 20.
工程（ｃ）では、半導体素子群１０ａの上面、半導体素子群１０ｂの下面にはんだ材７１が塗布され、フィルム状膜２０の上面に熱硬化性の接着剤７２が塗布される。そして、半導体素子群１０ａの上面に低電位電極１０１が載置され、半導体素子群１０ｂの下面に高電位電極１０２が載置される。電極１０１、１０２は、それぞれ一部に切欠き１０１ｃ、１０２ｃを有しており、切欠き１０１ｃ、１０２ｃからは、配線パターン領域４０ａ、４０ｂとＩＧＢＴ１１ａ、１１ｂの一部とが露出する。 In the step (c), the solder material 71 is applied to the upper surface of the semiconductor element group 10 a and the lower surface of the semiconductor element group 10 b, and the thermosetting adhesive 72 is applied to the upper surface of the film-like film 20. The low potential electrode 101 is placed on the upper surface of the semiconductor element group 10a, and the high potential electrode 102 is placed on the lower surface of the semiconductor element group 10b. The electrodes 101 and 102 have notches 101c and 102c, respectively, and the wiring pattern regions 40a and 40b and parts of the IGBTs 11a and 11b are exposed from the notches 101c and 102c.
この状態ではんだ材７１及び接着剤７２の塗布位置を加熱すると、接着剤７２が硬化して電極１０１、１０２がフィルム状膜２０に接着・固定される。これと同時に、はんだ材７１が溶融して低電位電極１０１がＩＧＢＴ１１ａ及びダイオード１２ａに実装されるとともに、高電位電極１０２がＩＧＢＴ１１ｂ及びダイオード１２ｂに実装される。このとき、電極１０１、１０２はフィルム状膜２０の上に載置されているので、電極１０１、１０２の自重によりはんだ材７１が潰れることはない。 When the application position of the solder material 71 and the adhesive 72 is heated in this state, the adhesive 72 is cured and the electrodes 101 and 102 are bonded and fixed to the film film 20. At the same time, the solder material 71 is melted and the low potential electrode 101 is mounted on the IGBT 11a and the diode 12a, and the high potential electrode 102 is mounted on the IGBT 11b and the diode 12b. At this time, since the electrodes 101 and 102 are placed on the film-like film 20, the solder material 71 is not crushed by the weight of the electrodes 101 and 102.
同様にして、フィルム状膜２０と交流電極１０３との接着、及び、半導体素子１１ａ〜１２ｂへの交流電極１０３の実装が行われる。交流電極１０３は、半導体素子群１０ａの下面から半導体素子群１０ｂの上面まで延びる平板部位を有する電極である。 Similarly, adhesion between the film-like film 20 and the AC electrode 103 and mounting of the AC electrode 103 on the semiconductor elements 11a to 12b are performed. The AC electrode 103 is an electrode having a flat plate portion extending from the lower surface of the semiconductor element group 10a to the upper surface of the semiconductor element group 10b.
工程（ｄ）では、ＩＧＢＴ１１ａの上面に配置される制御端子電極がワイヤ６０（信号線）によって配線パターン領域４０ａ内の配線パターンと電気的に接続される。同様に、ＩＧＢＴ１１ｂの上面に配置される制御端子電極がワイヤ６０（信号線）によって配線パターン領域４０ｂ内の配線パターンと電気的に接続される。 In the step (d), the control terminal electrode disposed on the upper surface of the IGBT 11a is electrically connected to the wiring pattern in the wiring pattern region 40a by the wire 60 (signal line). Similarly, the control terminal electrode arranged on the upper surface of the IGBT 11b is electrically connected to the wiring pattern in the wiring pattern region 40b by the wire 60 (signal line).
ワイヤ６０は低電位電極１０１の上面、高電位電極１０２の上面よりもフィルム状膜２０側、かつ、切欠き１０１ｃ、１０２ｃ内（電極１０１、１０２の側方空間内）に配置される。 The wire 60 is disposed on the upper surface of the low potential electrode 101 and the upper surface of the high potential electrode 102 on the film-like film 20 side and in the notches 101c and 102c (in the lateral space of the electrodes 101 and 102).
工程（ｅ）では、電極１０１、１０２に絶縁材７３を介してヒートシンク９０ａが取り付けられ、交流電極１０３に絶縁材７３を介してヒートシンク９０ｂが取り付けられる。 In the step (e), the heat sink 90 a is attached to the electrodes 101 and 102 via the insulating material 73, and the heat sink 90 b is attached to the AC electrode 103 via the insulating material 73.
図２Ｄは、以上の工程（ａ）〜（ｅ）を経て製造される半導体装置の回路図である。半導体装置においては、ＩＧＢＴ１１ａとダイオード１２ａが逆並列接続されて半導体素子群１０ａを構成し、ＩＧＢＴ１１ｂ及びダイオード１２ｂが逆並列接続されて半導体素子群１０ｂを構成する。さらに、半導体素子群１０ａ、１０ｂは、直列に接続され、インバータ回路の電気的１相分の回路を構成する。 FIG. 2D is a circuit diagram of a semiconductor device manufactured through the above steps (a) to (e). In the semiconductor device, the IGBT 11a and the diode 12a are connected in reverse parallel to form the semiconductor element group 10a, and the IGBT 11b and the diode 12b are connected in reverse parallel to form the semiconductor element group 10b. Furthermore, the semiconductor element groups 10a and 10b are connected in series to constitute a circuit for one electrical phase of the inverter circuit.
続いて、第２実施形態の作用効果について説明する。 Then, the effect of 2nd Embodiment is demonstrated.
通常、複数の半導体素子は上下同じ向きで配置され、これらを直列に接続する場合、屈曲した電極を用いて接続する必要が生じる。例えば、ある２つの半導体素子を直列接続する場合、一方の下面と他方の上面とを接続するクランク形状の電極が必要である。 Usually, a plurality of semiconductor elements are arranged in the same direction up and down, and when they are connected in series, it is necessary to connect them using bent electrodes. For example, when two semiconductor elements are connected in series, a crank-shaped electrode that connects one lower surface and the other upper surface is necessary.
しかしながら、屈曲した電極の使用は、配置スペースの増大、製造コストの増大の原因となり、また、半導体素子の周囲に絶縁材を充填する場合、この屈曲した電極が障害となって絶縁材が十分に充填しきれないという問題が生じる可能性がある。 However, the use of a bent electrode causes an increase in arrangement space and an increase in manufacturing cost. Also, when an insulating material is filled around a semiconductor element, the bent electrode becomes an obstacle and the insulating material is not sufficient. There may be a problem that it cannot be filled.
これに対し、上記製造方法によれば、半導体素子群１０ａ、１０ｂを上下逆に配置、固定することができ、これによって、単純に横方向に延びる交流電極１０３を用いて両半導体素子群１０ａ、１０ｂを接続することができる。これにより、交流電極１０３を配置するスペースが縮小されるので、半導体装置の設置スペースが低減され、ひいては当該装置が搭載されるインバータを小型化することができる。また、上記屈曲した電極に起因する絶縁材の充填不良の問題も生じることがない。 On the other hand, according to the manufacturing method described above, the semiconductor element groups 10a and 10b can be arranged and fixed upside down, whereby both the semiconductor element groups 10a, 10b can be connected. Thereby, since the space for arranging the AC electrode 103 is reduced, the installation space for the semiconductor device is reduced, and the inverter on which the device is mounted can be downsized. Further, the problem of poor filling of the insulating material due to the bent electrode does not occur.
その他の作用効果は、第１実施形態の効果と同様である。 Other functions and effects are the same as those of the first embodiment.
第３実施形態
続いて、本発明の第３実施形態について説明する。第３実施形態は第２実施形態の一部変形例である。
Third Embodiment Subsequently, a third embodiment of the present invention will be described. The third embodiment is a partial modification of the second embodiment.
第３実施形態に係る半導体装置の製造方法では、第２実施形態と同じ工程（ａ）〜（ｅ）を経て、上下逆に配置された半導体素子群１０ａ、１０ｂに電極１０１、１０２及び交流電極１０３ａ、１０３ｂが実装される。 In the method for manufacturing a semiconductor device according to the third embodiment, the same steps (a) to (e) as in the second embodiment are performed, and the semiconductor elements 10a and 10b arranged upside down are connected to the electrodes 101 and 102 and the AC electrode. 103a and 103b are mounted.
第２実施形態との相違点は、半導体素子群１０ａ、１０ｂそれぞれに独立した交流電極１０３ａ、１０３ｂが実装されている点と、実装後、半導体素子群１０ａと半導体素子群１０ｂとの間の部位（フィルム状膜２０又は絶縁材の一部）で装置が直角に折り曲げられている点である。また、独立した交流電極１０３ａ、１０３ｂは、実装後、中間電極１０３ｃによって互いに接続される。回路図は図２Ｄに示したものと同じである。 The difference from the second embodiment is that independent AC electrodes 103a and 103b are mounted on the semiconductor element groups 10a and 10b, respectively, and a portion between the semiconductor element group 10a and the semiconductor element group 10b after mounting. The point is that the device is bent at a right angle (a part of the film-like film 20 or the insulating material). The independent AC electrodes 103a and 103b are connected to each other by the intermediate electrode 103c after mounting. The circuit diagram is the same as shown in FIG. 2D.
続いて、第３実施形態の作用効果について説明する。 Then, the effect of 3rd Embodiment is demonstrated.
第３実施形態によれば、半導体素子群１０ａが半導体素子群１０ｂに対して直角な方向に配置されるので、半導体素子群１０ａと半導体素子群１０ｂとを、これらが収容される筐体の隅部壁面（例えば、底面と側面）に配置することができる。これにより、半導体装置の設置スペースを低減し、ひいては当該装置が搭載されるインバータを小型化することができる。 According to the third embodiment, since the semiconductor element group 10a is arranged in a direction perpendicular to the semiconductor element group 10b, the semiconductor element group 10a and the semiconductor element group 10b are arranged at the corners of the housing in which they are accommodated. It can arrange | position to a part wall surface (for example, a bottom face and a side surface). As a result, the installation space of the semiconductor device can be reduced, and the inverter on which the device is mounted can be downsized.
交流電極１０３ａ、１０３ｂへの中間電極１０３ｃの接続は、装置を筐体内に配置した後に行ってもよい。中間電極１０３ｃを接続する前は搭載場所の形状に合わせて装置全体を自由に屈曲させることができるので、装置のレイアウト自由度が向上する。なお、装置を筐体内に配置した後に中間電極１０３ｃを接続することに格別な困難性はない。 The connection of the intermediate electrode 103c to the AC electrodes 103a and 103b may be performed after the device is arranged in the housing. Before the intermediate electrode 103c is connected, the entire apparatus can be freely bent according to the shape of the mounting place, so that the degree of layout freedom of the apparatus is improved. Note that there is no particular difficulty in connecting the intermediate electrode 103c after the device is arranged in the housing.
その他の作用効果は、第１及び第２実施形態の効果と同様である。 Other functions and effects are the same as those of the first and second embodiments.
第４実施形態
続いて第４実施形態について説明する。第４実施形態は、第１〜第３実施形態の一部変形例であり、半導体素子を膜に固定する方法が第１〜第３実施形態と異なる。
Fourth Embodiment Next, a fourth embodiment will be described. The fourth embodiment is a partial modification of the first to third embodiments, and the method for fixing the semiconductor element to the film is different from the first to third embodiments.
ここでは、第２実施形態と同様に、半導体素子群１０ａ、１０ｂを膜に固定する場合を例に挙げて説明する。 Here, as in the second embodiment, the case where the semiconductor element groups 10a and 10b are fixed to a film will be described as an example.
第４実施形態では、まず、半導体素子群１０ａ、１０ｂが平板上に載置され、熱可塑性樹脂が塗布される。塗布範囲は、半導体素子群１０ａ、１０ｂを含み、半導体素子群１０ａ、１０ｂよりも広い範囲（フィルム状膜２０及び絶縁材５０に対応する範囲）である。熱可塑性樹脂の塗布には印刷技術が利用される。その後、半導体素子群１０ａ、１０ｂの表面（上面及び下面）に付着している不要な樹脂材がエッチングにより除去される。 In the fourth embodiment, first, the semiconductor element groups 10a and 10b are placed on a flat plate, and a thermoplastic resin is applied thereto. The application range includes the semiconductor element groups 10a and 10b and is wider than the semiconductor element groups 10a and 10b (a range corresponding to the film-like film 20 and the insulating material 50). Printing technology is used to apply the thermoplastic resin. Thereafter, unnecessary resin materials adhering to the surfaces (upper and lower surfaces) of the semiconductor element groups 10a and 10b are removed by etching.
これにより、図４に示すように、フィルム状膜２０、及び、フィルム状膜２０と半導体素子との間に充填される絶縁材に対応する樹脂膜２１が形成され、樹脂膜２１に半導体素子群１０ａ、１０ｂが接着・固定される。 As a result, as shown in FIG. 4, a film-like film 20 and a resin film 21 corresponding to an insulating material filled between the film-like film 20 and the semiconductor element are formed, and a semiconductor element group is formed on the resin film 21. 10a and 10b are bonded and fixed.
なお、ここではエッチングにより不要な樹脂材を除去しているが、これに代えて、熱可塑性樹脂を塗布する前に半導体素子群１０ａ、１０ｂの表面をマスクし、これらの部位に樹脂材が塗布されないようにしてもよい。 Here, unnecessary resin material is removed by etching, but instead, the surfaces of the semiconductor element groups 10a and 10b are masked before applying the thermoplastic resin, and the resin material is applied to these portions. It may not be done.
その後の電極の実装工程は第１〜第３実施形態と同じである。 The subsequent electrode mounting process is the same as in the first to third embodiments.
続いて、第４実施形態の作用効果について説明する。 Then, the effect of 4th Embodiment is demonstrated.
第４実施形態によれば、第１〜第３実施形態と比較して、半導体素子を容易に樹脂膜２１に接着・固定することができ、製造コストを低減することができる。また、半導体素子の主電極及び制御端子電極の周辺部のように、電気特性確保のために電極やはんだ材７１などを接触させたくない部分を樹脂材で被覆することもできる。 According to the fourth embodiment, the semiconductor element can be easily bonded and fixed to the resin film 21 as compared with the first to third embodiments, and the manufacturing cost can be reduced. In addition, a portion that does not want to be brought into contact with the electrode, the solder material 71, or the like can be covered with a resin material in order to ensure electrical characteristics, such as the peripheral portion of the main electrode and the control terminal electrode of the semiconductor element.
また、開口３１〜３４を有するフィルム状膜２０を予め用意する必要がないので、材料費、製造コストともに低減することができる。 Moreover, since it is not necessary to prepare the film-like film | membrane 20 which has the openings 31-34 beforehand, both material cost and manufacturing cost can be reduced.
また、電極１０１〜１０３を実装する時の熱により樹脂膜２１が潰れ変形するので、半導体素子１１ａ〜１２ｂの厚さが不均一な場合や電極１０１〜１０３に若干の反りがある場合に、これらを吸収することができる。これにより、実装前に厚さの不均一をスペーサで調整することや、電極１０１〜１０３の反りを修正することが不要になり、製造コストを低減することができる。 In addition, since the resin film 21 is crushed and deformed by heat when mounting the electrodes 101 to 103, when the thickness of the semiconductor elements 11a to 12b is not uniform or the electrodes 101 to 103 are slightly warped, Can be absorbed. Thereby, it becomes unnecessary to adjust the thickness non-uniformity with the spacer before mounting and to correct the warp of the electrodes 101 to 103, and the manufacturing cost can be reduced.
その他の作用効果は、第１〜第３実施形態の効果と同様である。 Other functions and effects are the same as those of the first to third embodiments.
以上、本発明の実施形態について説明したが、上記実施形態は本発明の適用例を示したに過ぎず、本発明の技術的範囲を上記実施形態の具体的構成に限定する趣旨ではない。本発明の趣旨を逸脱しない範囲で種々の変更が可能である。 The embodiment of the present invention has been described above, but the above embodiment is merely an example of application of the present invention, and the technical scope of the present invention is not intended to be limited to the specific configuration of the above embodiment. Various modifications can be made without departing from the spirit of the present invention.
例えば、上記実施形態はいずれも半導体素子の表面に金属電極単体を実装しているが、実装される金属電極は基盤上に配置されている金属電極であってもよい。 For example, in all of the above embodiments, the metal electrode alone is mounted on the surface of the semiconductor element, but the metal electrode to be mounted may be a metal electrode arranged on the substrate.
１１、１１ａ、１１ｂ ＩＧＢＴ（半導体素子）
１２、１２ａ、１２ｂ ダイオード（半導体素子）
２０ フィルム状膜（膜）
２１ 樹脂膜（膜）
４０、４０ａ、４０ｂ 配線パターン領域
５０ 絶縁材
８１ 上側金属電極（金属電極）
８２ 下側金属電極（金属電極）
１０１ 低電位電極（第１金属電極）
１０２ 高電位電極（第２金属電極）
１０３、１０３ａ、１０３ｂ 交流電極（第３金属電極）
11, 11a, 11b IGBT (semiconductor element)
12, 12a, 12b Diode (semiconductor element)
20 Film-like membrane (membrane)
21 Resin film (film)
40, 40a, 40b Wiring pattern region 50 Insulating material 81 Upper metal electrode (metal electrode)
82 Lower metal electrode (metal electrode)
101 Low potential electrode (first metal electrode)
102 High potential electrode (second metal electrode)
103, 103a, 103b AC electrode (third metal electrode)
Claims (6)
半導体素子を膜に接着・固定する工程と、
前記半導体素子の少なくとも一方の面にはんだ材を塗布する工程と、
前記膜に熱硬化性の接着剤を塗布する工程と、
前記はんだ材及び前記接着剤の塗布位置を加熱することによって、前記接着剤を硬化させて前記膜に金属電極を接着・固定するとともに前記はんだ材を溶融させて前記半導体素子の前記少なくとも一方の面に前記金属電極を実装する工程と、
を含むことを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising:
Bonding and fixing the semiconductor element to the film;
Applying a solder material to at least one surface of the semiconductor element;
Applying a thermosetting adhesive to the film;
By heating the coating position of the solder material and said adhesive, said at least one surface of the semiconductor device by melting the solder material with the adhesive is cured to bond and fix the metal electrode on the film Mounting the metal electrode on
A method for manufacturing a semiconductor device, comprising:
前記半導体素子を前記膜に接着・固定する工程が、
前記半導体素子に対応する開口を有するフィルム状膜を用意する工程と、
前記開口内に前記半導体素子を配置する工程と、
前記フィルム状膜と前記半導体素子との間に絶縁材を充填する工程と、
を含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
The step of bonding and fixing the semiconductor element to the film includes
Preparing a film-like film having an opening corresponding to the semiconductor element;
Disposing the semiconductor element in the opening;
Filling an insulating material between the film-like film and the semiconductor element;
A method for manufacturing a semiconductor device, comprising:
前記半導体素子を前記膜に接着・固定する工程が、
前記半導体素子を含み前記半導体素子よりも広い範囲に樹脂を塗布する工程と、
前記樹脂を塗布する前に前記半導体素子の前記一方の面をマスクする前工程、又は、
前記樹脂を塗布した後に前記半導体素子の前記一方の面上に塗布された前記樹脂を除去する後工程と、
を含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
The step of bonding and fixing the semiconductor element to the film includes
Applying the resin to a wider area than the semiconductor element including the semiconductor element;
A pre-process for masking the one surface of the semiconductor element before applying the resin, or
A post-process for removing the resin applied on the one surface of the semiconductor element after applying the resin;
A method for manufacturing a semiconductor device, comprising:
前記膜が、セラミックス板又は金属板である、若しくは、内部にセラミックス板又は金属板を含む、
ことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1 or 2,
The film is a ceramic plate or a metal plate, or contains a ceramic plate or a metal plate inside,
A method for manufacturing a semiconductor device.
前記膜に配線パターンを形成する工程と、
前記半導体素子と前記配線パターンとをワイヤにより接続し、前記ワイヤを前記金属電極の上面よりも前記膜側に配置する工程と、
を含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to any one of claims 1 to 4,
Forming a wiring pattern on the film;
Connecting the semiconductor element and the wiring pattern with a wire, and disposing the wire on the film side of the upper surface of the metal electrode;
A method for manufacturing a semiconductor device, comprising:
第１半導体素子及び第２半導体素子を用意する工程と、
請求項１から５のいずれか一つに記載の半導体装置の製造方法によって、前記第１半導体素子の上面が前記第２半導体素子の下面と同じ側となるように前記第１半導体素子及び前記第２半導体素子を前記膜に固定し、前記第１半導体素子の上面に第１金属電極を実装し、前記第２半導体素子の下面に第２金属電極を実装する工程と、
前記第１半導体素子の下面と前記第２半導体素子の上面とに第３金属電極を実装する工程と、
を含むことを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising:
Preparing a first semiconductor element and a second semiconductor element;
6. The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor element and the first semiconductor element are arranged so that an upper surface of the first semiconductor element is on the same side as a lower surface of the second semiconductor element. Fixing two semiconductor elements to the film, mounting a first metal electrode on the upper surface of the first semiconductor element, and mounting a second metal electrode on the lower surface of the second semiconductor element;
Mounting a third metal electrode on the lower surface of the first semiconductor element and the upper surface of the second semiconductor element;
A method for manufacturing a semiconductor device, comprising:
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