JP2010117509A - Display device and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device, in which flicker is hard to see, while preventing sounding, and to provide a method of driving the same. <P>SOLUTION: A common signal Vcom is generated and output to a common electrode so that a voltage polarity to a center voltage Vcomc of a voltage amplitude at start timing may become the same with that at end timing, in each output period of a gate-on voltage VGH, and so that the voltage polarity may be reversed at least once. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device that inverts the polarity of a voltage applied to a liquid crystal for each display pixel corresponding to a predetermined number of scanning lines, and a driving method thereof.

  As a dot matrix type display panel used in a liquid crystal display device, a simple matrix type display panel and an active matrix type display panel are known. Among these, in an active matrix display panel, a plurality of scanning lines are arranged on one substrate of the display panel, and a plurality of signal lines are arranged orthogonal to these scanning lines. Thin film transistors (hereinafter referred to as TFTs) and pixel electrodes connected to the scan lines and signal lines via the TFTs are arranged near the intersections of the scan lines and the signal lines, respectively. ing. A common electrode is disposed on the other substrate so as to face each pixel electrode. Each display pixel is configured by filling liquid crystal between the pixel electrode and the common electrode.

  In each display pixel, a display signal supplied to the signal line is applied to the pixel electrode via the TFT that is selected (on state) by the gate-on voltage input via the scan line as a scan signal, and then the pixel electrode. The TFT is turned off by the gate-off voltage input as the scanning signal, and a voltage corresponding to the applied display signal is held in the pixel electrode. In addition, a common signal having the same potential between the display pixels is applied to the common electrode. In each display pixel, a voltage corresponding to the difference between the voltage level held in the pixel electrode and the voltage level in the common signal is applied to the liquid crystal, and the alignment state of the liquid crystal changes according to the voltage applied to the liquid crystal. .

Here, AC driving is essential for driving the liquid crystal for reasons such as extending the life. As this AC driving method, for example, frame inversion driving is known in which the polarity of the voltage applied to the liquid crystal is inverted every one vertical period (one frame). Further, in order to make it difficult to visually recognize flicker generated due to frame inversion driving, line inversion driving is also known in which the polarity of the voltage applied to the liquid crystal is inverted for each display pixel corresponding to one scanning line. (For example, refer to Patent Document 1). In line inversion driving, the polarity (voltage level) of the display signal supplied to the signal line is inverted every horizontal period, and the polarity of the voltage held in the pixel electrode of the corresponding display pixel is inverted between adjacent scanning lines. I am letting. In recent years, the voltage polarity of the common signal is inverted every horizontal period in synchronization with the change of the voltage polarity of the display signal. By doing in this way, the voltage level handled can be made lower than the case where the polarity of the voltage of only one of the two electrodes sandwiching the liquid crystal is reversed.
JP 2006-72211 A

  By the way, in the line inversion driving, the polarity inversion frequency of the common signal is higher than that in the frame inversion driving. Therefore, the polarity inversion frequency approaches the audible range (1 kHz to 20 kHz), and noise is generated when the display panel is driven. That is a problem.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a display device and a driving method thereof in which it is difficult for a flicker to be visually recognized but a noise is hardly generated.

  In order to achieve the above object, a display device according to one embodiment of the present invention includes a plurality of scan lines extending in the row direction, and a plurality of signal lines extending to intersect the scan lines. The pixel electrode is disposed so as to correspond to the intersection of the scanning line and the signal line, and is disposed so as to face the pixel electrode via the liquid crystal and the pixel electrode connected to the signal line via the switching element. A display device that reverses the polarity of a voltage applied to the liquid crystal for each display pixel corresponding to a predetermined number of scanning lines, and the switching element is turned on for each scanning line. Scanning side driving means for outputting a gate-on voltage to be output for a predetermined period, and a voltage polarity of the voltage amplitude with respect to the center voltage is determined depending on a start timing and an end timing in each of the predetermined periods. Grayed and in equal manner and at least once to invert, characterized by comprising a common electrode drive unit that outputs to the common electrode to generate a common signal.

  The display device driving method according to one embodiment of the present invention includes a plurality of scan lines extending in the row direction, a plurality of signal lines extending and intersecting the scan lines, and the scan lines. And a pixel electrode connected to the signal line through a switching element, a common electrode arranged to face the pixel electrode through a liquid crystal, A display device driving method for inverting the polarity of a voltage applied to the liquid crystal for each display pixel corresponding to a predetermined number of scanning lines, wherein the switching element is turned on for each scanning line. The scanning side driving step for outputting the gate-on voltage for a predetermined period, and the voltage polarity of the voltage amplitude with respect to the center voltage are the start timing and end timing in each of the predetermined periods. Is to invert equal manner and at least once in the ring, characterized in that a common electrode driving step of outputting to the common electrode to generate a common signal.

  According to the present invention, it is possible to make it difficult to generate sound while making it difficult to visually recognize flicker.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a liquid crystal display device as an example of a display device according to an embodiment of the present invention. The liquid crystal display device shown in FIG. 1 includes a display panel 10, a scan driver 20, a signal driver 30, a common signal generation circuit 40, a timing generator 50, a power supply circuit 60, and an input unit 70. .

  The display panel 10 has a liquid crystal sandwiched between a pair of substrates. On one substrate, a plurality of scanning lines G (j) extending in the row direction and a plurality of extending lines in the column direction so as to intersect each scanning line G (j) are arranged. Signal line S (i). In the vicinity of the intersection of the scanning line G (j) and the signal line S (i), the thin film transistor (TFT) and the scanning line G (j) and the signal line are connected via the TFT so as to correspond to the intersection. A pixel electrode connected to S (i) is formed. On the other substrate, a common electrode set to the same potential between the display pixels is formed so as to face each pixel electrode. Here, i = 1, 2, 3,..., M, j = 1, 2, 3,.

  FIG. 2 is a diagram illustrating an equivalent circuit of one display pixel provided in the display panel 10. A gate electrode of the TFT 11 is connected to the scanning line G (j) shown in FIG. 2, and a drain electrode of the TFT 11 is connected to the signal line S (i). Further, a pixel electrode is connected to the source electrode of the TFT 11. A common electrode is disposed so as to face the pixel electrode, and liquid crystal is filled (sandwiched) between the pixel electrode and the common electrode. Further, a storage capacitor Ccs is connected in parallel to the liquid crystal capacitor CLcd configured as described above. In such a configuration, when a voltage is applied between the pixel electrode and the common electrode, the alignment state of the liquid crystal filled between the pixel electrode and the common electrode changes according to the voltage, and the liquid crystal layer The transmittance of light at is changed. Thereby, the transmission state of light from a light source (not shown) arranged on the back surface of the display pixel shown in FIG. 2 is changed, and gradation display is performed.

  The scan driver 20 is connected to each scan line G (j) in the display panel 10. For example, based on the vertical control signal Vsig output from the timing generator 50 and the horizontal control signal Hsig, the scan driver 20 is connected to each scan line. A scanning signal for turning on each TFT 11 for a predetermined period is output for each row. That is, as shown in FIG. 3, the scanning driver 20 starts scanning in the frame in accordance with the vertical control signal Vsig, and in accordance with the horizontal control signal Hsig (consisting of the gate clocks GCK1 and GCK2). Voltage output such as switching from the gate-off voltage VGL to the gate-on voltage VGH for a period is performed for each scanning line in order from the scanning line G (1) at the front stage to the scanning line G (n) at the last stage.

  That is, the scan driver 20 sequentially turns on the TFTs corresponding to the scan line for each scan line, and the display signal Vs output to the signal line at this time is applied to the corresponding pixel electrode as the pixel electrode voltage Vs ′. Hold.

  The signal driver 30 is connected to each signal line S (i) in the display panel 10, and the horizontal control signal output from the timing generator 50, for example, gradation data input from the outside via the input unit 70. Based on Hsig, a display pixel unit for one row is captured, a display signal Vs is generated as an analog voltage corresponding to each captured gradation data, and each is supplied to a corresponding signal line S (i).

  Further, as shown in FIG. 3, the signal driver 30 inverts the voltage polarity of the display signal Vs with reference to the predetermined center voltage Vsc in accordance with the first polarity inversion control signal Pol1 input from the timing generator 50. Thus, the display signal Vs is generated and supplied to the signal line S (i). That is, each time the signal driver 30 supplies a display signal corresponding to the gradation data for one screen to the display panel 10, the polarity of the voltage applied to the liquid crystal of each display pixel is reversed, and one row The voltage polarity of the display signal Vs is switched so that the polarity of the voltage applied to the liquid crystal is inverted between adjacent display pixels every time.

  The common signal generation circuit 40 is connected to the common electrode and is supplied by the power supply circuit 60 in correspondence with the second polarity inversion control signal Pol2 input from the timing generator 50 as shown in FIG. By selecting one of the two types of common signal voltages VcomH and VcomL, the common signal Vcom is generated and supplied to the common electrode. In the present embodiment, switching of the voltage level of the common signal Vcom to these two types of common signal voltages VcomH and VcomL is referred to as polarity inversion of the common signal Vcom. In the present embodiment, in order to simplify the description, the common signal Vcom is not considered without considering the influence of the parasitic capacitance Cgd generated between the gate electrode of the TFT 11 and the pixel electrode corresponding to the TFT 11. The description will be made assuming that the amplitude center voltage Vcomc and the above-described predetermined center voltage Vsc are set to the same voltage level. The relationship between the amplitude center voltage Vcomc of the common signal Vcom and the above-described predetermined center voltage Vsc is a parasitic capacitance. It is preferable that fine adjustment is performed according to the magnitude of the value of Cgd.

  Here, as shown in FIG. 3, the first polarity reversal control signal Pol1 is switched between the voltage levels every one horizontal period (1H), so that the display signal Vs supplied to the signal line S (i) The voltage polarity is set to switch every horizontal period. The second polarity inversion control signal Pol2 is a voltage polarity inversion of the common signal Vcom supplied to the common electrode by setting the voltage level switching period to 1/3 that of the first polarity inversion control signal Pol1. The frequency is set to be three times the voltage polarity inversion frequency of the display signal Vs.

  The timing generator 50, based on the vertical synchronization signal and horizontal synchronization signal input from the input unit 70, the vertical control signal Vsig as described above, the first polarity inversion control signal Pol1, and the second polarity inversion control signal Pol2. The horizontal control signal Hsig is generated, and the generated control signals are supplied.

  The power supply circuit 60 generates and supplies various drive voltages in the scan driver 20, the signal driver 30, and the common signal generation circuit 40, and includes a booster circuit that boosts the power supply voltage Vcc.

Next, the operation of the display device having the configuration as shown in FIG. 1 will be described.
When the video data is supplied to the input unit 70, the vertical synchronization signal and the horizontal synchronization signal included in the video data are supplied from the input unit 70 to the timing generator 50. The timing generator 50 generates the vertical control signal Vsig based on the vertical synchronization signal supplied from the input unit 70. The vertical control signal Vsig generated by the timing generator 50 is output to the scanning driver 20 and the signal driver 30.

  Further, the timing generator 50 generates a horizontal control signal Hsig based on the horizontal synchronization signal supplied from the input unit 70. The horizontal control signal Hsig generated by the timing generator 50 is output to the scanning driver 20 and the signal driver 30.

  Further, the timing generator 50 generates the first polarity inversion control signal Pol1 and the second polarity inversion control signal Pol2 based on the vertical synchronization signal and the horizontal synchronization signal supplied from the input unit 70. Then, the first polarity inversion control signal Pol1 generated by the timing generator 50 is output to the signal driver 30, and the second polarity inversion control signal Pol2 is output to the common signal generation circuit 40.

  When the vertical control signal Vsig is input to the scan driver 20, the scan driver 20 starts scanning the scan line in the frame. When the vertical control signal Vsig is input to the signal driver 30, the signal driver 30 starts supplying the display signal Vs corresponding to the gradation data in the frame to the signal line S (i).

  In each frame, when the horizontal control signal Hsig is input to the scanning driver 20 and the signal driver 30, the scanning driver 20 turns on each TFT 11 for each TFT 11 for one row, so that the horizontal control signal Hsig The voltage level of the scanning signal Vg (j) output to the scanning line is sequentially changed from the gate-off voltage VGL for a predetermined period in order from the scanning line G (1) at the front stage to the scanning line G (n) at the last stage. Switch to gate-on voltage VGH.

  In addition, the signal driver 30 supplies a display signal Vs corresponding to a display pixel for which the scanning driver 20 turns on the TFT 11 by the scanning signal Vg to each signal line S (i). At this time, the signal driver 30 makes the voltage level of the display signal Vs the reference of the predetermined center voltage Vsc as described above in correspondence with the first polarity inversion control signal Pol1 input together with the horizontal control signal Hsig. And reverse.

  On the other hand, when the second polarity inversion control signal Pol2 is input to the common signal generation circuit 40, the common signal generation circuit 40 corresponds to the second polarity inversion control signal Pol2 and the common signal voltages at different voltage levels. By selecting one of VcomH and VcomL, a common signal Vcom is generated and supplied to the common electrode.

  In each display pixel in the display panel 10, as shown in FIG. 4, when the gate-on voltage VGH is supplied and the TFT 11 is turned on, the display signal Vs is supplied to the pixel electrode via the TFT 11 and the pixel electrode voltage Vs ′. Then, the gate-off voltage VGL is supplied and the TFT 11 is turned off, whereby the pixel electrode voltage Vs ′ is held in the pixel electrode. As a result, a voltage VLCD comprising a difference between the pixel electrode voltage Vs ′ and the common signal voltage Vcom (VcomL or VcomH) is applied to the liquid crystal. As a result, the alignment state of the liquid crystal changes, the light transmittance in the liquid crystal layer changes, and gradation display is performed. Here, the voltage applied to the liquid crystal is held by the auxiliary capacitor Ccs until the display signal Vs is applied to the pixel electrode in the next frame (that is, until the TFT 11 is turned on again in the next frame). .

  Here, for example, in the case of a QVGA (Quarter Video Graphics Array 320 × 240 pixels) display panel, when the voltage level of the common signal Vcom is switched only once in 1H, the voltage polarity inversion frequency of the common signal Vcom is, for example, about 7.2 kHz (frame frequency 60 Hz × 240/2). However, since the frequency of 7.2 kHz is in the audible range (1 kHz to 20 kHz), a sound is generated when the voltage level of the common signal Vcom is switched. On the other hand, by switching the voltage level of the common signal Vcom only 3 times to 1H, the voltage polarity inversion frequency of the common signal Vcom can be set to about 21.6 kHz, that is, outside the audible range, thereby preventing noise. Is possible. Further, by switching the voltage level of the common signal Vcom only 3 times in 1H, the voltage level can be made equal at the start timing and end timing of the on period of the on period in which the TFT 11 is turned on, and adjacent to each other. The voltage polarity state of the common signal Vcom in the ON period can be reversed between the scanning lines to be performed. Therefore, the polarity of the voltage applied to the liquid crystal can be reliably reversed between pixels corresponding to the adjacent scanning lines, and flicker can be prevented even if the polarity of the voltage applied to the liquid crystal of each display pixel is reversed for each frame. It can be difficult to see. Further, since the polarity (voltage level) of the display signal Vs is kept constant for about 1H, the display signal Vs to be written is supplied to the pixel electrode without unnecessarily consuming power. Vs ′ can be held.

  Although the present invention has been described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention. For example, in the above example, the number of times of switching the voltage level of the common signal Vcom is set to 3 times within 1H. However, the voltage polarity of the common signal Vcom is equal to or greater than 3 so that the voltage polarity of the common signal Vcom is equal at the start time and end time of 1H It may be an odd number of times. That is, the voltage polarity inversion frequency of the common signal Vcom supplied to the common electrode may be set to be an odd multiple of 3 or more with respect to the voltage polarity inversion frequency of the display signal Vs.

  Further, the above-described embodiments include various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some configuration requirements are deleted from all the configuration requirements shown in the embodiment, the above-described problem can be solved, and this configuration requirement is deleted when the above-described effects can be obtained. The configuration can also be extracted as an invention.

It is a schematic block diagram of a display apparatus. It is a figure which shows the equivalent circuit for one display pixel. It is a timing chart which shows the relationship between the scanning signal in each scanning line, and a common signal. It is a timing chart which shows the relationship between a display signal, a common signal, and a pixel electrode voltage.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Display panel, 11 ... Thin-film transistor (TFT), 20 ... Scan driver, 30 ... Signal driver, 40 ... Common signal voltage generation circuit, 50 ... Timing generator, 60 ... Power supply circuit, 70 ... Input part

Claims (6)

A plurality of scanning lines extending in the row direction;
A plurality of signal lines extending to intersect each of the scanning lines;
A pixel electrode disposed to correspond to the intersection of the scan line and the signal line, and connected to the signal line via a switching element;
A common electrode disposed so as to face the pixel electrode through a liquid crystal,
A display device that inverts the polarity of the voltage applied to the liquid crystal for each display pixel corresponding to a predetermined number of scanning lines,
Scanning-side driving means for outputting a gate-on voltage for turning on the switching element for a predetermined period for each scanning line;
A common signal is generated and output to the common electrode so that the voltage polarity of the voltage amplitude with respect to the center voltage becomes equal at the start timing and the end timing in each of the predetermined periods and is inverted at least once. Common electrode driving means
A display device comprising:   The signal-side driving means for supplying a display signal to each of the signal lines so as to maintain a constant voltage level during each of the predetermined periods. The display device according to 1.   The display device according to claim 2, wherein the polarity inversion frequency of the common signal is set to three times the polarity inversion frequency of the display signal.   The display device according to claim 3, wherein a polarity inversion frequency of the common signal is higher than an audible frequency.   The display device according to claim 4, wherein a polarity inversion frequency of the display signal is within an audible frequency range. A plurality of scanning lines extending in the row direction;
A plurality of signal lines extending to intersect each of the scanning lines;
A pixel electrode disposed to correspond to the intersection of the scan line and the signal line, and connected to the signal line via a switching element;
A common electrode disposed so as to face the pixel electrode through a liquid crystal,
A display device driving method for inverting the polarity of a voltage applied to the liquid crystal for each display pixel corresponding to a predetermined number of scanning lines,
A scanning side driving step for outputting a gate-on voltage for turning on the switching element for a predetermined period for each scanning line;
A common signal is generated and output to the common electrode so that the voltage polarity of the voltage amplitude with respect to the center voltage becomes equal at the start timing and the end timing in each of the predetermined periods and is inverted at least once. A common electrode driving step,
A method for driving a display device, comprising:

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