JP2010096793A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of data signal lines without significantly increasing the number of scanning signal lines. <P>SOLUTION: The liquid crystal display device comprises: a data signal line S(1) arranged to cross a first scanning signal line G(2) and a second scanning signal line G(1); a first pixel electrode E(1, 2, a) with one end connected to the data signal line S(1) via a first thin film transistor T(1, 2, a) connected to the first scanning signal line G(2) and in which a gradation signal supplied to the connected data signal line S(1) is applied; and a second pixel electrode E(1, 1, b) with one end connected to the first pixel electrode E(1, 2, a) via a second thin film transistor T(1, 1, b) connected to the second scanning signal line G(1) and in which the gradation signal is applied via the first pixel electrode E(1, 2, a). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix liquid crystal display device.

  In an active matrix type display device used for a liquid crystal display device or the like, a plurality of scanning signal lines arranged in the row direction of the display unit and a plurality of data signal lines arranged in the column direction of the display unit A display pixel is connected in the vicinity of the intersection with and a predetermined voltage is applied to the display pixel for display. A conventional display device requires a data signal line and a scanning signal line corresponding to each display pixel. Therefore, the number of output terminals of the source driver connected to the data signal line (the number of connection terminals between the source driver and the data signal line) for driving the data signal line is also required for the number of data signal lines, and the scanning signal The number of output terminals of the gate driver connected to the line for driving the scanning signal line (the number of connection terminals between the gate driver and the scanning signal line) is also required by the number of scanning signal lines.

  As one of proposals for reducing the total number of output terminals (number of connection terminals), for example, there is a method disclosed in Patent Document 1. In Patent Document 1, two TFTs are provided on both sides of one data signal line, the first scanning signal line is connected to one of the two TFTs, and the second scanning signal line is connected to the other TFT. is doing. Further, an image output circuit for applying an image signal for four pixels is provided, and a first switching element and a second switching element for switching an image signal applied to the data signal line are provided, and the first control line and the second control line are provided. By switching between the first switching element and the second switching element in accordance with the control signal from, one data signal line can be shared by two TFTs, that is, two display pixels. That is, instead of doubling the number of scanning signal lines corresponding to pixel rows designed with a relatively small number of rows, the number of data signal lines corresponding to pixel columns designed with a relatively large number of columns. By reducing the ½, the total number of output terminals is prevented from increasing.

JP 2006-201315 A

  However, in the method of Patent Document 1, as described above, the number of data signal lines can be reduced to half the number of display pixels for one row, but the number of scanning signal lines is one column. The number of display pixels is twice as many as the number of display pixels per minute, and it is not always possible to reduce the total number of output terminals (number of connection terminals).

  The present invention has been made in view of the above circumstances, and provides a display device and a display device driving method capable of reducing the number of data signal lines without significantly increasing the number of scanning signal lines. For the purpose.

In order to achieve the above object, a liquid crystal display device according to claim 1,
A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode, and
ΔV1 is a voltage shift amount in the second pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the on state;
A voltage shift amount in the second pixel electrode when the second thin film transistor is switched from the on state to the off state when the first thin film transistor is in the off state is ΔV2.
When the voltage shift amount in the first pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the off state is ΔV3,
Both ΔV1 and ΔV2 are smaller than ΔV3.

  A liquid crystal display device according to claim 2 is the liquid crystal display device according to claim 1, wherein ΔV3 = ΔV1 + ΔV2 is satisfied.

In addition, the liquid crystal display device according to claim 3 is:
A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode, and
ΔV1 is a voltage shift amount in the second pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the on state;
A voltage shift amount in the second pixel electrode when the second thin film transistor is switched from the on state to the off state when the first thin film transistor is in the off state is ΔV2.
When the voltage shift amount in the first pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the off state is ΔV3,
ΔV3 = ΔV1 + ΔV2
It is characterized by satisfying.

In addition, the liquid crystal display device according to claim 4 is:
A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode, and
When the scan signal for turning on the second thin film transistor is supplied to the second scan signal line, the scan signal supplied to the first scan signal line is turned on. A voltage shift amount in the second pixel electrode when switching from the scanning signal to the scanning signal to be turned off to ΔV1,
When the scanning signal for turning off the first thin film transistor is supplied to the first scanning signal line, the scanning signal supplied to the second scanning signal line is turned on. A voltage shift amount in the second pixel electrode when the scanning signal is switched from the scanning signal to the scanning signal to be turned off to ΔV2,
When the scanning signal for turning off the second thin film transistor is supplied to the second scanning signal line, the scanning signal supplied to the first scanning signal line is changed to the on state of the first thin film transistor. When the voltage shift amount in the first pixel electrode when switching from the scanned signal to the scanned signal to be turned off is ΔV3,
ΔV3 = ΔV1 + ΔV2
It is characterized by satisfying.

The liquid crystal display device according to claim 5
A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode,
A common electrode disposed opposite to the first pixel electrode or the second pixel electrode via a liquid crystal and set to an equal potential between the display pixels;
An auxiliary capacitance electrode disposed opposite to the first pixel electrode or the second pixel electrode via an insulating film and set to an equal potential between the display pixels,
A voltage level of a scanning signal for turning on the first thin film transistor is Vgha,
A voltage level of a scanning signal for turning off the first thin film transistor is Vgla,
The voltage level of the scanning signal for turning on the second thin film transistor is Vghb,
The voltage level of the scanning signal for turning off the second thin film transistor is Vglb,
A parasitic capacitance between the gate electrode of the first thin film transistor and the first pixel electrode is Cgsa,
The parasitic capacitance between the gate electrode of the second thin film transistor and the second pixel electrode is Cgsb,
A parasitic capacitance between the gate electrode of the second thin film transistor and the first pixel electrode is Cgd,
The liquid crystal capacitance between the first pixel electrode and the common electrode is Clca,
The liquid crystal capacitance between the second pixel electrode and the common electrode is Clcb, and the auxiliary capacitance between the first pixel electrode and the auxiliary capacitance electrode is Csa,
The auxiliary capacitance between the second pixel electrode and the auxiliary capacitance electrode is Csb,
(Vgha−Vgla) × (Cgsa / (Cgsa + Csa + Clca + Cgd + Cgsb + Csb + Clcb)) = ΔV1
(Vghb−Vglb) × (Cgsb / (Cgsb + Csb + Clcb)) = ΔV2,
When (Vgha−Vgla) × (Cgsa / (Cgsa + Csa + Clca + Cgd)) = ΔV3,
ΔV3 = ΔV1 + ΔV2
It is characterized by satisfying.

  The liquid crystal display device according to claim 6 is the liquid crystal display device according to claim 5, wherein each of the liquid crystal capacitors is applied with a predetermined voltage between the corresponding pixel electrode and the common electrode. It is characterized by the liquid crystal capacity when being used.

  According to the present invention, the number of data signal lines can be reduced without significantly increasing the number of scanning signal lines.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
As shown in FIG. 1, a schematic overall configuration of a display device 1 according to the present invention is as follows. A display panel 10, a source driver 20, a gate driver 30, a pixel data generation circuit 40, a common voltage generation circuit 50, and timing control. A circuit 60 and a power generation circuit 70 are included.

  As shown in FIG. 2, the display panel 10 has a configuration in which a liquid crystal LC is sandwiched between two transparent substrates 16 and 17 that are arranged to face each other and are bonded by a sealing material 15. One substrate 16 has a plurality of scanning signal lines G (for example, n scanning signal lines) extended in the row direction and a plurality of data signal lines S (for example, extended in the column direction). m data signal lines), a plurality of pixel electrodes E arranged in a matrix so as to correspond to each display pixel P, and a plurality of thin film transistors in which source electrodes are connected to the corresponding pixel electrodes E (TFT). On the other substrate 17, a common electrode 18 set at a common potential between the display pixels P is formed so as to face each pixel electrode E. Note that alignment films 13 and 14 for defining the initial alignment of the liquid crystal are formed on the opposing surfaces of the pixel electrode E and the common electrode 18, respectively.

  In the display panel 10, as shown in FIG. 3, a plurality of scanning signal lines G (j) extending in the row direction and a plurality of data signal lines S (i) extending in the column direction are provided. Are arranged to cross each other, more specifically, to be orthogonal to each other. Then, the first pixel electrode E (i, j,) connected to the two thin film transistors so as to correspond to each intersection (i, j) of the scanning signal line G (j) and the data signal line S (i). a first display pixel P (i, j, a) having a) and a second display pixel P (i) having a second pixel electrode E (i, j, b) connected to one thin film transistor , J, b) are formed adjacent to each other in the extending direction of the scanning signal line G (j). That is, in each pixel row of the display panel 10, the first display pixel P (i, j, a) and the second display pixel P (i, j, b) are alternately arranged. In each pixel column, either the first display pixel P (i, j, a) or the second display pixel P (i, j, b) is arranged to be continuous. Here, i = 1, 2,..., M, j = 1, 2,.

  In the first display pixel P (i, j, a), a first pixel electrode E (i, j, a) and a first thin film transistor T (i, j, a) are formed. The electrode E (i, j, a) is connected to the source electrode of the first thin film transistor T (i, j, a). The first thin film transistor T (i, j, a) has a gate electrode connected to the scanning signal line G (j) and a drain electrode connected to the data signal line S (i).

  The second display pixel P (i, j, b) is formed with a second pixel electrode E (i, j, b) and a second thin film transistor T (i, j, b). The pixel electrode E (i, j, b) is connected to the source electrode of the second thin film transistor T (i, j, b). The second thin film transistor T (i, j, b) has a first pixel electrode E (i, j + 1) in which the gate electrode is arranged on the scanning signal line G (j) and the drain electrode is arranged as a pixel row on the rear stage side. , A), respectively. That is, the second display pixel P (i, j, b) includes the first pixel electrode E (i, j, b) in which the gradation signal supplied to the data signal line S (i) is arranged as a pixel row on the rear stage side. The second pixel electrode E (i, j, b) is written via j + 1, a).

  That is, in the display panel 10, one data signal line is assigned to two columns of display pixels. In such a pixel configuration of the display panel 10, the number of data signal lines can be halved compared to the case where one data signal line is assigned to each column of display pixels. is there. In other words, the number of data signal lines can be halved with respect to the number of display pixels for one row. At this time, it is not necessary to greatly increase the number of scanning signal lines. That is, for example, if the number of display pixels is 240 rows, the number of scanning signal lines may be 240 + 1, and the number of scanning signal lines can be made approximately equal to the number of display pixels for one column.

  Here, a specific configuration of each display pixel will be described based on FIGS. 4, 5, and 6. One substrate 16 is provided with a scanning signal line G (j) including a gate electrode 51. A storage capacitor line 48 is provided in the same layer as the scanning signal line G (j). That is, the scanning signal line G (j) and the auxiliary capacitance line 48 are formed together. A gate insulating film 52 is provided on the entire upper surface. A semiconductor thin film 53 made of intrinsic amorphous silicon is provided on the upper surface of the gate insulating film 52. A channel protective film 54 is provided in the substantially central portion of the overlapping region with the scanning signal line G (j) on the upper surface of the semiconductor thin film 53. Contact layers 55 and 56 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 54 and on the upper surface of the semiconductor thin film 53 on both sides thereof. A source electrode 57 is provided on the upper surface of one contact layer 55. Further, a data signal line S (i) or a connection wiring L including the drain electrode 58 is provided on the upper surface of the other contact layer 56. Then, the first thin film transistor T (i, j, a) or the second thin film transistor T (i, j, a) is formed by the gate electrode 51, the gate insulating film 52, the semiconductor thin film 53, the channel protective film 54, the contact layers 55 and 56, the source electrode 57 and the drain electrode 58. Thin film transistor T (i, j, b) is configured. The source electrode 57 of the first thin film transistor T (i, j, a) and the drain electrode 56 of the second thin film transistor T (i, j-1, b) formed in the previous pixel row are electrically connected to each other. It also serves as a connection wiring L for connection.

  A planarizing film 59 is provided on the entire top surface of the gate insulating film 52 including the first thin film transistor T (i, j, a), the second thin film transistor T (i, j, b), and the like. The planarizing film 59 is provided with a contact hole 60 at a location corresponding to the source electrode 57. On the upper surface of the planarizing film 59, pixel electrodes E (i, j, a) and E (i, j, b) made of ITO are provided. The pixel electrodes E (i, j, a) and E (i, i, j and b) are electrically connected to the source electrode 57 through the contact hole 60.

  Here, the portion of the auxiliary capacitance line 48 that overlaps the pixel electrodes E (i, j, a) and E (i, j, b) is an auxiliary capacitance electrode. The auxiliary capacitors Csa and Csb are formed by the overlapped portions. In each display pixel P (i, j, a), P (i, j, b), the pixel electrode E (i, j, a), between E (i, j, b) and the common electrode 18 is used. By changing the alignment state of the liquid crystal LC to be arranged on the basis of the potential difference between the pixel electrode E (i, j, a), E (i, j, b) and the common electrode 18, The display state can be controlled. The auxiliary capacitance electrode is electrically connected to the common electrode 18 so that the common signal Vcom supplied to the common electrode 18 is also supplied to the auxiliary capacitance electrode. In each first display pixel P (i, j, a), as shown in FIG. 7A, the first display pixel P (i, j, a) is sandwiched between the first pixel electrode E (i, j, a) and the common electrode 18. A liquid crystal capacitor Clca connected in parallel with the auxiliary capacitor Csa is formed by the liquid crystal layer thus formed. Further, in each second display pixel P (i, j, b), as shown in FIG. 7B, the second display pixel P (i, j, b) is sandwiched between the second pixel electrode E (i, j, b) and the common electrode 18. A liquid crystal capacitor Clcb connected in parallel with the auxiliary capacitor Csb is formed by the liquid crystal layer thus formed.

  The source driver 20 is connected to each data signal line S (i), and the pixel data generation circuit 40 is based on horizontal control signals (clock signal, start signal, latch operation control signal, etc.) output from the timing control circuit 60. The pixel data corresponding to each display pixel supplied from is acquired in a predetermined unit, and the gradation signal corresponding to the acquired pixel data is supplied to the data signal line at a predetermined timing.

  The gate driver 30 is connected to each scanning signal line G (j), receives the vertical control signal from the timing control circuit 60, and receives the first thin film transistor T (i, j, connected to the scanning signal line G (j). A scanning signal for turning on or off a) and the second thin film transistor T (i, j, b) is supplied to the scanning signal line G (j).

  The pixel data generation circuit 40 generates pixel data corresponding to each display pixel from, for example, a video signal (analog or digital) supplied from the outside of the display device 1 and outputs the pixel data to the source driver 20. Here, an inversion signal (FRP) is input from the timing control circuit 60 to the pixel data generation circuit 40 every predetermined period (for example, one frame, one field, one line). The pixel data generation circuit 40 inverts the bit value of the pixel data output to the source driver 20 every time an inversion signal is input. In this way, the polarity of the gradation signal applied to the display pixel is inverted every predetermined period by inverting the bit value of the pixel data every predetermined period. As a result, the voltage applied to the liquid crystal in each display pixel can be AC driven.

  Based on the inverted signal output from the timing control circuit 60, the common voltage generation circuit 50 generates a common signal Vcom whose polarity is inverted every predetermined period and supplies the common signal Vcom to the common electrode 18.

  The timing control circuit 60 generates various control signals such as a vertical control signal, a horizontal control signal, and an inversion signal. For example, the inversion signal is supplied to the pixel data generation circuit 40 and the common signal generation circuit 50, and the vertical control signal is supplied to the gate driver. 30, the horizontal control signal is output to the source driver 20.

  The power supply generation circuit 70 generates power supply voltages Vgh and Vgl necessary for generating a scanning signal and supplies them to the gate driver 30, and also generates a power supply voltage Vsh necessary for generating a grayscale signal to generate a source. It is supplied to the driver 20. The power supply generation circuit 70 generates a logic power supply Vcc and supplies it to the source driver 20 and the gate driver 30.

  Next, the operation of the display device 1 will be described based on the timing chart shown in FIG. Here, in FIG. 8, in order from the top, the gradation signal supplied to the data signal line S (i), the scanning signal supplied to the first scanning signal line G (1), and the second scanning. Scan signal supplied to signal line G (2), scan signal supplied to third stage scan signal line G (3), scan signal supplied to fourth stage scan signal line G (4), 5 The scanning signal supplied to the scanning signal line G (5) at the stage, the scanning signal supplied to the scanning signal line G (6) at the sixth stage, and the first pixel electrode E corresponding to the pixel row at the third stage. Application state of gradation signal in (i, 3, a) Application state of gradation signal in second pixel electrode E (i, 3, b) corresponding to third pixel row, fourth pixel Application state of gradation signal in first pixel electrode E (i, 4, a) corresponding to the row Second pixel electrode E (i, 4, b) corresponding to the fourth pixel row The gradation signal application state in the first pixel electrode E (i, 5, a) corresponding to the fifth pixel row and the second gradation signal application state corresponding to the fifth pixel row Application state of gradation signal in pixel electrode E (i, 5, b), application state of gradation signal in first pixel electrode E (i, 6, a) corresponding to the sixth pixel row, six stages The gradation signal application state in the second pixel electrode E (i, 6, b) corresponding to the pixel row of the eye and the common signal Vcom supplied to the common electrode 18 are shown. Further, in FIG. 8, each gradation signal supplied by the data signal line S (i) is indicated by a coordinate value on the display panel 10 corresponding to the pixel data. Note that old indicates an applied state based on the gradation signal written in the previous frame.

  In the display device 1, the pixel data related to the first pixel electrode E (i, j, a) and the pixel data related to the second pixel electrode E (i, j, b) The information is alternately input to the source driver 20 every time. That is, pixel data related to the second pixel electrode E (i, j, b) corresponding to a predetermined pixel row is input in the first half of each horizontal period, and the predetermined pixel row and Pixel data relating to the first pixel electrode E (i, j, a) corresponding to the same pixel row is input. In addition, the inverted signal is controlled so that the bit value (that is, the polarity of the gradation signal) of the input pixel data is inverted every frame. In FIG. 8, the sign of “+” is given to the gradation signal when the bit inversion of the pixel data is not performed, and “−” is applied to the gradation signal when the bit inversion of the pixel data is performed. The symbol is attached. Further, the relationship between the voltage level of the common signal Vcom and the voltage level of the grayscale signal is shown in FIG. 9, for example.

  Here, in the present embodiment, the polarity of the gradation signal written to the first pixel electrode E (i, j, a) for the display of the first display pixel P (i, j, a), and the first Invert signal so that the polarity of the gradation signal written to the second pixel electrode E (i, j, b) for display of the two display pixels P (i, j, b) differs within the frame. Is controlled.

  As described above, as shown in FIG. 8, the gradation signal and the second pixel electrode E (i, j, b) related to the first pixel electrode E (i, j, a) in each pixel row in the frame. The gradation signals according to are + (i, 1, b), − (i, 1, a), + (i, 2, b), − (i, 2, a), + (i, 3, b),-(i, 3, a),... are supplied to the data signal line S (i) in a time division manner. Then, such supply of the gradation signal to the data signal line S (i) is repeatedly executed in each frame. Note that the polarity of each gradation signal is inverted for each frame.

  On the other hand, the scanning signal input to each scanning signal line G (j) is set to High (Vgh) twice in each frame.

  First, in a predetermined horizontal period of each frame, for example, in the first display pixel P (i, 3, a) and the second display pixel P (i, 3, b) corresponding to the third pixel row. A gradation signal for display is written. In the horizontal period, the scanning signal of the third scanning signal line G (3) and the scanning signal of the fourth scanning signal line G (4) are High in synchronization with the start timing T11a of the horizontal period. To. Here, in the horizontal period, during the period in which the scanning signal of the third scanning signal line G (3) is High, for example, the gradation signal + (i, 3, b) is applied to the data signal line S (i). A period from when the supply is started to immediately before the supply of the gradation signal − (i, 3, a) to be supplied next to the gradation signal + (i, 3, b) is completed. In the horizontal period, for example, the gradation signal + (i, 3, b) is supplied to the data signal line S (i) during the period when the scanning signal of the fourth scanning signal line G (4) is High. Is a period from the start of the operation until immediately before the supply of the gradation signal + (i, 3, b) ends.

  By setting the scanning signal of the third scanning signal line G (3) to High at timing T11a, the first thin film transistor T (i, 3, a) connected to the third scanning signal line G (3). ) And the second thin film transistor T (i, 3, b) are turned on. Further, by setting the scanning signal of the fourth scanning signal line G (4) to High, the first thin film transistor T (i, 4, a) connected to the fourth scanning signal line G (4). Then, the second thin film transistor T (i, 4, b) is turned on. As a result, the gradation signal + (i, 3, b) supplied to the data signal line S (i) corresponds to the first pixel electrode E (i, 3, a) corresponding to the third pixel row and Data is written to the second pixel electrode E (i, 3, b) and the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row, and corresponds to the third pixel row. The first display pixel P (i, 3, a) and the second display pixel P (i, 3, b) and the first display pixel P (i, 4,4) corresponding to the fourth pixel row. In a), display corresponding to the gradation signal + (i, 3, b) is performed.

  Next, at the timing T11b, the scanning signal of the fourth scanning signal line G (4) is changed from High to Low (Vgl) while the scanning signal of the third scanning signal line G (3) is kept High. At the timing T11b, the second thin film transistor T (i, 3, b) connected to the third-stage scanning signal line G (3) remains in the on state, but the fourth-stage scanning signal line G The first thin film transistor T (i, 4, a) connected to (4) is turned off. For this reason, the gradation signal + (i, 3, b) corresponding to the coordinates is held in the second pixel electrode E (i, 3, b) corresponding to the third pixel row. In the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row, a gradation signal + (i, 3, b) different from the coordinates is held. However, as will be described later, this state is resolved in approximately one horizontal period to two horizontal periods.

  At the timing T11b, the gradation signal applied to the data signal line S (i) immediately after that is switched from + (i, 3, b) to − (i, 3, a). Therefore, the first pixel electrode E (i, 3, a) corresponding to the third pixel row is connected to the third scanning signal line G (3) that is continuously in the ON state. The gradation signal − (i, 3, a) is written through the first thin film transistor T (i, 3, a), and the first display pixel P (i, 3, a) corresponding to the third pixel row is written. In a), display corresponding to the gradation signal-(i, 3, a) is performed.

  Next, at timing T11c, the scanning signal of the scanning signal line G (3) at the third stage is changed from High to Low. As a result, the gradation signal − (i, 3, a) is held in the first pixel electrode E (i, 3, a) corresponding to the third pixel row. Further, between the second pixel electrode E (i, 3, b) corresponding to the third pixel row and the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row. Is disconnected by the second thin film transistor T (i, 3, b) connected to the scanning signal line G (3) at the third stage.

  In this manner, the first display pixel P (i, 3, a) and the second display pixel P (i, 3, b) corresponding to the third pixel row are displayed in the horizontal period. Is written for.

  In the next horizontal period, the first display pixel P (i, 4, a) and the second display pixel P (i, 4, b) corresponding to the fourth pixel row are displayed. A gradation signal is written. In the horizontal period, the scanning signal of the fourth scanning signal line G (4) and the scanning signal of the fifth scanning signal line G (5) are High in synchronization with the start timing T12a of the horizontal period. To. Here, in the horizontal period, during the period when the scanning signal of the fourth scanning signal line G (4) is High, for example, the gradation signal + (i, 4, b) is applied to the data signal line S (i). A period from when supply is started to immediately before the supply of the gradation signal − (i, 4, a) to be supplied next to the gradation signal + (i, 4, b) is completed. In the horizontal period, for example, the gradation signal + (i, 4, b) is supplied to the data signal line S (i) during the period in which the scanning signal of the fifth scanning signal line G (5) is High. Is a period from the start of the operation until immediately before the supply of the gradation signal + (i, 4, b) ends.

  By setting the scanning signal of the fourth scanning signal line G (4) to High at timing T12a, as described above, the first thin film transistor T ( i, 4, a) and the second thin film transistor T (i, 4, b) are turned on. Further, by setting the scanning signal of the fifth scanning signal line G (5) to High, the first thin film transistor T (i, 5, a) connected to the fifth scanning signal line G (5). Then, the second thin film transistor T (i, 5, b) is turned on. As a result, the gradation signal + (i, 4, b) supplied to the data signal line S (i) corresponds to the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row and Data is written to the second pixel electrode E (i, 4, b) and the first pixel electrode E (i, 5, a) corresponding to the fifth pixel row, and corresponds to the fourth pixel row. The first display pixel P (i, 4, a) and the second display pixel P (i, 4, b) and the first display pixel P (i, 5,5) corresponding to the fifth pixel row. In a), display corresponding to the gradation signal + (i, 4, b) is performed.

  Next, at timing T12b, the scanning signal of the fifth scanning signal line G (5) is changed from High to Low while the scanning signal of the fourth scanning signal line G (4) is kept High. At this timing T12b, the second thin film transistor T (i, 4, b) connected to the fourth-stage scanning signal line G (4) remains on, but the fifth-stage scanning signal line G The first thin film transistor T (i, 5, a) connected to (5) is turned off. For this reason, the gradation signal + (i, 4, b) corresponding to the coordinates is held in the second pixel electrode E (i, 4, b) corresponding to the fourth pixel row. In the first pixel electrode E (i, 5, a) corresponding to the fifth pixel row, a gradation signal + (i, 4, b) different from the coordinates is held. However, this state is also resolved in approximately one horizontal period to two horizontal periods.

  At timing T12b, the gradation signal applied to the data signal line S (i) immediately after that is switched from + (i, 4, b) to − (i, 4, a). For this reason, the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row is connected to the fourth scanning signal line G (4) which is continuously turned on. The gradation signal − (i, 4, a) is written through the first thin film transistor T (i, 4, a), and the first display pixel P (i, 4, a) corresponding to the fourth pixel row is written. In a), display corresponding to the gradation signal-(i, 4, a) is performed. That is, the display based on the gradation signal different from the coordinates is canceled, and the display based on the gradation signals corresponding to the coordinates is performed.

  Next, at timing T12c, the scanning signal of the scanning signal line G (4) at the fourth stage is changed from High to Low. As a result, the gradation signal − (i, 4, a) is held in the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row. Further, between the second pixel electrode E (i, 4, b) corresponding to the fourth pixel row and the first pixel electrode E (i, 5, a) corresponding to the fifth pixel row. Is disconnected by the second thin film transistor T (i, 4, b) connected to the fourth-stage scanning signal line G (4).

  In this way, in the horizontal period, the first display pixel P (i, 4, a) and the second display pixel P (i, 4, b) corresponding to the fourth pixel row are displayed. Is written for.

  In the subsequent horizontal period, the above-described gradation signal is sequentially written to the display pixels corresponding to each stage, so that an appropriate video display to be displayed based on the video signal in the display device 1 is performed. Will be made.

  As described above, in the display device 1, the number of scanning signal lines is greatly increased by connecting another display pixel to a display pixel connected to a predetermined data signal line via a thin film transistor. Thus, the number of data signal lines and the number of output terminals of the source driver can be reduced. As a result, it is possible to increase the bonding pitch width of the LSI constituting the source driver, and when the LSI constituting the source driver is mounted on the display panel 10 and joined, the joining can be easily performed. It becomes possible. Further, since the number of output terminals of the source driver can be reduced, the LSI constituting the source driver 20 can be downsized.

[Second Embodiment]
The schematic overall configuration of the display device according to the second embodiment is substantially the same as that of the first embodiment described above. In the first embodiment, the case where the parasitic capacitance generated between the thin film transistor and the pixel electrode is not considered has been described. In the second embodiment, the gate electrode and the pixel electrode of the thin film transistor are not connected. A case where the generated parasitic capacitance is taken into account will be described. That is, as shown in FIG. 10, the gate electrode of the first thin film transistor T (i, j, a) and the first pixel electrode E (i) connected to the first thin film transistor T (i, j, a). , J, a), a parasitic capacitance Cgsa occurs, and the second thin film transistor T (i, j, b) connected to the gate electrode and the second thin film transistor T (i, j, b). Parasitic capacitance Cgsb is generated between the second pixel electrode E (i, j, b) and the second thin film transistor T (i, j, b) and the second thin film transistor T (i, j, b). A case where a parasitic capacitance Cgd is generated between the first pixel electrode E (i, j + 1, a) connected to b) will be described. Note that the values of the parasitic capacitances Cgsa, Cgsb, and Cgd generated at each location are the same between the corresponding display pixels.

  Further, as described with reference to FIGS. 7A and 7B, the auxiliary capacitor Csa is formed between the first pixel electrode E (i, j, a) and the auxiliary capacitor electrode. It is assumed that an auxiliary capacitance Csb is formed between the second pixel electrode E (i, j, b) and the auxiliary capacitance electrode. Further, a liquid crystal capacitor Clca is formed between the first pixel electrode E (i, j, a) and the common electrode 18, and between the second pixel electrode E (i, j, b) and the common electrode 18. It is assumed that a liquid crystal capacitor Clcb is formed.

  Hereinafter, based on FIG. 8 and FIG. 11, the third stage connected via the second thin film transistor T (i, 3, b) having the gate electrode connected to the third scanning signal line G (3). Of the parasitic capacitance between the second pixel electrode E (i, 3, b) corresponding to the second pixel row and the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row. The difference in the occurrence of potential fluctuation due to the influence will be specifically described. In order to simplify the description, it is assumed that the gradation signal supplied to each display pixel is supplied with a gradation signal having the same voltage level for each polarity. That is, the display device 1 will be described assuming that a gradation signal is supplied so that a solid image is displayed. Further, FIG. 11 shows potential changes at the pixel electrodes E (i, 3, b) and E (i, 4, a) when the potential at the common electrode 18 is set as a reference potential. That is, FIG. 11 shows that the potential change of the pixel electrode due to the amplitude of the common signal Vcom is omitted.

  In each frame, the second pixel electrode E (i, 3, b) corresponding to the third pixel row is connected to the third scanning signal line G (3) at the timing T11b. The first thin film transistor T (i, 4, a) connected to the fourth scanning signal line G (4) is switched from the on state to the off state while maintaining T (i, 3, b) in the on state. As a result, the gradation signal + (i, 3, b) or gradation signal − (i, 3, b) corresponding to the coordinates is held. However, at this time, the gate electrode of the first thin film transistor T (i, 4, a) connected to the fourth-stage scanning signal line G (4) and the first thin film transistor T (i, 4, a) are connected. Since a parasitic capacitance Cgsa exists between the connected first pixel electrodes E (i, 4, a), the second pixel electrode corresponding to the third pixel row is affected by the parasitic capacitance Cgsa. A first voltage shift occurs in E (i, 3, b) together with the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row. The voltage shift amount ΔV1 generated by the first voltage shift can be derived from (Equation 1).

(Equation 1)
ΔV1 = (Vgha−Vgla) × (Cgsa / (Cgsa + Csa + Clca + Cgd + Cgsb + Csb + Clcb))

  Here, Vgha is the voltage level of the scanning signal that turns on the first thin film transistor T (i, 4, a) connected to the scanning signal line G (4) at the fourth stage. The voltage level Vgh is equal to the voltage level of the scanning signal when the second thin film transistor T (i, 3, b) connected to the third scanning signal line G (3) is turned on. Vgla is a voltage level of a scanning signal for turning off the first thin film transistor T (i, 4, a) connected to the fourth-stage scanning signal line G (4). The voltage level Vgl is equal to the voltage level of the scanning signal when the second thin film transistor T (i, 3, b) connected to the third scanning signal line G (3) is turned off.

  In each frame, the third scanning signal line is maintained while the first thin film transistor T (i, 4, a) connected to the fourth scanning signal line G (4) is maintained in the OFF state at the timing T11c. The second thin film transistor T (i, 3, b) connected to G (3) is switched from the on state to the off state. At this time, the gate electrode of the second thin film transistor T (i, 3, b) connected to the third-stage scanning signal line G (3) and the second thin film transistor T (i, 3, b) are connected. Since the parasitic capacitance Cgsb exists between the second pixel electrode E (i, 3, b), the second pixel electrode E (corresponding to the third pixel row is affected by the parasitic capacitance Cgsb. A second voltage shift occurs in i, 3, b). The voltage shift amount ΔV2 generated by the second voltage shift can be derived from (Equation 2).

(Equation 2)
ΔV2 = (Vghb−Vglb) × (Cgsb / (Cgsb + Csb + Clcb))

  Here, Vghb is a voltage level of a scanning signal for turning on the first thin film transistor T (i, 3, b) connected to the third-stage scanning signal line G (3). The voltage level Vgh is equal to the voltage level of the scanning signal when the first thin film transistor T (i, 4, a) connected to the fourth-stage scanning signal line G (4) is turned on. Vglb is the voltage level of the scanning signal that turns off the second thin film transistor T (i, 3, b) connected to the scanning signal line G (3) at the third stage. In this embodiment, The voltage level Vgl is equal to the voltage level of the scanning signal when the first thin film transistor T (i, 4, a) connected to the fourth scanning signal line G (4) is turned off.

  As described above, in the second pixel electrode E (i, 3, b) corresponding to the third pixel row, the voltage is shifted by ΔV1 + ΔV2 with respect to the gradation signal to be held for each frame.

  On the other hand, the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row is connected to the second scanning signal line G (3) at the timing T12c in each frame. The first thin film transistor T (i, 4, a) connected to the fourth scanning signal line G (4) is changed from the on state to the off state while the thin film transistor T (i, 3, b) is maintained in the off state. By switching, the gradation signal + (i, 4, a) or gradation signal − (i, 4, a) corresponding to the coordinates is held. However, at this time, the gate electrode of the first thin film transistor T (i, 4, a) connected to the fourth-stage scanning signal line G (4) and the first thin film transistor T (i, 4, a) are connected. Since there is a parasitic capacitance Cgsa between the connected first pixel electrode E (i, 4, a), the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row. ) Causes a third voltage shift. The voltage shift amount ΔV3 generated by the third voltage shift can be derived from (Equation 3).

(Equation 3)
ΔV3 = (Vgha−Vgla) × (Cgsa / (Cgsa + Csa + Clca + Cgd))

  Note that at the timing T12c, the second thin film transistor T (i, 3, b) connected to the third-stage scanning signal line G (3) is in an off state, and thus the third voltage shift is performed in three stages. Since the influence on the second pixel electrode E (i, 3, b) corresponding to the pixel row of the eye is slight, it is omitted here.

  As described above, in the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row, the voltage is shifted by ΔV3 with respect to the gradation signal to be held for each frame.

  By the way, if the effective voltage applied to the liquid crystal is different between the positive writing frame and the negative writing frame, the difference in effective voltage is recognized as flicker, and the display quality is deteriorated. Therefore, the effective voltage applied to the liquid crystal between the positive writing frame and the negative writing frame is equal for the second display pixel P (i, 3, b) corresponding to the third pixel row. In order to achieve this, it is preferable to make the common signal Vcom amplitude center voltage coincide with the center voltage of the voltage amplitude Vppb at the second pixel electrode E (i, 3, b) corresponding to the third pixel row. That is, as shown in FIG. 12A, the amplitude center voltage Vcc of the common signal Vcom is increased by ΔV1 + ΔV2 from the amplitude center voltage Vsc of the gradation signal supplied to the data signal line S (i) in the direction of voltage shift. It is preferable to set the common signal Vcom so that it is shifted in advance.

  In addition, the effective voltage applied to the liquid crystal between the positive writing frame and the negative writing frame is equal for the first display pixel P (i, 4, a) corresponding to the fourth pixel row. In order to achieve this, it is preferable to match the amplitude center voltage of the common signal Vcom with the center voltage of the voltage amplitude Vppa at the first pixel electrode E (i, 4, a) corresponding to the fourth pixel row. . That is, as shown in FIG. 12B, the amplitude center voltage Vcc of the common signal Vcom is increased by ΔV3 from the amplitude center voltage Vsc of the gradation signal supplied to the data signal line S (i) in the voltage shift generation direction. It is preferable to set the common signal Vcom so that it is shifted in advance.

  If ΔV3 = ΔV1 + ΔV2, then the center voltage of the voltage amplitude Vppb at the second pixel electrode E (i, 3, b) corresponding to the third pixel row and the fourth pixel row corresponding to the fourth pixel row. The second display pixel corresponding to the common signal Vcom amplitude center voltage Vcc can be matched with the center voltage of the voltage amplitude Vppa at one pixel electrode E (i, 4, a) and the common signal Vcom amplitude center voltage Vcc corresponds to the third pixel row. Preferably, P (i, 3, b) and the first display pixel P (i, 4, a) corresponding to the fourth pixel row can be set in common. That is, the second display pixel P (i, 3, b) corresponding to the third pixel row and the first display pixel P (i, 4, a) corresponding to the fourth pixel row simultaneously. The occurrence of flicker can be prevented.

  Note that the parasitic capacitance Cgsa is a first signal connected to the scanning signal line G (j) corresponding to the first thin film transistor T (i, j, a) and the first thin film transistor T (i, j, a). The capacitance value can be appropriately adjusted by adjusting the distance from the pixel electrode E (i, j, a) and the dielectric constant of the insulating film provided therebetween. Further, the parasitic capacitance Cgsb includes the scanning signal line G (j) corresponding to the second thin film transistor T (i, j, b) and the second thin film transistor T (i, j, b) connected to the second thin film transistor T (i, j, b). The capacitance value can be appropriately adjusted by adjusting the distance from the pixel electrode E (i, j, b) and the dielectric constant of the insulating film provided therebetween. In addition, the parasitic capacitance Cgd is a first signal connected to the scanning signal line G (j) corresponding to the second thin film transistor T (i, j, b) and the second thin film transistor T (i, j, b). The capacitance value can be adjusted as appropriate by adjusting the distance from the pixel electrode E (i, j-1, b) and the dielectric constant of the insulating film provided therebetween. In addition, the auxiliary capacitance Csa adjusts the area of the auxiliary capacitance electrode that is arranged so as to overlap with the first pixel electrode E (i, j, a), and the dielectric constant and film thickness of the insulating film provided therebetween. Thus, the capacitance value can be adjusted as appropriate. Further, the auxiliary capacitor Csb adjusts the area of the auxiliary capacitor electrode that is arranged so as to overlap with the second pixel electrode E (i, j, b), the dielectric constant, the film thickness, and the like of the insulating film provided therebetween. Thus, the capacitance value can be adjusted as appropriate.

  As described above, ΔV3 = ΔV1 + ΔV2 can be satisfied by appropriately adjusting each parasitic capacitance and auxiliary capacitance, and further, the liquid crystal capacitance in a state where a predetermined voltage is applied to the liquid crystal. The voltage shift amount generated in the display pixel P (i, j, a) can be made equal to the voltage shift amount generated in the second display pixel P (i, j, b).

  Further, even if ΔV3 = ΔV1 + ΔV2 cannot be satisfied by adjusting both ΔV1 and ΔV2 so that they are at least smaller than ΔV3, the value of ΔV1 + ΔV2 is extreme compared to ΔV3. Can be prevented from becoming too large. That is, the difference between the voltage shift amount generated in the first display pixel P (i, j, a) and the voltage shift amount generated in the second display pixel P (i, j, b) in each frame is extremely large. It can be prevented from becoming large.

  In order to realize ΔV3 = ΔV1 + ΔV2 with higher accuracy, a change in the liquid crystal capacitance before and after the voltage shift may be considered. Specifically, since the voltage applied to the liquid crystal changes before and after the voltage shift, the tilt angle of the liquid crystal molecules with respect to the pixel electrode or the common electrode 18 differs before and after the voltage shift, and the liquid crystal having dielectric anisotropy The apparent dielectric constant is also different. Then, ΔV3 = ΔV1 + ΔV2 is realized in consideration of the change in the liquid crystal capacitance caused by this.

  In this case, ΔV1 can be derived from (Equation 4), ΔV2 can be derived from (Equation 5), and ΔV3 can be derived from (Equation 6).

(Equation 4)
ΔV1 = (Vgha × (Cgsa / (Cgsa + Csa + Clcah + Cgd + Cgsb + Csb + Clcbh))) − (Vgla × (Cgsa / (Cgsa + Csa + Clcam + Cgd + Cgsb + Csb + Clcbm))

(Equation 5)
ΔV2 = (Vghb × (Cgsb / (Cgsb + Csb + Clcbm)) − (Vglb × (Cgsb / (Cgsb + Csb + Clcbl)))

(Equation 6)
ΔV3 = (Vgha × (Cgsa / (Cgsa + Csa + Clcah + Cgd)) − (Vgla × (Cgsa / (Cgsa + Csa + Clcal + Cgd)))

  Here, Clcah, Clcam, Clcal, Clcbh, Clcbm, and Clcbl will be described as specific examples based on FIG. Clcah is a liquid crystal capacitance in the first display pixel P (i, 4, a) immediately before the voltage shift occurs at the timing T11b or the timing T12c. Clcam is a liquid crystal capacitance in the first display pixel P (i, 4, a) immediately after the voltage shift occurs at the timing T11b. Clcal is a liquid crystal capacitance in the first display pixel P (i, 4, a) immediately after the voltage shift occurs at the timing T12c. Clcbh is a liquid crystal capacitance in the second display pixel P (i, 3, b) immediately before the voltage shift occurs at the timing T11b. Clcbm is a liquid crystal capacitance in the second display pixel P (i, 3, b) immediately after the voltage shift occurs at the timing T11b or immediately before the voltage shift occurs at the timing T11c. Clcbl is a liquid crystal capacitance in the second display pixel P (i, 3, b) immediately after the voltage shift occurs at the timing T11c.

  By the way, in FIG. 11, the first thin film transistor T (i, 4, a) connected to the scanning signal line G (4) at the fourth stage is kept 3 from the timing Tx to the timing Ty while maintaining the OFF state. The second thin film transistor T (i, 3, b) connected to the scanning signal line G (3) at the stage is turned on. For this reason, between the first thin film transistor T (i, 4, a) and the second thin film transistor T (i, 3, b), the gradation signal held as the gradation signals having opposite polarities in the previous frame is displayed. Neutralized. That is, for the second display pixel P (i, j, b), the second pixel electrode E (i, j, b) is previously stored before the gradation signal held in the frame is switched. ) Voltage level is shifted to the polarity side of the gradation signal held in the frame, and a preliminary charging effect can be obtained.

It is a figure which shows the schematic whole structure of a display apparatus. It is a figure which shows the cross-sectional structure of a display panel. It is a figure which shows a pixel arrangement | sequence. It is a top view which shows a pixel structure. FIG. 5 is a cross-sectional view illustrating a pixel structure, which is a cross section taken along line X-X ′ in FIG. 4. FIG. 5 is a cross-sectional view showing a pixel structure, which is a Y-Y ′ cross section in FIG. 4. It is a figure which shows the connection relation of a liquid crystal capacity | capacitance and an auxiliary capacity, (a) is a 1st display pixel, (b) is a 2nd display pixel. 6 is a timing chart showing the operation of the display device. It is a relationship diagram between the voltage level of the gradation signal and the voltage level of the common signal. It is a figure which shows the pixel arrangement | sequence which considered the parasitic capacitance. 6 is a timing chart showing a potential change at a pixel electrode when a potential at a common electrode is set as a reference potential. It is a relationship diagram between the voltage level of the grayscale signal and the voltage level of the common signal when the parasitic capacitance is taken into consideration, (a) is the second display pixel, (b) is the first display pixel.

Explanation of symbols

10: Display panel 18: Common electrode 20: Source driver 30: Gate driver 40: Pixel data generation circuit 50: Common signal generation circuit 60: Timing control circuit 70: Power generation time E, E (i, j, a), E (I, j, b): Pixel electrodes P, P (i, j, a), P (i, j, b): Display pixels T (i, j, a), T (i, j, b): Thin film transistor G (j): Scanning signal line S (i): Data signal line L: Connection wiring

Claims (6)

A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode, and
ΔV1 is a voltage shift amount in the second pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the on state;
A voltage shift amount in the second pixel electrode when the second thin film transistor is switched from the on state to the off state when the first thin film transistor is in the off state is ΔV2.
When the voltage shift amount in the first pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the off state is ΔV3,
A liquid crystal display device characterized in that ΔV1 and ΔV2 are both smaller than ΔV3. ΔV3 = ΔV1 + ΔV2
The liquid crystal display device according to claim 1, wherein: A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode, and
ΔV1 is a voltage shift amount in the second pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the on state;
A voltage shift amount in the second pixel electrode when the second thin film transistor is switched from the on state to the off state when the first thin film transistor is in the off state is ΔV2.
When the voltage shift amount in the first pixel electrode when the first thin film transistor is switched from the on state to the off state when the second thin film transistor is in the off state is ΔV3,
ΔV3 = ΔV1 + ΔV2
The liquid crystal display device characterized by satisfy | filling. A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode, and
When the scan signal for turning on the second thin film transistor is supplied to the second scan signal line, the scan signal supplied to the first scan signal line is turned on. A voltage shift amount in the second pixel electrode when switching from the scanning signal to the scanning signal to be turned off to ΔV1,
When the scanning signal for turning off the first thin film transistor is supplied to the first scanning signal line, the scanning signal supplied to the second scanning signal line is turned on. A voltage shift amount in the second pixel electrode when the scanning signal is switched from the scanning signal to the scanning signal to be turned off to ΔV2,
When the scanning signal for turning off the second thin film transistor is supplied to the second scanning signal line, the scanning signal supplied to the first scanning signal line is changed to the on state of the first thin film transistor. When the voltage shift amount in the first pixel electrode when switching from the scanned signal to the scanned signal to be turned off is ΔV3,
ΔV3 = ΔV1 + ΔV2
The liquid crystal display device characterized by satisfy | filling. A first scanning signal line and a second scanning signal line extending in a predetermined direction;
A data signal line arranged to intersect the first scanning signal line and the second scanning signal line;
The data signal line is connected through a first thin film transistor having one end connected to the first scanning signal line, and a gradation signal supplied to the connected data signal line is applied to the data signal line. A pixel electrode,
The second pixel is connected to the first pixel electrode via a second thin film transistor having one end connected to the second scanning signal line, and the gradation signal is applied to the first pixel electrode via the first pixel electrode. A pixel electrode,
A common electrode disposed opposite to the first pixel electrode or the second pixel electrode via a liquid crystal and set to an equal potential between the display pixels;
An auxiliary capacitance electrode disposed opposite to the first pixel electrode or the second pixel electrode via an insulating film and set to an equal potential between the display pixels,
A voltage level of a scanning signal for turning on the first thin film transistor is Vgha,
A voltage level of a scanning signal for turning off the first thin film transistor is Vgla,
The voltage level of the scanning signal for turning on the second thin film transistor is Vghb,
The voltage level of the scanning signal for turning off the second thin film transistor is Vglb,
A parasitic capacitance between the gate electrode of the first thin film transistor and the first pixel electrode is Cgsa,
The parasitic capacitance between the gate electrode of the second thin film transistor and the second pixel electrode is Cgsb,
A parasitic capacitance between the gate electrode of the second thin film transistor and the first pixel electrode is Cgd,
The liquid crystal capacitance between the first pixel electrode and the common electrode is Clca,
The liquid crystal capacitance between the second pixel electrode and the common electrode is Clcb, and the auxiliary capacitance between the first pixel electrode and the auxiliary capacitance electrode is Csa,
The auxiliary capacitance between the second pixel electrode and the auxiliary capacitance electrode is Csb,
(Vgha−Vgla) × (Cgsa / (Cgsa + Csa + Clca + Cgd + Cgsb + Csb + Clcb)) = ΔV1
(Vghb−Vglb) × (Cgsb / (Cgsb + Csb + Clcb)) = ΔV2,
When (Vgha−Vgla) × (Cgsa / (Cgsa + Csa + Clca + Cgd)) = ΔV3,
ΔV3 = ΔV1 + ΔV2
The liquid crystal display device characterized by satisfy | filling.   6. The liquid crystal display device according to claim 5, wherein each of the liquid crystal capacitors is a liquid crystal capacitor when a predetermined voltage is applied between the corresponding pixel electrode and the common electrode.

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