JP2010117492A - Drive unit of display device, the display device, and method of driving the display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive unit, a display device, and a method of driving the display device, in which shortage of a data voltage applied to a pixel is corrected. <P>SOLUTION: In the drive unit, a first driver has a scanning voltage for putting a transistor device into a selection state, a first non-scanning voltage for putting the transistor device into a non-selection state, and a second non-scanning voltage for putting the transistor device into the non-selection state, which is a higher voltage than the first non-scanning voltage. When each transistor element is set from the selection state to the non-selection state by applying the non-scanning voltage to a gate line by the first driver, if a voltage higher than a voltage applied to a common electrode is supplied to a drain line, the first driver outputs the second non-scanning voltage to the gate line, after outputting the first non-scanning voltage to the gate line for a predetermined period. If a voltage lower than the voltage applied to the common electrode is supplied to the drain line, the first driver outputs the first non-scanning voltage to the gate line, after outputting the second non-scanning voltage to the gate line for a predetermined period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix display panel drive device using TFT liquid crystal, and the like, and more particularly to a display device drive device and display device for correcting insufficient application of a data voltage to a pixel in a high-resolution display device, and It relates to the driving method.

  In general, a plurality of scanning lines, a plurality of data lines, pixel electrodes arranged in a matrix, a switching transistor (hereinafter referred to as TFT) in the pixel electrode, and a display element connected to the source terminal of the TFT And an active matrix display having a storage capacitor Cst that reduces charge loss at the source terminal, a common common electrode disposed on the opposite side of the display element and the storage capacitor Cst, and a parasitic capacitance Cgs between the source terminal and the scanning line. In the apparatus, a scanning voltage indicating a selected state is applied to the scanning line line by line for every scanning period, a data voltage corresponding to display data is applied to the data line, and a common voltage corresponding to the polarity is applied to the common electrode. The difference between the data voltage and the common voltage on the scanning line in the selected state becomes the applied voltage of the display element, and the display brightness of the display device is controlled according to the value of the applied voltage. It is. In recent years, the resolution of the above display devices such as mobile devices has been increasing to the resolution of VGA or WVGA, so one scanning period has been shortened, and the wiring resistance and wiring capacity of the data lines and common electrodes have been reduced with the increase in resolution. Since the size becomes large, insufficient application of the data voltage to the pixel occurs, and there is a problem that image quality deterioration occurs due to the display luminance being different from the desired display luminance.

Regarding the effective value correction method of the pixel, a display device disclosed in Patent Document 1 can be given. That is, in the display device disclosed in Patent Document 1, input terminals are provided on the side closer to and far from the gate driver of the common electrode arranged opposite to the pixel electrodes arranged in a matrix, and the gate voltage falls at both terminals. By applying different voltages having a potential difference corresponding to the difference in jump voltage based on the parasitic capacitance Cgs between the gate and the source terminal of the TFT according to the difference in jump voltage across the left and right of the display area in the common electrode A potential gradient is formed to correct the jump voltage across the entire display area.
Japanese Patent Laid-Open No. 9-179098

  The technique disclosed in Japanese Patent Laid-Open No. 2004-228561 has different voltages having a potential difference corresponding to the difference in jump voltage based on the parasitic capacitance Cgs between the gate and the source terminal of the TFT when the gate voltage falls from the near side and the remote side with respect to the gate driver. Is applied to correct the jump voltage across the entire display area. For this reason, as in the case of line inversion driving, the off-level of the gate voltage is changed up and down in the same manner as the common voltage so that the capacitance between the common electrode and the source (display element capacitance Clc (pixel capacitance (Cpix) and holding capacitance Cst)) Coupling fluctuations due to capacitive coupling can be corrected.

  However, in addition to the increase in the wiring resistance and the wiring capacity described above with the increase in the resolution of display devices in recent years, the increase in the number of TFTs connected to one gate line due to the increase in the number of pixels, that is, the increase in load capacity, In addition, although a reduction in the TFT area due to a reduction in the area allocated to one pixel, that is, a reduction in TFT driving capability is a problem, the technique described in Patent Document 1 does not consider it, and the pixel in one scanning period There was a problem that it was not possible to compensate for the insufficient application of the data voltage.

  The present invention has been made in view of these problems, and it is an object of the present invention to provide a driving device, a display device, and a driving method thereof capable of correcting insufficient application of a data voltage to a pixel in a high-resolution display device. .

  In order to solve the above problems, a transistor element is provided for each pixel electrode in a pixel region including a plurality of drain lines and a plurality of gate lines intersecting with the drain lines, and surrounded by the drain lines and the gate lines. And a first driver that outputs a voltage for switching selection or non-selection of the transistor element to the gate line, and a voltage corresponding to display data to the drain line. A second driver for supplying a third driver for supplying a common signal to a common common electrode, wherein the first driver selects the transistor element in a selected state; and the transistor element is in a non-selected state. A first non-scanning voltage that is higher than the first non-scanning voltage, and a second non-scanning voltage that makes the transistor element non-selective A voltage higher than a voltage applied to the common common electrode when the non-scanning voltage is applied to the gate line from the first driver and each transistor element is changed from a selected state to a non-selected state. When supplied to a line, the first driver outputs the first non-scanning voltage to the gate line for a predetermined period, and then outputs the second non-scanning voltage to the gate line. When a voltage lower than a voltage applied to the electrode is supplied to the drain line, the first driver outputs the second non-scanning voltage to the gate line for a predetermined period, and then outputs the first non-scanning voltage. A driving device that outputs a scanning voltage to the gate line;

  In order to solve the above problems, a transistor element is provided for each pixel electrode in a pixel region including a plurality of drain lines and a plurality of gate lines intersecting with the drain lines, and surrounded by the drain lines and the gate lines. And a first driver that outputs a voltage for switching selection or non-selection of the transistor element to the gate line, and a voltage corresponding to display data to the drain line. A second driver to supply; a third driver to supply a common signal to a common common electrode; and the first driver to set the transistor element in a selected state, and to set the transistor element in a non-selected state. A first non-scanning voltage; a second non-scanning voltage that is higher than the first non-scanning voltage and sets the transistor element in a non-selected state; And a third non-scanning voltage for setting the transistor element in a non-selected state, and applying the non-scanning voltage to the gate line from the first driver. When a voltage higher than a voltage applied to the common common electrode is supplied to the drain line when switching from a selected state to a non-selected state, the first driver sets the third non-scanning voltage to When the second non-scanning voltage is output to the gate line after being output to the gate line for a predetermined period, and a voltage lower than the voltage applied to the common common electrode is supplied to the drain line, One driver is a driving device that outputs the first non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period.

  In order to solve the above problem, a transistor is provided for each pixel electrode in a pixel region having a plurality of drain lines and a plurality of gate lines intersecting with the drain lines and surrounded by the drain lines and the gate lines. A display panel in which elements are formed, a first driver that outputs a voltage for switching selection or non-selection of the transistor elements to the gate line, and a second driver that supplies a voltage corresponding to display data to the drain line And a third driver for supplying a common signal to the common common electrode, wherein the first driver sets the transistor element in a selected state and the transistor element in a non-selected state. A first non-scanning voltage, and a second non-scanning voltage that is higher than the first non-scanning voltage and puts the transistor element in a non-selected state. When the non-scanning voltage is applied to the gate line from the first driver and each transistor element is changed from the selected state to the non-selected state, a voltage higher than the voltage applied to the common common electrode is supplied to the drain line. The first driver outputs the first non-scanning voltage to the gate line for a predetermined period, and then outputs the second non-scanning voltage to the gate line and applies it to the common common electrode. When a voltage lower than the applied voltage is supplied to the drain line, the first driver outputs the second non-scanning voltage to the gate line for a predetermined period, and then outputs the first non-scanning voltage. It is a display device that outputs to the gate line.

  In order to solve the above problem, a transistor is provided for each pixel electrode in a pixel region having a plurality of drain lines and a plurality of gate lines intersecting with the drain lines and surrounded by the drain lines and the gate lines. A display panel in which elements are formed, a first driver that outputs a voltage for switching selection or non-selection of the transistor elements to the gate line, and a second driver that supplies a voltage corresponding to display data to the drain line And a third driver for supplying a common signal to the common common electrode, wherein the first driver sets the transistor element in a selected state and the transistor element in a non-selected state. A first non-scanning voltage, a second non-scanning voltage that is higher than the first non-scanning voltage and puts the transistor element in a non-selected state, And a third non-scanning voltage for setting the transistor element in a non-selected state, and applying the non-scanning voltage to the gate line from the first driver. When a voltage higher than a voltage applied to the common common electrode is supplied to the drain line when switching from a selected state to a non-selected state, the first driver sets the third non-scanning voltage to When the second non-scanning voltage is output to the gate line after being output to the gate line for a predetermined period, and a voltage lower than the voltage applied to the common common electrode is supplied to the drain line, One driver is a display device that outputs the first non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period.

  In order to solve the above problems, a scanning voltage for selecting a transistor element, a first non-scanning voltage for deselecting the transistor element, and a voltage higher than the first non-scanning voltage, A first driver that outputs a voltage for switching selection or non-selection of the transistor element to a gate line, and drains a voltage corresponding to display data A second driver for supplying a line, and a third driver for supplying a common signal to a common common electrode, and the transistor element is provided for each pixel electrode in a pixel region surrounded by the drain line and the gate line. A method for driving a formed display panel, wherein a non-scanning voltage is applied from the first driver to the gate line to change each transistor element from a selected state to a non-selected state. When a voltage higher than a voltage applied to the common common electrode is supplied to the drain line, the first driver outputs the first non-scanning voltage to the gate line for a predetermined period. A step of outputting the second non-scanning voltage to the gate line, and when a voltage lower than a voltage applied to the common common electrode is supplied to the drain line, the first driver And outputting the first non-scanning voltage to the gate line after outputting the second non-scanning voltage to the gate line for a predetermined period.

  In order to solve the above problems, a scanning voltage for selecting a transistor element, a first non-scanning voltage for deselecting the transistor element, and a voltage higher than the first non-scanning voltage, A second non-scanning voltage that causes the transistor element to be in a non-selected state; and a third non-scanning voltage that is higher than the second non-scanning voltage and that causes the transistor element to be in a non-selected state; A first driver that outputs a voltage for switching between selection and non-selection of the transistor element to a gate line; a second driver that supplies a voltage corresponding to display data to a drain line; and a common signal to a common common electrode And a third driver, wherein the transistor element is formed for each pixel electrode in a pixel region surrounded by the drain line and the gate line, When a non-scanning voltage is applied to the gate line from the first driver and each transistor element is changed from a selected state to a non-selected state, a voltage higher than a voltage applied to the common common electrode is supplied to the drain line. The first driver outputs the second non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period; and the common common electrode When a voltage lower than the voltage applied to the drain line is supplied to the drain line, the first driver outputs the third non-scanning voltage to the gate line for a predetermined period, and then the first non-scanning And a step of outputting a voltage to the gate line.

  According to the present invention, the gate terminal voltage of the TFT is changed by switching the gate-off voltage once in one frame period after a certain period from the end of one scanning period. By correcting the potential of the TFT source terminal to a desired source potential due to the coupling fluctuation of the parasitic capacitance Cgs between the lines, it is possible to obtain a desired display luminance in a high-resolution active matrix display device. Become.

  Other effects of the present invention will become apparent from the description of the entire specification.

  Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted.

<Embodiment 1>
FIG. 1 is a block diagram of a display device according to Embodiment 1 of the present invention. Hereinafter, the display device of Embodiment 1 will be described with reference to FIG. However, in the following description, m and n are natural numbers of 1 or more.

  In FIG. 1, 100 is a CPU, 101 is a drive circuit (drive device), 102 is a system interface unit, 103 is a register unit, 104 is a memory control unit, 105 is a display memory unit, 106 is a VGL binary-compatible timing generation unit, 107 Is a latch circuit unit, 108 is a data voltage generation unit, 109 is a reference voltage generation unit corresponding to a VGL binary value, 110 is a data voltage selection unit, 111 is an operational amplifier unit, 112 is a gate signal generation unit corresponding to a VGL binary value, and 113 is a common signal generation unit 114 denotes a display portion (display panel), and 115 denotes a pixel portion.

  The drive circuit 101 is a so-called display memory built-in controller / driver and includes means for realizing the present invention. Here, the drive circuit 101 of the present invention is not limited to a display memory built-in type, and can be applied to a type without a built-in memory. Hereinafter, the configuration and operation of the internal block of the drive circuit 101 will be described.

  The system interface unit 102 receives display data and instructions output from the CPU 100, which is an external device (external system), and performs an operation of outputting to the register unit 103. Here, the instruction is information for determining the internal operation of the drive circuit 101, and includes various parameters such as a frame frequency, the number of drive lines, and a drive voltage. Further, it is assumed that information regarding the operation timing of a gate signal, which will be described later, which is a feature of the present invention is included.

  The register unit 103 is a block that stores instruction data and outputs the data to each block. For example, an instruction regarding the frame frequency, the number of drive lines, and the data voltage switching timing input from the CPU 100 is output to the VGL binary value corresponding timing generation unit 106, and an instruction regarding the drive voltage is output to the VGL binary value corresponding reference voltage generation unit 109. The The display data is also temporarily stored in the register unit 103, and is output to the memory control unit 104 together with instructions for indicating the display position.

  The memory control unit 104 is a block that performs the write and read operations of the display memory unit 105. First, during a write operation, a signal for selecting an address of the display memory unit 105 is output based on the display position instruction transferred from the register unit 103. At the same time, the display data is transferred to the display memory unit 105. With this operation, display data can be written to a predetermined address in the display memory unit 105. On the other hand, during the read operation, the operation of sequentially selecting a predetermined word line group one by one in the display memory unit 105 is repeated. With this operation, the display data on the selected word lines can be read all at once via the bit lines. It should be noted that setting of the range of the word line to be read, one selection period (equivalent to one scanning period), selection operation repetition period (equivalent to one frame period), and the like are instructed by the instruction.

  The display memory unit 105 has word lines and bit lines corresponding to the scanning lines and data lines of the display unit 114, and is a well-known memory unit for writing and reading display data described above. Note that the read display data is output to the latch circuit unit 107.

  The timing generator 106 self-generates and outputs a signal group indicating one scanning period or one frame period based on a reference clock generated by a built-in oscillator, and outputs a gate-off voltage switching signal that is a feature of the present invention. The data is output to the VGL binary corresponding gate signal generation unit 112.

  The latch circuit unit 107 latches the display data input from the display memory 105 based on the signal output from the VGL binary correspondence timing generation unit 106 and outputs it to the data voltage selection unit 110.

  The VGL binary-corresponding reference voltage generation unit 109 generates a necessary voltage level in the drive circuit 101 from the input power supply voltage Vci, and also requires a gate-on voltage (hereinafter referred to as VGH) required by the VGL binary-corresponding gate signal generation unit 112. And a binary gate-off voltage (hereinafter referred to as VGL0 and VGL1), which is a feature of the present invention.

  The data voltage generation unit 108 divides the voltage input from the VGL binary-corresponding reference voltage generation unit 109. For example, if 24-bit display data is input from the CPU 100, the data voltage generation unit 108 generates a 256-level data voltage, and the data Output to the voltage selector 110.

  The data voltage selection unit 110 selects one level from 256 levels of data voltage according to the value of the display data output from the latch circuit unit 107, and outputs the selected data voltage.

  The operational amplifier unit 111 is a known buffer for impedance conversion of the output of the data voltage selection unit 110, and is configured by a voltage follower circuit.

  The VGL binary-corresponding gate signal generation unit 112 performs line-sequential scanning voltage (VGH level in the first embodiment) indicating a selected state in synchronization with one scanning period with respect to a scanning line (gate line) of the display unit 114 described later. This is a block for outputting to. Although the output timing will be described later, the voltage level of the gate signal is determined based on the timing signal output from the VGL 2-value corresponding timing generation unit 106 based on the VGH and VGL 0 or VGL 1 generated by the VGL 2-value corresponding reference voltage generation unit 109. The level is shifted to a potential, and the level-shifted signal is output to the display device 114 as a gate signal.

  The common signal generation unit 113 switches between the common high voltage (VcomH) and the common low voltage (VcomL) generated by the VGL binary correspondence reference voltage generation unit 109 based on the timing signal output from the VGL binary correspondence timing generation unit 106. The common signal is output to the common common electrode on the opposite side of the display element.

  The display unit 114 is a known flat panel (display panel) called a so-called active matrix type in which switching transistors are arranged in each pixel unit 115 located at the intersection of a data line (drain line) and a scanning line (gate line). ).

  Next, FIG. 2 is a diagram for explaining a schematic configuration of the pixel portion arranged in a matrix on the display panel. Hereinafter, the configuration of the pixel portion 115 will be described with reference to FIG. As apparent from FIG. 2, in the pixel portion 115, a pixel composed of a transistor element (hereinafter referred to as TFT) and a display element (pixel capacitance) Cpix is formed at each intersection of the gate line Gn and the drain line Dm. ing. Further, a common line Cn for supplying a common voltage (common signal) that is an output of the common signal generation unit 113 is formed on a common common electrode (not shown) of the pixel. A gate signal for pixel selection from the VGL binary-compatible gate signal generation unit 112 is supplied to the gate line Gn, and a drain signal that is a writing voltage to the pixel is supplied from the operational amplifier unit 111 to the drain line Dm. It has become. A drain line is connected to the drain terminal of the TFT, and a gate line is connected to the gate terminal. In the configuration of the pixel portion 115 shown in FIG. 2, the common signal is input to the common electrode formed independently for each pixel through the common line Cn. However, the configuration is not limited thereto. The common electrode is formed so that the common electrode of the pixel adjacently arranged in the extending direction of the gate line Gn is directly connected, and a common signal is transmitted from one end of the display unit 114 or from both sides via the common line Cn. An input configuration may be used.

  The TFT has a source terminal connected to the display element Cpix and a storage capacitor Cst that reduces the loss of charge from the source terminal. A common common electrode is connected to the opposite side of the display element Cpix and the storage capacitor Cst, and a common signal is output to the common electrode. Therefore, in the scanning line in the selected state, the difference between the data voltage and the common voltage is the voltage applied to the display element Cpix. Further, a parasitic capacitance Cgs is attached between the source terminal of the TFT and the gate line. The type of display element is typically liquid crystal or the like, but scanning pulses are sequentially applied every scanning period, and a data voltage corresponding to display data on the selected scanning line is applied to the data line. Other elements may be used as long as the display luminance can be controlled.

  FIG. 3 is a circuit configuration diagram of the VGL binary-corresponding gate signal generation unit according to the first embodiment of the present invention. Hereinafter, based on FIG. 3, the VGL binary-corresponding gate signal generation unit 112 of the display device according to the first embodiment of the present invention. The structure of will be described.

  As shown in FIG. 3, the VGL binary corresponding gate signal generation unit 112 according to the first embodiment of the present invention includes a shift register circuit 300 and a level shifter circuit 301. The shift register circuit 300 is a circuit that shift-clocks the gate signal start pulse VST based on the vertical synchronization signal VCLK and the horizontal synchronization signal HCLK generated by the VGL binary correspondence timing generation unit 106. Further, the level shifter circuit 301 is based on the shift clock signals S0 to Sn + 1 generated by the shift register circuit 300 and the VGL voltage conversion signal TRA generated by the VGL binary corresponding timing generator 106, and the VGL binary corresponding reference voltage generator 109. The shift clock signals S0 to Sn + 1 are level-shifted to the VGH and VGL0 and VGL1 generated in Step 1, and the level-shifted shift clock signals are output as gate signals (output signals) G0 to Gn. Note that the voltages of VGL0 and VGL1 are voltages that can sufficiently turn off the TFT provided in the pixel portion 115, and the voltage relationship between VGL0 and VGL1 is VGL0> VGL1.

  Next, FIG. 4 shows a diagram for explaining the operation timing of the shift register circuit according to the first embodiment of the present invention. Hereinafter, the operation of the shift register circuit will be described with reference to FIG. However, FIG. 4A is a diagram showing the operation timing when the data voltage in the selected state changes to a high potential level, and FIG. 4B shows the data voltage in the selected state changed to a low potential level. It is a figure which shows the operation timing at the time.

  As described above, the shift register circuit 300 according to the first embodiment shifts the gate signal start pulse VST based on the vertical synchronization signal VCLK and the horizontal synchronization signal HCLK, and outputs it as the shift clock signals S0 to Sn + 1. Note that the VST start time Δt1 can be set by instruction data input from the CPU 100, and can also be set by instruction data in the high period Δt0 of the gate signal start pulse VST. With such a configuration, driving corresponding to any display panel 114 having a different number of pixels is possible. Further, the shift clock signals S0 to Sn + 1 have the same operation timing at the positive time shown in FIG. 4A and at the negative time in FIG. 4B.

  As shown in FIG. 4A, the VGL voltage conversion signal TRA changes in polarity in synchronization with the vertical synchronization signal VCLK. In the first embodiment, the rising (input) timing of the vertical synchronization signal VCLK. Synchronously with this, TRA = 1 (high level) indicating the positive polarity is obtained (T0). At this time, the horizontal synchronization signal HCLK is also output in synchronization with the rising timing of the vertical synchronization signal VCLK (T0). When the gate signal start pulse VST is input after the lapse of Δt1 period from the input of the vertical synchronization signal VCLK (T2 to T3), the shift operation of the shift register circuit 300 is started. By this shift operation, the 0th shift clock signal S0 becomes 1 horizontal synchronization period S0 = 1 (high level) in synchronization with the rising timing of the next horizontal synchronization signal HCLK, and the next horizontal synchronization signal HCLK rises. The timing returns to S0 = 0 (low level) (T3 to T4). At the rising timing of the horizontal synchronization signal HCLK when the 0th shift clock signal S0 becomes S0 = 0, the first shift clock signal S1, which is the next shift clock signal, becomes S1 = 1 (T4). . Thereafter, the shift operation described above is sequentially performed in synchronization with the horizontal synchronization signal HCLK, and when the (n + 1) th shift clock signal Sn + 1 = 1 is held for one horizontal period (hereinafter referred to as 1H period), it is input at timing T2. The shift operation by the gate signal start pulse VST thus completed is completed (T5).

  As shown in FIG. 4 (b), the period of the VGL voltage conversion signal TRA = 0 is also in the same way as the period of TRA = 1, first, in synchronization with the rising (input) timing of the vertical synchronization signal VCLK. TRA = 0 (low level) shown (T0). Thereafter, the shift operation of the shift register circuit 300 is started by the input of the gate signal start pulse VST, and when the (n + 1) -th shift clock signal Sn + 1 = 1 is held for 1H period, the gate signal input input at the timing T2 is started. A series of shift operations by the pulse VST ends (T5).

  Note that the polarity of the VGL voltage conversion signal TRA can be set by instruction data input from the CPU 100. When the data voltage in the selected state changes to a high potential level, TRA = 0, and the data voltage in the selected state changes. It is also possible to set TRA = 1 when changing to a low potential level.

  Next, FIG. 5 is a diagram for explaining a schematic configuration of the level shifter circuit according to the first embodiment of the present invention. Hereinafter, the configuration and operation of the level shifter circuit according to the first embodiment will be described with reference to FIG. 5A is a circuit configuration diagram of the level shifter circuit according to the first embodiment of the present invention, and FIG. 5B is a circuit configuration diagram of the nth level shifter according to the first embodiment of the present invention. FIG. 5C is a timing chart for explaining the operation of the level shifter shown in FIG.

As shown in FIG. 5A, the level shifter circuit 301 according to the first embodiment includes n + 1 level shifters 500 that are the same as the number of gate lines. Each level shifter 500 is configured to receive a VGL voltage conversion signal TRA, VGH, VGL0, and VGL1 from the VGL binary-corresponding reference voltage generation unit 109, and two shift clock signals. For example, the level shifter 500 that outputs the nth gate signal Gn includes:
Then, VGH, VGL0, VGL1 and two shift clock signals Sn, Sn + 1 from the VGL binary-corresponding reference voltage generation unit 109 are input. With this configuration, level shift is performed based on the shift clock signals S0 to Sn + 1 and the VGL voltage conversion signal TRA.

  Next, the configuration of the level shifter 500 according to the first embodiment will be described with reference to FIG. However, in the following description, the n-th level shifter 500 that outputs the n-th gate signal Gn will be described. However, the other level shifters 500 are different only in the two shift clock signals that are input. The same thing.

  As shown in FIG. 5B, the level shifter 500 according to the first embodiment is a well-known switch (switching which of the gate-on voltage VGH and the gate-off voltages VGL0 and VGL1 is supplied to the amplifier 506 based on the shift clock signal Sn. (Hereinafter referred to as SW.) 501 and 502 are provided. In addition, two SW503 and SW504 are connected in parallel to the analog voltage input side of SW502, and the gate-off voltage VGL0 is input to SW503, and the gate-off voltage VGL1 is input to SW504. Yes. The switching of the SWs 503 and 504 is controlled by an output signal Tn from an output terminal Q of a flip-flop (hereinafter referred to as FF) 505. When the output signal Tn is 1 (high level), the SW 503 When the output signal Tn is 0 (low level), the SW 504 is turned on. In the FF 505, the (n + 1) th shift clock signal Sn + 1 is connected to a clock input terminal (indicated by C), and the VGL voltage conversion signal TRA is connected to a data input terminal (indicated by D). With this configuration, it is possible to switch between two different gate-off voltages VGL0 and VGL1 that are characteristic of the level shifter 500 of the first embodiment. Note that the SWs 501 to 504 are configured to receive two signals: a signal via the inverter 507 and a signal input directly.

  That is, when the shift clock signal Sn = 1, SW501 is turned on and SW502 is turned off, so that the gate signal Gn outputs the VGH voltage. On the other hand, when the shift clock signal Sn = 0, SW501 is turned off and SW502 is turned on, so that a gate-off voltage is output to the gate signal Gn. The gate-off voltage level at this time is determined by the shift clock signal Sn + 1 and TRA input to the FF 505.

  Next, the operation timing of the FF 505 will be described with reference to FIG. When the shift clock signal Sn + 1 = 1, the on / off level of the VGL voltage conversion signal TRA is output as the output signal Tn (T2). Since the shift clock signal Sn + 1 becomes Sn + 1 = 1 only once per frame, the on / off level of the output signal Tn is held for one frame period (T4). When Tn = 1, SW503 is on and SW504 is off so that the output signal Gn outputs the VGL0 voltage. When Tn = 0, SW503 is off and SW504 is on, so the output signal Gn outputs the VGL1 voltage.

  That is, the FF 505 transfers the signal input to the D terminal at the timing (falling edge) when the shift clock signal Sn + 1 input to the C bar terminal changes from the high level to the low level until the falling edge of the next shift clock signal Sn + 1. It is the structure to hold. Therefore, at time T0, the VGL voltage conversion signal TRA becomes TRA = 1, but the output signal Tn holds Tn = 0. At time T1, the shift clock signal Sn + 1 changes to Sn + 1 = 1. At this timing, the output signal Tn is held at Tn = 0, and at time T2, the output signal Tn changes at the timing when the shift clock signal Sn + 1 changes to Sn + 1 = 0. Changes to Tn = 1. For the same reason, the VGL voltage conversion signal TRA becomes TRA = 0 at time T3 by the inversion operation accompanying the frame inversion driving, but the output signal Tn is held until Tn = 1 until time t4. As described above, in the first embodiment, in addition to the shift clock signal Sn related to the write operation of the nth gate line Gn, the shift clock signal Sn + 1 that is the shift clock signal next to the shift clock signal Sn is used. The gate-off voltage output to the nth gate line Gn is controlled. That is, by controlling ON / OFF of SW503 and SW504 at the falling edge of the next shift clock signal Sn + 1, the gate-off voltage output to the nth gate line Gn is changed from the gate-off voltage VGL0 to the gate-off voltage VGL1 for 1H period. The control is performed to change after the 1H period or from the gate-off voltage VGL1 to the gate-off voltage VGL0.

  FIG. 6 is a diagram for explaining the timing of writing display data to the pixel in the display device according to the first embodiment of the present invention. In particular, FIG. 6A shows that the potential of the common electrode is lower than the potential of the pixel electrode. FIG. 6B is a diagram showing the write timing when the potential of the common electrode is higher than the potential of the pixel electrode (at the time of the negative electrode).

  The operation timing shown in FIG. 6A shows the operation timing when the data voltage when the gate is turned on changes to a high potential. When the gate signal 603 is output as the VGH voltage, the TFT in the pixel portion 115 is turned on. A data voltage 605 is applied as a drain signal to the source terminal. At this time, in the high-resolution display panel, the 1H period from T1 to T2 is shortened, and the potential of the source terminal (source signal 603), that is, the pixel electrode reaches the data voltage 605 as shown in FIG. (T2), the potential is reduced by ΔV with respect to the desired source potential 604. Here, in the conventional display device, as shown in the left diagram of FIG. 6A, the gate signal 601 outputs a one-value VGL voltage after the writing is completed (period after T2). The effective voltage decreases by ΔV for one frame period, resulting in a decrease in luminance.

  On the other hand, in the display device according to the first embodiment, as shown in the write operation timing with the VGL2 value in the right diagram in FIG. 6A, the gate-off voltage after 1H period (T5) after completion of the write at T4. Is switched from VGL1 to VGL0, and the potential of the TFT source terminal, that is, the pixel electrode is increased by ΔV due to the coupling fluctuation of the parasitic capacitance Cgs between the source terminal of the TFT in the pixel portion 115 and the gate line. Since the potential 607 can be obtained, a reduction in luminance can be suppressed.

  That is, in the display device of Embodiment 1, when the gate-on voltage VGH of the gate signal 606 is input and the TFT is turned on (T3), the drain signal 605 is applied to the source terminal of the TFT to which the pixel electrode is connected as the source signal 607. Supplied. At this time, when the gate signal 606 returns to the gate-off voltage VGL1 which is the gate-off voltage at time T4 as in the conventional case, the potential of the pixel electrode, that is, the voltage level of the source terminal is also shown as the source signal 607. Is a potential reduced by ΔV. Here, in the display device of the first embodiment, the gate signal 606 returns to the gate-off voltage VGL1 at time T4 and rises by ΔV to the gate-off voltage VGL0 at time T5 after the 1H period has elapsed. As a result, the potential of the TFT source terminal, that is, the pixel electrode is increased by ΔV due to the coupling fluctuation of the parasitic capacitance Cgs between the TFT source terminal and the gate line of the pixel portion 115, and a desired source potential 607 can be obtained.

  On the other hand, as shown in FIG. 6B, when the data voltage at the gate-on time changes to a low potential, the gate-off voltage is switched from VGL0 to VGL1 1H after the end of the write operation. Due to the coupling fluctuation of the parasitic capacitance Cgs, the potential of the source terminal of the TFT is decreased by ΔV and a desired source potential is obtained, so that a decrease in luminance is suppressed.

  That is, when the gate-on voltage VGH of the gate signal 606 is input and the TFT is turned on (T3), the drain signal 605 is supplied as the source signal 607 to the source terminal of the TFT to which the pixel electrode is connected. As a result, the potential of the pixel electrode shown in FIG. At this time, when the gate signal 616 returns to the gate-off voltage VGL0, which is the gate-off voltage, at the time T4 as in the conventional case, the potential of the pixel electrode, that is, the voltage level of the source terminal is also shown as the source signal 607. As a result, only ΔV is higher. Here, in the display device according to the first embodiment, the gate signal 606 returns to the gate-off voltage VGL0 at time T4 and decreases to the gate-off voltage VGL1 by ΔV at time T5 after 1H period has elapsed. As a result, the potential of the TFT source terminal, that is, the pixel electrode is reduced by ΔV due to the coupling fluctuation of the parasitic capacitance Cgs between the TFT source terminal and the gate line of the pixel portion 115, and a desired source potential 607 can be obtained.

  Note that the potential difference ΔV between the gate-off voltage VGL0 and the gate-off voltage VGL1 can be calculated from the display element Cpix, the storage capacitor Cst, the parasitic capacitance Cgs, and the underapplied voltage ΔV. For example, since the jump voltage of the parasitic capacitance Cgs is calculated from the capacitance ratio between the parasitic capacitance Cgs in one pixel and the total capacitance including the parasitic capacitance Cgs and the amount of change in the applied voltage, the following equation (1) Shows the calculation formula.

VGL0−VGL1 = (Cpix + Cst + Cgs) / Cgs × ΔV (1)
As described above, in a high-resolution display device, the coupling fluctuation of the parasitic capacitance Cgs between the source terminal of the TFT and the gate line is switched by switching the binary gate-off voltage after 1 H has passed after applying the data voltage. As a result, the potential of the source terminal of the TFT can be corrected to a desired source potential.

  In FIGS. 6A and 6B, the operation timing has been described in the frame inversion driving in which the polarity is changed for each frame. However, the operation timing is not limited to this. The effect of the present invention can be sufficiently obtained even in dot inversion driving for inverting the polarity.

  Although the common electrode is connected to the opposite side of the display element Cpix and the storage capacitor Cst, the present invention is not limited to this, and the present invention can be applied without any problem to a display device in which a common line is wired for each line.

  The binary gate-off potential is switched in synchronization with the Sn + 1 shift clock signal. However, the present invention is not limited to this. For example, a switching clock that can be arbitrarily set by the user after the VST start time Δt1 + 3H period is set to VGL2. A switching signal generated by the value-corresponding timing generator 106 and shifted by the VGL binary-corresponding gate signal generator 112 is input instead of the shift clock signal Sn + 1 in FIG. The user can arbitrarily set the switching timing of the binary gate-off voltage. However, desired luminance can be obtained by switching the binary gate-off voltage in a short period from the end of the selection period.

  In the first embodiment, the case where a liquid crystal display panel is used as the display panel has been described. However, the present invention is not limited to this. For example, the display panel is also used for driving other display panels such as an organic EL display panel and an inorganic EL display panel. Applicable.

  Furthermore, the present invention is not limited to a mobile display device, and can be applied to a large display device for television or the like.

  As described above, in the display device according to the first exemplary embodiment of the present invention, the VGL binary-compatible gate signal generation unit 112 that outputs to the gate line the voltage for switching the on state that is the TFT selection operation or the off state that is the non-selection operation. And a driver having an operational amplifier 111 that supplies a voltage corresponding to display data to the drain line, and a common signal generation unit that supplies a common signal to the common common electrode. The scanning voltage for selecting the TFT, the gate-off voltage VGL1 for setting the TFT in the non-selected state, and the gate-off voltage VGL0 for generating a transistor element in the non-selected state that is higher than the gate-off voltage VGL1. A gate-off voltage is applied to the gate line from the VGL binary corresponding gate signal generation unit, and each TFT When a voltage higher than the voltage applied to the common common electrode is supplied to the drain line when switching from the selected state to the non-selected state, the VGL2 value-corresponding gate signal generation unit uses the gate-off voltage VGL1 as a gate line for a predetermined period. When the gate-off voltage VGL0 is output to the gate line after being output for 1H period and a voltage lower than the voltage applied to the common common electrode is supplied to the drain line, the VGL binary-corresponding gate signal generator generates the gate-off voltage Since the gate-off voltage VGL1 is output to the gate line after VGL0 is output to the gate line for a predetermined period of 1H, the coupling variation of the parasitic capacitance Cgs between the source terminal of the TFT and the gate line causes the TFT The potential of the source terminal of the pixel can be corrected to a desired source potential, that is, the potential of the pixel electrode Come, it becomes possible to display a desired display luminance.

<Embodiment 2>
FIG. 7 is a block diagram for explaining a schematic configuration of the display device according to the second embodiment of the present invention. Hereinafter, the display device according to the second embodiment will be described with reference to FIG. The basic configuration and effect of the second embodiment are the same as those of the display device of the first embodiment. Therefore, in the following description, the configuration of the VGL 3-value compatible memory control unit 700, the VGL 3-value compatible timing control unit 701, the VGL 3-value compatible reference voltage generation unit 702, and the VGL 3-value compatible gate signal generation unit 703, which is different from the display device of the first embodiment. The operation will be described in detail.

  The VGL 3-value compatible memory control unit 700 controls the write and read operations of the display memory 105, compares pixel values on the upper and lower sides of each adjacent horizontal line, and outputs an output signal STRA0 based on the comparison result. Is configured to switch. The details of the VGL 3-value compatible memory control unit 700 will be described later.

  Similar to the VGL 2-value compatible timing control unit 106 of the first embodiment, the VGL 3-value compatible timing control unit 701 self-generates a signal group instructing one scanning period or one frame period based on the reference clock generated by the built-in oscillator. And output. Furthermore, a gate-off voltage switching signal, which is a feature of the second embodiment, is output to the VGL 3-value corresponding gate signal generation unit 703.

  The VGL 3-value corresponding reference voltage generation unit 702 generates ternary voltages of gate-off voltages VGL0, VGL1, and VGL2, which are reference voltages for output to the gate terminal of the TFT when the gate is off. The gate-off voltages VGL0, VGL1, and VGL2 are generated from the input power supply voltage Vci, the gate-on voltage VGH required by the VGL 3-value corresponding gate signal generation unit 703, and the ternary gate-off voltages VGL0 and VGL1 that are the characteristics of the second embodiment. , VGL2 is generated. Note that the gate-off voltages VGL0, VGL1, and VGL2 are voltages that can sufficiently turn off the TFT provided in the pixel portion 115, and the voltage relationship between the ternary gate-off voltages VGL0, VGL1, and VGL2 is VGL0> VGL1. > VGL2.

  The VGL three-value corresponding gate signal generation unit 703 applies a gate-on voltage VGH that is a scanning voltage indicating a selected state and gate-off voltages VGL0, VGL1, and VGL2 that indicate a non-selected state to the scanning line of the display unit 114 in synchronization with one scanning period. This is a block for outputting line-sequentially. Although the output timing will be described later, the voltage level of the gate signal is determined based on the timing signal output from the VGL 3-value corresponding timing generation unit 701, and the VGH, VGL0, VGL1, The level is shifted to the potential of VGL2, and the level-shifted signal is output to the display device 114 as a gate signal.

  FIG. 8 is a diagram for explaining a schematic configuration of the VGL 3-value compatible memory control unit 700 according to the second embodiment. In particular, FIG. 8A shows a block configuration of the VGL 3-value compatible memory control unit 700. It is a figure for demonstrating the block configuration of the display data determination circuit 801. FIG. Hereinafter, the display device according to the second embodiment will be described with reference to FIG.

  As shown in FIG. 8A, the VGL 3-value compatible memory control unit 700 according to the second embodiment includes a display memory control circuit 800 and a display determination circuit 801. The display memory 800 is a block that performs the write and read operations of the display memory unit 105. The display memory 800 outputs a signal for selecting an address of the display memory unit 105 based on the display position instruction transferred from the register unit 103 during the write operation. At the same time, the display data is transferred to the display memory unit 105. With this operation, display data can be written to a predetermined address in the display memory unit 105.

  On the other hand, during the read operation of the display memory 800, the operation of sequentially selecting a predetermined word line group one by one in the display memory unit 105 is repeated. With this operation, the display data on the selected word lines can be read all at once via the bit lines. It should be noted that setting of the range of the word line to be read, one selection period (equivalent to one scanning period), selection operation repetition period (equivalent to one frame period), and the like are instructed by the instruction.

  Next, the display data determination circuit 801 will be described with reference to FIG. The display data determination circuit 801 includes a line memory control circuit 802, an n−1 line display data line memory 807, an n line display data line memory 808, and a display data comparison circuit 809.

  The line memory control circuit 802 is a signal for selecting the addresses of the line memory 807 for n−1 line display data and the line memory 808 for n line display data based on the register data which is the instruction of the display position transferred from the register unit 103. Simultaneously with the output of (803.805), the display data (804.806) is transferred to the line memories 807.808. On the other hand, when the display data in the line memories 807 and 808 is transferred to the display data comparison circuit 809, predetermined pixel groups in the line memories 807 and 808 are sequentially selected.

  The display data comparison circuit 809 compares the pixel unit data output from the line memories 807 and 808, and if the n-line display data is larger than the n-1 line display data, the counter in the display data 809 is displayed. Count up at. This operation is performed for 1H period, and if the count value is more than half of the number of one horizontal pixel, the output signal STRA0 is output as “1”, and if the count value is less than half of the number of one horizontal pixel, the output signal STRA0 is set to “0”. "Is output.

  FIG. 9 is a diagram for explaining the operation timing of the VGL 3-value correspondence timing generation unit according to the second embodiment. Hereinafter, the operation of the VGL 3-value correspondence timing generation unit 701 according to the second embodiment will be described with reference to FIG.

  The VGL 3-value corresponding timing generation unit 701 outputs the STRA0 signal output from the VGL 3-value compatible memory control unit 700 as STRA1 after the VST start time Δt1 + 2H during the positive polarity. on the other hand. At the negative polarity, the STRA0 signal is output as STRA1 as a signal obtained by inverting the polarity after the VST start time Δt1 + 2H. The VST start time Δt1 can be set by instruction data input from the CPU 100. As described above, in the VGL 3-value correspondence timing generation unit 701 of the second embodiment, a gate signal (not shown) that is input (T1) after the Δt1 period (2H period in FIG. 9) has elapsed from the input (T0) of the vertical synchronization signal VCLK. The STRA0 signal is output as STRA1 at the time of positive polarity after a further 2H period from the rising edge of the start pulse VST (T2). On the other hand, when negative, a signal obtained by inverting the STRA0 signal is output as STRA1 (T2).

  FIG. 10 is a diagram for explaining a schematic configuration of the level shifter circuit according to the second embodiment, and FIG. 11 is a timing diagram for explaining the operation of the level shifter circuit according to the second embodiment. 10A is a block configuration diagram of a level shifter circuit, and FIG. 10B is a circuit configuration diagram of a level shifter.

  Hereinafter, the VGL 3-value corresponding gate signal generation unit 703 will be described with reference to FIGS. 10 and 11.

  As shown in FIG. 10A, the VGL 3-value corresponding gate signal generation unit 703 includes a shift register circuit 300 and a level shifter circuit 1000. The shift register circuit 300 has the same operation timing as the operation timing described in the first embodiment. Further, the level shifter circuit 1000 uses the level shifter 1001 based on the STRA1 output from the VGL three-value corresponding timing generation unit 701 and the shift clocks S0 to Sn + 1 output from the shift register circuit 300, and uses the level shifter 1001. The level shift is performed to the ternary voltages of the gate-on voltage VGH and the gate-off voltages VGL0, VGL1, and VGL2 that are generated in the above.

  Next, the structure of the level shifter 1001 of Embodiment 2 is demonstrated based on FIG.10 (b). However, in the following description, the n-th level shifter 1001 that outputs the n-th gate signal Gn will be described. The other level shifters 1001 are different only in the two shift clock signals that are input. The same thing. The basic configuration of the level shifter 1001 of the second embodiment is the same as that of the level shifter 500 of the first embodiment. Therefore, in the following description, a configuration different from the level shifter 500 of the first embodiment will be described in detail. However, regarding the SWs 501 to 504 and the FF 505, the operation described in the first embodiment is performed.

  As shown in FIG. 10B, the SW504 is configured to receive the gate-off voltage VGL2. The SW 504 is configured such that when the output signal Tn from the output terminal Q of the FF 505 is 0 (low level), the SW 504 is turned on and the gate-off voltage VGL2 is output to the SW 502.

  Further, in the level shifter 1001 of the second embodiment, the SW 1002 is connected in parallel to the SWs together with the SW 503 and the SW 504 connected in parallel. The SW 1002 is configured to receive a gate-off voltage VGL1. The SW 1002 is controlled by a shift clock signal Sn + 1 input to a clock input terminal (indicated by C) of the FF 505. The SW 1002 is turned on when the shift clock Sn + 1 is “1”, and outputs the voltage VGL1 to the gate signal Gn as an output.

  Next, the operation timing of the level shifter circuit 1000 will be described with reference to FIG. However, in the following description, the four gate signals from the gate signal Gn-3 to the gate signal Gn will be described in detail.

As is clear from FIG.
The gate signal Gn-3 outputs the VGH voltage because the shift clock signal Sn-3 is “1” in the first period. In the second period, the VGL1 voltage is output because the shift clock signal Sn-2 is "1". In the third period, since the output signal Tn-3 of the FF 505 is “1”, the VGL0 voltage is output. In the fourth to sixth periods, the VGL0 voltage is output as in the third period.

  The gate signal Gn-2 outputs VGL0 that is the output voltage until then in the first period. In the second period, the VGH voltage is output because the shift clock signal Sn-2 is “1”. In the third period, the voltage VGL1 is output because Sn-1 is “1”. In the fourth period, since the output signal Tn-2 of the FF 505 is “0”, the VGL2 voltage is output. In the fifth and sixth periods, the VGL2 voltage is output as in the fourth period.

  The gate signal Gn-1 outputs VGL0 that is the output voltage until then in the first and second periods. In the third period, the VGH voltage is output because the shift clock signal Sn-1 is “1”. In the fourth period, the voltage VGL1 is output because Sn is “1”. In the fifth period, since the output signal Tn−1 of the FF 505 is “0”, the VGL2 voltage is output. In the sixth period, the VGL2 voltage is output as in the fifth period.

  The gate signal Gn outputs the VGL2 voltage that is the output voltage until then in the first to third periods. In the fourth period, the VGH voltage is output because the shift clock signal Sn is “1”. In the fifth period, the VGL1 voltage is output because the shift clock signal Sn + 1 is “1”. In the sixth period, since the output signal Tn of the FF 505 is “1”, the VGL0 voltage is output.

  As the write operation, as in FIGS. 6A and 6B of the first embodiment, the potential of the TFT source terminal is changed by the coupling fluctuation of the parasitic capacitance Cgs between the TFT source terminal and the gate line. It will be corrected to the desired source potential.

  As described above, by switching the ternary gate-off voltage according to the display data for each line, the potential of the TFT source terminal can be set to a desired value due to the coupling fluctuation of the parasitic capacitance Cgs between the TFT source terminal and the gate line. It becomes possible to correct to the source potential of.

  That is, in the display device according to the second embodiment of the present invention, a VGL three-value corresponding gate signal generation unit 703 that outputs a voltage for switching an ON state that is a TFT selection operation or an OFF state that is a non-selection operation to a gate line, and display data And a common signal generation unit for supplying a common signal to the common common electrode. Here, the VGL 3-value corresponding gate signal generation unit 703 generates a scanning voltage for selecting the TFT and a gate-off voltage VGL0, VGL1, and VGL2 for setting the TFT in a non-selected state. When a gate-off voltage is applied to the gate line and each TFT is changed from the selected state to the non-selected state, the VGL 3-value corresponding memory control unit 700 monitors the display data for each line, and 3 based on the monitoring result and the common signal. Since the two gate-off voltages VGL0, VGL1, and VGL2 are switched and applied to the gate terminal of the TFT, the potential of the TFT source terminal is changed by the coupling fluctuation of the parasitic capacitance Cgs between the source terminal of the TFT and the gate line. A desired source potential, that is, a potential of the pixel electrode can be corrected to a desired potential, and display with a desired display luminance is possible.

It is a block diagram for demonstrating schematic structure of the display apparatus which concerns on Embodiment 1 of this invention. FIG. 3 is a diagram for explaining a schematic configuration of pixel units arranged in a matrix on the display panel according to the first embodiment of the present invention. It is a circuit block diagram of the VGL binary corresponding | compatible gate signal generation part of Embodiment 1 of this invention. It is a figure for demonstrating the operation timing of the shift register circuit of Embodiment 1 of this invention. It is a figure for demonstrating schematic structure of the level shifter circuit of Embodiment 1 of this invention. FIG. 5 is a diagram for explaining display data writing timing to a pixel in the display device according to the first embodiment of the present invention. It is a block diagram for demonstrating schematic structure of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating schematic structure of the VGL 3-value corresponding | compatible memory control part of Embodiment 2 of this invention. It is a figure for demonstrating the operation timing of the VGL 3-value corresponding | compatible timing generation part of Embodiment 2 of this invention. It is a figure for demonstrating schematic structure of the level shifter circuit of Embodiment 2 of this invention. It is a timing diagram for demonstrating operation | movement of the level shifter circuit of Embodiment 2 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... CPU, 101 ... Drive circuit, 102 ... System interface part, 103 ... Register part, 104 ... Memory control part, 105 ... Display memory part, 106 ... VGL2 value Corresponding timing generation unit, 107 ... latch circuit unit, 108 ... data voltage generation unit, 109 ... VGL binary correspondence reference voltage generation unit, 110 ... data voltage selection unit, 111 ... operational amplifier unit, 112: VGL binary-corresponding gate signal generation unit, 113: common signal generation unit, 114: display unit, 115: pixel unit, 300: shift register circuit, 301: level shifter circuit, 500 ... Level shifter, 501 ... SW1, 502 ... SW2, 503 ... SW3, 504 ... SW4, 505 ... FF, 506 ... 507... Inverter 700... VGL 3-value compatible memory control unit 701... VGL 3-value compatible timing generation unit 702. Signal generation unit, 800 ... display memory control circuit, 801 ... display data determination circuit, 802 ... line memory control circuit, 803 ... n-1 line memory address selection signal, 804 ... n −1 line memory display data, 805... N line memory address selection signal, 806... N line memory display data, 807... N−1 line display data line memory, 808. Line display data line memory, 809... Display data comparison circuit, 1001... Level shifter, 1002. Transistor elements, Cst · · · holding capacitor, Cpix · · · display device (pixel capacitor), the parasitic capacitance between the gate and source of the Cgs · · · transistor element

Claims (11)

A display panel comprising a plurality of drain lines and a plurality of gate lines intersecting the drain lines, wherein a transistor element is formed for each pixel electrode in a pixel region surrounded by the drain lines and the gate lines. A driving device for driving,
A first driver for outputting a voltage for switching selection or non-selection of the transistor element to the gate line;
A second driver for supplying a voltage corresponding to display data to the drain line;
A third driver for supplying a common signal to the common common electrode,
The first driver has a scanning voltage for selecting the transistor element, a first non-scanning voltage for deselecting the transistor element, and a voltage higher than the first non-scanning voltage, A second non-scanning voltage for deactivating the transistor element;
When applying a non-scanning voltage from the first driver to the gate line to change each transistor element from a selected state to a non-selected state,
When a voltage higher than the voltage applied to the common common electrode is supplied to the drain line,
The first driver outputs the second non-scanning voltage to the gate line after outputting the first non-scanning voltage to the gate line for a predetermined period;
When a voltage lower than the voltage applied to the common common electrode is supplied to the drain line,
The first driver outputs the first non-scanning voltage to the gate line after outputting the second non-scanning voltage to the gate line for a predetermined period. The drive device according to claim 1,
The driving device according to claim 1, wherein the first non-scanning voltage and the second non-scanning voltage are voltage values capable of turning off the transistor element. In the drive device according to claim 1 or 2,
The driving device characterized in that a period for outputting the first non-scanning voltage to the gate line and a period for outputting the second non-scanning voltage to the gate line can be arbitrarily set. The drive device according to any one of claims 1 to 3,
The voltage difference between the first non-scanning voltage and the second non-scanning voltage is:
A capacitance of the pixel, a storage capacitor Cst formed for each pixel, and a parasitic capacitance Cgs between the gate and the source of the transistor element;
An ideal applied voltage that is a difference between a voltage applied to the common common electrode in the selected state and a voltage corresponding to display data;
A jump voltage based on the parasitic capacitance Cgs when the scan voltage is changed to the non-scan voltage;
A driving device that calculates based on an actual applied voltage that is a difference between a potential of the common common electrode in a non-selected state and a potential of a source terminal of the transistor element. A display panel comprising a plurality of drain lines and a plurality of gate lines intersecting the drain lines, wherein a transistor element is formed for each pixel electrode in a pixel region surrounded by the drain lines and the gate lines. A driving device for driving,
A first driver for outputting a voltage for switching selection or non-selection of the transistor element to the gate line;
A second driver for supplying a voltage corresponding to display data to the drain line;
A third driver for supplying a common signal to the common common electrode;
The first driver has a scanning voltage for selecting the transistor element, a first non-scanning voltage for deselecting the transistor element, and a voltage higher than the first non-scanning voltage, A second non-scanning voltage that causes the transistor element to be in a non-selected state; and a third non-scanning voltage that is higher than the second non-scanning voltage and that causes the transistor element to be in a non-selected state;
When applying a non-scanning voltage from the first driver to the gate line to change each transistor element from a selected state to a non-selected state,
When a voltage higher than the voltage applied to the common common electrode is supplied to the drain line,
The first driver outputs the second non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period,
When a voltage lower than the voltage applied to the common common electrode is supplied to the drain line,
The first driver outputs the first non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period. The drive device according to claim 5, wherein
The voltage values of the first non-scanning voltage, the second non-scanning voltage, and the third non-scanning voltage are voltage values that can turn off the transistor element. apparatus. The drive device according to claim 5 or 6,
A period for outputting the first non-scanning voltage to the gate line; a period for outputting the second non-scanning voltage to the gate line; and a period for outputting the third non-scanning voltage to the gate line. Can be arbitrarily set. A display panel having a plurality of drain lines and a plurality of gate lines intersecting the drain lines, wherein a transistor element is formed for each pixel electrode in a pixel region surrounded by the drain lines and the gate lines When,
A first driver for outputting a voltage for switching selection or non-selection of the transistor element to the gate line;
A second driver for supplying a voltage corresponding to display data to the drain line;
A display device comprising: a third driver for supplying a common signal to the common common electrode;
The first driver has a scanning voltage for selecting the transistor element, a first non-scanning voltage for deselecting the transistor element, and a voltage higher than the first non-scanning voltage, A second non-scanning voltage for deactivating the transistor element;
When applying a non-scanning voltage from the first driver to the gate line to change each transistor element from a selected state to a non-selected state,
When a voltage higher than the voltage applied to the common common electrode is supplied to the drain line,
The first driver outputs the second non-scanning voltage to the gate line after outputting the first non-scanning voltage to the gate line for a predetermined period;
When a voltage lower than the voltage applied to the common common electrode is supplied to the drain line,
The display device, wherein the first driver outputs the first non-scanning voltage to the gate line after outputting the second non-scanning voltage to the gate line for a predetermined period. A display panel having a plurality of drain lines and a plurality of gate lines intersecting the drain lines, wherein a transistor element is formed for each pixel electrode in a pixel region surrounded by the drain lines and the gate lines When,
A first driver for outputting a voltage for switching selection or non-selection of the transistor element to the gate line;
A second driver for supplying a voltage corresponding to display data to the drain line;
A display device comprising: a third driver for supplying a common signal to the common common electrode;
The first driver has a scanning voltage for selecting the transistor element, a first non-scanning voltage for deselecting the transistor element, and a voltage higher than the first non-scanning voltage, A second non-scanning voltage that causes the transistor element to be in a non-selected state; and a third non-scanning voltage that is higher than the second non-scanning voltage and that causes the transistor element to be in a non-selected state;
When applying a non-scanning voltage from the first driver to the gate line to change each transistor element from a selected state to a non-selected state,
When a voltage higher than the voltage applied to the common common electrode is supplied to the drain line,
The first driver outputs the second non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period,
When a voltage lower than the voltage applied to the common common electrode is supplied to the drain line,
The display device, wherein the first driver outputs the first non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period. A scanning voltage for selecting a transistor element; a first non-scanning voltage for deselecting the transistor element; and a voltage higher than the first non-scanning voltage; A first driver that outputs to the gate line a voltage that switches between selection and non-selection of the transistor element,
A second driver for supplying a voltage corresponding to the display data to the drain line;
And a third driver for supplying a common signal to a common common electrode, and the transistor element is formed for each pixel electrode in a pixel region surrounded by the drain line and the gate line. And
When applying a non-scanning voltage from the first driver to the gate line to change each transistor element from a selected state to a non-selected state,
When a voltage higher than the voltage applied to the common common electrode is supplied to the drain line,
Outputting the second non-scanning voltage to the gate line after the first driver outputs the first non-scanning voltage to the gate line for a predetermined period;
When a voltage lower than the voltage applied to the common common electrode is supplied to the drain line,
And a step of outputting the first non-scanning voltage to the gate line after the first driver outputs the second non-scanning voltage to the gate line for a predetermined period. Driving method. A scanning voltage for selecting a transistor element; a first non-scanning voltage for deselecting the transistor element; and a voltage higher than the first non-scanning voltage; A second non-scanning voltage, and a third non-scanning voltage that is higher than the second non-scanning voltage and puts the transistor element into a non-selection state. A first driver that outputs a voltage for switching selection to the gate line;
A second driver for supplying a voltage corresponding to the display data to the drain line;
A third driver for supplying a common signal to the common common electrode;
A display panel driving method in which the transistor element is formed for each pixel electrode in a pixel region surrounded by the drain line and the gate line,
When applying a non-scanning voltage from the first driver to the gate line to change each transistor element from a selected state to a non-selected state,
When a voltage higher than the voltage applied to the common common electrode is supplied to the drain line,
The first driver outputting the second non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period;
When a voltage lower than the voltage applied to the common common electrode is supplied to the drain line,
The first driver includes a step of outputting the first non-scanning voltage to the gate line after outputting the third non-scanning voltage to the gate line for a predetermined period. Driving method.

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