JP2010103153A - Circuit board and method of producing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board which ensures adhesion of solder resist onto an insulating layer after a metal foil is removed even in a case where a metal foil having a low surface roughness on the surface adhering to the insulating layer is used, while exhibiting excellent reliability for PCT, having fine wiring, and reducing transmission loss of high frequency signal. <P>SOLUTION: In a circuit board having a conductor pattern which is formed by removing the metal foil from a laminate with a metal foil where a metal foil is bonded onto an insulating layer, a rough surface shape is formed on the surface of the insulating layer which is exposed after removing the metal foil. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit board and a manufacturing method thereof, and more particularly to a circuit board having fine wiring and used for high frequency applications and a manufacturing method thereof.

  In general, copper foil is used as the metal foil of the laminate with metal foil used for the production of the circuit board, and the surface in contact with the resin has a ten-point average roughness (for the purpose of improving the adhesion with the resin) Hereinafter, the shape (roughened surface shape) roughened to an uneven shape of about 7 to 8 μm is given.

  In recent years, circuit boards mounted on information terminal devices such as personal computers and mobile phones have been required to process large amounts of information at high speed, and it is necessary to increase the speed of signal processing and reduce transmission loss. ing. In addition, a finer wiring pattern is required due to the demand for higher density. Along with this, the copper foil of the laminate with metal foil used for the circuit board is also roughened from the viewpoint of securing the interlayer distance (insulating layer thickness), the importance of impedance control, and the formability of fine wiring by etching. Is getting smaller. For this reason, circuit boards using a so-called low profile Rz 2.7-3.3 μm copper foil or a profile free Rz 1.1-1.5 μm copper foil as conductor patterns have been proposed. (Patent Documents 1 and 2, Non-Patent Document 1).

When a circuit board is formed, a solder resist is formed on the conductor pattern and the insulating layer after removing the copper foil at unnecessary portions and forming the conductor pattern on the insulating layer. As a method for improving the adhesion of the solder resist on the conductor pattern, a method of roughening the circuit surface after circuit formation has been proposed (Patent Document 3).
Japanese Patent Laying-Open No. 2005-072493 JP 2008-111188 A Nobuyuki Ogawa and four others, “Profile-free copper foil technology for fine wiring formation”, Hitachi Chemical Technical Report, Japan, January 2006, No. 46 (2006-1), p. 15-18 JP H11-191482 A

  However, a circuit board mounted on an information terminal device or the like may be required to have durability in a PCT (pressure cooker test) that is a durability promotion test. In this PCT, there was a case where the solder resist formed on the circuit board was insufficiently adhered and peeled off.

  On the other hand, considering the formability of fine wiring and transmission loss at high frequencies, it is desirable that the copper foil used for conductor pattern formation has a smaller surface roughness, so the surface of the mat surface that is in close contact with the insulating layer of the circuit board There is a tendency to use low profile copper foil or profile free copper foil with low roughness. Since the surface roughness of the surface of the insulating layer after the copper foil having such a small surface roughness is removed by etching, there is a problem that it is difficult to ensure the adhesion of the solder resist in PCT.

  In Patent Document 4, although the adhesion of the solder resist on the conductor pattern is improved, there is a problem that it is difficult to ensure the adhesion of the solder resist on the insulating layer because the surface is not roughened on the insulating layer. It was.

  The present invention has been made in view of the above problems, and ensures the adhesion of the solder resist on the insulating layer after removing the metal foil, even when a metal foil having a small surface roughness on the surface in close contact with the insulating layer is used. An object of the present invention is to provide a circuit board that is excellent in reliability with respect to PCT, has fine wiring, and has low transmission loss of high-frequency signals.

The present invention relates to the following.
(1) In a circuit board having a conductor pattern formed by removing the metal foil of a laminated sheet with a metal foil laminated with a metal foil on an insulating layer, on the surface of the exposed insulating layer after the metal foil is removed A circuit board with a rough surface.
(2) The circuit board according to (1), wherein the surface roughness of the exposed insulating layer surface is larger than the surface roughness of the insulating layer surface in contact with the conductor pattern.
(3) The circuit board according to (1) or (2), wherein the metal foil is a profile-free copper foil.
(4) The circuit board according to any one of (1) to (3), wherein the rough surface is formed by plasma processing.
(5) In the manufacturing method of a circuit board having a conductor pattern formed by removing the metal foil of the laminated sheet with the metal foil laminated with the metal foil on the insulating layer, the conductor pattern is formed by removing the metal foil. A method for manufacturing a circuit board, comprising: a step; and a step of forming a rough surface shape on the exposed surface of the insulating layer.
(6) A method for manufacturing a circuit board according to (5), wherein a profile-free copper foil is used as the metal foil.
(7) The method for manufacturing a circuit board according to (5) or (6), wherein the step of forming a rough surface includes plasma treatment.

  According to the present invention, even when a profile-free copper foil is used, it is possible to ensure adhesion of the solder resist on the insulating layer after removing the copper foil, which is excellent in reliability with respect to PCT and has fine wiring. It is possible to provide a circuit board having a low transmission loss of high-frequency signals.

  The circuit board referred to in the present invention is used as a wiring board or a semiconductor mounting board. For example, as shown in FIG. 1, the laminated board 1 with a metal foil in which a metal foil 4 is laminated on an insulating layer 3 is used. What has the conductor pattern 6 formed by removing the unnecessary part of the said metal foil 4 is mentioned.

  In the present invention, the insulating layer 3 refers to an insulating substrate, a core substrate, a film, an interlayer insulating layer, a build-up layer, and the like formed using an organic insulating material. The insulating layer 3 used in the present invention has a surface that is in close contact with the metal foil 4 or an exposed surface after the metal foil 4 that has been in close contact is removed. That is, the insulating layer 3 used in the present invention is in a state where the surface shape of the metal foil 4 is transferred to the surface thereof. Here, the surface shape of the metal foil 4 refers to the surface shape of a surface (usually corresponding to a so-called mat surface) of the metal foil 4 that is in close contact with the insulating layer 3. Usually, since the metal foil 4 and the insulating layer 3 are laminated and integrated to form the laminated sheet 1 with the metal foil, the surface shape of the metal foil 4 is on the surface of the insulating layer 3 that is in close contact with the metal foil 4. Transferring forms a so-called replica. As the insulating layer 3, those used for the circuit board 11 such as a general wiring board or a semiconductor mounting board can be used. For example, a glass epoxy substrate or a glass polyimide substrate using a prepreg in which a glass cloth is impregnated with an epoxy resin or a polyimide resin, an adhesive sheet mainly composed of a high molecular weight epoxy resin, or the like can be used. Examples of the prepreg include GEA679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.), and examples of the adhesive sheet include AS-3000, AS-2600W (both manufactured by Hitachi Chemical Co., Ltd.).

  The metal foil 4 used in the present invention may be any metal foil that can be used for forming the conductor pattern 6 of the circuit board 11 and is not particularly limited. From the viewpoint of good conductivity, a copper foil or an aluminum foil is preferable. In particular, a copper foil is desirable from the viewpoint of versatility, and an electrolytic copper foil, a rolled copper foil, or the like can be used as the copper foil.

  Moreover, as a copper foil, for the purpose of improving the adhesiveness with the insulating layer 3, the surface roughness of the surface in close contact with the insulating layer 3 on the surface where the copper foil is in contact with the insulating layer 3 is about 7 to 8 μm in Rz. A general copper foil having a roughened shape of unevenness, a so-called low profile copper foil Rz of 2.7 to 3.3 μm, and a profile free copper foil of Rz 1.1 to 1 It is also possible to use a copper foil of 5 μm. Among these, the profile of the rough surface shape 10 is particularly small from the viewpoint of securing the interlayer distance (thickness of the insulating layer 3), the importance of impedance control, the suppression of transmission loss of high-frequency signals, and the formation of fine wiring by etching. Free copper foil is desirable. Examples of such profile-free copper foil include PF-E-3 (manufactured by Hitachi Chemical Co., Ltd., trade name), MultiFoil-G series (trade name, manufactured by Mitsui Metal Mining Co., Ltd.), and the like. Here, the surface roughness means “ten-point average” defined in Annex 1 of JIS B0601: 2001 “Product Geometric Characteristics Specification (GPS) —Surface Properties: Contour Curve Method—Terms, Definitions, and Surface Property Parameters”. “Roughness: Rz”.

  Moreover, what has suitable thickness can be used for the copper foil used as the metal foil 4 as needed. Commercially available copper foil has a thickness in the range of about 10 to 150 μm, and copper foils having thicknesses of 18 μm and 35 μm are generally used for circuit board applications. From the viewpoint of forming a finer circuit pattern, it is more preferable to use a relatively thin copper foil such as one having a thickness of 12 μm, 9 μm, or 5 μm.

  The laminate 1 with a metal foil referred to in the present invention has a structure in which an insulating layer 3 and a metal foil 4 are laminated and integrated. For example, an insulating substrate, a core substrate, a film, an interlayer insulating layer, a buildup layer, etc. It refers to a state in which a metal foil 4 such as a copper foil or an aluminum foil is bonded to the insulating layer 3. Moreover, a single-sided board, a double-sided board, and a multilayer board are included. A material for forming the insulating layer 3 such as an adhesive sheet or a prepreg and the metal foil 4 can be overlapped, and can be produced by pressing and heating using a press device or a laminating device.

  The conductor pattern 6 referred to in the present invention is formed from a portion left after removing an unnecessary portion of the metal foil 4 in close contact with the insulating layer 3 of the laminated sheet 1 with metal foil. After thickening the portion to be the conductor pattern 6 on the metal foil 4 with a pattern (partial plating), the other portion of the metal foil 4 is removed, so-called semi-additive method, or panel plating on the metal foil 4 ( After the entire surface is thickened by (entire surface plating), it can be formed by a so-called subtracting method or the like, in which unnecessary portions other than the portion to be the conductor pattern 6 are removed. Thus, since the conductor pattern 6 is formed from the remaining portion after removing the unnecessary portion of the metal foil 4 in close contact with the insulating layer 3, the surface of the insulating layer 3 exposed after forming the conductor pattern 6 is a metal The surface shape of the foil 4 is transferred.

  The removal of the metal foil 4 on the insulating layer 3 for forming the conductor pattern 6 can be performed by a general etching method used in the production of a wiring board or a semiconductor mounting substrate. As an etching solution, ferric chloride solution, cupric chloride solution, alkali etchant, or the like can be used, and can be performed by spraying or the like.

  In the present invention, the surface of the insulating layer 3 in contact with the conductor pattern 6 refers to the surface of the insulating layer 3 in contact with the conductor pattern 6. That is, the insulating layer 3 in the portion where the conductor pattern 6 is formed has a close contact portion with the metal foil 4, and the surface shape of the metal foil 4 is transferred.

  In the present invention, the exposed surface of the insulating layer 3 refers to the surface of the exposed insulating layer 3 after the metal foil 4 other than the portion where the conductor pattern 6 is formed is removed. The exposed surface of the insulating layer 3 where the conductor pattern 6 was not formed (removed portion) was in close contact with the metal foil 4 until the conductor pattern 6 was formed. Is transcribing. A solder resist 7 is formed on the exposed surface of the insulating layer 3.

  In the present invention, the rough surface shape 10 is formed with respect to the surface shape of the exposed surface of the insulating layer 3. That is, the surface shape of the metal foil 4 that is in close contact with the exposed surface of the insulating layer 3 is transferred, but the rough surface shape 10 of the present invention is formed with respect to this surface shape.

  A rough surface shape 10 is formed on the exposed surface of the insulating layer 3 after the metal foil 4 is removed. For the formation of the rough surface shape 10 on the surface of the insulating layer 3, it is desirable to use plasma treatment from the viewpoint of ensuring the adhesion between the insulating layer 3 and the solder resist 7. Plasma treatment includes vacuum plasma treatment and atmospheric pressure plasma treatment, both of which can improve the adhesion. The gas to be used is not particularly limited as long as it contains argon or oxygen, but argon, oxygen, oxygen / argon, oxygen / nitrogen, or the like can be used. Further, it is preferable that the oxygen mixed gas has a flow ratio of oxygen of 1% or more. When the oxygen ratio is less than 1%, the effect of the oxidation treatment tends to be small.

  Formation of the rough surface shape 10 on the exposed surface of the insulating layer 3 is desirably performed so that Rz increases by 1.0 μm to 2.0 μm with respect to the initial Rz. That is, Rz after forming the rough surface shape 10 is increased by 1.0 μm to 2.0 μm with respect to the surface roughness Rz of the insulating layer 3 in a state where the surface shape of the metal foil 4 is transferred. Is desirable. As the metal foil 4 laminated and integrated with the insulating layer 3, a general copper foil of 7.0 μm to 8.0 μm in Rz, a low profile copper foil of 2.7 μm to 3.3 μm in Rz, and 1.1 μm to 1 in Rz When a profile-free copper foil of .5 μm is used, the surface of the insulating layer 3 has the same surface roughness as those copper foils because the surface shape of these copper foils is transferred. That is, in this case, the initial Rz of the exposed surface of the insulating layer 3 has a surface roughness of 1.0 μm to 8.0 μm. For this reason, when the rough surface shape 10 is formed so that Rz increases by 1.0 μm to 2.0 μm with respect to the initial Rz, the rough surface shape 10 is formed on the exposed insulating layer 3 surface. The surface roughness is 2.0 μm to 10.0 μm in Rz. In this way, in addition to the surface roughness originally possessed by the surface shape of the insulating layer 3, fine irregularities of 1.0 μm to 2.0 μm are formed in Rz and the surface roughness Rz increases, so-called anchors. The effect is enhanced, and the adhesion of the solder resist 7 formed on the surface of the insulating layer 3 is improved. If the Rz of the rough surface shape 10 to be formed is less than 1.0 μm, the unevenness of the rough surface shape 10 formed with respect to the surface shape of the insulating layer 3 is too small, so it is difficult to obtain a so-called anchor effect, and the surface of the insulating layer 3 It is difficult to ensure adhesion of the solder resist 7 to be formed in the PCT. On the other hand, if Rz exceeds 2.0 μm, it takes time for the treatment to give the rough surface shape 10, causing problems in terms of cost, and surface roughness that the surface shape of the insulating layer 3 originally had. Therefore, it is considered that the roughness of the rough surface shape 10 formed thereon is absorbed by the surface roughness originally possessed and the anchor effect is reduced.

  Further, by forming the rough surface shape 10 on the exposed insulating layer 3 surface, the surface roughness of the exposed insulating layer 3 surface is made larger than the surface roughness of the insulating layer 3 surface in contact with the conductor pattern 6. Is possible. Thereby, even if the surface roughness of the surface of the conductor pattern 6 that is in close contact with the insulating layer 3 is small, the exposed surface of the insulating layer 3 can be provided with sufficient irregularities for the close contact of the solder resist 7. As the metal foil 4 forming the pattern 6, a metal foil having a smaller surface roughness can be selected. As the metal foil 4 having a small surface roughness, for example, a low profile copper foil or a profile free copper foil can be selected. Therefore, it is possible to provide the circuit board 11 having fine wiring and suppressing transmission loss at high frequencies.

  The metal foil 4 used for forming the conductor pattern 6 is preferably a profile-free copper foil. As profile-free copper foil, for example, PF-E-3 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having Rz of 1.1 μm to 1.5 μm, MultiFoil-G series (trade name, manufactured by Mitsui Metal Mining Co., Ltd.), etc. Is mentioned. As a result, it is possible to provide the circuit board 11 having finer wiring and suppressing transmission loss at high frequencies. On the other hand, since the Rz of the profile-free copper foil is 1.1 μm to 1.5 μm, which is smaller than that of a general copper foil or low profile copper foil, the surface roughness of the insulating layer 3 to which this surface shape is transferred is also equivalent. For this reason, when the solder resist 7 is formed on the exposed surface of the insulating layer 3 after the conductor pattern 6 is formed, the adhesion between the solder resist 7 and the insulating layer 3 tends to be insufficient. However, in the present invention, since the rough surface shape 10 is formed on the exposed insulating layer 3 surface after the conductor pattern 6 is formed, the solder resist is formed while ensuring the formation of fine wiring and the suppression of transmission loss at high frequencies. 7 and the insulating layer 3 can be secured.

  The solder resist 7 may be a liquid type or dry film type used in the manufacture of wiring boards and semiconductor mounting substrates. In the case of a liquid type, application can be performed using a roll coater or a screen printer. In the case of the dry film type, it is desirable to use a vacuum pressurization laminator from the point of followability to the rough surface shape 10 on the surface of the insulating layer 3. Examples of the liquid type solder resist 7 include PSR-4000AUS308 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.). Examples of the dry film type solder resist 7 include PFR-800AUS402 (manufactured by Taiyo Ink Manufacturing Co., Ltd., Product name).

  Below, an example of the manufacturing method of the circuit board 11 of this invention is demonstrated.

  First, the insulating layer 3 and the metal foil 4 are laminated and integrated to produce the laminated plate 1 with the metal foil. As the insulating layer 3, for example, GEA679FG (manufactured by Hitachi Chemical Co., Ltd., trade name) is used, and as the metal foil 4, for example, PF-E-3 (product made by Hitachi Chemical Co., Ltd., product) is a profile-free copper foil. 1), the metal foils 4 are stacked on the upper and lower sides of the insulating layer 3, and heated and pressed using a press device or the like to be laminated and integrated (FIG. 1 (a)). In addition, the laminated board 1 with metal foil is not restricted to a double-sided board like FIG. 1, A single-sided board and a multilayer board may be sufficient.

  Next, plating 9 is performed on the metal foil 4 of the laminated sheet 1 with metal foil so that the conductor pattern 6 has a required thickness. The plating 9 can be formed using electroless copper plating, electrolytic copper plating, or the like used in the manufacture of wiring boards or semiconductor mounting substrates.

  Next, as a photosensitive dry film for circuit formation, for example, NIT-225 (trade name, manufactured by Nichigo Morton Co., Ltd.) is used. Form. Thereafter, etching is performed to remove the unnecessary metal foil 4 other than the portion where the conductor pattern 6 is to be formed. After the conductor pattern 6 is formed, the etching resist is peeled off (FIG. 1B). In addition, although the example which used the subtractive construction method was demonstrated here, especially the construction method used for formation of the conductor pattern 6 should just be a construction method including the process of removing the metal foil 4 closely_contact | adhered with the insulating layer 3, It is also possible to use the semi-additive method.

  Next, a rough surface shape 10 is formed on the surface of the insulating layer 3 exposed after the conductor pattern 6 is formed. As a method for forming the rough surface shape 10, for example, plasma processing is used, and the laminate 1 with metal foil formed up to the conductor pattern 6 is placed in the plasma chamber for processing. As described above, oxygen, argon, or the like is used as the plasma gas (FIG. 1C).

  Next, in order to improve the adhesion between the surface of the conductor pattern 6 and the solder resist 7, the surface of the conductor pattern 6 is roughened. As the roughening treatment, for example, etching with a roughening solution such as CZ-8100 (trade name, manufactured by MEC Co., Ltd.), mechanical polishing, or the like can be used.

  Next, a solder resist 7 is formed on the surface of the insulating layer 3 and the conductor pattern 6. If the material of the solder resist 7 is a liquid type, for example, PSR-4000 AUS308 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) can be used. If the material is a dry film type, for example, PFR-800. AUS402 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) can be used. When a liquid type is used as the solder resist 7, coating is performed using a roll coater or a screen printing machine, and further semi-cure is performed to reduce the tack of the coated surface and improve the handleability. When using a dry film type, lamination is performed using a vacuum pressure laminator. Next, a solder resist 7 is formed by performing exposure, development, thermal curing using a photomask having a predetermined pattern, and then further ultraviolet exposure if necessary (FIG. 1D).

  Next, in order to suppress the oxidation of the surface of the conductor pattern 6 on the exposed conductor pattern 6 where the solder resist 7 is not formed and to impart solderability and wire bonding property, for example, nickel-gold plating 8 It is desirable to form the connection terminal 14 by performing a surface treatment such as the above. Finally, the circuit board 11 is formed by cutting into a predetermined size.

  According to the manufacturing method of the circuit board 11 of the present invention described above, since the rough surface shape 10 is formed after the conductor pattern 6 is formed, the surface roughness of the metal foil 4 used for forming the conductor pattern 6 is reduced. Even if it is small, the adhesion between the surface of the insulating layer 3 exposed after the formation of the conductor pattern 6 and the solder resist 7 formed thereon can be ensured, and the reliability can be improved.

  Hereinafter, the circuit board 11 and the manufacturing method thereof according to the present invention will be described based on examples, but the present invention is not limited to the examples.

Example 1
MCL-E-679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.), a glass epoxy substrate provided with the inner layer copper foil 12 and the insulating layer 3, a copper foil thickness of 5 μm, a substrate size of 333 mm × 500 mm, and a substrate thickness of 0.8 mm are prepared. did. Next, a through hole 2 having a diameter of 0.2 mm was formed at a predetermined position using a drill. The substrate was subjected to electroless copper plating and electrolytic copper plating so as to have a predetermined conductor thickness, thereby forming a plating 9. Next, the conductor pattern 6 was formed using the subtractive construction method (FIG. 2A).

  Next, the surface of the conductor pattern 6 was roughened using a so-called blackening treatment. Next, GEA-679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.) that is the insulating layer 3 and PF-E-3 (trade name, manufactured by Hitachi Chemical Co., Ltd.) of the profile-free copper foil 13 that is the metal foil 4 are used. The laminate was laminated and integrated by heating and pressurizing with a press device to form a laminate 1 with a metal foil (FIG. 2B).

  Next, an etching resist for forming a window hole for forming a via hole 5 at a predetermined position on the profile-free copper foil 13 of the laminated sheet 1 with a metal foil by using a so-called conformal method is prepared and etched. After removing the profile free copper foil 13 at the position where the via hole 5 is to be formed, the etching resist is peeled off. Next, the carbon dioxide gas laser is used to remove the insulating layer 3 resin where the profile-free copper foil 13 has been removed. Next, desmear treatment is performed to remove smear at the bottom of the Via, and then electroless copper plating is performed. Next, after laminating a dry film for a plating resist, forming a predetermined plating resist pattern by a photolithographic method, and forming a plating 9 on the portion where the plating resist was removed by development, using electrolytic copper plating, Strip and remove the plating resist. That is, plating 9 is formed on the profile-free copper foil 13 in the portion that becomes the conductor pattern 6, and only the profile-free copper foil 13 remains in the portion other than the conductor pattern 6. Next, the entire surface is etched so that only the portion where the plating 9 is formed using the electrolytic copper plating remains and only the profile-free copper foil 13 other than the portion where the plating 9 is formed is completely removed. Thus, the conductor pattern 6 is formed (FIG. 2C).

  Next, oxygen plasma treatment was carried out on the laminate 1 with metal foil on which the conductor pattern 6 was formed. Oxygen plasma was performed using oxygen as a plasma gas, with an output of 1000 W, an atmospheric pressure of 100 Pa, and a treatment time of 5 minutes (FIG. 3D).

  Next, the surface of the conductive pattern 6 is roughened by chemical etching (MEC, CZ-8100), and then dry film type solder resist 7 PFR-800AUS402 (manufactured by Taiyo Ink Manufacturing Co., Ltd.) In order to form a predetermined opening, a solder resist 7 was formed using a photolithographic method (FIG. 3E).

  Next, surface treatment such as nickel-gold plating 8 is performed on the exposed conductor pattern 6 in order to suppress oxidation of the surface of the conductor pattern 6 and to provide solderability and wire bonding property, so that the connection terminal 14 The circuit board 11 was produced (FIG. 3F).

(Example 2)
Oxygen plasma treatment was performed on the laminate 1 with metal foil (FIG. 2C) on which the conductor pattern 6 was formed. Oxygen plasma was performed using oxygen as a plasma gas, with an output of 1000 W, an atmospheric pressure of 100 Pa, and a treatment time of 10 minutes. Other than that was carried out similarly to Example 1, and produced the circuit board 11. FIG.

(Example 3)
Plasma treatment using argon gas as the plasma gas was performed on the laminate 1 with metal foil (FIG. 2C) on which the conductor pattern 6 was formed. The argon gas was output at 1000 W, the atmospheric pressure was 100 Pa, and the treatment time was 15 minutes. Other than that was carried out similarly to Example 1, and produced the circuit board 11. FIG.

(Comparative Example 1)
The treatment for forming the rough surface shape 10 such as plasma was not performed on the laminate 1 with metal foil (FIG. 2C) on which the conductor pattern 6 was formed. Other than that was carried out similarly to Example 1, and produced the circuit board 11. FIG.

(Comparative Example 2)
Desmear treatment was performed on the laminated sheet 1 with metal foil (FIG. 2C) on which the conductor pattern 6 was formed. The desmear treatment was performed under conditions of a temperature of 85 ° C. for 6 minutes using a sodium permanganate aqueous solution used for manufacturing a wiring board or a semiconductor mounting substrate. Other than that was carried out similarly to Example 1, and produced the circuit board 11. FIG.

(PCT)
About Examples 1-3 obtained by the above and Comparative Examples 1 and 2, the adhesiveness evaluation of the insulating layer 3 and the soldering resist 7 was evaluated using the pressure cooker test (PCT). The PCT conditions were 121 ° C., 100% RH, and 2 atm, and were continuously maintained for 96 hours. Then, it observed with the stereomicroscope and the presence or absence of peeling between the insulating layer 3 and the soldering resist 7 was confirmed.

(Measurement of surface roughness)
Based on “ten-point average roughness: Rz” defined in Appendix 1 of JIS B0601: 2001 “Product Geometrical Specification (GPS) —Surface Properties: Contour Curve Method—Terms, Definitions, and Surface Property Parameters” It was measured. For the measurement, a stylus type surface roughness meter of JIS B0651 and a light wave interference type surface roughness meter of JIS B0652 can be used. Was used to measure Rz on the surface of the insulating layer 3.

  For Examples 1 to 3 and Comparative Examples 1 and 2, the surface roughness Rz of the insulating layer 3 and the adhesion between the surface of the insulating layer 3 and the solder resist 7 by PCT were evaluated. The results are shown in Table 1.

○：全く界面剥離が認められないもの ×：界面剥離が認められるもの

○: No interfacial delamination ×: Interfacial delamination

In Example 1, due to the oxygen plasma treatment, the rough surface shape 10 was formed on the surface of the insulating layer 3, and Rz was 2.1 μm larger than the untreated product, and the adhesion with the solder resist 7 was improved. No peeling occurred.
Similarly, in Example 2, the rough surface shape 10 was formed on the surface of the insulating layer 3 by the oxygen plasma treatment, the Rz was 2.4 μm, and the adhesion of the solder resist 7 was improved, so that no peeling occurred by PCT. .
In Example 3, the treatment was performed using argon plasma. In this case as well, the rough surface shape 10 was formed on the surface of the insulating layer 3, the Rz was 2.1 μm, and the adhesion with the solder resist 7 was improved. No peeling occurred.
In Comparative Example 1, since the surface of the base material was not roughened, Rz was as small as 1.0 μm, adhesion to the solder resist 7 was low, and peeling occurred due to PCT.
In Comparative Example 2, an attempt was made to roughen the substrate surface by desmearing, but the entire surface of the substrate was uniformly roughened by desmearing, and the formation of irregularities was not sufficient, so Rz was 1.3 μm. Small and peeled off by PCT.

It is an example of the circuit board which concerns on this invention, and an example of the manufacturing method. It is the manufacturing method of the first half of the circuit board of Examples 1-3 of this invention. It is the circuit board of Examples 1-3 of this invention, and its manufacturing method of the second half.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Laminated board with metal foil, 2 ... Through hole, 3 ... Insulating layer, 4 ... Metal foil, 5 ... Via hole, 6 ... Conductor pattern, 7 ... Solder resist, 8 ... Nickel-gold plating, 9 ... Plating, 10 ... rough surface shape, 11 ... circuit board, 12 ... inner layer copper foil, 13 ... profile-free copper foil, 14 ... connection terminal

Claims (7)

  In a circuit board having a conductor pattern formed by removing the metal foil of a laminate with metal foil laminated with a metal foil on an insulating layer, the exposed surface of the insulating layer after removing the metal foil has a rough surface shape. Formed circuit board.   2. The circuit board according to claim 1, wherein the surface roughness of the exposed insulating layer surface is larger than the surface roughness of the insulating layer surface in contact with the conductor pattern.   The circuit board according to claim 1 or 2, wherein the metal foil is a profile-free copper foil.   4. The circuit board according to claim 1, wherein the rough surface is formed by plasma processing.   In the method of manufacturing a circuit board having a conductor pattern formed by removing the metal foil of the laminate with metal foil laminated with a metal foil on an insulating layer, a step of forming the conductor pattern by removing the metal foil; Forming a rough surface shape on the exposed surface of the insulating layer.   6. The method for manufacturing a circuit board according to claim 5, wherein a profile-free copper foil is used as the metal foil.   7. The method for manufacturing a circuit board according to claim 5, wherein the step of forming the rough surface shape includes plasma treatment.

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