JP2010073971A - Nonvolatile semiconductor memory cell and nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which reduces an area for layout and improves the reliability of memory storage. <P>SOLUTION: In the nonvolatile semiconductor memory cell, a first selection transistor, two floating gate type memory devices and a second selection transistor are sequentially connected in series, and drains and sources for the respective elements are arranged in series in a transistor forming part 220 as a layout. An n+ type diffused layer 219 as a control gate electrode of the memory device is placed in parallel to the transistor forming part, polysilicons 203a and 203b as a floating gate of the memory device are placed in a direction crossing vertically the transistor forming part 220 and the n+ type diffused layer 219, and polysilicons 214a and 214b as the gate electrode of the first and second selection transistors are placed in a direction crossing vertically the transistor forming part 220. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention mainly relates to a nonvolatile semiconductor memory device, and more particularly to a memory element that increases the reliability of stored data and a nonvolatile semiconductor memory device including the memory element.

  Nonvolatile semiconductor memory devices represented by EEPROM (Electrically Erasable Programmable Read Only Memory) are used in many applications because stored information does not disappear even when power supply is stopped. For example, typical applications of EEPROM are NAND flash memory for large-capacity file applications, NOR type flash memory used for storage control of cellular phones, etc., and typical applications of EEPROM are IC cards. is there.

  Moreover, EEPROM and flash memory are used as a replacement for a mask ROM (Read Only Memory) in a microcomputer because of the convenience of rewriting according to the application at any time. Further, in recent years, embedded type so-called embedded memory, which incorporates a nonvolatile memory as an internal memory of a system LSI or logic IC, has been used. Furthermore, a small-sized non-volatile memory of about several hundred bits to several K bits is also used as an adjustment switch that is incorporated in an analog circuit and performs tuning and the like of a high-precision analog circuit.

FIG. 19 is a schematic diagram showing a nonvolatile semiconductor memory cell 9 as a conventional example. 19A shows an equivalent circuit of the nonvolatile semiconductor memory cell 9, FIG. 19B is a schematic diagram showing a layout configuration of the nonvolatile semiconductor memory cell 9, and FIG. 19C shows the layout of FIG. It is the schematic which shows the cross-sectional structure along A9-A'9, (d) is the schematic which shows the cross-sectional structure along B9-B'9 of (b).
As shown in FIG. 19A, the nonvolatile semiconductor memory cell 9 includes a transistor Tr9, a drain terminal D, a source terminal S, a control gate terminal CG, a floating gate FG connected to the control gate terminal CG, and a control gate. A capacitor C (FC) is provided between the floating gate FG.

  Structurally, as shown in FIGS. 19B to 19D, an n-type well 901 formed on a p-type semiconductor substrate 900, an n + type diffusion region 902 formed on the n-type well 901, Polysilicon 903 to be the floating gate FG, n + -type diffusion layer 904 to be the drain of the transistor Tr9, n + -type diffusion layer 905 to be the source of the transistor Tr9, the gate region portion 906 of the transistor Tr9, and the source of the transistor Tr9 via the contact 907b A metal wiring 908 equivalent to the source terminal S, a metal wiring 909 equivalent to the drain terminal D connected to the drain of the transistor Tr9 via the contact 907a, and a gate region portion 910 in which a channel of the transistor Tr9 is formed, Contacts 912a, 91 in the n + diffusion region 902 Metal wiring 911 becomes a control gate connected via a b, constituted by preparative field oxide film 913 of a nonvolatile semiconductor memory cell 9.

  FIG. 20 is a diagram showing the voltage relationship between the terminals in the write operation, erase operation, and read operation of the nonvolatile semiconductor memory cell 9. As shown in the figure, there are two methods of writing, writing 1 and writing 2.

(Operation of write 1)
The write 1 operation is performed by applying a voltage of 7 V to the control gate terminal CG, applying a voltage of 5 V to the drain terminal D, and applying a voltage of 0 V to the source terminal S and the semiconductor substrate 900. As a result, the voltage of the floating gate FG becomes about 4.2 V by the coupling capacitor C (FC) and the setting of the coupling ratio described later, and the channel of the transistor Tr9 is turned on. At this time, since 5 V is applied to the drain terminal D, the transistor Tr9 operates in the saturation region and an excessive voltage is applied. Therefore, near the drain, hot electrons, which are electrons having high energy, are generated together with the channel current. appear. Hot electrons are injected and accumulated in the floating gate FG. Thus, when electrons are injected and accumulated in the floating gate FG, the threshold voltage of the nonvolatile semiconductor memory cell 9 changes to a voltage higher than the initial state. A state in which the threshold voltage of the nonvolatile semiconductor memory cell 9 is changed to a voltage higher than the initial state is referred to as a write state.

(Operation of write 2)
The operation of writing 2 is performed by applying a voltage of 12V to the control gate terminal CG and applying a voltage of 0V to the drain terminal D, the source terminal S, and the semiconductor substrate 900. As a result, a high electric field is applied between the p-type semiconductor substrate 900 and the floating gate FG, and electrons pass through the gate oxide film due to Fowler-Nordheim current (hereinafter referred to as FN current) and float from the channel. It is injected into the gate and accumulated. As a result, the threshold voltage of the nonvolatile semiconductor memory cell 9 is increased, and the data is written (hereinafter referred to as a written state).

(Operation of erase 1)
The erase 1 operation is performed by applying a voltage of 0 V to the control gate terminal CG and applying a voltage of 10 V to the drain terminal D, the source terminal S, and the p-type semiconductor substrate 900. As a result, a high electric field is applied between the p-type semiconductor substrate 900 and the floating gate FG, an FN current flows, and electrons are emitted from the floating gate FG to the semiconductor substrate. As a result, the threshold voltage of the nonvolatile semiconductor memory cell 9 is lowered. The threshold voltage of the nonvolatile semiconductor memory cell 9 changes to a voltage lower than that in the initial state and data is erased (hereinafter referred to as erased state).

(Erase 2 operation)
The erase 2 operation is performed by applying a voltage of 8V to the source terminal S and applying a voltage of 0V to the control gate terminal CG, the drain terminal D and the p-type semiconductor substrate 900. As a result, a high electric field is applied in the vicinity of the source, an FN current and a hot hole are generated, and electrons are emitted from the floating gate FG. As a result, the threshold voltage of the memory element 9 is lowered and an erased state is entered.

(reading)
Reading is performed by applying a voltage of 3V to the control gate terminal CG and applying a voltage of 1V to the drain terminal D.
Note that data “0” is stored when the threshold voltage of the nonvolatile semiconductor memory cell 9 is higher than the voltage (3 V) applied to the control gate terminal CG at the time of reading (write state). It is assumed that “1” is stored when the threshold voltage of the volatile semiconductor memory cell 9 is low (erased state).

  Next, FIG. 21 is a graph schematically showing static characteristics when the nonvolatile semiconductor memory cell 9 is in a write state. The vertical axis direction represents the drain current Id, and the horizontal axis direction represents the drain voltage Vd. The static characteristic that is the relationship between the drain voltage Vd and the drain current Id is indicated by a solid line. In the process of raising the voltage applied to the drain to VBD, hot electrons are generated, and the generated hot electrons are injected into the floating gate FG. As a result, the potential of the floating gate FG is lowered, and the threshold voltage is apparently increased. As the threshold voltage increases, the drain current decreases rapidly. When the drain voltage is further increased to reach VBD, breakdown occurs and the drain current increases rapidly.

  Although two load lines are illustrated, normally, the load of the nonvolatile semiconductor memory cell 9 is set like the NMOS load 1 and the illustrated operating point 1 is used as the voltage for the write operation. When the load is set as illustrated with the NMOS load 2, the voltage of the write operation becomes the voltage illustrated at the operating point 2. When writing is performed in the state of the operating point 2, since the writing operation is performed in the area where the nonvolatile semiconductor memory cell 9 is broken down, hot electrons are generated so that the writing characteristics are improved. On the other hand, since a large number of hot holes are generated, there is a problem that it is not preferable in terms of reliability, and control is difficult because a large current flows. For this reason, it is preferable to use the point shown in the operation point 1 where writing can be performed without flowing a large current for the writing operation.

  FIG. 22 is a graph schematically showing write characteristics for injecting hot electrons into the floating gate FG. The vertical axis direction represents the threshold voltage of the nonvolatile semiconductor memory cell 9, and the horizontal axis direction represents the logarithm (log) of the write time. Using the drain voltage as a parameter, the case where the drain voltage is high (VDh) and the case where the drain voltage is low (VDl) are compared. A voltage indicated by VCG is a read voltage applied to the control gate terminal CG of the nonvolatile semiconductor memory cell 9 in the read operation. When the drain voltage is high, the threshold voltage can be changed in a shorter time than when the drain voltage is low.

The operation of writing 2 is writing by the tunnel effect of Fowler-Nordheim. A voltage of 12 V is applied to the control gate terminal CG, and a voltage of 0 V is applied to the drain terminal D, the source terminal S, and the semiconductor substrate 900. The potential of the floating gate FG is 7.2 V, and electrons are injected from the source, drain, or channel region into the floating gate FG and accumulated.
FIG. 23 is a graph schematically showing the writing characteristics by the tunnel effect of Fowler-Nordheim. The vertical axis direction represents the threshold voltage, and the horizontal axis direction represents the logarithm (log) of the writing time. The threshold voltage increases linearly with respect to the writing time (logt).

FIG. 24 is a graph schematically showing the characteristics of erase 1. The vertical axis represents the threshold voltage, and the horizontal axis represents the logarithm (log) of the writing time. As shown in the figure, the characteristics are opposite to the above-mentioned write characteristics. The erase 1 operation is performed by applying a voltage of 0 V to the control gate terminal CG and applying a voltage of 10 V to the drain terminal D, the source terminal S, and the p-type semiconductor substrate.
Note that when the voltage applied to the control gate in the read operation is VCG, a region having a higher threshold voltage than the VCG is referred to as a write state, and a region having a lower threshold voltage is referred to as an erase state.

FIG. 25 is a graph schematically showing the characteristics of the drain current with respect to the drain voltage applied to the drain when VCG = 0 V at the time of erasing. The vertical axis direction represents the drain current, and the horizontal axis direction represents the drain voltage. When the voltage applied to the drain is gradually increased, electric field concentration in the depletion layer occurs in the vicinity of the drain, and so-called high energy causes a B to B (Band to Band) current (band-to-band current) to flow, generating a hole-electron pair. To do. A part of hot holes which are holes having high energy is taken into the floating gate FG. When the voltage is further increased, an over electric field is applied to the oxide film between the drain and the floating gate FG, a Fowler-Nordheim tunnel current flows, and electrons are emitted from the floating gate FG to the drain. When the voltage is subsequently raised, a junction breakdown occurs and a large current flows between the drain and the p-type semiconductor substrate. This breakdown voltage is referred to as VBD. As the erasing characteristics, the same characteristics as in FIG. 24 are obtained.
When writing or erasing is performed, the number of electrons in the floating gate FG increases or decreases, and as a result, the threshold voltage changes.

  FIG. 26 is a graph schematically showing an example of the characteristics (Vg-Id characteristics) between the gate voltage and the drain current in the initial state, the written state, and the erased state. The threshold voltage in the initial state is 0.5V, and when the write operation is performed, the threshold voltage increases and the threshold voltage changes to 5V. Further, when the erasing operation is performed, the threshold voltage becomes low, and the threshold voltage changes to -3V to a negative value.

FIG. 27 is a diagram showing an equivalent circuit of a coupling system of the nonvolatile semiconductor memory cell 9. The potential applied to the control gate terminal CG is VCG, the capacitance of the control gate terminal CG and the floating gate FG is C (FC), the potential applied to the source S is VS, and the potential between the source S and the floating gate FG is The electrostatic capacity is C (FS), the potential applied to the semiconductor substrate SUB is Vsub, the electrostatic capacity between the semiconductor substrate SUB and the floating gate FG is C (FB), and the potential applied to the drain D is VD, The capacitance between the drain D and the floating gate FG is C (FD), and the potential applied to the floating gate is VFG.
When the state of the floating gate FG is the initial state (neutral state), the total charge of this system is zero, so the following equation (1) holds.

  When the total capacitance of this system is CT, CT is expressed by the following equation (2).

  When Expression (1) is transformed with respect to VFG using Expression (2), it can be expressed as the following Expression (3).

  Here, assuming that C (FD) = C (FS) ≈0 and Vsub = VS = 0, Expression (3) is expressed as the following Expression (4).

  Here, when C (FG) / {C (FC)} + C (FB) = α (coupling ratio), Expression (4) is expressed by the following Expression (5).

  Normally, α≈0.6 is set, and the capacitance of the floating gate FG and the like is determined, and the nonvolatile semiconductor memory cell is designed.

  Such a charge-holding nonvolatile semiconductor memory cell has a problem that the stored data cannot be maintained due to the loss of charge from which the charge from the floating gate is lost.

  FIG. 28 shows charge retention (data retention) characteristics. The vertical axis direction represents the threshold voltage, and the horizontal axis direction represents the logarithm (log) of time. There are defects in the oxide film, and when a small amount of charge accumulated in the floating gate is released from the defect, a write cell (a state in which more electrons are accumulated than in the initial state) and an erase cell (electron) Is a state where there are fewer electrons than the initial state, in other words, a state where holes are injected and accumulated), with the passage of time, the initial state (neutral state, state where there is no charge bias in the floating gate) Asymptotically approach the threshold voltage. The defect in which the charge accumulated in the floating gate is released with the passage of time is a defect due to an oxide film defect, and therefore, a memory cell having an oxide film defect and a memory cell having no defect are mixed in the manufacturing process. Another cause of the failure is that the oxide film deteriorates in the process of repeatedly performing the write and erase operations, and the same failure occurs.

As a method for solving such a problem, there is a circuit as shown in FIG. 29 (Patent Document 1). By providing two charge holding memory elements Tr92 and Tr93, even if one of the memory elements becomes defective, data can be held as a memory cell if the other operates normally.
Japanese Patent No. 2685966

  However, the configuration in which a plurality of memory elements are arranged in parallel like the conventional nonvolatile semiconductor memory cell has a problem that the layout area becomes large.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device that reduces the layout area and improves the reliability of memory retention.

  (1) In order to solve the above problem, the present invention is a non-volatile semiconductor memory cell comprising a MOS transistor formed on a semiconductor substrate, wherein the first terminal is connected to the drain and the first is connected to the gate. A first select transistor connected to a select terminal; a first memory element having a drain connected to a source of the first select transistor; a control gate connected to a control gate terminal; and a drain connected to the first select transistor. A source of the memory element is connected, a second memory element having the control gate connected to the control gate terminal, a drain connected to the source of the second memory element, and a source connected to the second terminal; A second select transistor having a gate connected to a second select terminal, and a source of the first select transistor; The n-type diffusion layer constituting the drain of the first memory element is shared, and the n-type diffusion layer constituting the source of the first memory element and the drain of the second memory element is shared, The nonvolatile semiconductor memory cell is characterized in that the n-type diffusion layer constituting the source of the second memory element and the drain of the second selection transistor is shared.

  (2) Further, the present invention is characterized in that, in the above-described invention, the first memory element and the second memory element are floating gate type transistors formed of one layer of polysilicon. To do.

  (3) In the present invention described above, the first memory element and the second memory element are floating gate transistors formed of two layers of polysilicon. .

  (4) In the present invention described above, when data is stored in the first memory element and the second memory element, the potential applied to the second terminal and the semiconductor substrate is used as a reference. When the potential is set, the first voltage is applied to the first terminal, the voltage higher than the first voltage is applied to the first select terminal and the second select terminal, and the first selection is performed. A transistor and the second selection transistor are turned on, a second voltage is applied to the control gate terminal, and hot electrons are generated by currents flowing between the drain and the source of the first memory element and the second memory element, respectively. And electrons are injected and accumulated in the floating gates of the first memory element and the second memory element, respectively, or the first cell element is stored. A third voltage is applied to the first select terminal and the second select terminal to turn on the first select transistor and the second select transistor, a fourth voltage is applied to the control gate terminal, and A Fowler-Nordheim tunneling current flowing from the floating gate to the drain of one memory element causes electrons to be injected and stored in the floating gate, and a Fowler-Nordheim tunnel flowing from the floating gate to the source of the second memory element. When electrons are injected and accumulated in the floating gate due to current, and the data stored in the first memory element and the second memory element are erased, the potential applied to the control gate terminal is set as a reference potential , The first terminal, the second terminal, and the half Applying the fourth voltage to the body substrate, applying the eighth voltage to the first select terminal and the second select terminal, and turning on the first select transistor and the second select transistor; Then, a Fowler-Nordheim tunnel current is caused to flow from the semiconductor substrate to the floating gates of the first memory element and the second memory element to emit electrons from the floating gate, or the semiconductor substrate and the semiconductor memory When the potential applied to the control gate terminal is a reference potential, a fifth voltage is applied to the first terminal and the second terminal, and the first voltage is applied to the first select terminal and the second select terminal. 8 is applied to turn on the first selection transistor and the second selection transistor, and A Fowler-Nordheim tunnel current is caused to flow from the drain and the source of the second memory element to the respective floating gates, electrons are emitted from the floating gates, and the electrons are stored in the first memory element and the second memory element. When the potential applied to the second terminal and the semiconductor substrate is a reference potential, a sixth voltage is applied to the first terminal, and the first select terminal and the first terminal are read out. A seventh voltage is applied to the second select terminal, a read voltage is applied to the control gate terminal, and whether or not a current flows between the first terminal and the second terminal is stored. It is characterized by reading data.

  (5) The present invention also provides a first memory element and a second memory element which are MOS transistors formed on a semiconductor substrate, a first selection transistor which is a MOS transistor for selecting the memory element, A non-volatile semiconductor memory cell composed of two select transistors, a first n-type diffusion layer forming a drain of the first select transistor, and a first electrode forming a gate electrode of the first select transistor 1 polysilicon, a second n-type diffusion layer forming the source of the first selection transistor and the drain of the first memory element, and a second forming the floating gate electrode of the first memory element. Polysilicon, a third n-type diffusion layer forming a source of the first memory element and a drain of the second memory element, and the second memory element. A third polysilicon for forming a floating gate electrode of the second element; a fourth n-type diffusion layer for forming a source of the second memory element and a drain of the second selection transistor; and the second selection. A transistor forming portion in which a fourth polysilicon forming a gate electrode of a transistor and a fifth n-type diffusion layer forming a source of the second selection transistor are arranged in series in order; and the transistor forming portion A sixth diffusion layer disposed in parallel with the second polysilicon and the third polysilicon in the series direction and connected to the sixth diffusion layer via a contact And a first metal wiring arranged in the series direction. The nonvolatile semiconductor memory cell.

  (6) Further, the present invention is characterized in that, in the above-described invention, the sixth diffusion layer is an n-type diffusion layer having a well structure.

  (7) Further, according to the present invention, in the invention described above, the sixth diffusion layer is an n + type diffusion layer laid on a p-type semiconductor substrate, or a depletion on a p-type semiconductor substrate. It is an n-type diffusion layer formed by channel implantation when forming a field type transistor.

(8) According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device including a memory cell array in which a plurality of non-volatile semiconductor memory cells made of MOS transistors formed on a semiconductor substrate are arranged, wherein the non-volatile semiconductor memory cell is The first terminal is connected to the drain, the first selection transistor is connected to the gate to the first select terminal, the source of the first selection transistor is connected to the drain, and the control gate terminal is connected to the control gate. A first memory element connected; a second memory element having a drain connected to a source of the first memory element; a control gate connected to the control gate terminal; and a drain connected to the second memory element. The source is connected, the second terminal is connected to the source, and the second select terminal is connected to the gate. The plurality of nonvolatile semiconductor memory cells are arranged in a matrix, and a control gate line and a drain are arranged for each column of the nonvolatile semiconductor memory cells arranged in the matrix. A line and a source line, and all the control gate terminals of the nonvolatile semiconductor memory cells in the column provided with the control gate line are connected in common to each control gate line, and each drain All the drain terminals of the nonvolatile semiconductor memory cells in the column provided with the drain line are commonly connected to a line,
All the source terminals of the nonvolatile semiconductor memory cells in the column provided with the source line are commonly connected to each of the source lines, and the rows of the nonvolatile semiconductor memory cells arranged in the matrix form A first select gate line and a second select gate line are provided for each, and the first select gate line includes the nonvolatile semiconductor memory cells in the row in which the first select gate line is provided. All of the first select gate terminals having the second select gate line are commonly connected, and the second select gate line has the second select gate line provided in the non-volatile semiconductor memory cell in the row in which the second select gate line is provided. A nonvolatile semiconductor memory device is characterized in that all select gate terminals are commonly connected.

  (9) According to the present invention, in the above-described invention, when data is written to the selected nonvolatile semiconductor memory cell using the voltage applied to the semiconductor substrate as a reference voltage, the nonvolatile semiconductor memory cell A fourth voltage is applied to the control gate line connected to the nonvolatile semiconductor memory cell, and a third voltage is applied to the first select gate line and the second select gate line connected to the nonvolatile semiconductor memory cell. Applying a voltage of 0 V to the drain line and the source line connected to the nonvolatile semiconductor memory cell, turning on the first selection transistor and the second selection transistor, and And a Fowler-Nordheim tunnel current from the floating gate of the second memory element to the semiconductor substrate, When erasing data of the selected nonvolatile semiconductor memory cell in which electrons are injected and stored in the gate, a voltage of 0 V is applied to the control gate line connected to the nonvolatile semiconductor memory cell, An eighth voltage is applied to the first select gate line and the second select gate line connected to the nonvolatile semiconductor memory cell, and the drain line and the source line connected to the nonvolatile semiconductor memory cell A fifth voltage is applied to the first selection transistor, the first selection transistor and the second selection transistor are turned on, and the drain of the first memory element and the source of the second memory element are connected to the respective floating gates. A tunnel current of Fowler-Nordheim is passed, electrons are emitted from the floating gate, and selected nonvolatile When reading data stored in a semiconductor memory cell, a voltage of 0 V is applied to the control gate line connected to the nonvolatile semiconductor memory cell, and a sixth voltage is applied to the drain line connected to the nonvolatile semiconductor memory cell. A voltage is applied, a voltage of 0 V is applied to the source line connected to the nonvolatile semiconductor memory cell, and the first select gate line and the second select gate connected to the nonvolatile semiconductor memory cell A seventh voltage is applied to the line, the stored data is detected based on whether or not a current flows through the nonvolatile semiconductor memory cell, and the nonvolatile semiconductor memory cell constituting the selected row is detected. When page writing is performed simultaneously, the fourth voltage is applied to all the control gate lines for each column, and the selected voltage is applied. The third voltage is applied to the first select gate line and the second select gate line connected to the row, and a voltage of 0 V is applied to the drain line and the source line connected to the column. Fowler-Nordheim tunnel current is caused to flow from the floating gates of the first and second memory cells of each of the nonvolatile semiconductor memory cells constituting the column to the semiconductor substrate, and electrons are supplied to the floating gates. In the case of performing page erasure for simultaneously erasing the nonvolatile semiconductor memory cells that are implanted and stored and constitute the selected row, a voltage of 0 V is applied to all the control gate lines provided for each column. And applying the fifth voltage to all of the drain lines and all of the source lines provided for each column. The eighth voltage is applied to the first select gate line and the second select gate line provided in the row, and each of the nonvolatile semiconductor memory cells constituting the column has the first voltage. A high electric field is applied in the vicinity of the drain of the memory element and the source of the second memory element, a Fowler-Nordheim tunnel current is caused to flow through the floating gate of the memory element, and electrons are emitted from the floating gate. .

  (10) Further, according to the present invention, in the above-described invention, the threshold values of the first memory element and the second memory element included in the nonvolatile semiconductor memory cell with respect to the selected nonvolatile semiconductor memory cell. When verifying whether or not the voltage has changed to a threshold voltage higher than a preset write state, the sixth voltage is applied to the drain line connected to the nonvolatile semiconductor memory cell, and the nonvolatile semiconductor memory A control gate line connected to the nonvolatile semiconductor memory cell by applying the seventh voltage higher than the sixth voltage to the first select gate line and the second select gate line connected to the cell. A threshold voltage is detected based on whether or not a current flows through the nonvolatile semiconductor memory cell.

(11) The present invention also provides a first memory element and a second memory element which are MOS transistors formed on a semiconductor substrate, a first selection transistor which is a MOS transistor for selecting the memory element, A non-volatile semiconductor memory device having a memory cell array in which a plurality of non-volatile semiconductor memory cells including two selection transistors are arranged,
The nonvolatile semiconductor memory cell includes a first n-type diffusion layer that forms a drain of the first selection transistor, a first polysilicon that forms a gate electrode of the first selection transistor, and the first A second n-type diffusion layer that forms a source of the select transistor and a drain of the first memory element, a second polysilicon that forms a floating gate electrode of the first memory element, and the first A third n-type diffusion layer forming a source of the memory element and a drain of the second memory element; a third polysilicon forming a floating gate electrode of the second memory element; and the second memory. A fourth n-type diffusion layer forming a source of the element and a drain of the second selection transistor; and a fourth n-type forming a gate electrode of the second selection transistor. A transistor forming portion in which re-silicon and a fifth n-type diffusion layer that forms a source of the second selection transistor are sequentially arranged in a series direction, and arranged in the series direction in parallel with the transistor forming portion; and A sixth diffusion layer disposed at a position intersecting with the second polysilicon and the third polysilicon, and disposed in the series direction connected to the sixth diffusion layer via a contact. And a plurality of nonvolatile semiconductor memory cells arranged in a matrix as the arrangement of the memory cell array, and the plurality of nonvolatile semiconductor memory cells are respectively connected in series One non-volatile semiconductor memory cell adjacent in the direction and the first n-type diffusion layer are shared, and the other adjacent non-volatile semiconductor memory The memory element sharing the cell and the fifth n-type diffusion layer and arranged in parallel in the series direction has the first metal wiring connected in a straight line, and the first n-type diffusion layer Are connected in common to a drain line through a contact, the fifth n-type diffusion layer is connected in common to a source line through a contact, and the memory device arranged parallel to the direction perpendicular to the series direction is The nonvolatile semiconductor memory device is characterized in that the first polysilicon and the fourth polysilicon of the nonvolatile semiconductor memory cells adjacent in the vertical direction are connected in common.

  (12) The present invention is also a nonvolatile semiconductor memory device having a memory cell array in which a plurality of nonvolatile semiconductor memory cells made of MOS transistors formed on a semiconductor substrate are arranged, wherein the plurality of nonvolatile semiconductor memories are The cell has a drain connected to the first terminal, a gate connected to the first select terminal, a drain connected to the source of the first select transistor, and a control gate connected to the control gate. A first memory element having a terminal connected thereto, a second memory element having a drain connected to a source of the first memory element, a control gate connected to the control gate terminal, and a drain connected to the second memory element; The source of the memory element is connected, the second terminal is connected to the source, and the second select is connected to the gate. And a second select transistor connected to a child, and when writing data to the first memory cell element and the second memory element, the first select gate signal and the second select transistor Select gate signal The memory cell array includes a control gate line in which the nonvolatile semiconductor memory cells are arranged in a matrix in a row direction and a column direction, and is commonly connected to the control gate for each column of the nonvolatile semiconductor memory cells; A drain line commonly connected to the drain terminal for each column of the nonvolatile semiconductor memory cells, a source line commonly connected to the source terminal for each column of the nonvolatile semiconductor memory cells, and the nonvolatile semiconductor memory cell A first select gate line connected to the first select gate terminal for each row, and the nonvolatile half A second switch gate line connected to the second select gate terminal for each row of the body memory cells, and a first switch provided between the drain line and the drain power supply line, A second switch provided between the source line and the source power supply line; a third switch provided between the control gate line and the first gate power supply line; the control gate line; A fourth switch provided between the gate power supply line, an address signal for selecting the nonvolatile semiconductor memory cell included in the memory cell array, and a command signal indicating any one of write, erase, and read operations And the first switch, the second switch, the third switch, and the fourth switch based on the input address signal and the command signal. A non-volatile circuit selected by the address signal by applying a voltage to the first gate power line, the second gate power line, the first select gate line, and the second select gate line; And a control unit that performs an operation corresponding to the command signal on the semiconductor memory cell.

  (13) The present invention also relates to a nonvolatile semiconductor memory cell comprising a MOS transistor formed on a semiconductor substrate, wherein the first terminal is connected to the drain and the first select terminal is connected to the gate. A first selection transistor; a first memory element having a drain connected to a source of the first selection transistor; a control gate connected to a first control gate terminal; and a drain connected to the first memory element. A second memory element having a source connected, a control gate connected to a second control gate terminal, a drain connected to the source of the second memory element, a source connected to the second terminal, and a gate; And a second select transistor connected to a second select terminal, the source of the first select transistor and the first select transistor The n-type diffusion layer constituting the drain of the memory element is shared, the n-type diffusion layer constituting the source of the first memory element and the drain of the second memory element is shared, and the second memory The non-volatile semiconductor memory cell is characterized in that the n-type diffusion layer constituting the source of the element and the drain of the second selection transistor is shared.

  (14) The present invention also provides a nonvolatile semiconductor memory device having a memory cell array using a plurality of the nonvolatile semiconductor memory cells described in the above invention, wherein the memory cell array is arranged in a matrix in the row direction and the column direction. A plurality of the non-volatile semiconductor memory cells arranged; a control gate line commonly connected to the first control gate terminal for each column of the non-volatile semiconductor memory cells arranged in the matrix; and the matrix A drain line commonly connected to the drain terminal of the nonvolatile semiconductor memory cell for each column arranged in common, and a common to the source terminal of the nonvolatile semiconductor memory cell for each column arranged in a matrix The nonvolatile semiconductor is connected to each of the connected source lines and the rows arranged in the matrix. A first select gate line commonly connected to the first select gate terminal of the memory cell, and a common connection to the second select gate terminal of the nonvolatile semiconductor memory cell for each row arranged in the matrix form A second switch provided between the source line and the source power line, and a first switch provided between the drain line and the drain power line. , A third switch provided between the control gate line and the first gate power supply line, and a fourth switch provided between the control gate line and the second gate power supply line And an address signal for selecting the non-volatile semiconductor memory cell included in the memory cell array and a command signal indicating any of write, erase, and read operations The first switch, the second switch, the third switch, the fourth switch, the first gate power supply line, the second switch based on the input address signal and the command signal An operation corresponding to the command signal is applied to the nonvolatile semiconductor memory cell selected by the address signal by applying a voltage to the gate power supply line, the first select gate line, and the second select gate line. And the non-volatile semiconductor memory cells adjacent to each other in the row direction share the control gate line with each other, and the first non-volatile semiconductor memory cells have the first control gate terminal And the second control gate terminal are connected to different control gate lines from each other. It is a position.

  (15) Further, according to the present invention, in the above invention, when the voltage applied to the semiconductor substrate is a reference voltage and a write operation is performed, the control unit is connected to the selected nonvolatile semiconductor memory cell. A first voltage is applied to the first select gate line and the second select gate line, and a voltage of 0 V is applied to the drain line and the source line connected to the nonvolatile semiconductor memory cell. The first select gate line connected to the nonvolatile semiconductor memory cell sharing the control gate with the selected nonvolatile semiconductor memory cell and the second select gate line are used as neighboring select gate lines. The first voltage is applied to the drain line and the source line connected to the nonvolatile semiconductor memory cell and the neighboring select gate line. A voltage applied to the neighboring select gate line after a predetermined time has elapsed is changed to 0 V, and a fourth voltage is applied to the control gate line connected to the selected nonvolatile semiconductor memory cell, A high electric field is applied to the vicinity of the drain of the first memory element and the source of the second memory element of the selected non-volatile semiconductor memory cell, and the first memory element and the second memory element are respectively A Fowler-Nordheim tunnel current is generated from the control gate to the semiconductor substrate, electrons are injected and stored in the floating gate of each of the memory elements, and the first semiconductor memory cell in the adjacent column is stored. The floating gate of each of the memory element and the second memory element is electrically coupled by coupling. The control unit applies a voltage of 0 V to the two control gate lines connected to the selected nonvolatile semiconductor memory cell when the applied electric field is relaxed to prevent erroneous writing and erase operation. Applying the eighth voltage to the first select gate line and the second select gate line connected to the selected nonvolatile semiconductor memory cell, and selecting the nonvolatile semiconductor memory cell A fifth voltage is applied to the drain line and the source line connected to each other, and near the drain of the first memory element and the source of the second memory element of the selected nonvolatile semiconductor memory cell. A high electric field is applied, and Fowler-Nordheim's drain from the drain of the first memory element and the source of the second memory element to each control gate. In the case of performing a read operation by generating a channel current, emitting electrons from the floating gates of the respective memory elements, the control unit includes the first select gate connected to the selected nonvolatile semiconductor memory cell. A seventh voltage is applied to the line and the second select gate line, a sixth voltage is applied to the drain line connected to the nonvolatile semiconductor memory cell, and the voltage is applied to the nonvolatile semiconductor memory cell. Applying a voltage of 0 V to the source line, applying the sixth voltage to the control gate line connected to the nonvolatile semiconductor memory cell, and sharing the control gate line with the nonvolatile semiconductor memory cell The first select gate line, the second select gate line, the drain line, and the source connected to the conductive semiconductor memory cell 0V is applied to the scan line, the stored data is read depending on whether or not a current flows through the selected nonvolatile semiconductor memory cell, and the nonvolatile semiconductor memory is read from the selected nonvolatile semiconductor memory cell When the verify operation is performed to determine whether the threshold voltages of the first memory element and the second memory element of the cell are changed to be higher than or equal to a preset threshold voltage of the write state, the control unit is selected The drain line connected to the selected non-volatile semiconductor memory cell by applying a seventh voltage to the first select gate line and the second select gate line connected to the non-volatile semiconductor memory cell. A sixth voltage is applied to the non-volatile semiconductor memory cell, and a voltage of 0 V is applied to the source line connected to the selected non-volatile semiconductor memory cell. The first voltage higher than the voltage applied at the time of data reading is applied to one of the first memory element and the second memory element connected to the semiconductor memory cell, and the other memory element is applied. A voltage for confirming a threshold voltage is applied, the first select gate and the second select gate connected to the selected nonvolatile semiconductor memory cell are turned on, the one memory element is turned on, Whether the other memory element is turned on is detected by a flowing current.

  (16) The present invention also provides a first memory element and a second memory element which are MOS transistors formed on a semiconductor substrate, a first selection transistor which is a MOS transistor for selecting the memory element, A non-volatile semiconductor memory device having a memory cell array in which non-volatile semiconductor memory cells composed of two select transistors are arranged, the first n-type diffusion layer forming the drain of the first select transistor, A first polysilicon for forming a gate electrode of the first select transistor; a second n-type diffusion layer for forming a source of the first select transistor and a drain of the first memory element; A second polysilicon for forming a floating gate electrode of the memory element; a source of the first memory element; and a second memory. A third n-type diffusion layer forming a drain of the second element, a third polysilicon forming a floating gate electrode of the second memory element, a source of the second memory element, and the second selection A fourth n-type diffusion layer forming the drain of the transistor; a fourth polysilicon forming the gate electrode of the second selection transistor; and a fifth n-type forming the source of the second selection transistor. A transistor forming portion in which a diffusion layer is sequentially arranged in a series direction; a sixth diffusion layer arranged in parallel with the transistor forming portion in the series direction and at a position intersecting with the second polysilicon; Parallel to the transistor formation portion, in the series direction on the opposite side of the sixth n-type diffusion layer with respect to the transistor formation portion, and intersecting with the third polysilicon. A seventh diffusion layer disposed at a position where the first diffusion layer is disposed; a first metal wiring disposed in the series direction connected to the sixth diffusion layer via a contact; A plurality of non-volatile semiconductor memory cells arranged in a matrix in the row direction and the column direction as the arrangement of the memory cell array. The nonvolatile semiconductor memory cells are arranged symmetrically with respect to a direction perpendicular to the series direction and the nonvolatile semiconductor memory cells adjacent to the series direction. And the first n-type diffusion layer in common and the other non-volatile semiconductor memory cell and the fifth n-type diffusion layer in common are adjacent to each other in the series direction. The sixth diffusion layer and the seventh diffusion layer of the nonvolatile semiconductor memory cell are connected, and the first metal wiring and the second metal of the nonvolatile semiconductor memory cell adjacent in the series direction are connected The wiring is connected, and the nonvolatile semiconductor memory cell includes the nonvolatile semiconductor memory cell adjacent in the direction perpendicular to the series direction, the sixth diffusion layer, the first metal wiring, and the seventh The diffusion layer and the second metal wiring are shared, the first polysilicon and the fourth polysilicon are connected, and the non-volatile semiconductor memory cell is connected to the first polysilicon layer for each column. A non-volatile semiconductor memory device, wherein an n-type diffusion layer is commonly connected to a drain line via a contact, and the fifth n-type diffusion layer is commonly connected to a source line via a contact. That.

  According to the present invention, a non-volatile semiconductor memory cell having a small arrangement area and improved memory retention reliability by arranging memory elements in series in a plane and in series with a select transistor, and The used nonvolatile semiconductor memory device can be realized.

  Hereinafter, a memory device and a nonvolatile semiconductor memory device using the memory device according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic diagram showing a circuit configuration of the nonvolatile semiconductor memory cell 1. As illustrated, the nonvolatile semiconductor memory cell 1 includes a selection transistor Tr11 (first selection transistor), a selection transistor Tr14 (second selection transistor), a floating gate type memory element Tr12 (first memory element), A floating gate type memory element Tr13 (second memory element) is provided.
The select transistor Tr11 has a drain connected to the drain terminal D (first terminal), a gate connected to the select gate terminal SGD (first select terminal), and a source connected to the drain of the memory element Tr12. The memory element Tr12 has a gate connected to the control gate terminal CG and a source connected to the drain of the memory element Tr13. The memory element Tr13 has a gate connected to the control gate terminal CG and a source connected to the drain of the selection transistor Tr14. The selection transistor Tr14 has a gate connected to the select gate terminal SGS (second select terminal) and a source connected to the source terminal S. That is, between the drain terminal D and the source terminal S, the selection transistor Tr11, the memory element Tr12, the memory element Tr13, and the selection transistor Tr14 are connected in series.

Next, the layout of the nonvolatile semiconductor memory cell 1 will be described with reference to FIGS. FIG. 2 is a schematic diagram showing a layout configuration of the nonvolatile semiconductor memory cell 1. FIG. 3A is a schematic diagram showing a cross-sectional structure along A1-A′1 of FIG. FIG. 3B is a schematic diagram showing a cross-sectional structure along B1-B′1 in FIG. FIG. 3C is a schematic diagram showing a cross-sectional structure along C1-C′1 in FIG.
The nonvolatile semiconductor memory cell 1 is formed (arranged) on the p-type semiconductor substrate 100. The transistor forming unit 120 includes an n-type diffusion layer 104 (first n-type diffusion layer), an n-type diffusion layer 116 (second n-type diffusion layer), and an n-type diffusion layer 117 (third n-type diffusion layer). ), An n-type diffusion layer 118 (fourth n-type diffusion layer), and an n-type diffusion layer 105 (fifth n-type diffusion layer) are sequentially formed in the series direction (first direction). The n-type diffusion layer 104 and the n-type diffusion layer 116 are arranged to face each other via the gate region portion 115a where the channel of the selection transistor Tr11 is formed. The n-type diffusion layer 116 and the n-type diffusion layer 117 are arranged to face each other via the gate region portion 106a in which the channel of the memory element Tr12 is formed. The n-type diffusion layer 117 and the n-type diffusion layer 118 are disposed to face each other via the gate region portion 106b where the channel of the memory element Tr13 is formed. The n-type diffusion layer 118 and the n-type diffusion layer 105 are disposed to face each other via the gate region portion 115b where the channel of the selection transistor Tr14 is formed.
The n-type diffusion layer 104 is connected to the drain terminal D via the contact 107a. The n-type diffusion layer 105 is connected to the source terminal S via the contact 107b.

The polysilicon 114a (first polysilicon) is a gate electrode of the selection transistor Tr11 provided above the gate region portion 115a. The polysilicon 103a (second polysilicon) is a gate electrode of the memory element Tr12 provided above the gate region portion 106a. The polysilicon 103b (third polysilicon) is a gate electrode of the memory element Tr13 provided above the gate region portion 106b. The polysilicon 114b (fourth polysilicon) is a gate electrode of the selection transistor Tr14 provided on the gate region 115b.
The n-type diffusion layer 101 (sixth diffusion layer) has a well structure on the p-type semiconductor substrate 100. The n-type diffusion layer 101 is provided in parallel with the transistor formation portion 120 and is disposed at a position intersecting with the polysilicon 103a and 103b. In addition, the n-type diffusion layer 101 is formed in a shape in which the gate region portion 102 (110a, 110b), which is partially raised in a convex shape, narrows the distance from the polysilicon 103a, 103b. The capacitance of the floating gate is set by this interval. Further, the polysilicons 103 a and 103 b are disposed perpendicular to the series direction of the transistor formation unit 120. Metal wiring 111 (first metal wiring) connects n-type diffusion layer 101 and control gate terminal CG through contacts 112a and 112b. Although not shown, an n-type (n +) diffusion layer is formed in a region of the gate region 102 other than under the polysilicons 114a, 103a, 103b, and 114b.

  FIG. 4 is a diagram showing operating voltages for writing 1, writing 2, erasing 1, erasing 2 and reading of the nonvolatile semiconductor memory cell 1. An operation of writing 1 and an operation of writing 2 in which electrons are injected and accumulated in the floating gates of the memory elements Tr12 and Tr13, an operation of erasing 1 and an operation of erasing 2 for emitting electrons from the floating gates of the memory elements Tr12 and Tr13, The operation of reading data stored in the memory elements Tr12 and Tr13, and the voltage applied in each case are shown.

(Operation of write 1)
A voltage of 5V (first voltage) is applied to the drain terminal D, a voltage of 0V is applied to the source terminal S and the semiconductor substrate 100, and a voltage of 7V that is equal to or higher than the voltage applied to the drain terminal D is applied to the select gate terminals SGD and SGS. A voltage (third voltage) is applied, and a voltage of 9 V (second voltage) equal to or higher than the voltage applied to the drain terminal D is applied to the control gate terminal CG.
Since the memory elements Tr12 and Tr13 are connected in series, it may take time to write, and the voltage applied to the control gate terminal CG is set to a higher voltage of 9V. Here, the voltage applied to the drain and gate of the memory elements Tr12 and Tr13 is a voltage at which the memory elements Tr12 and 13 operate in a saturation region.
At this time, a channel is formed in each of the gate regions 106a and 106b of the memory elements Tr12 and Tr13, hot electrons that are electrons having high energy are generated along with the channel current, and the generated hot electrons are injected into the floating gate. Accumulated. As a result, the threshold voltage of the nonvolatile semiconductor memory cell 1 changes to a voltage higher than the initial state, and a write state is set.

(Operation of write 2)
A voltage of 0V is applied to the drain terminal D, the source terminal S, and the semiconductor substrate 100, a voltage of 7V is applied to the select gate terminals SGD and SGS, and a voltage of 12V (fourth voltage) is applied to the control gate terminal CG. . Here, the voltage (fourth voltage) applied to the control gate terminal CG is a voltage that generates a Fowler-Nordheim tunnel current between the semiconductor substrate 100 and the control gates of the memory elements Tr12 and Tr13.
At this time, a high electric field is applied between the floating gates of the memory elements Tr12 and Tr13 and the semiconductor substrate 100, an FN current is generated, and electrons are injected into the floating gate and accumulated. As a result, the threshold voltage of the nonvolatile semiconductor memory cell 1 changes to a voltage higher than the initial state, and a write state is set.
This writing 2 is writing by FN current, and unlike writing 1, even if writing is performed simultaneously on a plurality of memory elements Tr12 and Tr13, there is no effect on the characteristics of the writing time.

(Operation of erase 1)
A voltage of 0 V is applied to the control gate terminal CG, and a voltage of 12 V is applied to the select gate terminals SGD, SGS, the drain terminal D, the source terminal S, and the semiconductor substrate 100.
At this time, an FN current flows in the opposite direction to that in the case of writing 2, electrons are emitted from the floating gate, and an erase state is entered in which the threshold voltage is changed to a voltage lower than the initial state.

(Erase 2 operation)
A voltage of 10V (fifth voltage) is applied to the drain terminal D and the source terminal S, a voltage of 0V is applied to the semiconductor substrate 100, and a voltage applied to the drain terminal D and the source terminal S to the select gate terminals SGD and SGS. The above voltage of 12V (eighth voltage) is applied, and a voltage of 0V is applied to the control gate terminal CG. Here, the voltage of 12 V (eighth voltage) applied to the select gate terminals SGD and SGS is higher than the voltage obtained by combining the voltage applied to the drain terminal D and the source terminal S and the threshold voltage of the selection transistors Tr11 and Tr12. Voltage. That is, (voltage applied to select gate terminals SGD, SGS (eighth voltage)) ≧ (voltage applied to drain terminal and source terminal) + (threshold voltage of selection transistors Tr11, 12) may be satisfied.
At this time, a high electric field is applied near the drain of the memory element Tr12 and near the source of the memory element Tr13, an FN current flows, and electrons are emitted from the floating gate. As a result, an erased state in which the threshold voltage is changed to a voltage lower than the initial state is obtained.

(Read operation)
A voltage of 1V (sixth voltage) is applied to the drain terminal D, a voltage of 0V is applied to the source terminal S and the semiconductor substrate 100, and a voltage of 3V higher than the voltage applied to the drain terminal D is applied to the select gate terminals SGD and SGS. A voltage (seventh voltage) is applied, and a voltage of 0 V to 3 V is applied to the control gate terminal CG. The voltage applied to the control gate terminal CG is set to a voltage exceeding the threshold voltage in the initial state of the memory elements Tr12 and Tr13, and an arbitrary voltage equal to or lower than the threshold voltage in the predetermined writing state is set as the reading voltage.

  By setting in this way, in the write operation, if the write operation is performed on at least one of the memory elements Tr12 and Tr13 connected in series, the nonvolatile semiconductor memory cell 1 is turned off, and the write operation is performed. It can be judged as a state. That is, by connecting the memory elements Tr12 and Tr13 in series, it is possible to improve the reliability of write data to the nonvolatile semiconductor memory cell 1.

  On the other hand, in the nonvolatile semiconductor memory cell 1 in the erased state, as shown in FIG. 28, the threshold voltages of the memory elements Tr12 and Tr13 gradually approach the initial voltage as electrons are removed. Therefore, by setting the read voltage to a voltage higher than the threshold voltage in the initial state, the read can be performed without causing a failure. That is, the nonvolatile semiconductor memory cell 1 needs to pay attention only to the write operation.

  Although not shown, in consideration of the case where the oxide film between the floating gate and the drain or the oxide film between the floating and the source is damaged and short-circuited, the initial state of the memory elements Tr12 and Tr13 is changed. The drain voltage and the read voltage of the control gate terminal CG are set higher than the threshold voltage. As a result, even if the gate is damaged, the damaged memory elements Tr12 and Tr13 are turned on, so that they do not become erasure defects, but only the off-side defects need to be paid attention.

Next, the write prohibiting operation will be described with reference to FIGS.
FIG. 5 is a diagram showing a write inhibit operation. For example, write prohibition means that a voltage of 0 V is applied to the drain terminal D, the source terminal S, the select gate terminals SGD, SGS, and the semiconductor substrate 100 in the nonvolatile semiconductor memory cell 1, and a voltage of 12 V is applied to the control gate terminal CG. A voltage is applied. At this time, the nonvolatile semiconductor memory cell 1 is in a non-selected state.

FIG. 6A is a schematic diagram showing the coupling of the capacitance of the nonvolatile semiconductor memory cell 1. C1 is a capacitance between the control gate terminal CG and the floating gate. C2 is a capacitance between the floating gates 103a and 103b and the n-type diffusion layers 116, 117, and 118 that are the sources and drains of the memory elements Tr12 and Tr13. C3 is a capacitance between the floating gates 103a and 103b and the gate region portions 106a and 106b where the channels are formed. C4 is a capacitance between the n-type diffusion layers 116, 117, and 118 and the semiconductor substrate 100. C5 is a capacitance between the inversion layers of the gate region portions 106a and 106b and the semiconductor substrate 100.
At this time, since the voltage of 0V is applied to the select gate terminals SGD and SGS, the select transistors Tr11 and Tr14 are off.

FIG. 6B is a schematic diagram showing an equivalent circuit of the capacitance of the nonvolatile semiconductor memory cell 1. In general, the capacitance ratio is preferably set to C1: C2: C3: C4: C5 = 15: 2: 6: 1: 1. When the capacitance ratio is set in this way, when the voltage VCG applied to the control gate terminal CG is set to 12V, the voltage VFG of the floating gate and the voltages Vdrain of the source and drain of the memory elements Tr12 and Tr13 are obtained by coupling. As shown in FIG. 5, VFG = 7.2V and Vdrain = 5.8V.
Since Vdrain is 5.8 V in the write inhibit operation, the applied electric field is weakened even when a voltage of 12 V is applied to the control gate terminal of the memory elements Tr12 and Tr13, and the FN current does not flow and writing is performed. There will be no write protection. This operation is an important operation when configuring a memory cell array in which the nonvolatile semiconductor memory cells 1 are arranged in a matrix.

  As described above, by connecting the memory elements Tr12 and Tr13 in series, it is possible to improve the reliability with respect to the written state. Further, by using the layout described above, four transistors can be arranged in series, and the nonvolatile semiconductor memory cell 1 can be mounted with a small arrangement area.

(Second Embodiment)
FIG. 7 is a schematic diagram showing the nonvolatile semiconductor memory cell 20 of the second embodiment. The nonvolatile semiconductor memory cell 20 is a circuit equivalent to the nonvolatile semiconductor memory cell 1 shown in FIG. By using the illustrated layout, the non-volatile semiconductor memory cell 20 of the second embodiment can be arranged with a smaller arrangement area than the first embodiment. FIG. 7A is a schematic diagram showing a plan view of the layout of the nonvolatile semiconductor memory cell 1. FIG. 7B is a schematic diagram showing a cross-sectional structure along A2-A′2 in FIG. FIG. 7C is a schematic diagram showing a cross-sectional structure along B2-B′2 in FIG. FIG. 7D is a schematic diagram showing a cross-sectional structure along C2-C′2 in FIG.

Compared to the first embodiment, the n + diffusion layer 219 (sixth diffusion layer) is used instead of the n-type diffusion layer 101. The transistor formation portion 220 on the p-type semiconductor substrate 200 includes an n-type diffusion layer 204 (first n-type diffusion layer), polysilicon 214a (first polysilicon), and n-type diffusion layer 216 (second n-type). Type diffusion layer), polysilicon 203a (second polysilicon), n-type diffusion layer 217 (third n-type diffusion layer), polysilicon 203b (third polysilicon), n-type diffusion layer 218 (fourth) N-type diffusion layer), polysilicon 214b (fourth polysilicon), and n-type diffusion layer 205 (fifth n-type diffusion layer) are sequentially formed in the series direction (first direction).
The n-type diffusion layer 204 is the drain of the selection transistor Tr11. The n-type diffusion layer 216 is the source of the selection transistor Tr11 and the drain of the memory element Tr12. The n-type diffusion layer 217 is a source of the memory element Tr12 and a drain of the memory element Tr13. The n-type diffusion layer 218 is the source of the memory element Tr13 and the drain of the selection transistor Tr14. The n-type diffusion layer 205 is the source of the selection transistor Tr14.
The n-type diffusion layer 204 is connected to the drain terminal D through the contact 207a. The n-type diffusion layer 205 is connected to the source terminal S via the contact 207b.

  The n-type diffusion layers 204 and 216 are arranged to face each other via the gate region portion 215a where the channel of the selection transistor Tr11 is formed. The n-type diffusion layers 216 and 217 are arranged to face each other via the gate region portion 206a where the channel of the memory element Tr12 is formed. The n-type diffusion layers 217 and 218 are arranged to face each other via the gate region portion 206b where the channel of the memory element Tr13 is formed. The n-type diffusion layers 218 and 205 are arranged to face each other via the gate region portion 215b where the channel of the selection transistor Tr14 is formed.

  The polysilicon 214a is a gate electrode of the selection transistor Tr11 provided above the gate region 215a. The polysilicon 203a is a gate electrode of the memory element Tr12 provided above the gate region 206a. The polysilicon 203b is a gate electrode of the memory element Tr13 provided on the gate region 206b. The polysilicon 214b is a gate electrode of the selection transistor Tr14 provided above the gate region 215b. Further, each of the polysilicones 214a, 203a, 203b, and 214b is formed in a direction perpendicular to the series direction of the transistor forming part 220.

  The n + -type diffusion layer 219 is disposed on the semiconductor substrate 200 in parallel with the transistor formation portion 220 and at a position where it intersects with the polysilicons 203a and 203b. Metal wiring 211 (first metal wiring) connects n + -type diffusion layer 219 and control gate terminal CG via contacts 212a and 212b. The oxide film 213 is provided on the semiconductor substrate 200 so as to separate the transistor formation part 220 and the polysilicons 214a, 203a, 203b, and 214b. The oxide film 213 is provided on the semiconductor substrate 200 so as to be separated from the n + type diffusion layer 219 and the polysilicons 214a, 203a, 203b, and 214b. A gate oxide film is formed on the gate region portions 215a, 206a, 206b, and 215b. The surface 210a of the n + -type diffusion layer 219 facing the polysilicon 203a and the polysilicon 203a form a floating gate capacitor of the memory element Tr12.

Since the nonvolatile semiconductor memory cell 20 uses an n + type diffusion layer, it is necessary to form an n + type diffusion layer before forming a gate oxide film as a manufacturing process. Although the number of processes increases compared to a standard CMOS process, which is a simple process, the area of the nonvolatile semiconductor memory cell 1 can be reduced.
As a different method, after the n-type diffusion layer is formed, an equivalent effect can be obtained by implanting a deeper depletion type channel implant (such as phosphorus or arsenic). Further, since only an implantation process is added, it is almost the same as the standard CMOS process.

  By using the non-volatile semiconductor memory cell 20 described above, the non-volatile semiconductor memory cell 1 can be mounted with a smaller area than the first embodiment.

(Third embodiment)
FIG. 8 is a schematic diagram showing a configuration of a memory cell array 21 using a plurality of nonvolatile semiconductor memory cells 1 or nonvolatile semiconductor memory cells 20. As shown in the figure, a memory cell array 21 is configured by arranging nonvolatile semiconductor memory cells 1 or nonvolatile semiconductor memory cells 20 in a matrix. In each of the nonvolatile semiconductor memory cells 1 in the same column, the drain terminal D, the source terminal S, and the control gate terminal CG are commonly connected. For example, in the same column of nonvolatile semiconductor memory cells M11, M21,..., Mm1 (hereinafter, memory cells M11, M21,..., Mm1), the drain terminal D is commonly connected to the drain line D1, and the source terminal S is the source line. S1 is commonly connected, and the control gate terminal CG is commonly connected to the control gate line CG1.
Further, the memory cells M11, M12,..., M1n in the same row commonly connect the select gate terminals SGD, SGS, respectively. For example, in the memory cells M11, M12,..., M1n in the same row, the select gate terminal SGD is commonly connected to the select gate line SGD1, and the select gate line SGS is commonly connected to the select gate line SGS1.

FIG. 9 is a schematic diagram showing a layout of the memory cell array 21. This is an example in which a nonvolatile semiconductor memory cell 20 is used.
In the memory cell array 21, the memory cells M11,..., Mmn are arranged in a matrix in the row direction and the column direction. In addition, the memory cells M11,..., Mmn adjacent in the vertical direction (series direction of the transistor formation portion 220) in the figure are arranged symmetrically with respect to the direction perpendicular to the series direction. Further, the memory cells M11,..., Mmn share one memory cell adjacent in the series direction with the n-type diffusion layer 204 and the contact 207a which are the drains of the selection transistor Tr11, and the other adjacent to the series direction and the selection transistor Tr14. Share the n-type diffusion layer 205 and the contact 207b.
A plurality of columns arranged in series in this way are arranged in parallel to constitute the memory cell array 21.

Further, the memory cell array 21 includes source lines S1, S2,..., Sn, drain lines D1, D2,. The source lines S1, S2,..., Sn provided for each column are connected in common to the source terminals of the memory cells in the column, and the drain lines D1, D2,. The terminals are connected in common. Further, the n + -type diffusion layer 219 and the metal wiring 211 connected to the n + -type diffusion layer 219 of the memory cells M11,..., Mmn adjacent in the vertical direction are connected to each other.
FIG. 10 is a diagram illustrating an example of voltages applied in the write, erase, read, and write verify operations of the memory cell array 21. As shown in the figure, the operation when M11 is selected to perform writing, erasing, reading and writing verification is shown.

(Write operation)
In the write operation, a voltage of 12V is applied to the control gate line CG1, and a voltage of 0V is applied to the other control gate lines. Further, a voltage of 7V is applied to the select gate lines SGD1, SGS1, and a voltage of 0V is applied to the other select gate lines SGD2,..., SGDm, SGS2,. A voltage of 0 V is applied to all drain lines, all source lines, and the semiconductor substrate.
As a result, the operation of writing 2 shown in FIG. 4 is performed on the selected memory cell M11, and writing is performed on the memory cell M11. On the other hand, for the memory cells M21,..., Mm1, a voltage of 12V is applied to the control gate terminal CG, but a voltage of 0V is applied to the select gate terminals SGD, SGS, and the write inhibit shown in FIG. The operation is performed and the stored data is held. In each of the memory cells M12,..., M1n, a voltage of 0 V is applied to the control gate terminal, and a voltage of 7 V is applied to the select gate terminals SGD, SGS. As a result, no electric field is applied to the floating gate and writing is not performed, and stored data is retained. A voltage of 0 V is applied to the control gate terminal CG, select gate terminals SGD, SGS, drain terminal D, and source terminal S of other memory cells, and writing is not performed.

(Erase operation)
In the erasing operation, a voltage of 12V is applied to the select gate lines SGD1 and SGS1, and a voltage of 0V is applied to the other select gate lines. Further, a voltage of 10 V is applied to the drain line D1 and the source line S1, and a voltage of 0 V is applied to the other drain lines and source lines. A voltage of 0 V is applied to all control gate lines and the semiconductor substrate.
As a result, the operation of erase 2 shown in FIG. 4 is performed on the selected memory cell M11, and the memory cell M11 is erased. On the other hand, for the memory cells M21,..., Mm1, a voltage of 0V is applied to the control gate terminal, a voltage of 0V is applied to the select gate terminals SGD, SGS, and a voltage of 10V is applied to the drain terminal D and the source terminal S. Is applied, and no voltage is applied to the drain and source of each of the memory elements Tr12 and Tr13, and erasing is not performed. For the memory cells M12,..., M1n, a voltage of 0V is applied to the control gate terminal, a voltage of 12V is applied to the select gate terminals SGD, SGS, and a voltage of 0V is applied to the drain terminal D and the source terminal S. Is applied, no electric field is applied to the floating gates of the memory elements Tr12 and Tr13, and erasing is not performed. For other memory cells, a voltage of 0 V is applied to the control gate terminal CG, select gate terminals SGD, SGS, drain terminal D, and source terminal S, and erasing is not performed.

(Read operation)
In the read operation, a voltage of 3V is applied to the select gate lines SGD1 and SGS1, and a voltage of 0V is applied to the other select gate lines. Further, a voltage of 1V is applied to the drain line D1, and a voltage of 0V is applied to the other drain lines. In addition, a voltage of 0 V is applied to all source lines, control gate lines, and the semiconductor substrate.
Accordingly, the read operation shown in FIG. 4 is performed on the selected memory cell M11, and the memory cell M11 is turned on or off depending on the threshold voltage state of the memory elements Tr12 and Tr13.

(Write verify operation)
When performing write verify, which is a check of the threshold voltage of the written memory cell, for example, a voltage of 1V is applied to the control gate line CG1, and a voltage of 0V is applied to the other control gate lines. Further, a voltage of 3V is applied to the select gate lines SGD1, SGS1, and a voltage of 0V is applied to the other select gate lines. Further, a voltage of 1V is applied to the drain terminal D1, and a voltage of 0V is applied to the other drain terminal. Further, a voltage of 0 V is applied to all the source lines and the semiconductor substrate.
At this time, if the threshold voltage after the write operation to the selected memory cell M11 is 1 V or less, a current flows. If the threshold voltage after the write operation is 1 V or more, no current flows. Can be determined. Furthermore, the threshold voltage after writing can be monitored by changing the voltage applied to the control gate line CG1 to 0 V to 3 V, for example. That is, it is possible to detect whether or not the threshold voltage of the memory element Tr12 or Tr13 has changed more than a predetermined threshold voltage in the writing state or higher than the reading voltage.

  FIG. 11 is a diagram illustrating an example of voltages applied in the write, erase, read, write verify, and erase verify operations of the memory cell array 21. As shown in the figure, an erase verify operation is additionally shown in addition to the operation shown in FIG. Here, the added erase verify will be described.

(Erase verify operation)
When performing erase verify, which is a check of the threshold voltage of the erased memory cell, for example, a voltage of 0 V is applied to the control gate line CG1, and a voltage of 0 V is applied to the other control gate lines. Further, a voltage of 3V is applied to the select gate lines SGD1, SGS1, and a voltage of 0V is applied to the other select gate lines. Further, a voltage of 1V is applied to the drain terminal D1, and a voltage of 0V is applied to the other drain terminal. Further, a voltage of 0 V is applied to all the source lines and the semiconductor substrate.
Similar to the write verify, the check is performed by the current caused by turning on and off the memory elements Tr12 and Tr13 of the selected memory cell M11. When the read voltage applied to the control gate line CG1 during the read operation is 1V, the voltage applied to the control gate line CG1 during the write verify is 2V, and the voltage applied to the control gate line CG1 during the erase verify is 0V. For both writing and erasing, a margin of 1 V with respect to the threshold voltage can be secured. This also makes it possible to detect whether the threshold voltage of the memory elements Tr12 and Tr13 has changed below a predetermined erase state threshold voltage or read voltage.

  Next, FIG. 12 is a diagram showing applied voltages in page write, page erase, and page read operations of the memory cell array 21. As shown in the figure, page write for performing batch write in row units and page erase for performing batch erase in row units for the memory cells M11 to M1n of the nonvolatile semiconductor memory cells 1 arranged in a matrix. Is shown.

(Page write operation)
In the page write operation, a voltage of 12V is applied to all the control gate lines CG1 to CGn, a voltage of 7V is applied to the select gate lines SGD1 and SGS1, and a voltage of 0V is applied to the other select gate lines. A voltage of 0 V is applied to the drain line, all source terminals and the semiconductor substrate.
As a result, writing is simultaneously performed on all the memory cells M11 to M1n connected to the select gate lines SGD1 and SGS1.

(Page erase operation)
In the page erase operation, a voltage of 10V is applied to all drain lines and all source lines, a voltage of 12V is applied to the select gate lines SGD1, SGS1, and a voltage of 0V is applied to the other select gate lines. By applying a voltage of 0 V to all the control gate lines and the semiconductor substrate, all the memory cells M11 to M1n connected to the select gate lines SGD1 and SGS1 are erased simultaneously.

  As described above, the non-volatile semiconductor memory cells 1 are arranged in a matrix, and the drain terminal D, the source terminal S, the select gate terminals SGD, SGS, and the control gate terminal CG are connected to store a plurality of data. The cell array 21 can be configured. Further, in the vertically adjacent nonvolatile semiconductor memory cells 1, the n-type diffusion layer 204 and the contact 207a that are the drains of the selection transistor Tr11 are shared, and the n-type diffusion layer 205 and the contact 207b that are the sources of the selection transistor Tr14. Share. Thereby, the area required for arrangement can be reduced.

(Fourth embodiment)
FIG. 13 is a schematic diagram showing a configuration of a nonvolatile semiconductor memory device 150 using the memory cell array 21 of the third embodiment. As illustrated, the nonvolatile semiconductor memory device 150 includes a control unit 160, a sense amplifier circuit 156, switches SWG1 to SWGn, SWG1B to SWGnB, SWD1 to SWDn, SWS1 to SWSn, and a gate power supply line connected to the gate power supply circuit 155. G, GB, gate selection lines G1 to Gn and G1B to GnB connected to the gate decoder / driver 154, source power supply lines SL and drain power supply lines DL connected to the drain power supply circuit 153, and column decoder / driver 152 Column selection lines C1 to Cn.
The control unit 160 includes a control circuit 151, row decoder / drivers ROW1 to ROWm, a column decoder / driver 152, a drain power supply circuit 153, a gate decoder / driver 154, and a gate power supply circuit 155.

The memory cell array 21 is configured by arranging a plurality of nonvolatile semiconductor memory cells 1 in a matrix. In each of the nonvolatile semiconductor memory cells 1 in the same column, the drain terminal D, the source terminal S, and the control gate terminal CG are commonly connected. For example, in the same column of nonvolatile semiconductor memory cells M11, M21,..., Mm1 (hereinafter, memory cells M11, M21,..., Mm1), the drain terminal D is commonly connected to the drain line D1, and the source terminal S is the source line. S1 is commonly connected, and the control gate terminal CG is commonly connected to the control gate line CG1.
In addition, each of the memory cells 1 in the same row commonly connects the select gate terminals SGD and SGS. For example, in the memory cells M11, M12,..., M1n in the same row, the select gate terminal SGD is commonly connected to the select gate line SGD1, and the select gate line SGS is commonly connected to the select gate line SGS1.

  The switches SWD1 to SWDn (first switch) are provided between the corresponding drain lines D1 to Dn and the drain power supply line DL. Switches SWS1 to SWSn (second switches) are provided between corresponding source lines S1 to Sn and source power supply line SL. The switches SWG1 to SWGn (third switch) are provided between the corresponding control gate lines CG1 to CGn and the gate power supply line G. The switches SWG1B to SWGnB (fourth switch) are provided between the corresponding control gate lines CG1 to CGn and the gate power supply line GB.

The control circuit 151 receives a command signal indicating any of write, erase, read, write verify, and erase verify operations. In addition, the control circuit 151 decodes the input command signal and applies voltages to the gate power supply circuit 155, the gate decoder / driver 154, the drain power supply circuit 153, the column decoder / driver 152, and the row decoder / driver ROW1 to ROWm. A control signal indicating is output. Here, the voltage indicated by the control signal is the voltage shown in FIGS.
The gate power supply circuit 155 performs control to output a voltage applied to the control gate terminal CG shown in FIGS. 10 to 12 to the gate line G and the gate line GB based on the control signal input from the control circuit 151. At this time, the voltage applied to the gate power supply line G is a voltage applied to the control gate terminal CG included in the selected memory cell among the memory cells M11 to Mmn. On the other hand, the voltage applied to the gate power supply line GB is a voltage applied to the control gate terminal CG of the non-selected nonvolatile semiconductor memory cell 1.

An address signal for selecting the memory cells M11 to Mmn and a control signal from the control circuit 151 are input to the gate driver 154 from the outside. The gate driver 154 applies a voltage to the gates of the switches SWG1 to SWGn and SWG1B to SWGnB via the gate lines G1 to Gn and G1B to GnB based on the input address signal and control signal, and turns on and off. The gate line G is connected to the control gate line of the column including the memory cell selected by the address signal, and the gate line GB is connected to the other column.
The drain power supply circuit 153 applies a voltage to the drain line DL and the source line SL based on the control signal input from the control circuit 151. Here, the voltage applied to the drain power supply line DL by the drain power supply circuit 153 is a voltage applied to the drain terminal D shown in FIGS. The voltage applied to the source power supply line SL by the drain power supply circuit 153 is the voltage applied to the source terminal S shown in FIGS.
The column decoder / driver 152 receives an address signal for selecting the memory cells M11 to Mmn from the outside and a control signal from the control circuit 151. In addition, the column decoder / driver 152 switches on and off by applying a voltage to the gates of the switches SWD1 to SWDn via the column selection lines C1 to Cn based on the input address signal and control signal, thereby switching the address signal. The drain line of the row including the memory cell selected by the above and the drain power supply line DL are connected. Further, the column decoder / driver 152 switches on and off by applying a voltage to the gates of the switches SWS1 to SWSn via the column selection lines C1 to Cn based on the input address signal and control signal, and the address signal The source line of the row including the memory cell selected by the above and the source power line SL are connected.

An address signal for selecting the memory cells M11 to Mmn and a control signal from the control circuit 151 are input to the row decoder / drivers ROW1 to ROWm. In addition, the row decoder / drivers ROW1 to ROWm decode the input address signals and determine whether or not the selected memory cell is included in the corresponding row. Further, the row decoder / drivers ROW1 to ROWm apply a voltage corresponding to the “selected cell” shown in FIGS. 10 to 12 to the select gate line when the selected memory cell is included in the corresponding row. To do. The row decoder / drivers ROW1 to ROWm select voltages corresponding to the “non-selected cells” shown in FIGS. 10 to 12 when the selected memory cell is not included in the corresponding row. Apply to.
In the read operation, the sense amplifier circuit 156 detects and amplifies the current flowing through the drain power supply line DL, and outputs the read data to the outside.

  In this way, by configuring the nonvolatile semiconductor memory device 150, the memory cell array 21 using the nonvolatile semiconductor memory cell 1 can be controlled, and data can be written, erased, and read.

(Fifth embodiment)
FIG. 14 is a schematic diagram showing a configuration of a memory cell array 22 in which a plurality of nonvolatile semiconductor memory cells 1 (memory cells M11a to Mmna) are arranged in a matrix in the row direction and the column direction. The memory cell array 22 is different from the memory cell array 21 shown in FIG. 8 of the third embodiment in that the write verify and erase verify can be performed individually for the memory elements Tr12 and Tr13.
Different control gate signals are applied to the gates of the memory elements Tr12 and Tr13 in the nonvolatile semiconductor memory cells 1 provided in the memory cell array 22 by using two control gate signals. As illustrated, for example, in the memory cell arrays M11a to Mm1a in the same column, the gate of the memory element Tr12 is connected to the control gate line CG1, and the gate of the memory element Tr13 is connected to the control gate line CG2. In the memory cell arrays M12a to Mm2a in adjacent columns, the gate of the memory element Tr12 is connected to the control gate line CG2, and the gate of the memory element Tr13 is connected to the control gate line CG3.

Further, in the memory cell arrays M13a to Mm3a in further adjacent columns, the gate of the memory element Tr12 is connected to the control gate line CG3, and the gate of the memory element Tr13 is connected to the control gate line CG4. The non-volatile semiconductor memory cells 1 adjacent in the row direction share a control gate line connected to the gates of the memory elements Tr12 and Tr13. In other words, the nonvolatile semiconductor memory cell 1 shares a control gate line connected to one of the nonvolatile semiconductor memory cells 1 adjacent in the row direction (lateral direction) and one of the gates of the memory elements Tr12 and Tr13. A control gate line connected to the other of the other adjacent nonvolatile semiconductor memory cells 1 and one of the gates of the memory elements Tr12 and Tr13 is shared.
In this way, in the write verify and erase verify, the threshold voltages of the memory elements Tr12 and Tr13 connected in series included in the nonvolatile semiconductor memory cell 1 can be independently verified, and the memory cell array 21 of the third embodiment. Compared to the above, it becomes possible to accurately determine the threshold voltage.

FIG. 15 is a schematic diagram showing a layout of the memory cell array 22. The plurality of nonvolatile semiconductor memory cells 1 (memory cells M11a to Mmna) provided in the memory cell array 22 are similarly arranged in a matrix in parallel in the column direction and the row direction. Here, the layout of the nonvolatile semiconductor memory cell 1 will be described using the layout of the memory cell M11a.
In the memory cell M11a, as shown in FIG. 7, the transistor formation unit 220 includes an n-type diffusion layer 204 (first n-type diffusion layer), polysilicon 214a (first polysilicon), n-type diffusion layer. 216 (second n-type diffusion layer), polysilicon 203a (second polysilicon), n-type diffusion layer 217 (third n-type diffusion layer), polysilicon 203b (third polysilicon), n-type A diffusion layer 218 (fourth n-type diffusion layer), polysilicon 214b (fourth polysilicon), and n-type diffusion layer 205 (fifth n-type diffusion layer) are formed in series in this order.

The n-type diffusion layer 204 is the drain of the selection transistor Tr11. The n-type diffusion layer 216 is the source of the selection transistor Tr11 and the drain of the memory element Tr12. The n-type diffusion layer 217 is a source of the memory element Tr12 and a drain of the memory element Tr13. The n-type diffusion layer 218 is the source of the memory element Tr13 and the drain of the selection transistor Tr14. The n-type diffusion layer 205 is the source of the selection transistor Tr14.
The n-type diffusion layers 204 and 216 are arranged to face each other via the gate region portion 215a where the channel of the selection transistor Tr11 is formed. The n-type diffusion layers 216 and 217 are arranged to face each other via the gate region portion 206a where the channel of the memory element Tr12 is formed. The n-type diffusion layers 217 and 218 are arranged to face each other via the gate region portion 206b where the channel of the memory element Tr13 is formed. The n-type diffusion layers 218 and 205 are arranged to face each other via the gate region portion 215b where the channel of the selection transistor Tr14 is formed.

The n + -type diffusion layer 219a (sixth diffusion layer) and the n + -type diffusion layer 219b (seventh diffusion layer) are arranged on both sides along the transistor formation portion 220 and are formed in the series direction. The n + -type diffusion layer 219a is connected to the control gate line CG1 (first metal wiring) via contacts 212a and 212b. The n + -type diffusion layer 219b is connected to the control gate line CG2 (second metal wiring) via the contacts 222a and 222b.
The polysilicon 203a is provided above the gate region 206a and is disposed at a position where it intersects with the n + -type diffusion layer 219a, and constitutes a floating gate of the memory element Tr12. The polysilicon 203b is provided above the gate region 206b and is disposed at a position where it intersects with the n + -type diffusion layer 219b, and constitutes a floating gate of the memory element Tr13.

In the memory cell array 22, the memory cells M11a to Mmna are arranged in parallel in a matrix in the row direction and the column direction.
The memory cells M11a to Mmna share the n-type diffusion layer 204 and the contact 207a, which are drains of the selection transistor Tr11, with one adjacent memory cell in the column direction, and select each other with the other adjacent memory cell. The n + type diffusion layer 205 and the contact 207b which are the sources of the transistor Tr14 are shared, and the n + type diffusion layers 219a and 219b of the memory cells adjacent in the column direction are connected. The memory cells M11a to Mmna adjacent in the column direction are arranged symmetrically with respect to the series direction and the vertical direction.

  The polysilicon 203a included in each of the memory cells M11a to Mmna adjacent in the row direction shares the n + -type diffusion layer 219a with any one of the memory cells adjacent in the row direction, and each of the memory cells M11a to Mmna includes The polysilicon 203b shares the n + type diffusion layer 219b with the other adjacent memory cell. For example, between the memory cell M11a and the memory cell M12a adjacent in the row direction, the n + type diffusion layer 219b and the control gate line CG2 to which the n + type diffusion layer 219b is connected are shared.

  In addition, drain lines D1 to Dn and source lines S1 to Sn are provided for each column of the matrix. The drain lines D1 to Dn are commonly connected to the n-type diffusion layer 204 included in each column of memory cells via a contact 207a. The source lines S1 to Sn are commonly connected to the n-type diffusion layer 205 included in each column of memory cells via a contact 207b.

  The memory cell array 22 arranged in this way is configured to be able to independently check the threshold voltages of the memory elements Tr12 and Tr13 provided in each nonvolatile semiconductor memory cell 1. As described above, the threshold voltage can be checked independently. However, since the arrangement position of the polysilicon 203b which is the floating gate electrode of the memory element Tr13 is only moved, the layout area is hardly increased. Is possible.

  Next, FIG. 16 is a diagram illustrating an example of applied voltages in the write, erase, read, and verify operations of the memory cell array 22. As shown in the figure, write, erase, read, and write verify operations when the memory cell M11 is selected are shown. Hereinafter, each operation will be described. Note that the threshold voltage of the selection transistors Tr11 and Tr14 is 1V.

(Write operation)
In the write operation, a voltage of 12V is applied to the control gate lines CG1 and CG2, and a voltage of 0V is applied to the control gate line CG3. Further, a voltage of 5V is applied to the select gate lines SGD1, SGS1, and a voltage of 5V is applied to the select gate lines SGD2, SGS2. Further, a voltage of 0V is applied to the drain line D1, and a voltage of 5V is applied to the drain line D2. Further, a voltage of 0V is applied to the source line S1, and a voltage of 5V is applied to the source line S2. After a predetermined time has elapsed, the voltage applied to the select gate lines SGD2 and SGS2 is changed from 5V to 0V. Thereafter, a voltage of 12V is applied to the control gate lines CG1 and CG2.

Thereby, writing by the FN current is performed in the memory elements Tr12 and Tr13 of the selected memory cell M11 as in the writing 2 shown in FIG.
The memory cell M21 included in the same column as the selected memory cell M11 has the source, drain, and channel (Vdrain) of the memory elements Tr12 and Tr13 of 0V while the voltage of 5V is applied to the select gate lines SGD2 and SGS2. The voltage that is discharged to the voltage and then applied to the select gate lines SGD2, SGS2 changes to 0V, and the select transistors Tr11, Tr14 are turned off. Further, when a voltage of 12V is applied to the control gate lines CG1 and CG2, the voltage Vdrain of the floating gate becomes about 5.8V by the coupling shown in FIG. 6, and the electric field applied to the memory elements Tr12 and Tr13 is increased. As a result, the memory cell M21 is not written.

In the memory cell M12 included in the same row as the selected memory cell M11, a voltage of 12 V is applied to the control gate of the memory element Tr12, but the drain terminal D, the source terminal S, the select gate terminals SGD, SGS. Since a voltage of 5 V is applied to the drains or sources of the memory elements Tr12 and Tr13, a voltage of about 4 V (5 V—the threshold voltage of the selection transistor) is applied, the applied electric field is relaxed, and the memory cell M12 is applied. Is not written.
Further, in the memory cell M22, a voltage of 5V is applied to the drain terminal D and the source terminal S, and a voltage of 5V is applied from the select gate lines SGD2, SGS2 to the select gate terminals SGD, SGS. As a result, the drains or sources of the memory elements Tr12 and Tr13 are charged to about 4V. Later, the voltage applied to the select gate lines SGD2 and SGS2 becomes 0V, and later, the voltage applied to the control gate line CG2 changes to 12V, but about 4V is applied to the drain or source of the memory elements Tr12 and Tr13. Since the voltage is charged, the applied electric field is relaxed, and writing is not performed in the memory cell M22.

(Erase operation)
Next, the erase operation will be described. In the erasing operation, a voltage of 0 V is applied to all the control gate lines CG1 to CGn. Further, a voltage of 12V is applied to the select gate lines SGD1 and SGS1, and a voltage of 0V is applied to the other select gate lines SGD2 to SGDm and SGS2 to SGSm. Further, a voltage of 10V is applied to the drain line D1 and the source line S1, a voltage of 5V is applied to the drain line D2 and the source line S2, and a voltage of 0V is applied to the other drain lines D3 to Dn and the source lines S3 to Sn. Applied.
As a result, the selected memory cell M11 is erased in the same manner as the erase 2 shown in FIG. The memory cell included in the same column as the selected memory cell M11, for example, the memory cell M21, stores the memory elements Tr12 and Tr13 without performing the erasing operation because the selection transistors Tr11 and Tr14 are off. Data is retained. The memory cell included in the same row as the selected memory cell M11, for example, the memory cell M12, is turned on when a voltage of 12V is applied to the gates of the selection transistors Tr11 and Tr14, and the drain of the memory element Tr12 and the memory element Tr13 A voltage of about 5 V is applied to the source, but the applied electric field is weak and erasure is not performed, and the stored data is retained. No voltage is applied to the other memory cells, and no erase operation is performed.

(Read operation)
A reading operation will be described. In the read operation, a read voltage of 1V is applied to all the control gate lines CG1 to CGn, a voltage of 3V is applied to the select gate lines SGD1 and SGS1, a voltage of 1V is applied to the drain line D1, and the source line S1. , S2, the drain line D2, and the select gate lines SGD2, SGS2 are applied with a voltage of 0V.
As a result, only the memory cell M11 is selected and the read operation shown in FIG. 4 is performed, and the data stored in the memory cell M11 is output. In other memory cells, no voltage is applied to all of the select gate terminals SGD, SGS, the drain terminal D, and the source terminal S, and therefore no reading is performed.

(Verify)
The verify operation will be described. The verification is performed individually for each of the memory elements Tr12 and Tr13 included in the memory cell M11. In the verify operation for the memory element Tr12, a voltage of 5V is applied to the control gate line CG2, a voltage of 3V is applied to the select gate lines SGD1 and SGS1, a voltage of 1V is applied to the drain line D1, and the source line S0 is applied. This is done by applying a voltage of 0V and changing the voltage applied to the control gate line CG1 to 0-3V.
Thereby, a voltage of 5V is applied to the control gate of the memory element Tr13 of the memory cell M11, a voltage of 0 to 3V is applied to the control gate of the memory element Tr12, and the current flowing through the drain line D1 is measured. The threshold voltage of the memory element Tr12 can be determined and verified.

For the memory element Tr13 included in the memory cell M11, a voltage of 5V is applied to the control gate line CG1, a voltage of 3V is applied to the select gate lines SGD1 and SGS1, and a voltage of 1V is applied to the drain line D1. Then, a voltage of 0V is applied to the source line S0, and the voltage applied to the control gate line CG2 is varied from 0 to 3V.
Thereby, a voltage of 5V is applied to the control gate of the memory element Tr12 of the memory cell M11, a voltage of 0 to 3V is applied to the control gate of the memory element Tr13, and the current flowing through the drain line D1 is measured. The threshold voltage of the memory element Tr12 can be determined and verified. In other words, whether or not the threshold voltage of the memory elements Tr12 and Tr13 has changed more than a predetermined write state threshold voltage or a read voltage, and further is less than or equal to a predetermined erase state threshold voltage or a read voltage. In addition, it is possible to detect whether or not the threshold voltages of the memory elements Tr12 and Tr13 have changed.

  As described above, the nonvolatile semiconductor memory has a configuration in which different control gate lines are connected to the gates of the two memory elements Tr12 and Tr13 provided in the plurality of nonvolatile semiconductor memory cells 1 included in the memory cell array 22. Verification can be performed independently for each of the memory elements Tr12 and Tr13 provided in the cell 1. Further, the nonvolatile semiconductor memory cells 1 adjacent to each other in the row direction of the plurality of nonvolatile semiconductor memory cells 1 arranged in a matrix in the row direction and the column direction share a control gate line. The verify function can be improved without increasing the area required for the arrangement.

(Sixth embodiment)
FIG. 17 is a schematic diagram showing a layout configuration of the nonvolatile semiconductor memory cell 30 of the sixth embodiment using a two-layer polysilicon MOS process. FIG. 17A is a schematic diagram showing a plane showing a layout of the nonvolatile semiconductor memory cell 30. FIG. FIG. 17B is a schematic diagram showing a cross-sectional structure along A3-A′3 in FIG. The layout 30 has the same configuration as the equivalent circuit shown by the nonvolatile semiconductor memory cell 1 shown in FIG.

The transistor formation part 320 on the p-type semiconductor substrate 300 includes an n-type diffusion layer 304, polysilicon 314a, n-type diffusion layer 316, polysilicon 319a, n-type diffusion layer 317, polysilicon 319b, n-type diffusion layer 318, poly This is a region in which the silicon 314b and the n-type diffusion layer 305 are sequentially arranged in the series direction (first direction).
The n-type diffusion layers 304 and 316 are disposed to face each other via the gate region portion 315a where the channel of the selection transistor Tr11 is formed. The n-type diffusion layers 316 and 317 are disposed to face each other via the gate region portion 306a where the channel of the memory element Tr12 is formed. The n-type diffusion layers 317 and 318 are arranged to face each other via the gate region portion 306b where the channel of the memory element Tr13 is formed. The n-type diffusion layers 318 and 305 are arranged to face each other via the gate region portion 315b where the channel of the selection transistor Tr14 is formed.

The polysilicon 314a is a gate electrode of the selection transistor Tr11. The polysilicon 319a is a control gate electrode of the memory element Tr12. The polysilicon 319b is a control gate electrode of the memory element Tr13. The polysilicon 314b is a gate electrode of the selection transistor Tr14.
The polysilicon 303a is provided between the polysilicon 319a and the gate region 306a, forms a floating gate of the memory element Tr12, and constitutes a capacitor. The polysilicon 303b is provided between the polysilicon 319b and the gate region 306b, forms a floating gate of the memory element Tr13, and constitutes a capacitor.

FIG. 18 is a schematic diagram showing a layout of the memory cell array 31. As shown in the drawing, the layouts 30 of the nonvolatile semiconductor memory cells 1 (memory cells M11b to Mmnb) are arranged in a matrix in the row direction and the column direction.
The non-volatile semiconductor memory cells 30 arranged in the series direction of the transistor formation unit 320 share the n-type diffusion layer 304 and the contact 307a which are the drains of the adjacent selection transistors Tr11, and further, the source of the selection transistor Tr14. An n-type diffusion layer 305 and a contact 307b are shared. Further, the polysilicons 314a, 319a, 319b, and 314b arranged in the direction perpendicular to the series direction are commonly connected to the other nonvolatile semiconductor memory cells 30 arranged along the direction. The

Further, the source lines S1 to Sn are connected in common to the n-type diffusion layer 305 of the nonvolatile semiconductor memory cell 30 via the contact 307b in the row direction in the direction perpendicular to the series direction. Further, the drain lines D1 to Dn arranged in parallel along the transistor forming portion 320 are commonly connected to the n-type diffusion layer 304 that is the drain of the selection transistor Tr11 in each corresponding column via the contact 307a.
Note that writing and reading of data in the memory cell array 31 are performed in the same manner as the writing, erasing, reading, and writing verification shown in FIG.

  Compared with the layout of the nonvolatile semiconductor memory cell 1 shown in the first to fifth embodiments, the n-type diffusion constituting the capacitor is formed along the transistor forming portion 320 by using the two-layer polysilicon MOS process. Since it is not necessary to dispose a layer or an n + type diffusion layer, it is possible to reduce the area required for mounting. Further, it is possible to improve reliability by storing data using two memory elements Tr12 and Tr13 for one data.

  As described above in the first to fifth embodiments, the one-layer polysilicon is formed by using the layout of the memory cell array 21 of the third embodiment or the layout of the memory cell array 22 of the fourth embodiment. The nonvolatile semiconductor memory cell 1 used can be manufactured using a process similar to that of a CMOS transistor forming a logic circuit, and can improve reliability. Thereby, the nonvolatile semiconductor memory cell 1 can be used easily and inexpensively as a logic embedded memory such as a SoC (System On Chip) product.

  Note that the nonvolatile semiconductor memory cell 30 shown in the fifth embodiment may be used in the nonvolatile semiconductor memory device 150 shown in the third embodiment.

1 is a schematic diagram illustrating a circuit configuration of a nonvolatile semiconductor memory cell according to a first embodiment. 1 is a schematic diagram illustrating a planar layout of a nonvolatile semiconductor memory cell according to a first embodiment. 1 is a schematic view showing a cross-sectional structure of a nonvolatile semiconductor memory cell according to a first embodiment. It is a figure which shows the operation voltage of writing 1, writing 2, erasing 1, erasing 2 and reading of the nonvolatile semiconductor memory cell of the first embodiment. It is a figure which shows the write-protection operating voltage with respect to the non-volatile semiconductor memory cell of 1st Embodiment. It is the schematic which shows the coupling of the electrostatic capacitance in the non-volatile semiconductor memory cell of 1st Embodiment. It is the schematic which shows the layout of the non-volatile semiconductor memory cell of 2nd Embodiment. It is the schematic which shows the structure of the memory cell array of 3rd Embodiment. It is the schematic which shows the layout of the memory cell array of 3rd Embodiment. It is a figure which shows an example of the applied voltage in each operation | movement of the memory cell array of 3rd Embodiment. It is a figure which shows an example of the applied voltage in each operation | movement of the memory cell array of 3rd Embodiment. It is a figure which shows an example of the applied voltage in each operation | movement of the memory cell array of 3rd Embodiment. It is the schematic which showed the structure of the non-volatile semiconductor memory device of 4th Embodiment. It is the schematic which shows the structure of the memory cell array of 5th Embodiment. It is the schematic which shows the layout of the memory cell array of 5th Embodiment. It is a figure which shows an example of the applied voltage in each operation | movement of the memory cell array of 5th Embodiment. It is the schematic which shows the layout of the non-volatile semiconductor memory cell of 6th Embodiment. It is the schematic which showed the layout of the memory cell array of 6th Embodiment. It is the schematic which shows the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows the operating voltage of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows the static characteristic of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows typically the write-in characteristic by the hot electron of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows typically the write-in characteristic by the tunnel effect of Fowler-Nordheim of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows typically the erasing characteristic of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows typically the characteristic of the drain current of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows typically the characteristic of the drain current in the initial state of the non-volatile semiconductor memory cell in a prior art example, a writing state, and an erased state. It is a figure which shows the equivalent circuit of the coupling type | system | group of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows typically the electric charge retention characteristic of the non-volatile semiconductor memory cell in a prior art example. It is a figure which shows an example of the circuit structure of the non-volatile semiconductor memory cell in a prior art example.

Explanation of symbols

Tr11, Tr14 ... selection transistor Tr12, Tr13 ... Memory element 1, 20 ... Non-volatile semiconductor memory cell 21, 22 ... Memory cell array 150 ... Non-volatile semiconductor memory device 151 ... Control circuit, 152 ... Column decoder / driver, 153 ... Drain power supply Circuit 154: Gate decoder / driver, 155 ... Gate power supply circuit, 156 ... Sense amplifier circuit 160 ... Control unit 30 ... Non-volatile semiconductor memory cell 31 ... Memory cell array 9 ... Non-volatile semiconductor memory cell Tr9 ... Memory element

Claims (16)

A nonvolatile semiconductor memory cell comprising a MOS transistor formed on a semiconductor substrate,
A first select transistor having a drain connected to a first terminal and a gate connected to a first select terminal;
A first memory element having a drain connected to a source of the first select transistor and a control gate connected to a control gate terminal;
A second memory element having a drain connected to a source of the first memory element and a control gate connected to the control gate terminal;
A second selection transistor having a drain connected to a source of the second memory element, a source connected to a second terminal, and a gate connected to a second select terminal;
The n-type diffusion layer constituting the source of the first selection transistor and the drain of the first memory element is shared,
The n-type diffusion layer constituting the source of the first memory element and the drain of the second memory element is shared,
A non-volatile semiconductor memory cell, wherein an n-type diffusion layer constituting a source of the second memory element and a drain of the second selection transistor is shared. The first memory element and the second memory element are:
The nonvolatile semiconductor memory cell according to claim 1, wherein the nonvolatile semiconductor memory cell is a floating gate type transistor formed of a single layer of polysilicon. The first memory element and the second memory element are:
The nonvolatile semiconductor memory cell according to claim 2, wherein the nonvolatile semiconductor memory cell is a floating gate type transistor formed of two layers of polysilicon. When storing data in the first memory element and the second memory element,
When a potential applied to the second terminal and the semiconductor substrate is a reference potential, a first voltage is applied to the first terminal, and the first select terminal and the second select terminal are subjected to the first voltage. Applying a voltage equal to or higher than 1 to turn on the first selection transistor and the second selection transistor, and applying a second voltage to the control gate terminal;
Hot electrons are generated by currents flowing between the drain and source of each of the first memory element and the second memory element, and electrons are injected into the floating gates of the first memory element and the second memory element, respectively. Or accumulated
Alternatively, a third voltage is applied to the first select terminal and the second select terminal to turn on the first select transistor and the second select transistor, and a fourth voltage is applied to the control gate terminal. Apply
The Fowler-Nordheim tunneling current flowing from the floating gate of the first memory element to the drain causes electrons to be injected and stored in the floating gate, and the Fowler-Nordheim flowing from the floating gate to the source of the second memory element. Tunneling current causes electrons to be injected and stored in the floating gate,
When erasing data stored in the first memory element and the second memory element,
When the potential applied to the control gate terminal is a reference potential, the fourth voltage is applied to the first terminal, the second terminal, and the semiconductor substrate, and the first select terminal and the second Apply the 8th voltage to the 2 select terminals,
The first selection transistor and the second selection transistor are turned on to pass a Fowler-Nordheim tunnel current from the semiconductor substrate to the floating gates of the first memory element and the second memory element, Emit electrons from the floating gate,
Alternatively, when a potential applied to the semiconductor substrate and the control gate terminal is a reference potential, a fifth voltage is applied to the first terminal and the second terminal, and the first select terminal and the first gate Applying the eighth voltage to the select terminals of 2;
Turning on the first selection transistor and the second selection transistor, and causing a Fowler-Nordheim tunnel current to flow from the drain of the first memory element and the source of the second memory element to the respective floating gates; Electrons are emitted from the floating gate,
When reading data stored in the first memory element and the second memory element,
When a potential applied to the second terminal and the semiconductor substrate is a reference potential, a sixth voltage is applied to the first terminal, and a seventh voltage is applied to the first select terminal and the second select terminal. And applying a read voltage to the control gate terminal,
3. The nonvolatile semiconductor memory cell according to claim 1, wherein stored data is read depending on whether or not a current flows between the first terminal and the second terminal. 4. A first memory element and a second memory element which are MOS transistors formed on a semiconductor substrate, and a nonvolatile memory including a first selection transistor and a second selection transistor which are MOS transistors for selecting the memory element A conductive semiconductor memory cell,
A first n-type diffusion layer forming a drain of the first select transistor;
First polysilicon forming a gate electrode of the first select transistor;
A second n-type diffusion layer forming a source of the first select transistor and a drain of the first memory element;
A second polysilicon forming a floating gate electrode of the first memory element;
A third n-type diffusion layer forming a source of the first memory element and a drain of the second memory element;
A third polysilicon forming a floating gate electrode of the second memory element;
A fourth n-type diffusion layer forming a source of the second memory element and a drain of the second select transistor;
A fourth polysilicon forming a gate electrode of the second select transistor;
A transistor forming section in which a fifth n-type diffusion layer that forms a source of the second selection transistor is sequentially arranged in a series direction;
A sixth diffusion layer disposed in parallel with the transistor formation portion in the series direction and at a position intersecting the second polysilicon and the third polysilicon;
A non-volatile semiconductor memory cell comprising: the sixth diffusion layer and a first metal wiring arranged in the series direction connected via a contact. The nonvolatile semiconductor memory cell according to claim 5, wherein the sixth diffusion layer is an n-type diffusion layer having a well structure. The sixth diffusion layer includes
n + type diffusion layer laid on a p-type semiconductor substrate, or
The nonvolatile semiconductor memory cell according to claim 5, wherein the nonvolatile semiconductor memory cell is an n-type diffusion layer formed by channel implantation when a depletion type transistor is formed on a p-type semiconductor substrate. A nonvolatile semiconductor memory device comprising a memory cell array in which a plurality of nonvolatile semiconductor memory cells made of MOS transistors formed on a semiconductor substrate are arranged,
The nonvolatile semiconductor memory cell is
A first select transistor having a drain connected to the first terminal and a gate connected to the first select terminal;
A first memory element having a drain connected to a source of the first select transistor and a control gate connected to a control gate terminal;
A second memory element having a drain connected to a source of the first memory element and a control gate connected to the control gate terminal;
A second select transistor having a drain connected to a source of the second memory element, a source connected to a second terminal, and a gate connected to a second select terminal.
The plurality of nonvolatile semiconductor memory cells are arranged in a matrix,
A control gate line, a drain line and a source line are provided for each column of the nonvolatile semiconductor memory cells arranged in the matrix,
All of the control gate terminals of the nonvolatile semiconductor memory cells in the column provided with the control gate line are commonly connected to each of the control gate lines,
All the drain terminals of the nonvolatile semiconductor memory cells in the column provided with the drain line are commonly connected to the drain lines.
All of the source terminals of the nonvolatile semiconductor memory cells in the column provided with the source line are commonly connected to each of the source lines,
A first select gate line and a second select gate line are provided for each row of the nonvolatile semiconductor memory cells arranged in the matrix;
All of the first select gate terminals of the nonvolatile semiconductor memory cells of the row in which the first select gate line is provided are commonly connected to the first select gate line,
All of the second select gate terminals of the nonvolatile semiconductor memory cells in the row in which the second select gate line is provided are commonly connected to the second select gate line. Nonvolatile semiconductor memory device. The voltage applied to the semiconductor substrate as a reference voltage,
When writing data to the selected nonvolatile semiconductor memory cell,
A fourth voltage is applied to the control gate line connected to the nonvolatile semiconductor memory cell, and a first voltage is applied to the first select gate line and the second select gate line connected to the nonvolatile semiconductor memory cell. 3 is applied, and a voltage of 0 V is applied to the drain line and the source line connected to the nonvolatile semiconductor memory cell,
The first selection transistor and the second selection transistor are turned on, and a Fowler-Nordheim tunnel current is caused to flow from the floating gates of the first memory element and the second memory element to the semiconductor substrate. Electrons are injected into the gate and accumulated,
When erasing data of the selected nonvolatile semiconductor memory cell,
A voltage of 0 V is applied to the control gate line connected to the nonvolatile semiconductor memory cell, and an eighth voltage is applied to the first select gate line and the second select gate line connected to the nonvolatile semiconductor memory cell. And applying a fifth voltage to the drain line and the source line connected to the nonvolatile semiconductor memory cell,
Turning on the first selection transistor and the second selection transistor, and causing a Fowler-Nordheim tunnel current to flow from the drain of the first memory element and the source of the second memory element to the respective floating gates; Electrons are emitted from the floating gate,
When reading data stored in the selected nonvolatile semiconductor memory cell,
A voltage of 0 V is applied to the control gate line connected to the nonvolatile semiconductor memory cell, a sixth voltage is applied to the drain line connected to the nonvolatile semiconductor memory cell, and the nonvolatile semiconductor memory cell A voltage of 0 V is applied to the source line connected to the non-volatile semiconductor memory cell, a seventh voltage is applied to the first select gate line and the second select gate line connected to the nonvolatile semiconductor memory cell;
Detects data stored depending on whether or not current flows in the nonvolatile semiconductor memory cell,
When performing page writing for simultaneously writing to the nonvolatile semiconductor memory cells constituting the selected row,
The fourth voltage is applied to all the control gate lines for each column, and the third voltage is applied to the first select gate line and the second select gate line connected to the selected row. Applying a voltage of 0 V to the drain line and the source line connected to the column;
Fowler-Nordheim tunnel current is caused to flow from the floating gates of the first and second memory cells of the nonvolatile semiconductor memory cells constituting the column to the semiconductor substrate, and electrons are injected into the floating gates. Has been accumulated,
When performing page erasure to simultaneously erase the nonvolatile semiconductor memory cells constituting the selected row,
A voltage of 0 V is applied to all the control gate lines provided for each column, and the fifth voltage is applied to all the drain lines and all the source lines provided for each column. Applying the eighth voltage to the first select gate line and the second select gate line provided in the row;
A high electric field is applied in the vicinity of the drain of the first memory element and the source of the second memory element of each of the nonvolatile semiconductor memory cells constituting the column, and Fowler-Nordheim's floating gate is applied to the floating gate of the memory element. The nonvolatile semiconductor memory device according to claim 8, wherein a tunnel current is allowed to flow and electrons are emitted from the floating gate. With respect to the selected nonvolatile semiconductor memory cell, the threshold voltage of the first memory element and the second memory element included in the nonvolatile semiconductor memory cell is changed to be equal to or higher than a threshold voltage of a preset write state. If you are verifying
The sixth voltage is applied to the drain line connected to the nonvolatile semiconductor memory cell, and the first select gate line and the second select gate line connected to the nonvolatile semiconductor memory cell are applied to the first select gate line and the second select gate line, respectively. Applying the seventh voltage higher than the sixth voltage, applying a voltage to the control gate line connected to the nonvolatile semiconductor memory cell, and determining whether or not a current flows through the nonvolatile semiconductor memory cell The nonvolatile semiconductor memory device according to claim 9, wherein the voltage is detected. A first memory element and a second memory element which are MOS transistors formed on a semiconductor substrate, and a non-volatile memory composed of a first selection transistor and a second selection transistor which are MOS transistors for selecting the memory element A nonvolatile semiconductor memory device having a memory cell array in which a plurality of conductive semiconductor memory cells are arranged,
The nonvolatile semiconductor memory cell is
A first n-type diffusion layer forming a drain of the first select transistor;
First polysilicon forming a gate electrode of the first select transistor;
A second n-type diffusion layer forming a source of the first select transistor and a drain of the first memory element;
A second polysilicon forming a floating gate electrode of the first memory element;
A third n-type diffusion layer forming a source of the first memory element and a drain of the second memory element;
A third polysilicon forming a floating gate electrode of the second memory element;
A fourth n-type diffusion layer forming a source of the second memory element and a drain of the second select transistor;
A fourth polysilicon forming a gate electrode of the second select transistor;
A transistor forming section in which a fifth n-type diffusion layer that forms a source of the second selection transistor is sequentially arranged in a series direction;
A sixth diffusion layer disposed in the series direction in parallel with the transistor formation portion and disposed at a position intersecting with the second polysilicon and the third polysilicon;
A first metal wiring arranged in the series direction connected to the sixth diffusion layer through a contact; and
As an arrangement of the memory cell array,
The plurality of nonvolatile semiconductor memory cells are arranged in a matrix,
Each of the plurality of nonvolatile semiconductor memory cells shares the first n-type diffusion layer with one of the nonvolatile semiconductor memory cells adjacent in the series direction, and the other adjacent nonvolatile semiconductor memory Sharing the cell and the fifth n-type diffusion layer;
In the memory elements arranged in parallel in the series direction, the first metal wiring is commonly connected in a straight line, the first n-type diffusion layer is commonly connected to a drain line through a contact, and the first 5 n-type diffusion layers are commonly connected to the source line via the contacts,
In the memory elements arranged in parallel to the series direction in the vertical direction, the first polysilicon and the fourth polysilicon of the nonvolatile semiconductor memory cells adjacent in the vertical direction are commonly connected. A non-volatile semiconductor memory device. A non-volatile semiconductor memory device having a memory cell array in which a plurality of non-volatile semiconductor memory cells made of MOS transistors formed on a semiconductor substrate are arranged,
The plurality of nonvolatile semiconductor memory cells include:
A first select transistor having a drain connected to the first terminal and a gate connected to the first select terminal;
A first memory element having a drain connected to a source of the first select transistor and a control gate connected to a control gate terminal;
A second memory element having a drain connected to a source of the first memory element and a control gate connected to the control gate terminal;
A second selection transistor having a drain connected to a source of the second memory element, a source connected to a second terminal, and a gate connected to a second select terminal;
The memory cell array includes:
The nonvolatile semiconductor memory cells are arranged in a matrix in a row direction and a column direction,
A control gate line commonly connected to the control gate for each column of the nonvolatile semiconductor memory cells;
A drain line commonly connected to the drain terminal for each column of the nonvolatile semiconductor memory cells;
A source line commonly connected to the source terminal for each column of the nonvolatile semiconductor memory cells;
A first select gate line connected to the first select gate terminal for each row of the nonvolatile semiconductor memory cells;
A second select gate line connected to the second select gate terminal for each row of the nonvolatile semiconductor memory cells;
A first switch provided between the drain line and the drain power supply line;
A second switch provided between the source line and the source power line;
A third switch provided between the control gate line and the first gate power supply line;
A fourth switch provided between the control gate line and a second gate power supply line;
An address signal for selecting the nonvolatile semiconductor memory cell included in the memory cell array and a command signal indicating any one of write, erase, and read operations are input, and the input address signal and the command signal are input Based on the first switch, the second switch, the third switch and the fourth switch, the first gate power supply line, the second gate power supply line, and the first select gate line. And a controller that applies a voltage to the second select gate line and performs an operation corresponding to the command signal on the nonvolatile semiconductor memory cell selected by the address signal;
A non-volatile semiconductor memory device comprising: A nonvolatile semiconductor memory cell comprising a MOS transistor formed on a semiconductor substrate,
A first select transistor having a drain connected to the first terminal and a gate connected to the first select terminal;
A first memory element having a drain connected to a source of the first select transistor and a control gate connected to a first control gate terminal;
A second memory element having a drain connected to a source of the first memory element and a control gate connected to a second control gate terminal;
A second selection transistor having a drain connected to a source of the second memory element, a source connected to a second terminal, and a gate connected to a second select terminal;
The n-type diffusion layer constituting the source of the first selection transistor and the drain of the first memory element is shared,
The n-type diffusion layer constituting the source of the first memory element and the drain of the second memory element is shared,
A non-volatile semiconductor memory cell, wherein an n-type diffusion layer constituting a source of the second memory element and a drain of the second selection transistor is shared. A non-volatile semiconductor memory device having a memory cell array using a plurality of non-volatile semiconductor memory cells according to claim 13,
The memory cell array includes:
A plurality of the nonvolatile semiconductor memory cells arranged in a matrix in a row direction and a column direction;
A control gate line commonly connected to the first control gate terminal for each column of the nonvolatile semiconductor memory cells arranged in a matrix;
For each column arranged in a matrix, a drain line commonly connected to the drain terminal of the nonvolatile semiconductor memory cell;
For each column arranged in a matrix, a source line commonly connected to the source terminal of the nonvolatile semiconductor memory cell;
A first select gate line commonly connected to the first select gate terminal of the nonvolatile semiconductor memory cell for each row arranged in a matrix;
A second select gate line commonly connected to the second select gate terminal of the nonvolatile semiconductor memory cell for each row arranged in a matrix;
Have
A first switch provided between the drain line and the drain power supply line;
A second switch provided between the source line and the source power line;
A third switch provided between the control gate line and the first gate power supply line;
A fourth switch provided between the control gate line and a second gate power supply line;
An address signal for selecting the nonvolatile semiconductor memory cell included in the memory cell array and a command signal indicating any one of write, erase and read operations are input, and based on the input address signal and the command signal The first switch, the second switch, the third switch, and the fourth switch, the first gate power supply line, the second gate power supply line, the first select gate line, and the A controller that applies a voltage to a second select gate line and performs an operation corresponding to the command signal on the nonvolatile semiconductor memory cell selected by the address signal;
Have
The nonvolatile semiconductor memory cells adjacent in the row direction share the control gate line with each other, and the first control gate terminal and the second control gate terminal included in the plurality of nonvolatile semiconductor memory cells are The nonvolatile semiconductor memory device is connected to the control gate lines different from each other. The voltage applied to the semiconductor substrate is a reference voltage,
When performing a write operation, the control unit
Applying a first voltage to the first select gate line and the second select gate line connected to the selected nonvolatile semiconductor memory cell;
A voltage of 0 V is applied to the drain line and the source line connected to the nonvolatile semiconductor memory cell;
The first select gate line connected to the non-volatile semiconductor memory cell sharing the control gate with the selected non-volatile semiconductor memory cell and the second select gate line are used as neighboring select gate lines, Applying the first voltage to the drain line and the source line connected to the nonvolatile semiconductor memory cell, and the neighboring select gate line;
The voltage applied to the neighboring select gate line after a predetermined time has elapsed is changed to 0V,
Applying a fourth voltage to the control gate line connected to the selected nonvolatile semiconductor memory cell;
A high electric field is applied to the vicinity of the drain of the first memory element and the source of the second memory element of the selected non-volatile semiconductor memory cell, and the first memory element and the second memory element are respectively A Fowler-Nordheim tunnel current is generated from the control gate to the semiconductor substrate, electrons are injected and stored in the floating gate of each of the memory elements, and the first semiconductor memory cell in the adjacent column is stored. The floating gate of each of the memory element and the second memory element relaxes the electric field applied by raising the potential by coupling, preventing erroneous writing,
When performing the erasing operation, the control unit
A voltage of 0 V is applied to the two control gate lines connected to the selected nonvolatile semiconductor memory cell;
Applying an eighth voltage to the first select gate line and the second select gate line connected to the selected nonvolatile semiconductor memory cell;
Applying a fifth voltage to the drain line and the source line connected to the selected nonvolatile semiconductor memory cell;
A high electric field is applied near the drain of the first memory element and near the source of the second memory element of the selected nonvolatile semiconductor memory cell, and the drain of the first memory element and the second memory element A Fowler-Nordheim tunneling current is generated from each source to each control gate, and electrons are emitted from each floating gate of the memory element,
When performing a read operation, the control unit
A seventh voltage is applied to the first select gate line and the second select gate line connected to the selected nonvolatile semiconductor memory cell, and the drain line connected to the nonvolatile semiconductor memory cell is applied to the drain line connected to the nonvolatile semiconductor memory cell. A sixth voltage is applied, a voltage of 0 V is applied to the source line connected to the nonvolatile semiconductor memory cell, and the sixth voltage is applied to the control gate line connected to the nonvolatile semiconductor memory cell. The first select gate line, the second select gate line, the drain line, and the source line connected to the nonvolatile semiconductor memory cell that are applied and share the control gate line with the nonvolatile semiconductor memory cell 0V is applied to
Reading stored data depending on whether or not current flows through the selected nonvolatile semiconductor memory cell,
For the selected nonvolatile semiconductor memory cell, the threshold voltage of the first memory element and the second memory element included in the nonvolatile semiconductor memory cell changes to a threshold voltage of a preset write state or more. When the verify operation is performed, the control unit applies the seventh voltage to the first select gate line and the second select gate line connected to the selected nonvolatile semiconductor memory cell. The sixth voltage is applied to the drain line connected to the selected nonvolatile semiconductor memory cell, and the voltage of 0 V is applied to the source line connected to the selected nonvolatile semiconductor memory cell. Then, data is stored in one of the first memory element and the second memory element connected to the selected nonvolatile semiconductor memory cell. High first voltage than the voltage applied is applied at the time of reading, a voltage for verifying the threshold voltage is applied to the other memory elements,
Whether the first select gate and the second select gate connected to the selected nonvolatile semiconductor memory cell are turned on, the one memory element is turned on, and the other memory element is turned on The non-volatile semiconductor memory device according to claim 14, wherein the non-volatile semiconductor memory device is detected by a current flowing through the non-volatile semiconductor memory. A first memory element and a second memory element which are MOS transistors formed on a semiconductor substrate, and a non-volatile memory composed of a first selection transistor and a second selection transistor which are MOS transistors for selecting the memory element A non-volatile semiconductor memory device having a memory cell array in which conductive semiconductor memory cells are arranged,
A first n-type diffusion layer forming a drain of the first select transistor;
First polysilicon forming a gate electrode of the first select transistor;
A second n-type diffusion layer forming a source of the first select transistor and a drain of the first memory element;
A second polysilicon forming a floating gate electrode of the first memory element;
A third n-type diffusion layer forming a source of the first memory element and a drain of the second memory element;
A third polysilicon forming a floating gate electrode of the second memory element;
A fourth n-type diffusion layer forming a source of the second memory element and a drain of the second select transistor;
A fourth polysilicon forming a gate electrode of the second select transistor;
A transistor forming section in which a fifth n-type diffusion layer that forms a source of the second selection transistor is sequentially arranged in a series direction;
A sixth diffusion layer disposed in parallel with the transistor formation portion in the series direction and at a position intersecting with the second polysilicon;
In parallel with the transistor formation portion, in the series direction on the opposite side of the sixth n-type diffusion layer with respect to the transistor formation portion, and disposed at a position intersecting with the third polysilicon. A seventh diffusion layer;
A first metal wiring arranged in the series direction connected to the sixth diffusion layer through a contact;
A second metal wiring arranged in the series direction connected to the seventh diffusion layer through a contact; and
As an arrangement of the memory cell array,
The plurality of nonvolatile semiconductor memory cells are arranged in a matrix in the row direction and the column direction,
The nonvolatile semiconductor memory cells are arranged symmetrically with respect to a direction perpendicular to the series direction and the nonvolatile semiconductor memory cells adjacent in the series direction, and one of the adjacent nonvolatile semiconductor memory cells and the Sharing the first n-type diffusion layer, sharing the fifth n-type diffusion layer with the other non-volatile semiconductor memory cell adjacent thereto,
The sixth diffusion layer and the seventh diffusion layer of the nonvolatile semiconductor memory cells adjacent in the series direction are connected,
The first metal wiring and the second metal wiring of the nonvolatile semiconductor memory cells adjacent in the series direction are connected,
The nonvolatile semiconductor memory cell includes the nonvolatile semiconductor memory cell adjacent in the direction perpendicular to the series direction, the sixth diffusion layer, the first metal wiring, the seventh diffusion layer, and the Sharing the second metal wiring, the first polysilicon and the fourth polysilicon are connected,
Further, in the nonvolatile semiconductor memory cell, for each column, the first n-type diffusion layer is commonly connected to a drain line through a contact, and the fifth n-type diffusion layer is connected to a source line through the contact. And a non-volatile semiconductor memory device.

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