JP2005286185A - Nonvolatile semiconductor memory device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an FG (floating gate) memory cell of a two-layer gate structure which can reduce a current flowing through a channel in a write mode by increasing a charge injection efficiency. <P>SOLUTION: The memory cell has the gate region 15A of a memory gate insulating film 16 and a floating gate (FG) sequentially formed on a p-type channel formation region 11A, an n-type source region (S) 17 and a drain region (D) 18 located at both sides of the gate region, the control gate (CG) of an impurity region formed in a semiconductor substrate 11 to be capacitively coupled with a floating gate (FG) 15, and a select gate (SG) 20 for channel control coupled with the channel formation region between the source (S) region 17 and the gate region 15A via a gate insulating film 9 disposed therebetween. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device having a two-layer gate structure capable of high-efficiency operation at a low voltage, and a method for manufacturing the same.

  As a memory cell capable of forming a transistor of a memory cell by a single polysilicon gate process, an N-type source region and drain region, an N-type source region and an N-type in a P-type well formed in a semiconductor substrate A memory cell having a single polysilicon gate structure having a polysilicon gate (floating gate) formed above a channel region between the drain region and the drain region is known. (For example, refer to Patent Document 1).

FIG. 6A shows a plan view of this memory cell. FIG. 6B is a cross-sectional view taken along line AA in FIG.
An insulator 102 is formed on the surface portion of the semiconductor substrate 101. In the memory cell, the insulator 102 is formed in a pattern that exposes the semiconductor surface at two locations. A well 103 having a conductivity type opposite to that of the semiconductor substrate 101 is formed on one first semiconductor exposed portion. When the semiconductor substrate 101 is a P-type, the well 103 is an N-type impurity region and constitutes a control gate CG (hereinafter, the well 103 is referred to as a control gate). A floating gate (FG) 105 is formed on the control gate (CG) 103 via an insulating film 104. In the floating gate (FG) 105, a portion capacitively coupled to the control gate (CG) 103 through the insulating film 104 is formed with a relatively large area as shown in FIG. The gate portion 105A has a pattern extending. The gate portion 105A intersects with the other second semiconductor exposed portion (a part of the semiconductor substrate 101). A gate insulating film 106 of a memory transistor is interposed between the gate portion 105A and the semiconductor substrate 101. As shown in FIG. 6A, a source region (S) 107 and a drain region (D) 108 made of an N-type impurity region are formed on both sides in the width direction of the gate portion 105A.

  The control gate (CG) 103 and the floating gate (FG) 105 of the memory cell 100 having the single polysilicon gate structure are similar to those of the memory cell having the more traditional stacked gate (double polysilicon) structure. Therefore, the memory cell 100 having the single polysilicon gate structure is programmed (data writing), erased and read out by the same method as that of the memory cell having the double polysilicon gate structure. Can be performed.

During programming, that is, data writing, for example, 0 V is applied to the source region (S) 107, 5 V is applied to the drain region (D) 108, and 10 to several tens V are applied to the control gate (CG) 103. At this time, electrons traveling in the channel are increased in energy by a horizontal electric field to generate hot electrons at the drain end. The hot electrons are injected and accumulated in the floating gate (FG) 105 by a vertical electric field generated by the floating gate (FG) 105 whose potential has been increased by capacitive coupling with the control gate (CG) 103. On the other hand, data is erased by, for example, extracting electrons from the floating gate (FG) 105 to the substrate or the source region (S) 107 by a tunnel operation.
US Pat. No. 4,649,520

  However, in this conventional memory cell, when data is written by channel hot electron (CHE) injection, a relatively large current of, for example, several 10 μA per cell needs to flow through the channel. Therefore, a very high current supply capability is required for the internal power supply provided in the peripheral circuit of the memory cell array. Further, with the normal internal power supply capability, the number of bytes written in parallel is limited to several tens of bytes. In this case, the current supply capability of the internal power supply is insufficient to set the data transfer speed at the time of writing to a transfer rate required for real-time image processing, for example, 10 Mbytes / second or more. Further, when the current supply capability of the internal power supply is increased, there are disadvantages such as an increase in circuit area and a cost increase factor.

  The problem to be solved by the present invention is that the current flowing through the channel at the time of writing can be reduced by increasing the charge injection efficiency, and as a result, the number of memory cells that can be written in parallel can be increased. A non-volatile semiconductor memory device is provided.

  A nonvolatile semiconductor memory device according to the present invention includes a gate insulating film and a floating gate that are sequentially formed on a channel formation region of a first conductivity type formed on a semiconductor substrate, and the above-described floating gates located on both sides of the floating gate. A control gate comprising a source region and a drain region of a second conductivity type formed in the surface portion of the channel formation region, and an impurity region formed in the semiconductor substrate and capacitively coupled to the floating gate via an insulating film A non-volatile semiconductor memory device having a channel insulating region coupled to a surface portion of the channel forming region between the source region and the floating gate via a gate insulating film. It further has a select gate for controlling the formed channel.

  In this nonvolatile semiconductor memory device, a select gate coupled via a gate insulating film is provided at the source side portion of the channel formation region between the source region and the drain region. The electric field of the channel can be controlled. That is, when a voltage is applied between the source region and the drain region, and an appropriate voltage is also applied to the select gate at this time, the channel direction electric field applied to the channel charge traveling in the channel from the source region is changed to the select gate. The height is appropriately increased in the vicinity of the end portion of the floating gate that enters the electric field control region of the floating gate from the electric field control region. As a result, the amount of charge excited in terms of energy when the same channel current flows is increased as compared with the case where there is no select gate.

  A method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a first conductive type channel forming region and a control gate formed of a second conductive type impurity region on a semiconductor substrate, and an insulating film on the control gate. A gate part that is partly capacitively coupled via the gate and that is not capacitively coupled to the control gate becomes a floating gate in a pattern arranged via a gate insulating film with respect to the channel formation region of the first conductivity type. Forming a conductive layer; forming a source region and a drain region comprising impurity regions of a second conductivity type in channel forming regions on both sides of the gate portion of the conductive layer to be a floating gate; and a drain region and an edge portion And the conductive layer and the underlying gate insulating film are added in a pattern that does not overlap the source region. To and forming and forming a floating gate, a select gate in the pattern which is disposed through a gate insulating film over portions of the channel forming region between the floating gate and the source region.

  Another method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a first conductivity type channel formation region and a control gate made of a second conductivity type impurity region on a semiconductor substrate, and a channel formation region. Forming a select gate over the gate insulating film, forming a second conductivity type impurity region in a channel forming region on one side of the select gate using the select gate as a self-aligning mask, and sandwiching the select gate The gate portion is disposed on the channel forming region opposite to the impurity region of the second conductivity type via the gate insulating film, and a part other than the gate portion is capacitively coupled to the control gate via the insulating film. Forming a floating gate in a pattern to perform, a gate portion of the floating gate and the select The over preparative and forming a source region and a drain region of the second conductivity type in the channel forming region as a self-aligned mask.

  According to the non-volatile semiconductor memory device of the present invention, when the charge traveling in the channel is energetically excited and injected into the floating gate, a larger amount of charge is generated with the same channel current due to the action of the select gate. Since it is excited energetically, there is an advantage that the amount of current flowing through the channel for obtaining the target threshold voltage change can be reduced accordingly. As a result, when charges are injected into a plurality of memory cells at a time, the number of memory cells that can be injected with a batch can be increased. When data is written by injecting electric charge, the number of write bytes increases, and in this sense, the performance of the nonvolatile semiconductor memory device can be improved.

According to the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the insulating film between the floating gate and the control gate and the gate insulating film immediately below the select gate can be formed from different films. There are advantages in that the degree of freedom of thickness selection is high and high performance is easy.
Particularly, of the two manufacturing methods described above, the latter method in which the select gate is formed prior to the floating gate has the advantage that the source region and the drain region can be formed in a self-aligned manner with respect to the select gate and the floating gate. There is.

FIG. 2 shows a schematic configuration of the nonvolatile semiconductor memory device.
The nonvolatile semiconductor memory device illustrated in FIG. 2 includes a memory cell array (MCA) 1 and a memory peripheral circuit that controls the operation of the memory cell array 1.
The memory peripheral circuit includes a column buffer 2a, a row buffer 2b, a pre-row decoder (PR.DEC) 3, a main row decoder (MR.DEC) 4, a column decoder (C.DEC) 5, and an input / output circuit (I / O). 6 and a column gate array (C.SEL) 7. Although not specifically illustrated, the memory peripheral circuit includes a power supply circuit that slightly boosts the power supply voltage as necessary and supplies the boosted voltage to the memory cell array via the main row decoder 4.
The input / output circuit 6 includes a program and read data buffer (BUF), a bit line driving circuit (BLD) for applying a predetermined voltage to the bit line BL at the time of writing or erasing, and a source line SL at the time of writing or erasing. Includes a source line driver circuit (SLD) for applying a predetermined voltage to the sense amplifier and a sense amplifier (SA).
Since FIG. 2 shows a general memory configuration, descriptions of functions and operations of other configurations of the peripheral circuit are omitted here.

[Memory cell configuration]
The memory cell array 1 is configured by arranging memory cells in a matrix. Each memory cell has a gate electrode structure composed of two polysilicon layers, and each cell has a memory transistor whose channel conductivity type is N type (hereinafter referred to as N channel type). Hereinafter, the structure of the memory cell will be described by taking the N channel type as an example. Note that the present invention can also be applied to a P-channel type memory cell. In that case, it is necessary to reverse the impurity conductivity type and reverse the voltage relationship between the source and the drain.

1A is a schematic plan view of the memory cell, and FIG. 1B is an enlarged cross-sectional view taken along line AA of FIG. FIG. 1C is an equivalent circuit diagram of the memory cell.
A memory cell 10 shown in FIG. 1B is formed on a P-type semiconductor substrate 11. The semiconductor substrate 11 can be replaced with a P-well formed on the semiconductor substrate, or a P-type SOI layer supported on the substrate via an insulating layer.
An insulator 12 such as a LOCOS oxide film or a trench insulating layer is formed on the surface portion of the semiconductor substrate 11. In the memory cell 10, the insulator 12 is formed in a pattern that exposes the semiconductor surface portion at two locations. A well 13 having a conductivity type opposite to that of the semiconductor substrate 11 is formed on one first semiconductor exposed portion. When the semiconductor substrate 11 is P-type, the well 13 is an N-type impurity region and constitutes a control gate CG. Hereinafter, the well 13 is referred to as a control gate. In the example of FIG. 1A, the control gate 13 is formed as a buried diffusion layer wiring that is long in one direction, and is shared by a plurality of other memory cells not shown.
The control gate (CG) 13 can also be formed from a P-type impurity region. In this case, an N-type well is formed in the semiconductor substrate 11 and a P-type well serving as a control gate (CG) is formed on the surface portion. It is necessary to form a double well structure.

  A floating gate (FG) 15 is formed on the control gate (CG) 13 via an insulating film 14. In the floating gate (FG) 15, a portion capacitively coupled to the control gate (CG) 13 through the insulating film 14 is formed with a relatively large area as shown in FIG. The gate portion 15A has a pattern extending. In the planar pattern shown in FIG. 1A, the gate portion 15A is arranged so as to bypass a bit contact BC, which will be described later, and the other second semiconductor exposed portion (a semiconductor substrate serving as an active region of the memory transistor) 11). The second semiconductor exposed portion 11A is referred to as a “channel forming region” in the present invention because a memory transistor is formed and a channel of the memory transistor is induced in a part of the second semiconductor exposing portion 11A during operation. A memory gate insulating film 16 of the memory transistor is interposed between the gate portion 15A and the channel formation region 11A.

In the channel formation region 11A, as shown in FIG. 1A, a source region (S) 17 and a drain region (D) 18 made of an N-type impurity region are formed on both sides in the width direction of the gate portion 15A. .
The drain region (D) 18 overlaps the edge portion of the gate portion 15A on the plane pattern, but the source region (S) 17 is formed at a position away from the edge portion of the gate portion 15A. A select gate (SG) 20 is formed at a position overlapping the edge portion of the gate portion 15A on the source region side on the plane pattern. The select gate (SG) 20 is coupled to the channel formation region 11A between the source region (S) 17 and the gate portion 15A via the select gate insulating film 19, and controls the potential of the portion of the channel formation region 11A. . In the example of the planar pattern shown in FIG. 1A, the select gate (SG) 20 is wired as a line parallel to the control gate (CG), and is shared with a plurality of memory cells not shown.

Although details of the manufacturing method will be described later, when the floating gate (FG) 15 including the gate portion 15A is formed from the first layer of polysilicon, the select gate (SG) 20 is connected to the second layer of polysilicon. On the contrary, when the select gate (SG) 20 is formed from the first layer polysilicon, the floating gate (FG) 15 is formed from the second layer polysilicon.
In the cross-sectional view shown in FIG. 1B, the select gate insulating film 19 immediately below the select gate (SG) 20 covers the entire floating gate (FG) including the gate portion 15A. 19 may be formed only directly under the select gate (SG).
Furthermore, although not shown, a pocket region having the same P-type conductivity as that of the channel formation region 11A at the end of the drain region (D) and having a P-type impurity concentration higher than that of the channel formation region 11A is provided. It may be formed. Due to the existence of such a high-concentration P-type pocket region, the extension of the depletion layer is suppressed at the time of operation, the concentration of the horizontal electric field is increased, combined with the control of the select gate (SG), Charge injection efficiency can be improved.

  An interlayer insulating film 21 is deposited over the entire area including the surface of the two-layer polysilicon gate structure, and a bit contact hole that opens a part of the drain region (D) is formed in the interlayer insulating film 21, and the bit contact hole is electrically conductive. The material is buried to form a bit contact (BC) 22. A bit line (BL) 23 connected on the bit contact (BC) is formed on the interlayer insulating film 21. The bit line (BL) 23 is usually wired in a direction orthogonal to the control gate (CG) and the select gate (SG).

  As shown in FIG. 1C, the memory cell 10 has a select gate (SG) as a gate electrode, which is connected in series between a source line SL composed of a source region (S) and a bit line BL. The transistor ST and the memory transistor MT controlled by the control gate (CG) using the floating gate (FG) as a charge storage layer. Note that a capacitor C illustrated in FIG. 1C indicates a coupling capacitance between the control gate (CG) and the floating gate (FG).

  In the memory cell 10 having such a configuration, since the FG type memory cell having the select gate (SG) is composed of two-layer polysilicon, the floating gate (FG), the control gate (CG), and the select gate ( Compared with a memory cell having a three-layer polysilicon gate in which SG) is formed from different polysilicon, there is an advantage that the structure is simple and easy to manufacture.

Further, there are the following advantages regarding the control gate (CG) having a buried diffusion layer type.
As another mode in which the FG type memory cell having the select gate (SG) has a two-layer polysilicon gate structure, the floating gate (FG) is formed from the first layer polysilicon, and the floating gate (FG) is formed. On the other hand, there may be a case where the control gate (CG) and the select gate (SG) are formed so as to be capacitively coupled at different locations. In this case, the control gate (CG) and the select gate (SG) are collectively formed by patterning the same polysilicon (second layer polysilicon).
However, in this case, the select gate insulating film (film 19 in FIG. 1B) and the insulating film between the control gate (CG) and the floating gate (FG) (14 in FIG. 1B). Film) is composed of the same film. Therefore, it is difficult to set the optimum material and film thickness for each film. It is also possible to form these two insulating films with different films by repeating film formation and selective etching twice, but in this case, there is a problem that the process becomes complicated.
On the other hand, in the present embodiment, the control gate (CG) is a buried diffusion layer type, one of the floating gate (FG) and the select gate (SG) is formed from the first layer of polysilicon, and the other is the first layer. Since it is formed from the second-layer polysilicon, there is an advantage that the optimum material and thickness of the insulating film can be set freely without complicating the process.

  Hereinafter, two examples of the manufacturing method capable of obtaining this advantage will be described with reference to the drawings. 3A to 3D are cross-sectional views of the memory transistor portion in the middle of manufacturing by the first manufacturing method, and FIGS. 4A to 4E show manufacturing by the second manufacturing method. Sectional drawing of the memory transistor part in the middle is shown.

[First manufacturing method]
In the process prior to FIG. 3A, an insulator 12 for element isolation is formed on the semiconductor substrate 11, another well is formed if necessary, and a well 13 serving as a control gate (CG) is formed. .

As shown in FIG. 3A, as the memory gate insulating film 16, for example, a SiO ₂ film or a SiON film is formed on the surface of the channel formation region 11A by about 8 to 11 nm in terms of SiO ₂ film.
A first polysilicon film is deposited on the memory gate insulating film 16, and the first polysilicon film is patterned to form a gate portion 15A of a floating gate (FG). The pattern of the gate portion 15A at this time is not a final pattern, and is a pattern in which only portions that become the source region and the drain region of the channel formation region 11A are opened. Therefore, at this stage, the control gate side shown in FIG. 1 is all covered with the first layer of polysilicon.

  Ion implantation is performed using the gate portion 15A of the floating gate (FG) as a self-aligned mask. Thereby, as shown in FIG. 3B, an N-type impurity region, that is, a source region (S) 17 and a drain region (D) 18 are formed in the channel formation region 11A.

  Thereafter, the gate portion 15A of the floating gate (FG) is processed by etching so as to have a final shape. At this time, the control gate (CG) side shown in FIG. 1 is also patterned to form a final floating gate (FG) shape. Further, the exposed portion of the underlying memory gate insulating film 16 is continuously removed by switching the etching gas system or the like. As a result, as shown in FIG. 3C, in the memory transistor portion, the edge portion on one side overlaps the drain region (D) 18 on the plane pattern, and the edge on the other side is separated from the source region (S) 17. A gate portion 15A is formed.

As shown in FIG. 3D, an SiO ₂ film having a thickness of about 8 to 25 nm, for example, is formed as the select gate insulating film 19 so as to cover the gate portion 15A. Next, a second layer of polysilicon is deposited, and the second layer of polysilicon is patterned to form a select gate (SG) 20. As a result, as shown in FIG. 3D, in the memory transistor portion, the channel formation region 11A between the gate portion 15A and the source region (S) 17 is located via the select gate insulating film 19. A select gate (SG) 20 is formed. Note that one edge portion of the select gate (SG) 20 is an edge portion of the gate portion 15A and the other edge portion is an edge of the source region (S) 17 so that a gap is not formed due to misalignment of the photomask at this time. It is desirable to overlap the part, but this is not essential when there is no concern about such misalignment.

  Thereafter, the memory cell is completed through the deposition of the interlayer insulating film 21 shown in FIG. 1, the opening of the bit contact hole, the embedding of the plug material, and the formation of the bit line (BL) 23.

[Second manufacturing method]
Prior to the step shown in FIG. 4A, forming an insulator or well for element isolation is the same as in the first manufacturing method.

In the step shown in FIG. 4A, first, as the select gate insulating film 19, a SiO ₂ film having a thickness of, for example, about 8 to 25 nm is formed on the surface of the channel formation region 11A. Next, a first layer of polysilicon is deposited, and the first layer of polysilicon is patterned to form a select gate (SG) 20.

  As shown in FIG. 4B, a resist R is formed in which an edge is located in the middle of the select gate (SG) 20 in the width direction, and one side thereof (source region forming side) is opened. The resist R also covers the control gate (CG) side shown in FIG. Next, an N-type impurity is introduced into the channel formation region 11A by ion implantation using the resist R as a mask. The N-type impurity region 17A formed at this time will eventually become a part of the source region (S) 17. Further, an N-type impurity region 17A in which the edge portion on one side of the pattern of the select gate (SG) 20 becomes the source region (S) 17 on the plane pattern due to the lateral diffusion of the N-type impurity after the subsequent annealing. And overlap.

4C, after removing the resist R, the select gate insulating film 19 around the select gate (SG) 20 is removed by etching using the select gate (SG) 20 as a mask. Next, as the memory gate insulating film 16, for example, a SiO ₂ film or a SiON film is formed to a thickness of about 8 to 11 nm in terms of SiO ₂ film, and the surface of the select gate (SG) 20 and the surface of the surrounding channel formation region 11A Cover.

  In the step shown in FIG. 4D, a second-layer polysilicon film is deposited on the memory gate insulating film 16, and the second-layer polysilicon film is patterned to form the floating gate (FG). A gate portion 15A is formed. Note that it is desirable to overlap one edge portion of the gate portion 15A with the edge portion of the select gate (SG) 20 so that a gap is not formed due to misalignment of the photomask at this time. It is not essential if there is no concern about deviation.

  In the step shown in FIG. 4E, ion implantation is performed using the gate portion 15A and the select gate (SG) 20 as a self-aligned mask in a state where the control gate (CG) side shown in FIG. Thereby, as shown in FIG. 4E, an N-type impurity region, that is, a source region (S) 17 and a drain region (D) 18 are formed in the channel formation region 11A.

  After removing the resist and the like that protected the control gate (CG) side, the interlayer insulating film 21 shown in FIG. 1 is deposited, the bit contact hole is opened, the plug material is buried, and the bit line (BL) 23 is formed. Then, the memory cell is completed.

[Operation]
Next, the operation of the memory cell will be described. In the operation of the present embodiment, charges are injected into the floating gate (FG) using source side injection using the select gate (SG). Here, in the present invention, the type of charge may be an electron or a hole. However, in the case of the above-described N-channel type memory cell, electrons traveling through the channel are excited and injected into hot electrons (HE) (CHE injection). ). Whether data is written or erased by charge injection is a matter of definition. Here, a case where data is written by source-side CHE injection will be described as an example.

  FIG. 5 is a diagram for explaining the operation of the source side CHE injection. In FIG. 5, for convenience of explanation, the control gate (CG) is depicted as being laminated on the floating gate (FG) 15 via the insulating film 14, but this shows the actual structure. Instead, in the actual structure in the present embodiment, it is noted that the control gate (CG) is formed in another place as a buried diffusion layer (well) and is capacitively coupled to the floating gate (FG) at that place. Cost.

At the time of data writing, for example, a voltage of 0 V is applied to the source region (S) 17, 4 V is applied to the drain region (D) 18, 1.6 V is applied to the select gate (SG) 20, and 14 V is applied to the control gate (CG) 13. These voltages are supplied from a power supply circuit (not shown) provided in the peripheral circuit of the memory cell array (MCA) shown in FIG.
Under this bias condition, an inversion layer (channel CH) is formed in the channel formation region 11A between the source region (S) 17 and the drain region (D) 18. The horizontal electric field strength of the channel CH is increased near the boundary P0 between the select gate (SG) 20 and the floating gate (FG) by the action of the voltage applied to the select gate (SG). In the case where there is no select gate (SG), the electric field strength in the horizontal direction is maximized near the drain end portion P1. As described above, a portion where the horizontal electric field strength increases due to the control of the channel electric field by the select gate (SG) starts from the source side end of the floating gate (FG) 15. The probability of acquiring high energy near the boundary P0 and becoming hot electrons increases. Therefore, as shown in the figure, electrons are injected into the floating gate (FG) in a wide range from the source side end to the drain side end of the floating gate (FG), and the electron injection efficiency is improved.

  This is advantageous in that a desired threshold voltage change can be obtained at an early stage of a predetermined data writing time, and the data writing time can be shortened accordingly. In addition, since the desired threshold voltage can be obtained even if the printing voltage is lowered for the same data writing time, there is an advantage that writing can be performed with a smaller amount of current. Furthermore, there is an advantage that power consumption is reduced by improving the charge injection efficiency.

In particular, the point of low write current will be described in more detail.
Data writing is performed collectively in a predetermined memory cell group in the memory cell array (MCA). For example, data writing is executed collectively in a group of memory cells (one word line sector) to which control gates (CG) are commonly connected. Even in such a case, since the electron injection efficiency is high in the present embodiment, for example, high-speed writing with a small channel current of 100 nA / cell is possible. Therefore, the number of bytes of data to be written in parallel can be increased by one to two digits compared to the conventional several tens of bytes, and even in a system where the data transfer speed at the time of writing is as high as 10 Mbytes / second or more, the memory is in real time. It can be used as a memory capable of inputting and outputting data.

  The threshold voltage of the memory transistor after such data writing is such that the electric charge amount of electrons trapped in the floating gate (FG) 15 weakens the electric field due to the positive voltage applied to the control gate (CG) 13 at the time of reading. As a result, the threshold voltage after writing becomes larger than the threshold voltage before writing (threshold voltage during erasure).

  Data is erased by extracting electrons accumulated in the floating gate (FG) 15 to at least one of the source region (S) 17 and the drain region (D) 18 by FN tunneling, or extracting the electrons to the entire channel surface. Alternatively, data can be erased by injecting charges (in this case, holes) having a polarity opposite to the accumulated charges (electrons) into the floating gate (FG) 15. A description of the specific erase operation is omitted here.

Since the threshold voltage after erasing has no negatively charged charge of the floating gate (FG), there is no effect of weakening the electric field exerted on the channel during reading. For this reason, the threshold voltage of the memory transistor after erasing is smaller than the threshold voltage immediately after writing.
The description of the data read operation is also omitted, but this operation may be performed for each bit or may be page read. In any case, the bit line (BL) potential at the time of reading changes depending on whether data is written (data “1” or “0”), and this potential change is amplified and read by the sense amplifier (SA). Thus, the stored data can be identified.

Regarding the threshold voltage after erasing, the advantage of having the select gate (SG) will be described.
As can be seen from the equivalent circuit shown in FIG. 1C, since the select gate (SG) 20 exists, the conduction of the select transistor ST having the select gate ST as a gate can be controlled. In particular, when reading data, the cell current of the non-selected memory cell connected to the same bit line BL as the memory cell to be read (selected memory cell) can be cut off by the select transistor ST. Therefore, the threshold voltage on the erase side of the memory cell can be a negative voltage.
Normally, it is necessary to control the threshold voltage on the erase side to a small positive voltage in a narrow range, so the erase pulse application and erase threshold voltage verification read cycle are repeated many times to narrow the threshold voltage to a narrow range. It was necessary to control the voltage.
In this embodiment, since the erase threshold voltage can be set to a negative voltage, the number of cycles of such erase verify operation is reduced, so that the erase time can be shortened.

Various modifications other than those described above are possible.
For example, the memory transistor can perform multi-bit data storage in which a plurality of bits, each of which is binary data, are written during one data write cycle. Further, the plane pattern shown in FIG. 1A can be changed without departing from the gist of the present invention.

  The present invention can be widely applied to non-volatile semiconductor memories such as flash EEPROMs.

FIG. 2A is a schematic plan view of a memory cell of a nonvolatile semiconductor memory device according to an embodiment of the present invention. (B) is sectional drawing of the AA of (A). (C) is an equivalent circuit diagram of the memory cell. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention. (A)-(D) are sectional drawings of the memory transistor part in the middle of manufacture by the 1st manufacturing method concerning embodiment of this invention. (A)-(E) are sectional drawings of the memory transistor part in the middle of manufacture by the 2nd manufacturing method concerning embodiment of this invention. It is operation | movement explanatory drawing of the source side CHE injection | pouring used by embodiment. (A) is a plan view of a conventional FG type memory cell having a two-layer polysilicon gate structure. (B) is sectional drawing of the AA of (A).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 10 ... Memory cell, 11 ... Semiconductor substrate, 11A ... Channel formation area, 13 ... Control gate (CG), 14 ... Insulating film, 15 ... Floating gate (FG), 15A ... Gate part, 16 ... Memory Gate insulating film, 17 ... Source region (S), 18 ... Drain region (D), 19 ... Select gate insulating film, 20 ... Select gate (SG), MT ... Memory transistor, ST ... Select transistor, BL ... Bit line

Claims (6)

A gate insulating film and a floating gate sequentially formed on a channel formation region of the first conductivity type formed on a semiconductor substrate, and formed on a surface portion of the channel formation region located on both sides of the floating gate. A non-volatile semiconductor memory device comprising: a source region and a drain region of a second conductivity type; and a control gate formed of an impurity region formed on the semiconductor substrate and capacitively coupled to the floating gate via an insulating film. And
A select gate is further coupled to a surface portion of the channel formation region between the source region and the floating gate via a gate insulating film, and controls a channel formed in the surface portion of the channel formation region. Semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1, wherein the insulating film between the floating gate and the control gate and the gate insulating film immediately below the select gate are made of different insulating films. Forming a channel formation region of the first conductivity type and a control gate made of an impurity region of the second conductivity type on the semiconductor substrate;
A pattern in which a part of the control gate is capacitively coupled to the control gate via an insulating film and a gate portion that is not capacitively coupled to the control gate is disposed via the gate insulating film with respect to the channel formation region of the first conductivity type. Forming a conductive layer to be a floating gate,
Forming a source region and a drain region comprising impurity regions of the second conductivity type in channel forming regions on both sides of the gate portion of the conductive layer to be a floating gate;
Forming a floating gate by processing the conductive layer and the underlying gate insulating film in a pattern in which the drain region and the edge portion overlap and do not overlap the source region;
Forming a select gate in a pattern arranged on a portion of a channel formation region between the floating gate and the source region via a gate insulating film. 4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the floating gate is formed of a first layer of polysilicon, and the select gate is formed of a second layer of polysilicon. 5. Forming a channel formation region of the first conductivity type and a control gate made of an impurity region of the second conductivity type on the semiconductor substrate;
Forming a select gate on the channel formation region via a gate insulating film;
Forming a second conductivity type impurity region in a channel formation region on one side of the select gate using the select gate as a self-alignment mask;
A gate portion is disposed on the channel forming region opposite to the second conductivity type impurity region with the select gate interposed therebetween via a gate insulating film, and a portion other than the gate portion has an insulating film on the control gate. Forming a floating gate with a capacitively coupled pattern through;
Forming a second conductivity type source region and drain region in a channel formation region using the gate portion of the floating gate and the select gate as a self-alignment mask. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the select gate is formed from a first layer of polysilicon, and the floating gate is formed from a second layer of polysilicon.

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