JP2005166158A - Nonvolatile semiconductor memory device and method for driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variation of threshold-value distribution after writing and erasing in a flash memory array without increasing an area as a flash memory core. <P>SOLUTION: In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells formed from MIS transistors each of which is provided at each of intersecting points of a plurality of word lines and a plurality of bit lines and disposed in a matrix pattern, means for applying voltage separately to odd-numbered word lines and even-numbered word lines is provided, and writing and erasing are performed separately to respective memory cells on the odd- and even-numbered word lines, thereby variation of threshold-value distribution after writing and erasing is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a driving method thereof.

  The EEPROM is capable of electrically writing and erasing data stored in the memory cell, and has a non-volatile property that does not permanently erase the data even when the power is turned off. It is well known that data writing is performed by hot electron injection from the drain side, and data erasing is performed by applying a high voltage to the source side and using a tunnel current. Among such EEPROMs, a flash EEPROM (hereinafter referred to as “flash memory”) in which data is erased all at once or in units of blocks can be composed of only one MOS transistor. Therefore, there is an advantage that high integration is possible.

FIG. 6A shows a structure of a flash memory cell which is one cell of a typical flash memory. In the flash memory cell, an n ⁺ -type drain region 2 and an n ⁺ -type source region 3 are formed in a p-type well 1 provided in the substrate. A channel region 4 is between the drain region 2 and the source region 3. A gate insulating film 5 made of, for example, a SiO ₂ film having a thickness of about 10 nm is formed on the channel region 4, and a floating gate electrode 6 is formed thereon. A control gate electrode 8 is formed on the floating gate electrode 6 via an interlayer insulating film 7 which is an ONO film having a three-layer structure of, for example, a SiO ₂ film, a Si ₃ N ₄ film, and a SiO ₂ film. ing.

  Data writing and erasing to the flash memory cell will be described. At the time of data writing, as shown in FIG. 6B, a low voltage (eg, 0 V) is applied to the source and the substrate, and a high voltage supplied from the outside or an internal boosted voltage (eg, 10 V) is applied to the control gate. A high voltage (for example, 5 V) is also applied to the drain. Then, an on-current flows between the drain and the source, hot electrons are generated near the drain, and are injected into the floating gate electrode 6. The threshold voltage of the control gate voltage necessary for forming a channel in the channel region 4 is increased by the electrons thus injected. A state in which this threshold value is about 6 V, for example, is a write completion state (“0”). At the time of erasing data, as shown in FIG. 6C, a positive voltage (for example, 5V) is applied to the source, a negative voltage (for example, −8V) is applied to the control gate, and a low voltage (for example, 0V) is applied to the substrate. Set to floating state (open state). As a result, excess electrons accumulated in the floating gate electrode 6 are passed through the gate insulating film 5 at the overlapping portion of the source region 3 and the floating gate electrode 6 to cause a current caused by a FN (Fowler-Nordheim) tunneling phenomenon ( Is pulled out to the source region 3 by the tunnel current. As a result, the threshold value of the control gate voltage necessary for forming a channel in the channel region 4 is lowered. A state in which this threshold value is about 2 V, for example, is an erase completion state (“1”).

  Next, a data read operation in the flash memory cell will be described. A low voltage (for example, 0 V) is applied to the source and the substrate, a sense voltage (for example, 5 V) is applied to the control gate, and a read voltage (for example, 1 V) is applied to the drain. Here, the sense voltage refers to an intermediate voltage between the threshold value in the written state and the threshold value in the erased state. When such a voltage is applied to the flash memory cell in the written state, no channel is formed in the channel region 4, so that no current flows between the drain region 2 and the source region 3. On the other hand, when applied to an erased flash memory cell, a channel is formed in the channel region 4, so that a current flows between the drain region 2 and the source region 3. Whether the flash memory cell is in a written state or an erased state is determined based on the presence or absence of the drain current.

  As shown in FIG. 7, such a flash memory cell has a source connected to a common source line (SL), a drain connected to bit lines (BL1 to BLm), and a control gate connected to word lines (WL1 to WLn). Connect to and arrange on the array. By arranging in this way, data writing is performed for each bit, and erasing is performed for all bits at once or in blocks.

  FIG. 8A shows an example of a plan view of a flash memory cell. FIG. 8B shows a plan view which is an example of a flash memory cell when manufactured according to this plan view. A flash memory manufacturing method will be briefly described with reference to FIGS. 9A to 9D which are cross-sectional views of the manufacturing process of the AA ′ portion in FIG. 8B.

  As shown in FIG. 9A, on the p-type well 1, a gate insulating film 5, a first polysilicon film 6a that becomes a floating gate electrode, an interlayer insulating film 7, and a second polysilicon film that becomes a control gate electrode 8a is formed sequentially. Before the interlayer insulating film 7 is formed, the first polysilicon film 6a serving as the floating gate electrode is long in the AA ′ direction in FIG. 8B and is perpendicular to the AA ′ direction. Are patterned in stripes spaced apart from each other. Thereafter, as shown in FIG. 9B, after patterning into a desired shape to form the floating gate electrode 6 and the control gate electrode 8, phosphorus and arsenic ions are introduced into the drain region and the source region by ion implantation. . After that, as shown in FIG. 9C, the drain region 2 and the source region 3 are formed by performing heat treatment at a high temperature. Thereafter, as shown in FIG. 9D, the interlayer insulating film 11, the contact 10, and the wiring 12 are sequentially formed to complete.

  By the way, when a flash memory cell is manufactured, writing / erasing of the flash memory cell is caused by variations in coupling capacitance ratio caused by mask misalignment in the diffusion process, variations in ion implantation angle during source / drain formation, and the like. The characteristic may be bipolar for each WL. These contents will be described with reference to FIG. The plan view of the flash memory cell is entirely composed of straight lines as shown in FIG. However, the element isolation region 9 made of a field oxide film actually manufactured by this mask has a rounded shape after the photolithography process and the LOCOS growth. When forming the gate electrode pattern of the flash memory transistor shown in FIG. 9B, a mask alignment shift occurs until the rounded portion overlaps the floating gate electrode 6 as shown in FIG. 8C. In this case, the capacitance between the floating gate electrode 6 and the source region 3 has different values between the left and right memory cell transistors sandwiching the drain region 2. This capacity difference is one cause of the fact that the write / erase characteristics of the flash memory cell are bipolar for each WL. For this reason, in order to avoid the above-described bipolarization of the write / erase characteristics, the distance L1 between the end of the element isolation region 9 and the gate electrode of the flash memory cell shown in FIG. Design with a margin in consideration of mask misalignment is required, and the area of the flash memory cell is designed to be larger than necessary.

  In addition, the source region and the drain region of the flash memory transistor are generally formed by an ion implantation process and a high temperature heat treatment process. The implantation angle in this ion implantation is managed as an ion implantation apparatus, but has a certain variation. For this reason, as shown in FIG. 10A, even when ions are implanted perpendicularly to the surface of the silicon substrate, a shadowed side and a non-shadowed side of the transistor are formed. If activation by high-temperature heat treatment is performed in this state, as shown in FIG. 10B, in the left and right transistors sandwiching the drain region 2, the distances D1 and D2 of the overlapping portion between the drain region 2 and the floating gate electrode 6, the source The distances S1 and S2 of the overlapping portion between the region 3 and the floating gate electrode 6 are different, which causes a difference in write / erase characteristics in each flash memory. This is the same when ion implantation is performed obliquely with respect to the surface of the silicon substrate, and causes a difference in write / erase characteristics in the flash memory. As described above, since the implantation angle in the ion implantation apparatus has a certain variation, the characteristic difference caused by this cannot be avoided in manufacturing the flash memory.

  The capacitance difference or characteristic difference as described above is different on the left and right sides of the drain region 2, and the write / erase characteristics of the flash memory cell are bipolar for each WL. Here, the flash memory array can be written in 1-bit units, but generally a plurality of bits are written in parallel for the purpose of shortening the rewrite time. The flash memory array is erased all at once or in units of blocks. An example of a writing method in the case where writing is performed simultaneously on a plurality of memory cells as described above will be described with reference to FIG. In this example, writing is performed by dividing the entire area of the flash memory array into eight areas a to h. First, writing is performed on the flash memory cells in the region a, and writing is performed on the flash memory cells in the region a until the threshold value of the slowest writing flash memory cell reaches a predetermined level (for example, 6 V). . After the writing of the area a is completed, the writing is similarly performed on the flash memory cells in the areas b to h. When writing to all areas is completed, writing to the flash memory array is completed. At this time, if there is a difference in the write characteristics of the flash memory cell, the threshold after writing has a certain distribution. As described above, when the writing characteristic is bipolar, there are two peaks in this distribution, and the threshold distribution variation becomes very large as shown in FIG. 12A (for example, 6V to 8V). ).

  Similarly, an example of an erasing method in the case where erasing is performed simultaneously on a plurality of memory cells will be described with reference to FIG. Here, a description is given of the case where all the areas of the flash memory array are erased collectively. First, the flash memory cells in the entire area are erased, and the flash memory cells in the entire area are erased until the threshold value of the slowest erased flash memory cell reaches a predetermined level (for example, 2V). Do. At this time, if there is a difference in the erasing characteristics of the flash memory cells, the threshold after erasing has a certain distribution. As described above, when the erasing characteristic is bipolar, the distribution has two peaks, and the threshold distribution variation becomes very large as shown in FIG. 12A (for example, 0V to 2V). ).

  As described above, when a plurality of flash memory cells of a flash memory array, a certain block, or all areas are written / erased collectively, the threshold distribution after writing / erasing as shown in FIG. However, even if it looks like a distribution of one mountain, it will have a distribution of two peaks when decomposed, and the distribution variation will be very large.

  This distribution is expected to expand further as capacity increases. For this reason, as shown in FIG. 12B, when the threshold variation after erasure becomes larger, over-erasure occurs that the flash memory cell is depleted due to excessive extraction of charge from the floating gate. . As a result, the access time is deteriorated, and in the worst case, all the flash memory cells sharing the bit line with the depleted flash memory cell are determined to be in the erased state and function normally. It becomes impossible. In order to prevent the occurrence of over-erasing, it is necessary to set a high threshold after over-erasing to increase the margin for over-erasing. However, as shown in FIG. 12C, it is necessary to take a certain margin to discriminate between the flash memory cell in the written state and the flash memory cell in the erased state. If set, the threshold value after writing must be set high accordingly. This leads to a decrease in the charge retention reliability of the flash memory cell in the written state. In addition, when the threshold distribution after writing or the threshold distribution variation after erasing increases, the number of electrons passing through the tunnel oxide film (gate insulating film 5) during the writing operation or erasing operation increases. As a result, the deterioration of the tunnel oxide film quality is accelerated, and the reliability due to the film quality of the tunnel oxide film is also reduced.

For example, Japanese Patent Application Laid-Open No. H10-228561 discloses that a different voltage pulse is applied to the word line WL evenly at the time of erasing.
Japanese Patent Laid-Open No. 06-259984

  However, according to this method, it is difficult to set the optimum voltage pulse width to be applied evenly and oddly to the word line WL for each semiconductor memory device, and it is necessary to add a complicated circuit. There is a problem that the area of the device increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device capable of easily narrowing the threshold distribution variation of memory cells after writing and erasing without increasing the area as a flash memory core and its rewriting. Is to provide a method. As a result, it is possible to secure a sufficient margin for over-erasure failure, to improve the charge retention reliability of the flash memory cell in the written state, and to improve the reliability degradation due to the film quality of the tunnel oxide film.

  A first nonvolatile semiconductor memory device of the present invention is provided at a crossing point of a plurality of word lines, a plurality of bit lines, and each word line and each bit line, and a threshold voltage corresponding to stored data is externally applied. A non-volatile semiconductor memory device comprising a plurality of MIS transistors that can be electrically controlled from a plurality of MIS transistors, comprising means for separately applying voltages to odd-numbered word lines and even-numbered word lines It is characterized by that.

  The second nonvolatile semiconductor memory device of the present invention further comprises means for applying a voltage simultaneously to the odd-numbered word lines and the even-numbered word lines in the first nonvolatile semiconductor memory device. It is characterized by.

  The third nonvolatile semiconductor memory device of the present invention is the first or second nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device is a flash memory, and the odd-numbered word lines and the even-numbered word lines. On the other hand, it further comprises means for applying a negative voltage when erasing data of the MIS transistor.

  According to a fourth nonvolatile semiconductor memory device of the present invention, in any one of the first to third nonvolatile semiconductor memory devices, the MIS transistors are separated by a LOCOS film, and correspond to an odd-numbered word line. The positional relationship between the source and the drain of the MIS transistor and the positional relationship between the source and the drain of the MIS transistor corresponding to the word line in the even column are reversed.

  The fifth nonvolatile semiconductor memory device driving method of the present invention is provided at the intersection of a plurality of word lines, a plurality of bit lines, each word line and each bit line, and corresponds to the stored data. Nonvolatile semiconductor memory device comprising a plurality of MIS transistors capable of electrically controlling threshold voltage from outside and means for separately applying voltages to odd-numbered word lines and even-numbered word lines In this driving method, data is written and erased separately for MIS transistors corresponding to odd word lines and MIS transistors corresponding to even word lines.

  The sixth method for driving a nonvolatile semiconductor memory device according to the present invention is provided at the intersection of a plurality of word lines, a plurality of bit lines, and each word line and each bit line, and corresponds to stored data. A plurality of MIS transistors capable of electrically controlling the threshold voltage from the outside, means for separately applying voltages to the odd-numbered word lines and the even-numbered word lines, and the odd-numbered word lines and the even-numbered word lines A method of driving a nonvolatile semiconductor memory device comprising means for simultaneously applying a voltage to word lines in a column, the MIS transistors corresponding to word lines in odd columns and MIS transistors corresponding to word lines in even columns When data is written to or erased from an MIS transistor corresponding to an odd-numbered word line in the initial stage, The MIS transistors corresponding to the word lines of the column are simultaneously written or erased, and one of all the MIS transistors on the odd-numbered word lines or all the MIS transistors on the even-numbered word lines is the target of writing or erasing. After reaching the level, writing or erasing is performed only on the MIS transistor corresponding to the word line that has not reached the target level.

  The seventh nonvolatile semiconductor memory device driving method of the present invention is the fifth or sixth nonvolatile semiconductor memory device driving method, wherein writing is performed by a write execution process in which electrons are injected into the floating gate of the MIS transistor. And a write verify process for detecting the threshold value of the MIS transistor, and erasing includes an erase execution process for extracting electrons from the floating gate of the MIS transistor and an erase verify process for detecting the threshold value of the MIS transistor thereafter. It is characterized by that.

  The eighth nonvolatile semiconductor memory device driving method of the present invention is the fifth or sixth nonvolatile semiconductor memory device driving method, wherein the odd-numbered word lines and the even-numbered word lines are erased at the time of erasing. A negative voltage is applied.

  According to the present invention, variation in threshold distribution of memory cells (MIS transistors) after writing and erasing can be easily narrowed without increasing the area as compared with the conventional case. As a result, a sufficient margin can be secured against over-erasure failure, and the charge retention reliability of the flash memory cell in the written state can be improved, and the reliability deterioration due to the film quality of the tunnel oxide film can be improved. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The flash memory cell according to the embodiment of the present invention is substantially the same as the conventional flash memory cell shown in FIG. 6 in its external structure. In the description, the same reference numerals as those used in FIG. 6 are used to indicate each part of the flash memory cell. Further, since the array configuration of the flash memory cell according to the embodiment of the present invention is the same as the conventional array configuration shown in FIG. 7, it will be used in FIG. 7 to show each part of the flash memory cell array in the following description. Use the same symbols as those used. Moreover, since the manufacturing method shown in FIG. 9 can be applied as it is to the embodiment of the present invention, the description thereof is omitted.

  Therefore, the array configuration of the flash memory cells according to the first and second embodiments of the present invention described below includes a common source line (SL) and a plurality of word lines (WL1) as shown in FIGS. To WLn), a plurality of bit lines (BL1 to BLm), and a plurality of nonvolatile memory cells (MC11 to MCnm) which are provided at intersections of each word line and bit line and are arranged in a matrix and configured by MIS transistors. Each of the memory cells (MC11 to MCnm) includes the transistor shown in FIG. 6A, the source region 3 is connected to a common source line (SL), and the drain region 2 is a bit line (BL1). To BLm), and the control gate electrode 8 is connected to the word lines (WL1 to WLn). Two adjacent memory cells connected to the same bit line and corresponding to every two word lines (hereinafter referred to as “adjacent memory cell pairs”) are shown in FIGS. 8B and 9D. As shown in the drawing, a common drain region 2 is provided, and a plurality of adjacent memory cell pairs are arranged in the longitudinal direction of the word line. An element isolation insulating film 9 made of a LOCOS film is formed between the pair and is electrically isolated.

(First embodiment)
First, the configuration of the flash memory device according to the first embodiment of the present invention will be described with reference to FIG. In FIG. 1, 21 is a word line decoder circuit for applying a voltage to the word line WL, 22 is a bit line decoder circuit for applying a voltage to the bit line BL, and 23 is a source line selection circuit for applying a voltage to a common source line SL. It is. Although not shown, there is also a substrate voltage supply circuit (ground circuit) that applies a voltage to the substrate on which the memory cells MC are formed. In the following description, a word line WL, a bit line BL, and a source line SL are provided. The substrate is supplied with a voltage from the above circuit.

  The flash memory device according to the present embodiment includes odd-numbered word lines (WL1, WL3,..., WLn-1) and even-numbered word lines (WL2, WL4,..., WLn) in the flash memory cell array. On the other hand, it is characterized by having a circuit capable of applying a voltage separately.

  For example, the word line decoder circuit 21 includes a decoder circuit 21a for applying a voltage only to odd-numbered word lines and a decoder circuit 21b for applying a voltage only to even-numbered word lines. In order to enable separate driving, a mode switching circuit 24, which is a two-stage switching circuit, is provided in the previous stage. That is, the mode switching circuit 24 selects the decoder circuit 21a for applying the voltage only to the odd-numbered word lines, or selects the decoder circuit 21b for applying the voltage only to the even-numbered word lines. This circuit has two modes, mode 2, and is used only when data rewrite operations (erase and write) are performed on flash memory cells.

  Hereinafter, a method for driving the flash memory array according to the present embodiment will be described with reference to FIG. Here, FIG. 2 shows only the erase operation.

  First, the erase operation will be described. A negative voltage (for example, -8V) is applied to the word line WL (memory cell control gate electrode 8) of the odd column, a low voltage (for example, 0V) to the word line WL (memory gate control gate electrode 8) of the even column, and the source line SL. A positive voltage (for example, 5 V) is applied to the (source region 3 of the memory cell), a low voltage (for example, 0 V) is applied to the substrate (P well region 1 in FIG. 6), and the bit line BL (the drain region 2 of the memory cell) is floating. A state (open state) is set, and a voltage is applied for a certain period (for example, 100 ms). At this time, the stress of the erase operation as shown in FIG. 6C is applied to the flash memory cells on the word lines of the odd columns. For this reason, excess electrons accumulated in the floating gate electrode 6 are caused by a current (tunnel current) caused by the FN tunneling phenomenon through the gate insulating film 5 in the overlapping portion of the source region 3 and the floating gate electrode 6. , The threshold voltage of the control gate voltage required for forming the channel in the channel region 4 is lowered. On the other hand, the flash memory cells on the even-numbered word lines do not generate an electric field necessary for FN tunneling as described above, and therefore, the electrons accumulated in the floating gate electrode 6 are It is kept as it is. Hereinafter, this operation is referred to as an erasing operation (odd column).

  Next, the threshold level is confirmed for the flash memory cells on the word lines in the odd columns. This confirmation is an operation for detecting whether or not the threshold value of the flash memory cell having the highest threshold value among the flash memory cells on the word lines in the odd-numbered columns is below a certain target level (for example, 2V). That's it. Hereinafter, this operation is referred to as erase verify (odd number column). In the erase verify (odd column), when the threshold value of the flash memory cell having the highest threshold value among the flash memory cells on the word line of the odd column does not reach the target level or lower, The erase operation (odd column) and erase verify (odd column) are repeated. Finally, it is confirmed by erase verify (odd column) that the threshold value of the flash memory cell having the highest threshold value among the flash memory cells on the word line of the odd column is below the target level. At this point, the erase operation for the flash memory cells on the word lines in the odd columns is completed.

  Next, the erase operation (even column) and erase verify (even column) are repeated in the same manner for the flash memory cells on the word lines in the even columns. Finally, the erase verify (even column) confirms that the threshold value of the flash memory cell having the highest threshold value among the flash memory cells on the word line of the even column is below the target level. At this point, the erase operation for the flash memory cells on the word lines in the even columns is completed, and the erase operation for the entire flash memory array is completed.

  When the flash memory array is erased in this way, as shown in FIG. 3A, the threshold distribution after erasure can be made narrower than in the prior art. For example, the distribution that has been distributed in the range of 0 to 2V as the threshold value after erasing can be suppressed to the range of 1 to 2V. As described above, according to the erasing method of the present embodiment, it is possible to ensure a sufficient margin for overerasing failure.

  Next, the write operation will be described. A positive voltage (for example, 5V) is applied to the bit line BL1 (the drain region 2 of the memory cell), and the memory cells MC11 to MC101 at the intersections with the bit line BL1 in the odd-numbered word lines WL (the control gate electrodes 8 of the memory cells). A write voltage (for example, 10V) is applied only to the word line that writes data to MC1n-1, and a low voltage (control gate electrode 8 of the memory cell) is applied to the remaining odd-numbered word lines and all even-numbered word lines WL. For example, a low voltage (eg, 0 V) is applied to the substrate (P well region 1 in FIG. 6) and the source line SL (source region 3 of the memory cell), and a voltage is applied for a certain period (eg, 10 μs).

  At this time, the stress of the write operation as shown in FIG. 6B is applied to the flash memory cells on the bit line BL1 and the odd-numbered word lines to which the write voltage is applied. For this reason, an on-current flows between the drain and the source, hot electrons are generated in the vicinity of the drain, and injected into the floating gate electrode 6. The threshold voltage of the control gate voltage necessary for forming a channel in the channel region 4 is increased by the electrons thus injected.

  On the other hand, the flash memory cells on the other bit lines and the flash memory cells on the bit lines BL1 and the odd-numbered word lines and all the even-numbered word lines to which no write voltage is applied include Since hot electrons are not generated in the vicinity of the drain as described above, electrons are not injected into the floating gate electrode 6. Hereinafter, this operation is referred to as write operation 1 (odd column).

  Next, the threshold level is confirmed for the flash memory cells on the bit line BL1 and on the odd-numbered word lines to which the write voltage is applied. This confirmation means that the threshold value of the flash memory cell having the lowest threshold value among the flash memory cells on the bit line BL1 and on the odd-numbered word lines to which the write voltage is applied is equal to or higher than a target level (for example, 6V). Hereinafter, this operation is referred to as write verify 1 (odd column).

  In the write verify 1 (odd number column), the threshold value of the flash memory cell having the lowest threshold value among the flash memory cells on the bit line BL1 and the odd number word line to which the write voltage is applied is If the target level is not reached, the write operation 1 (odd column) and the write verify 1 (odd column) are repeated. Finally, in the write verify 1 (odd column), the threshold of the flash memory cell having the lowest threshold value among the flash memory cells on the bit line BL1 and on the odd word line to which the write voltage is applied. When it is confirmed that the value is equal to or higher than the target level, the write operation 1 (odd column) for the desired flash memory cell on the bit line BL1 and on the word line of the odd column is completed.

  Similarly, writing to the flash memory cells on the bit lines BL2 to BLm and the word lines in the odd columns is sequentially performed, thereby completing the writing to the desired flash memory cells on the word lines in the odd columns.

  Next, the write operation 1 (even column) and the write verify 1 (even column) are repeatedly performed in the same manner for the flash memory cells on the bit line BL1 and on the even word line to which data is written. . Finally, in the write verify 1 (even column), the threshold of the flash memory cell having the lowest threshold value among the flash memory cells on the bit line BL1 and the word line of the even column to which the write voltage is applied. When it is confirmed that the value is equal to or higher than the target level, the write operation 1 (even column) for a desired flash memory cell on the bit line BL1 and on the word line of the even column is completed.

  Similarly, the flash memory cells on the bit lines BL2 to BLm and the even-numbered word lines are sequentially written, so that the writing to the desired flash memory cells on the even-numbered word lines is completed at the same time. The write operation for the desired flash memory cell in the entire array is completed.

  In this way, when the flash memory array is written, the threshold distribution after writing can be narrowed as compared with the conventional case, as shown in FIG. For example, the distribution of the threshold value after writing in the range of 6 to 8V can be suppressed to the range of 6 to 7V. As described above, according to the write method of the present embodiment, the charge retention reliability of the flash memory cell in the write state can be improved. In addition, since the threshold distribution can be narrowed, the target level of the threshold value after erasure and the target level of the threshold value after writing can be lowered within a range where no overerasing failure occurs. For example, as shown in FIG. 3B, the target level of the threshold after erasing can be changed from 2V to 1V, and the target level of the threshold after writing can be changed from 6V to 5V. As a result, the threshold value after writing can be lowered to a range of 5 to 6 V, and the charge retention reliability of the flash memory cell in the written state can be improved.

  Further, according to the rewriting method of the present embodiment, the number of electrons passing through the tunnel oxide film (gate insulating film 5) can be reduced at the time of writing operation or erasing operation as compared with the conventional case. Degradation of the quality of the tunnel oxide film is suppressed, and this leads to an improvement in reliability reduction due to the quality of the tunnel oxide film.

(Second Embodiment)
Next, the configuration of the flash memory device according to the second embodiment of the present invention will be described with reference to FIG. In FIG. 4, the same components as those in FIG.

  The flash memory device according to the present embodiment includes odd-numbered word lines (WL1, WL3,..., WLn-1) and even-numbered word lines (WL2, WL4,..., WLn) in the flash memory cell array. On the other hand, a circuit capable of applying a voltage separately and a circuit capable of applying a voltage to all word lines are provided.

  For example, the word line decoder circuit 21 includes a decoder circuit 21a for applying a voltage only to odd-numbered word lines and a decoder circuit 21b for applying a voltage only to even-numbered word lines. In order to be able to drive at the same time or drive each separately, a mode switching circuit 24 which is a three-stage switch circuit is provided in the previous stage. That is, the mode switching circuit 24 selects the decoder circuit 21a for applying a voltage only to the odd-numbered word lines and the decoder circuit 21b for simultaneously applying the voltage only to the even-numbered word lines to select the mode 1 and the odd-numbered columns. There are three modes: mode 2 for selecting only the decoder circuit 21a for applying a voltage only to the word lines of the first mode, and mode 3 for selecting only the decoder circuit 21b for applying a voltage only to the word lines of even columns. This circuit is used only when data rewrite operations (erase and write) are performed on flash memory cells.

  Hereinafter, a driving method of the flash memory array according to the present embodiment will be described with reference to FIG. Here, FIG. 5 shows only the erase operation.

  First, the erase operation will be described. All word lines WL (control gate electrode 8 of the memory cell) have a negative voltage (for example, −8V), source line SL (the source region 3 of the memory cell) has a positive voltage (for example, 5V), and the substrate (P well region in FIG. 6). 1) is applied with a low voltage (for example, 0 V), the bit line BL (drain region 2 of the memory cell) is set in a floating state (open state), and a voltage is applied for a certain period (for example, 100 ms). After this erase operation, erase verify (odd column) for the flash memory cells on the odd word lines and erase verify (even column) for the flash memory cells on the even word lines are performed separately. As a result, when neither the odd-numbered column nor the even-numbered column has reached the target threshold level, the erase operation, erase verify (odd column), and erase verify (even column) are repeatedly performed. If the target threshold level is not reached only in the odd columns, the erase operation (odd columns) and erase verify (odd columns) are repeated only for the flash memory cells on the word lines in the odd columns. carry out. If the target threshold level is not reached only in the even column, the erase operation (even column) and erase verify (even column) are repeatedly performed only for the flash memory cells on the word line of the even column. . Finally, when both the odd and even columns reach the target threshold level, the erase operation is completed.

  When the flash memory array is erased in this way, the threshold distribution after erasure can be narrowed compared to the conventional case, and the same effect as the erasing method in the first embodiment can be obtained. Furthermore, according to the erasing method in the second embodiment, the total erasing operation time can be shortened compared with the erasing method in the first embodiment.

  Next, the write operation will be described. A positive voltage (for example, 5V) is applied to the bit line BL1 (the drain region 2 of the memory cell), and the memory cells MC11 to MC1n at the intersections with the bit line BL1 among all the word lines WL (the control gate electrode 8 of the memory cell). A write voltage (for example, 10 V) is applied only to the word line for writing data, a low voltage (for example, 0 V) is applied to the remaining word line (control gate electrode 8 of the memory cell), and the substrate (P well region 1 in FIG. 6). A low voltage (eg, 0 V) is applied to the source line SL (memory cell source region 3), and a voltage is applied to the desired flash memory cell on the bit line BL1 by applying a voltage for a certain period (eg, 10 μs). Write operation 1 is performed.

  Next, write verify 1 (odd column) for the flash memory cells on the bit line BL1 and the odd-numbered word line to which the write voltage is applied, and the even-numbered word line to which the write voltage is applied on the bit line BL1. Write verify 1 (even column) for a certain flash memory cell is performed separately.

  As a result, when the threshold value of the flash memory cell having the lowest threshold value among the flash memory cells to which the write voltage is applied does not reach the target threshold level in both the odd and even columns of the word line. Repeats the write operation 1, the write verify 1 (odd column), and the write verify 1 (even column).

  If only the odd-numbered column does not reach the target threshold level, the write operation 1 (odd-numbered column) and the write verify 1 (odd-numbered) are performed only for the desired flash memory cells on the odd-numbered word lines. Repeat). If only the even column does not reach the target threshold level, the write operation 1 (even column) and the write verify 1 (even column) are performed only on a desired flash memory cell on the word line of the even column. Repeatedly. When the threshold value of the flash memory cell having the lowest threshold value among the flash memory cells to which the write voltage is finally applied reaches the target threshold level in both the odd and even columns of the word line, The write operation 1 for the flash memory cell on the bit line BL1 is completed.

  Similarly, the writing operation of the entire flash memory array is completed by sequentially writing data to desired flash memory cells on the bit lines BL2 to BLm.

  In this way, when writing to the flash memory array is performed, the threshold distribution after erasure can be made narrower than in the prior art, and the same effect as the writing method in the first embodiment can be obtained. Furthermore, according to the write method in the second embodiment, the total write operation time can be shortened as compared with the write method in the first embodiment.

  Therefore, according to the rewriting method in the second embodiment, an effect equivalent to that of the rewriting method in the first embodiment can be obtained, and compared with the rewriting method in the first embodiment. , Total rewriting operation time can be shortened.

  As described above, according to the first and second embodiments of the present invention, the threshold distribution variation after write / erase caused by the write / erase characteristic difference generated in the manufacturing process of the flash memory is The increase in the area as the flash memory core can be suppressed and suppressed easily. Therefore, it is possible to secure a sufficient margin for over-erasing failure, improve the charge retention reliability of the flash memory cell in the written state, and improve the reliability degradation due to the film quality of the tunnel oxide film. .

  The nonvolatile semiconductor memory device and the driving method thereof according to the present invention can easily suppress variations in threshold distribution after writing and erasing, and are useful for flash memories and the like.

1 is a simple block diagram showing a configuration of a flash memory device according to a first embodiment of the present invention. FIG. 3 is a flowchart showing an erase operation for the flash memory array in the first embodiment of the present invention; Schematic diagram showing a threshold distribution after writing and erasing the flash memory array in the first embodiment of the present invention Simple block diagram showing a configuration of a flash memory device according to a second embodiment of the present invention FIG. 7 is a flowchart showing an erase operation for the flash memory array in the second embodiment of the present invention; Schematic showing a cross-sectional structure for explaining a structure of a flash memory cell and a write / erase operation Configuration diagram of a typical flash memory cell array Plan view of flash memory cell and plan view of flash memory cell after manufacture FIG. 8 is a schematic view showing a manufacturing process of a flash memory cell in a cross section along A-A ′ of FIG. 8. Schematic showing the asymmetry when forming the source / drain in FIG. Flow diagram showing write and erase operations for a flash memory array in a conventional example Schematic showing the threshold distribution after writing and erasing the flash memory array according to the conventional example

Explanation of symbols

1 P-type well 2 Drain region 3 Source region 4 Channel region 5 Gate insulating film (tunnel oxide film)
6 Floating gate electrode 7 Interlayer insulating film 8 Control gate electrode 9 Element isolation region 10 Drain contact 21 Word line decoder circuit 22 Bit line decoder circuit 23 Source line selection circuit 24, 25 Mode switching circuit

Claims (8)

A plurality of word lines, a plurality of bit lines, and a plurality of MISs provided at the intersections of the word lines and the bit lines and capable of electrically controlling a threshold voltage corresponding to stored data from the outside. A non-volatile semiconductor memory device comprising a transistor,
A non-volatile semiconductor memory device comprising means for separately applying voltages to odd-numbered word lines and even-numbered word lines.   2. The nonvolatile semiconductor memory device according to claim 1, further comprising means for simultaneously applying a voltage to the odd-numbered word lines and the even-numbered word lines.   The nonvolatile semiconductor memory device is a flash memory, further comprising means for applying a negative voltage to the odd-numbered word lines and even-numbered word lines when erasing data of the MIS transistor. The nonvolatile semiconductor memory device according to claim 1.   The MIS transistors are separated by a LOCOS film, the positional relationship between the source and drain of the MIS transistor corresponding to the odd-numbered word line, and the source and drain of the MIS transistor corresponding to the even-numbered word line. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the positional relationship is reversed. 5. A plurality of word lines, a plurality of bit lines, and a plurality of MISs provided at the intersections of the word lines and the bit lines and capable of electrically controlling a threshold voltage corresponding to stored data from the outside. A method of driving a nonvolatile semiconductor memory device comprising a transistor and means for separately applying a voltage to an odd-numbered word line and an even-numbered word line,
A method for driving a nonvolatile semiconductor memory device, wherein data writing and erasing are separately performed on the MIS transistors corresponding to the odd-numbered word lines and the MIS transistors corresponding to the even-numbered word lines, respectively. . A plurality of word lines, a plurality of bit lines, and a plurality of MISs provided at the intersections of the word lines and the bit lines and capable of electrically controlling a threshold voltage corresponding to stored data from the outside. A transistor; means for separately applying voltages to odd-numbered word lines and even-numbered word lines; and means for simultaneously applying voltages to the odd-numbered word lines and even-numbered word lines. A non-volatile semiconductor memory device driving method comprising:
When writing or erasing data to / from the MIS transistors corresponding to the odd-numbered word lines and the MIS transistors corresponding to the even-numbered word lines,
In an initial stage, MIS transistors corresponding to the odd-numbered word lines and MIS transistors corresponding to the even-numbered word lines are simultaneously written or erased,
After one of all the MIS transistors on the odd-numbered word line or all the MIS transistors on the even-numbered word line has reached the target level for writing or erasing, the one that has not reached the target level. A method for driving a nonvolatile semiconductor memory device, wherein writing or erasing is performed only on a MIS transistor corresponding to a word line.   The write includes a write execution process for injecting electrons into the floating gate of the MIS transistor, and a write verify process for detecting the threshold value of the MIS transistor, and the erasure extracts electrons from the floating gate of the MIS transistor. 7. The method for driving a nonvolatile semiconductor memory device according to claim 5, further comprising: erase execution processing and subsequent erase verification processing for detecting a threshold value of the MIS transistor.   7. The method of driving a nonvolatile semiconductor memory device according to claim 5, wherein a negative voltage is applied to the odd-numbered word lines and even-numbered word lines during the erasing.

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