TW201010062A - Nonvolatile semiconductor memory element, nonvolatile semiconductor memory cell and nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory element, nonvolatile semiconductor memory cell and nonvolatile semiconductor memory device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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Abstract
Description
201010062 、 六、發明說明： 【發明所屬之技術領域】 本發明係有關於非揮發性半導體記憶元件、非揮發性 半導體記憶胞元及非揮發性半導體記憶裝置。 【先前技術】 由 EEPROM(Electrically Erasble Programmmable Read Only Memory)所代表之非揮發性記憶體，因爲即使關掉電 源，資訊亦不會消失，所以用於很多用途。例如，作爲 〇 EEPRO Μ之代表性用途，有1C卡。又，由於可隨時因應於 用途而改寫的便利性，而作爲微電腦內之遮蔽罩ROM的置 換，使用EEPROM或快閃記憶體。此外，近年來，逐漸需 要在系統LSI或邏輯1C的一部分取入非揮發性記憶體之所 謂埋入型的邏輯元件混載記憶體（Embedded Memory)。此 外，作爲裝入類比電路並進行高精度類比電路之調整等的 調整用開關，亦逐漸需要從約數百位元至數千位元之小規 格的非揮發性記憶體。 φ 可是，一般非揮發性記憶體是使用2層多晶矽層或3 層多晶矽層之胞元構造，製程比標準CMOS邏輯元件製程 複雜且製造步驟亦多，若想將非揮發性記憶體和標準邏輯 元件同時埋入一晶元內，發生製造步驟多、良率亦降低、 產品的價格（cost)上漲的問題。 又，作爲可靠性上的要求，近年來在車上用途，強烈 要求將保證溫度從以往的150 °C提高至170 °c或更髙，對非 揮發性半導體記憶體的高溫、高可靠性的要求亦變得強烈。 作爲解決此問題的一種手段，提議使用1層多晶矽的 201010062 EEPROM(參照專利文獻 1)。若使用此 1層多晶矽的 EEP ROM，可比以往的2層多晶矽製程更減少製造步驟。 另一方面，作爲解決可靠性問題的手法，發明者使用 2層多晶矽型的非揮發性半導體記憶體，並進行如專利文 獻2的提案。201010062, VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile semiconductor memory devices, non-volatile semiconductor memory cells, and non-volatile semiconductor memory devices. [Prior Art] The non-volatile memory represented by the EEPROM (Electrically Erasble Programmmable Read Only Memory) is used for many purposes because the information does not disappear even if the power is turned off. For example, as a representative use of 〇 EEPRO ,, there is a 1C card. Further, since it is possible to rewrite at any time in accordance with the use, it is used as a mask ROM in the microcomputer, and an EEPROM or a flash memory is used. Further, in recent years, there has been a demand for a buried type logic element mixed memory (Embedded Memory) in which a nonvolatile memory is taken in a part of the system LSI or the logic 1C. In addition, as an adjustment switch for loading an analog circuit and performing adjustment of a high-precision analog circuit, a non-volatile memory of a small size of about several hundred bits to several thousands of bits is gradually required. φ However, general non-volatile memory is a cell structure using a 2-layer polysilicon layer or a 3-layer polysilicon layer. The process is more complex than standard CMOS logic devices and has many manufacturing steps. If you want to use non-volatile memory and standard logic. The components are buried in one wafer at the same time, and there are many manufacturing steps, a decrease in yield, and an increase in the cost of the product. In addition, as a requirement for reliability, in recent years, it has been strongly demanded to increase the temperature from the conventional 150 ° C to 170 ° C or more, and to high temperature and high reliability of nonvolatile semiconductor memory. The requirements have also become strong. As a means for solving this problem, it is proposed to use a 1-layer polysilicon 201010062 EEPROM (refer to Patent Document 1). If this 1-layer polysilicon EEP ROM is used, the manufacturing steps can be reduced compared to the previous 2-layer polysilicon process. On the other hand, as a method for solving the reliability problem, the inventors used a two-layer polycrystalline non-volatile semiconductor memory, and proposed a proposal as disclosed in Patent Document 2.
可是，爲了省略用作控制閘極之第2層多晶矽，需要 將由擴散層所構成之控制閘極埋入浮動閘極之下，而成爲 比在邏輯元件所使用之標準CMOS製程更複雜的製程。此 外，若使以高濃度所埋入的擴散層變成氧化，成爲質差的 氧化膜，發生不良的機率變高，可靠性亦成爲問題。 如上述所示，在以往之使用1層多晶矽的EEP ROM， 爲了省略用作控制閘極之第2層多晶矽，需要將由擴散層 所辦成之控制閘極埋入浮動閘極之下，而成爲比在邏輯元 件所使用之標準CMOS製程更複雜的製程。此外，若使以 高濃度所埋入的擴散層變成氧化，成爲質差的氧化膜，發 生不良的機率變高，可靠性亦成爲問題。However, in order to omit the second-layer polysilicon used as the control gate, it is necessary to embed the control gate composed of the diffusion layer under the floating gate, which is a more complicated process than the standard CMOS process used for the logic element. Further, when the diffusion layer buried at a high concentration is oxidized and becomes a poor quality oxide film, the probability of occurrence of defects increases, and reliability also becomes a problem. As described above, in the conventional EEP ROM using one-layer polysilicon, in order to omit the second-layer polysilicon used as the control gate, it is necessary to embed the control gate formed by the diffusion layer under the floating gate. A more complex process than the standard CMOS process used for logic components. In addition, when the diffusion layer embedded in a high concentration is oxidized and becomes a poor quality oxide film, the probability of occurrence of defects is increased, and reliability is also a problem.
又，例如，作爲EEPROM之代表性的其他用途，用作 中容量之遮蔽罩ROM微電腦內之遮蔽罩ROM的置換。又， 雖然EEPROM以紫外線可拭除並可改寫複數次，但是因爲 使用透明玻璃之封裝貴，作爲封入便宜的塑膠封裝，雖然 無法拭除，但是便宜的非揮發性記憶體，〇TP(One Time Programmable ROM)逐漸普及。此外，近年來，逐漸需要 在系統LSI或邏輯1C的一部分取入非揮發性記憶體之所謂 埋入型的邏輯元件混載記憶體（Embedded Memory)。此外， 作爲裝入類比電路並進行高精度類比電路之調整等的調整 -6- 201010062 用開關，亦逐漸需要從約數百位元至數千位元之小規格的 非揮發性記憶體。 可是，一般非揮發性記憶體是使用2層多晶矽層或3 層多晶矽層之胞元構造，製程比標準CMOS邏輯元件製程 複雜且製造步驟亦多，若想將非揮發性記憶體和標準邏輯 元件同時埋入一晶元內，發生製造步驟多、良率亦降低、 產品的價格（cost)上漲的問題。 作爲解決此問題的一種手段，提議使用1層多晶矽的 EEPROM(Electrically Erasble Programmmable Read OnlyFurther, for example, as a representative other use of the EEPROM, it is used as a replacement for the mask ROM in the medium-capacity mask ROM microcomputer. Moreover, although the EEPROM can be erased by ultraviolet light and can be rewritten multiple times, since the package using transparent glass is expensive, it is an inexpensive plastic package, although it cannot be erased, but inexpensive non-volatile memory, 〇TP (One Time) Programmable ROM) is gradually becoming popular. Further, in recent years, there has been a need for a so-called embedded logic element mixed memory (Embedded Memory) in which a nonvolatile memory is taken in a part of the system LSI or the logic 1C. In addition, as a switch for loading an analog circuit and performing adjustment of a high-precision analog circuit, the switch -6-201010062 also requires a small-sized non-volatile memory from about several hundred bits to several thousands of bits. However, general non-volatile memory is a cell structure using a 2-layer polysilicon layer or a 3-layer polysilicon layer. The process is more complex than standard CMOS logic devices and has many manufacturing steps. If you want to use non-volatile memory and standard logic components. At the same time, it is buried in a crystal cell, and there are problems of many manufacturing steps, a decrease in yield, and an increase in the price of the product. As a means of solving this problem, it is proposed to use a 1-layer polysilicon EEPROM (Electrically Erasble Programmmable Read Only).
Memory)(例如，參照專利文獻1)。若使用此1層多晶矽的 EEPROM，可比以往的2層多晶矽製程更減少製造步驟。 又，亦開始出現不是浮動閘極型，而是抗熔（antifuse)型之 標準CMOS製程的OTP，其對電容器之氧化膜施加高電 壓，而破壞閘極，以記憶。 可是，在1層多晶矽EEPROM，爲了省略用作控制閘 極之第2層多晶矽，需要將由擴散層所構成之控制閘極埋 Q 入浮動閘極之下，而成爲比在邏輯元件所使用之標準 CMOS製程更複雜的製程。此外，若使以高濃度所埋入的 擴散層變成氧化，成爲質差的氧化膜，發生不良的機率變 高，可靠性亦成爲問題》 又，抗熔型的OTP，因爲發生100%的閘極破壞，所以 —旦破壞後就無法復原，因爲出貨時亦無法測試，而無法 保證，所以亦有可靠性上的問題。 如上述所示，在以往之使用1層多晶矽的EEPROM， 爲了省略用作控制閘極之第2層多晶矽，需要將由擴散層 201010062 所構成之控制閘極埋入浮動閘極之下，而成爲比在邏輯元 件所使用之標準CMOS製程更複雜的製程。此外，若使以 高濃度所埋入的擴散層變成氧化，成爲質差的氧化膜，發 生不良的機率變高，可靠性亦成爲問題》 又，抗熔型的OTP，因爲發生100%的閘極破壞，所以 一旦破壞後就無法復原，因爲出貨時亦無法測試，而無法 保證，所以亦有可靠性上的問題。 在浮動閘極型的非揮發性半導體記憶體，爲了防止電 子脫逃，而需要高品質的氧化膜，需要特殊的技術。可是， 在標準CMOS製程，只要不破壞氧化膜的可靠性即可。因 爲在一般的品質無問題，所以作爲非揮發性半導體記憶體 的氧化膜品質不充分的情況多。即，可靠性成爲問題。此 外，在1層多晶矽型的非揮發性半導體記憶體，爲了省略 用作控制閘極之第2層多晶矽，需要將由擴散層所構成之 控制閘極埋入浮動閘極之下。那時，若使以高濃度所埋入 的擴散層變成氧化，成爲質差的氧化膜，又發生不良的機 率變高，可靠性亦成爲問題。在第77A圖〜第77D圖表示 浮動閘極之非揮發性半導體記憶胞元的構造，而在第78圖 表不電荷保持（data retention)特性。 第77A圖係表示具有2層多晶矽構造之浮動閘極型非 揮發性半導體記憶胞元之構造之槪略的平面圖，第77B圖 係等價電路圖，第77C圖係沿著第7 7A圖之A30— A30’ 的剖面圖，第77D圖係沿著第77A圖之D30-D30’的剖 面圖。如第77B圖所示，非揮發性半導體記憶胞元由串列 連接之 MOS 電晶體（Metal Oxide Semiconductor 201010062 、Memory) (for example, refer to Patent Document 1). If this 1-layer polysilicon EEPROM is used, the manufacturing steps can be reduced compared to the conventional 2-layer polysilicon process. In addition, an OTP that is not a floating gate type but an anti-fuse type standard CMOS process has begun to appear, which applies a high voltage to the oxide film of the capacitor and breaks the gate to memorize. However, in the 1-layer polysilicon EEPROM, in order to omit the second-layer polysilicon used as the control gate, it is necessary to embed the control gate composed of the diffusion layer under the floating gate, which is the standard used in the logic element. More complex processes in CMOS processes. In addition, when the diffusion layer embedded in a high concentration is oxidized and becomes an oxide film having a poor quality, the probability of occurrence of defects is increased, and reliability is also a problem. Further, the anti-fuse OTP has a gate of 100%. It is extremely destructive, so it cannot be recovered after it is destroyed. Because it cannot be tested at the time of shipment, it cannot be guaranteed, so there are also problems in reliability. As described above, in the conventional EEPROM using one-layer polysilicon, in order to omit the second-layer polysilicon used as the control gate, it is necessary to embed the control gate composed of the diffusion layer 201010062 under the floating gate. A more complex process in the standard CMOS process used by logic components. In addition, when the diffusion layer embedded in a high concentration is oxidized and becomes an oxide film having a poor quality, the probability of occurrence of defects is increased, and reliability is also a problem. Further, the anti-fuse OTP has a gate of 100%. It is extremely destructive, so once it is destroyed, it cannot be recovered. Because it cannot be tested at the time of shipment, it cannot be guaranteed, so there is also a problem of reliability. In the floating gate type non-volatile semiconductor memory, in order to prevent electrons from escaping, a high-quality oxide film is required, and a special technique is required. However, in the standard CMOS process, as long as the reliability of the oxide film is not destroyed. Since there is no problem in general quality, the quality of the oxide film as a non-volatile semiconductor memory is insufficient. That is, reliability becomes a problem. Further, in the one-layer polycrystalline non-volatile semiconductor memory, in order to omit the second-layer polysilicon used as the control gate, it is necessary to embed the control gate composed of the diffusion layer under the floating gate. At that time, if the diffusion layer buried at a high concentration is oxidized to become a poor-quality oxide film, the probability of occurrence of defects increases, and reliability also becomes a problem. The structures of the non-volatile semiconductor memory cells of the floating gate are shown in Figs. 77A to 77D, and the data retention characteristics are shown in Fig. 78. Figure 77A is a schematic plan view showing the structure of a floating gate type non-volatile semiconductor memory cell having a two-layer polysilicon structure, the 77B is an equivalent circuit diagram, and the 77C is an A30 along the 7th 7A chart. — Sectional view of A30', section 77D is a section along D30-D30' of Figure 77A. As shown in Fig. 77B, the non-volatile semiconductor memory cells are connected in series by a MOS transistor (Metal Oxide Semiconductor 201010062,
Transistor;以下只稱爲「電晶體」）T301和浮動聞極電晶 體T3 02所構成。在此，電晶體T3 01是用以選擇記憶胞元 的開關。在此記憶胞元，電晶體T3 01的汲極成爲記憶胞元 的汲極D300，電晶體T302的源極成爲記憶胞元的源極 S300,電晶體T301的閘極成爲選擇閘極SG3 00,一端和電 晶體T302的浮動閘極連接之電容器的另一端成爲控制閘 極 CG3 00。 又，在第77A圖、第77C圖以及第77D圖，符號3001 Ο 是P型半導體基板，符號3 00 3是構成電晶體T3 01的電晶 體，符號30 04是構成電晶體T3 02的浮動閘極型電晶體， 符號3005是電晶體T301的η型汲極擴散層，符號30 06 是成爲電晶體Τ3 01之源極（或電晶體Τ3 02之汲極）的η型 擴散層，符號3 007是成爲電晶體Τ3 02之源極的η型擴散 層。又，符號3008是成爲電晶體Τ301之閘極的多晶矽層， 符號3009是成爲電晶體Τ3 02之浮動閘極的多晶矽層，並 成爲電容器的一端，符號3010是和η型擴散層3005連接 Q 的接點，符號3011是和η型擴散層3007連接的接點。而， 符號301 9Ρ是成爲控制閘極配線的第2多晶矽配線層，符 號3020是分離用絕緣氧化膜。 第78圖係表示電荷保持（data retention)特性的圖。縱 軸方向表示臨限値電壓 Vth，橫軸方向表示時間的對數 (kg)。氧化膜有缺陷等，而位於浮動閘極之電荷少量地脫 逃時’寫入胞元（被注入電子之狀態）、拭除胞元（放出電 + ’換言之被注入電洞之狀態）都隨著時間而逐漸接近起始 値（中性狀態：不是電子亦不是電洞之空的狀態）。因爲此 201010062 不良是由氧化膜的缺陷所引起的，所以良胞元和不良胞元 混合存在。又，作爲其他的不良，亦有在重複寫入、拭除 中’氧化膜被破壞而成爲不良的事例。 另一方面，作爲解決可靠性問題的手法，發明者進行 如專利文獻2的提案。在第79圖表示在專利文獻2所提議 之非揮發性半導體記憶胞元的等價電路。 在一個記憶胞元中，並列地設置2個浮動閘極型電晶 體T312、T3 13，將各閘極和控制閘極CG共同連接。依此 方式，即使任一個變成不良，只要另一方的電晶體良好， 作爲胞元是正常。此外，電晶體T3 1 1是記憶胞元選擇用的 開關。 如本專利文獻2的記載所示，使用並列地設置之2個 非揮發性半導體記憶元件來構成非揮發性半導體記億胞元 時，可提高在電荷保持特性的可靠性。可是，因爲並列地 配置非揮發性半導體記憶元件，所以即使使用複雜之2層 多晶矽製程亦有難配置、布置面積變大的缺點。因此，因 爲在使用1層多晶矽製程的情況配置的自由度變低，所以 認爲布置配置的增大成爲更大的課題。 又，在該專利文獻1的技術，在浮動閘極型的非揮發 性記憶體，爲了防止電子從浮動閘極脫逃，而需要高品質 的氧化膜。在該高品質之氧化膜的形成，需要特殊的製程。 可是，在標準CMOS製程，只要不破壞電晶體，氧化膜的 可靠性就足夠，因爲在一般的品質無問題，所以作爲非揮 發性記憶體的氧化膜，品質不充分的情況多，非揮發性記 憶體的可靠性成爲問題。此外，爲了省略用作控制閘極之 -10- 201010062 第2層多晶矽，需要將由擴散層所構成之控制閘極埋入浮 動閘極之下，若使以高濃度所埋入的擴散層變成氧化，成 爲質差的氧化膜，發生不良的機率變高，可靠性降低，而 成爲問題。 如上述所示，在以往之使用1層多晶矽的EE PROM， 若利用標準CMOS製程製造，具有浮動閘極的電荷保持受 到品質比非揮發性半導體記憶胞元所使用之氧化膜差的氧 化膜阻礙的問題。此外，如上述之專利文獻2所示，因爲 〇 並列地配置複數個記憶元件，而有布置面積變大、難配置 的問題。 [專利文獻1]特開平1 0 - 289959號公報 [專利文獻2]專利第2685966號公報 【發明內容】 (發明所欲解決之課題） 本發明係鑑於該實情者，本發明的目的在於提供一種 非揮發性半導體記憶元件及非揮發性半導體記憶裝置，而 Q 該非揮發性半導體記憶元件以標準邏輯元件的CMOS製程 可實現非揮發性記憶體，同時可緊密地配置面積變大的電 容器（在浮動閘極和半導體基板表面所形成之電容器），並 使面積變成最小限度。 又，本發明之目的在於提供一種非揮發性半導體記憶 元件及非揮發性半導體記憶裝置，而該非揮發性半導體記 憶元件以標準邏輯元件的CMOS製程可實現非揮發性記憶 體，同時使用 1 層多晶矽的 OTP、MTP(Multi Time Programmable ROM) 〇 -11- 201010062 又，其目的在於提供一種非揮發性半導體記憶元件及 非揮發性半導體記億裝置，在該非揮發性半導體記憶元 件，可緊密地配置面積變大的電容器（在浮動閘極和半導體 基板表面所形成之電容器），並使面積變成最小限度。 又，本發明之目的在於提供可一面抑制布置面積的增 大一面提高可靠性之以1層多晶矽製程可製造的非揮發性 半導體記憶胞元及非揮發性半導體記憶裝置。 又，本發明之目的在於提供一種非揮發性半導體記憶 裝置，其實現使用標準CMOS製程可製造之1層多晶矽之 0 胞元構造的半導體記憶元件，同時藉高效率的配置而使組 裝面積變小，並提高記憶保持的可靠性。 (解決課題之手段） (1)本發明是爲了解決該課題而想出來的，本發明之一種 形態的非揮發性半導體記憶元件，是浮動閘極型之1層多 晶矽非揮發性半導體記憶元件，其由形成於半導體基板上 之MOS構造的第1電晶體、和浮動閘極型之第2電晶體所 構成，並以標準CMOS製程構成，該非揮發性半導體記憶 Q 元件構成爲：在對該浮動閘極儲存電荷時，在該第2電晶 體的汲極附近產生熱電子，並對該浮動閘極注入電荷，或 對該浮動蘭極施加髙電壓，而利用Fowler — Nordheim的穿 隧電流對該浮動閘極注入電荷；及在拭除該浮動閘極所儲 存的電荷時’對該第2電晶體的汲極和浮動閘極之間施加 高電壓’而利用該Fowler— Nordheim的穿隧電流放出該浮 動閘極所儲存的電荷；作爲該非揮發性半導體記憶元件之 構成部分的布置，在以上下方向表示該半導體基板上的第 -12- 201010062 1方向，並以左右方向表示和該第1方向正交之第2方向 的情況，具備有：方形的電晶體形成部，係在該上下方'向 依序配置：成爲該第1電晶體之汲極的第In型擴散層、形 成第1電晶體之通道的第1閘極區域部、是第1電晶體之 源極並亦成爲第2電晶體之汲極的第2η型擴散層、形成第 2電晶體之通道的第2閘極區域部、以及成爲源極的第3η 型擴散層；第1金屬配線，係在該電晶體形成部的左側或 右側，配置成和該電晶體形成部平行而且從半導體基板表 〇 面隔著既定之距離，同時利用接點和該第1電晶體之汲極 連接；方形的多晶矽層，係在左右方向形成爲一部分和該 第1電晶體之閘極區域部相對向，並成爲該第1電晶體之 閘極；方形的η型井，係在該半導體基板上，在該電晶體 形成部的左側，以既定之寬度和深度在左右方向所形成； 方形的浮動閘極，係在左右方向配置成和該半導體基板表 面相對向，同時配置成其左端部側的區域和該η型井的表 面相對向，而且右端部側的區域和該第2電晶體的該第2 Q 閘極區域部相對向；Ρ型擴散層，係和該η型井之與該浮 動閘極相對向之區域的左側相鄰，並以既定之寬度和深度 在左右方向形成，同時成爲對控制閘極配線的連接端子； 控制閘極配線，係從該半導體基板表面隔著既定之距離在 左右方向配置成和該浮動閘極相對向，同時利用接點和該 Ρ型擴散層連接：以及第2金靥配線，係從該半導體基板 表面隔著既定之距離在左右方向配置成和成爲該第2電晶 體之源極的第3η型擴散層相對向，同時利用接點和該第 3η型擴散層連接。 -13- 201010062 (2) 又，本發明之一形態的非揮發性半導體記憶元件，是 浮動閘極型之1層多晶矽非揮發性半導體記憶元件，其由 形成於半導體基板上之MOS構造的第1電晶體、和浮動閘 極型之第2電晶體所構成，並以標準CMOS製程構成，該 非揮發性半導體記憶元件構成爲：在對該浮動閘極儲存電 荷時，在該第2電晶體的汲極附近產生熱電子，並對該浮 動閘極注入電荷，或對該浮動閘極施加高電壓，而利用 Fowler— Nordheim的穿隧電流對該浮動閘極注入電荷；及 在拭除該浮動閘極所儲存的電荷時，對該第2電晶體的汲 © 極和浮動聞極之間施加高電壓，而利用該 Fowler -Nordheim的穿隧電流放出該浮動閘極所儲存的電荷；作爲 該非揮發性半導體記憶元件之構成部分的布置，在以上下 方向表示該半導體基板上的第1方向，並以左右方向表示 和該第1方向正交之第2方向的情況，具備有：方形的電 晶體形成部，係在該上下方向依序配置：成爲該第1電晶 體之汲極的第In型擴散層、形成第1電晶體之通道的第1 閘極區域部、是第1電晶體之源極並亦成爲第2電晶體之 汲極的第2η型擴散層、形成第2電晶體之通道的第2閘極 區域部、以及成爲源極的第3ιι型擴散層；第1金屬配線， 係在該電晶體形成部的左側或右側，配置成和該電晶體形 成部平行而且從半導體基板表面隔著既定之距離，同時利 用接點和該第1電晶體之汲極連接；方形的多晶矽層，係 在左右方向形成爲一部分和該第1電晶體之閘極區域部相 對向’並成爲該第1電晶體之聞極；方形之空乏型（depletion -type)通道注入，係在該半導體基板上，在該電晶體形成 -14- 201010062 部的左側，以既定之寬度和深度在左右方向所形成：方形 的浮動閘極，係在左右方向配置成和該半導體基板表面相 對向，同時配置成左端部側的區域和該通道注入的表面相 對向，而且右端部側的區域和該第2電晶體的該第2閘極 區域部相對向；第4ri型擴散層，係和該通道注入的左側相 鄰，並以既定之寬度和深度在左右方向形成，同時成爲對 該控制閘極配線的連接端子：控制閘極配線，係從該半導 體基板表面隔著既定之距離在左右方向配置成和該浮動閘 〇 極相對向，同時利用接點和該第4n型擴散層連接；以及第 2金屬配線，係從該半導體基板表面隔著既定之距離在左 右方向配置成和成爲該第2電晶體之源極的第3η型擴散層 相對向，同時利用接點和該第3η型擴散層連接。 (3) 又，本發明之一形態的非揮發性半導體記憶元件，亦 可在對該浮動閘極儲存電荷時，對該第1電晶體的閘極施 加第1高電壓，並對汲極施加第2電壓；對該第2電晶體 的控制閘極施加第3電壓，並對源極施加0V的電壓；在該 Q 第2電晶體的汲極附近產生熱電子，並對該浮動閘極注 入；同時在拭除該浮動閘極所儲存的電荷時，對該第1電 晶體的閘極施加第4電壓，並對該汲極施加第5電壓；對 該第2電晶體的控制閘極施加0V，並將源極設爲開路，或 施加比該第4電壓或該第5電壓更小的第6電壓；藉由對 該第2電晶體的汲極和浮動閘極之間施加高電場，而使從 浮動閘極向汲極放出電荷。 (4) 又，本發明之一形態的非揮發性半導體記憶元件，亦 可在對該浮動閘極儲存電荷時，使施加於該第2電晶體之 -15- 201010062 控制閘極的第3電壓分段地上昇並施加。 (5)又，本發明之一形態的非揮發性半導體記億元件，是 浮動閘極型之1層多晶矽非揮發性半導體記憶元件，其由 形成於半導體基板上之MOS構造的第1電晶體、和浮動閘 極型之第2電晶體所構成，並以標準CMOS製程構成，該 非揮發性半導體記憶元件構成爲：在對該浮動閘極儲存電 荷時，在該第2電晶體的汲極附近產生熱電子，並對該浮 動閘極注入電荷，或對該浮動閘極施加高電壓，而利用 Fowler— Nordheim的穿隧電流對該浮動閘極注入電荷；及 在拭除該浮動閘極所儲存的電荷時，對該第2電晶體的汲 極和浮動閘極之間施加高電壓，而利用FN電流放出該浮動 閘極所儲存的電荷；作爲該非揮發性半導體記憶元件之構 成部分的布置，在以上下方向表示該半導體基板上的第1 方向，並以左右方向表示和該第1方向正交之第2方向的 情況，具備有：方形的電晶體形成部，係在該上下方向依 序配置：成爲該第1電晶體之汲極的第In型擴散層、形成 第1電晶體之通道的第1閘極區域部、是第1電晶體之源 極並亦成爲第2電晶體之汲極的第2n型擴散層、形成第2 電晶體之通道的第2閘極區域部、以及成爲源極的第3n型 擴散層；第1金屬配線，係在該電晶體形成部的左側或右 側，配置成和該電晶體形成部平行而且從半導體基板表面 隔著既定之距離，同時利用接點和該第1電晶體之汲極連 接；方形的多晶矽層，係在左右方向形成爲一部分和該第 1電晶體之閘極區域部相對向，並成爲該第1電晶體的閘 極；方形之空乏型通道注入，係在該半導體基板上，在該 -16- 201010062 電晶體形成部的左側，以既定之寬度和深度在左右方向所 形成；方形的浮動閘極，係在左右方向配置成和該半導體 基板表面相對向，同時配置成左端部側的區域和該通道注 入的表面相對向，而且右端部側的區域和該第2電晶體的 該第2閘極區域相對向；第4η型擴散層，係和該通道注入 的左側相鄰，並以既定之寬度和深度在左右方向形成，同 時成爲對該控制閘極配線的連接端子；控制閘極配線，係 從該半導體基板表面隔著既定之距離在左右方向配置成和 〇 該浮動閘極相對向，同時利用接點和該第411型擴散層連 接；第2金屬配線，係從該半導體基板表面隔著既定之距 離在左右方向配置成和成爲該第2電晶體之源極的第3η型 擴散層相對向，同時利用接點和該第3ri型擴散層連接；以 及副接點，係用以在是該半導體基板上之該第1金屬配線 的側方，而且成爲該第1電晶體的閘極之方形的多晶矽層 之上側的位置，抑制形成該記憶胞元之半導體基板的區域 之電壓的上昇。 Q (6)又，本發明之一形態的非揮發性半導體記憶元件，是 浮動閘極型之1層多晶矽非揮發性半導體記憶元件，其由 形成於半導體基板上之MOS構造的第1電晶體、和浮動閘 極型之第2電晶體所構成，並以標準CMOS製程構成，該 非揮發性半導體記憶元件構成爲：在對該浮動閘極儲存電 荷時，在該第2電晶體的汲極附近產生熱電子，並對該浮 動閘極注入電荷，或對該浮動閘極施加高電壓，而利用 Fowler—Nordheim的穿隧電流對該浮動閘極注入電荷；及 在拭除該浮動閘極所儲存的電荷時，對該第2電晶體的汲 -17- 201010062Transistor; hereinafter referred to as "transistor" T301 and floating horn electro-optical crystal T3 02. Here, the transistor T3 01 is a switch for selecting a memory cell. In this memory cell, the drain of the transistor T3 01 becomes the drain D300 of the memory cell, the source of the transistor T302 becomes the source S300 of the memory cell, and the gate of the transistor T301 becomes the selection gate SG3 00, The other end of the capacitor whose one end is connected to the floating gate of the transistor T302 becomes the control gate CG3 00. Further, in the 77A, 77C, and 77D, the symbol 3001 Ο is a P-type semiconductor substrate, the symbol 3 00 3 is a transistor constituting the transistor T3 01, and the symbol 30 04 is a floating gate constituting the transistor T3 02. The polar transistor, symbol 3005 is an n-type drain diffusion layer of the transistor T301, and the symbol 30 06 is an n-type diffusion layer which becomes the source of the transistor Τ301 (or the drain of the transistor Τ302), symbol 3 007 It is an n-type diffusion layer that becomes the source of the transistor Τ302. Further, reference numeral 3008 is a polysilicon layer which becomes a gate of the transistor 301, symbol 3009 is a polysilicon layer which becomes a floating gate of the transistor Τ302, and becomes one end of the capacitor, and symbol 3010 is connected to the n-type diffusion layer 3005. The contact, symbol 3011, is a contact that is connected to the n-type diffusion layer 3007. Further, reference numeral 301 9 denotes a second polysilicon wiring layer for controlling gate wiring, and symbol 3020 is an insulating oxide film for separation. Figure 78 is a graph showing the characteristics of charge retention. The vertical axis direction represents the threshold voltage Vth, and the horizontal axis direction represents the logarithm of time (kg). The oxide film is defective, etc., and when the charge at the floating gate is slightly escaped, the cell is written (the state in which the electron is injected), and the cell is erased (the state of the discharge + 'in other words, it is injected into the hole) Time is gradually approaching the starting 値 (neutral state: not the state of electrons or the void of the hole). Because this 201010062 defect is caused by a defect in the oxide film, a good cell and a bad cell are mixed. Further, as another defect, there is an example in which the oxide film is broken and becomes defective in repeated writing and erasing. On the other hand, as a method for solving the reliability problem, the inventors made a proposal as disclosed in Patent Document 2. Fig. 79 shows an equivalent circuit of the nonvolatile semiconductor memory cell proposed in Patent Document 2. In one memory cell, two floating gate type electric crystals T312 and T3 13 are arranged side by side, and the gates and the control gates CG are connected in common. In this way, even if any one becomes bad, as long as the other transistor is good, it is normal as a cell. Further, the transistor T3 1 1 is a switch for selecting a memory cell. As described in the Patent Document 2, when the nonvolatile semiconductor memory cells are formed by using two nonvolatile semiconductor memory elements arranged in parallel, the reliability of the charge retention characteristics can be improved. However, since the non-volatile semiconductor memory device is disposed side by side, even if a complicated two-layer polysilicon process is used, it is difficult to arrange and the layout area becomes large. Therefore, since the degree of freedom in the case of using the one-layer polysilicon process is lowered, it is considered that the increase in the arrangement configuration becomes a larger problem. Further, in the technique of Patent Document 1, in the floating gate type non-volatile memory, in order to prevent electrons from escaping from the floating gate, a high-quality oxide film is required. In the formation of this high quality oxide film, a special process is required. However, in the standard CMOS process, as long as the transistor is not destroyed, the reliability of the oxide film is sufficient, because there is no problem in general quality, so the oxide film as a non-volatile memory is insufficient in quality and non-volatile. The reliability of the memory becomes a problem. In addition, in order to omit the -10-201010062 second-layer polysilicon used as the control gate, it is necessary to embed the control gate composed of the diffusion layer under the floating gate, so that the diffusion layer buried at a high concentration becomes oxidized. As a poor quality oxide film, the probability of occurrence of defects increases, and reliability is lowered, which is a problem. As described above, in the conventional EE PROM using one-layer polysilicon, if it is fabricated by a standard CMOS process, the charge retention of the floating gate is hindered by an oxide film having a lower quality than the oxide film used for the non-volatile semiconductor memory cell. The problem. Further, as shown in the above-mentioned Patent Document 2, since a plurality of memory elements are arranged in parallel, there is a problem that the arrangement area becomes large and it is difficult to arrange. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei. No. 2685966 (Patent Document 2) Patent No. 2685966 (Draft of the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a Non-volatile semiconductor memory devices and non-volatile semiconductor memory devices, and Q non-volatile semiconductor memory devices can realize non-volatile memory in a CMOS process with standard logic components, and can closely configure capacitors with large area (on floating) The gate and the capacitor formed on the surface of the semiconductor substrate) minimize the area. Moreover, it is an object of the present invention to provide a non-volatile semiconductor memory device and a non-volatile semiconductor memory device which can realize non-volatile memory in a CMOS process of standard logic components while using a 1-layer polysilicon. OTP, MTP (Multi Time Programmable ROM) 〇-11- 201010062 Further, it is an object of the invention to provide a non-volatile semiconductor memory device and a non-volatile semiconductor memory device in which a non-volatile semiconductor memory device can be closely arranged Larger capacitors (capacitors formed on the floating gate and the surface of the semiconductor substrate) minimize the area. Further, it is an object of the present invention to provide a nonvolatile semiconductor memory cell and a nonvolatile semiconductor memory device which can be manufactured by a one-layer polysilicon process while improving the reliability of the arrangement area. Further, it is an object of the present invention to provide a nonvolatile semiconductor memory device which realizes a semiconductor memory device of a 1-cell polysilicon structure which can be fabricated by a standard CMOS process, and which has a small assembly area by a high-efficiency configuration. And improve the reliability of memory retention. (Means for Solving the Problem) (1) The present invention has been conceived to solve the problem, and a nonvolatile semiconductor memory device according to one aspect of the present invention is a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor memory device. It is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process, and the non-volatile semiconductor memory Q element is configured to: float When the gate stores a charge, hot electrons are generated near the drain of the second transistor, and a charge is injected to the floating gate, or a 髙 voltage is applied to the floating blue, and the tunneling current is used by Fowler — Nordheim The floating gate injects a charge; and when a charge stored in the floating gate is erased, 'a high voltage is applied between the drain of the second transistor and the floating gate', and the tunneling current of the Fowler-Norway is released The electric charge stored in the floating gate; the arrangement as a constituent part of the non-volatile semiconductor memory element, in the upper and lower directions, the -12-201010062 1 on the semiconductor substrate In the case where the direction is the second direction orthogonal to the first direction, the rectangular crystal forming portion is disposed in the upper and lower portions in order to be in the order of the first transistor. The first In-type diffusion layer, the first gate region portion forming the channel of the first transistor, and the second n-type diffusion layer which is the source of the first transistor and also serves as the drain of the second transistor, forming the first a second gate region portion of the channel of the transistor and a third n-type diffusion layer serving as a source; and the first metal wiring is disposed on the left side or the right side of the transistor forming portion in parallel with the transistor forming portion Further, the semiconductor substrate is separated from the surface of the semiconductor substrate by a predetermined distance, and the contact is connected to the drain of the first transistor; the square polysilicon layer is formed in a portion in the left-right direction and a gate region of the first transistor. The portion is opposed to the gate of the first transistor; a square n-type well is formed on the semiconductor substrate, and is formed in a left-right direction with a predetermined width and depth on the left side of the transistor forming portion; Floating gate, tied around Arranging to face the surface of the semiconductor substrate while being disposed such that a region on the left end side thereof faces the surface of the n-type well, and a region on the right end side and the second Q gate region of the second transistor The opposite portion; the 扩散-type diffusion layer is adjacent to the left side of the region of the n-type well opposite to the floating gate, and is formed in the left-right direction with a predetermined width and depth, and serves as a gate wiring for controlling the gate. The connection terminal; the gate wiring is disposed so as to face the floating gate from the surface of the semiconductor substrate at a predetermined distance in the left-right direction, and is connected to the 扩散-type diffusion layer by the contact: and the second metal 靥 wiring The surface of the semiconductor substrate is disposed so as to face the third n-type diffusion layer which is the source of the second transistor in a horizontal direction with a predetermined distance therebetween, and is connected to the third n-type diffusion layer by a contact. Further, the nonvolatile semiconductor memory device according to one aspect of the present invention is a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor memory device, which is formed of a MOS structure formed on a semiconductor substrate. a transistor, and a second gate of a floating gate type, and configured by a standard CMOS process, the non-volatile semiconductor memory device being configured to: when storing charge on the floating gate, in the second transistor Producing hot electrons near the drain, and injecting a charge to the floating gate, or applying a high voltage to the floating gate, and injecting a charge to the floating gate using a tunneling current of Fowler-Norweg; and erasing the floating gate When the charge stored in the pole is high, a high voltage is applied between the 汲© pole and the floating horn of the second transistor, and the charge stored by the floating gate is released by the Fowler-Nordheim tunneling current; as the non-volatile The arrangement of the constituent parts of the semiconductor memory device indicates the first direction on the semiconductor substrate in the upper and lower directions, and the second direction orthogonal to the first direction in the left-right direction. A rectangular transistor forming portion is disposed in the vertical direction in order: an In-type diffusion layer that serves as a drain of the first transistor, and a first gate region that forms a channel of the first transistor. a second n-type diffusion layer which is a source of the first transistor and also serves as a drain of the second transistor, a second gate region in which the channel of the second transistor is formed, and a third diffusion type which serves as a source The first metal wiring is disposed on the left side or the right side of the transistor forming portion, and is disposed in parallel with the transistor forming portion, and is separated from the surface of the semiconductor substrate by a predetermined distance, and the contact point and the first transistor are simultaneously used. a drain-connected layer; a square polycrystalline germanium layer formed in a portion in the left-right direction and a gate region portion of the first transistor facing 'and becomes the smell of the first transistor; a depletion-type of a square shape The channel implantation is formed on the semiconductor substrate, and the left side of the transistor is formed on the left side of the -14-201010062, and is formed in a left-right direction with a predetermined width and depth: a square floating gate is disposed in the left-right direction and the semiconductor base The surface is opposed to each other, and the region on the left end side is opposed to the surface on which the channel is implanted, and the region on the right end side faces the second gate region of the second transistor; the fourth ri type diffusion layer, It is adjacent to the left side of the channel injection, and is formed in the left-right direction with a predetermined width and depth, and serves as a connection terminal for the control gate wiring: the control gate wiring is separated from the surface of the semiconductor substrate by a predetermined distance. Arranged in the left-right direction so as to face the floating gate drain, and connected to the fourth n-type diffusion layer by the contact; and the second metal wiring is arranged in the left-right direction from the surface of the semiconductor substrate via a predetermined distance The third n-type diffusion layer which is the source of the second transistor is opposed to each other, and is connected to the third n-type diffusion layer by a contact. (3) In the nonvolatile semiconductor memory device according to the aspect of the invention, when the charge is stored in the floating gate, the first high voltage is applied to the gate of the first transistor, and the drain is applied to the drain. a second voltage; a third voltage is applied to the control gate of the second transistor, and a voltage of 0 V is applied to the source; hot electrons are generated near the drain of the Q second transistor, and the floating gate is implanted Simultaneously, when the charge stored in the floating gate is erased, a fourth voltage is applied to the gate of the first transistor, and a fifth voltage is applied to the drain; and the control gate of the second transistor is applied. 0V, and the source is set to be open, or a sixth voltage smaller than the fourth voltage or the fifth voltage is applied; by applying a high electric field between the drain of the second transistor and the floating gate, The charge is discharged from the floating gate to the drain. (4) Further, in the nonvolatile semiconductor memory device according to the aspect of the present invention, when the charge is stored in the floating gate, the third voltage applied to the control gate of the -15-201010062 of the second transistor may be applied. Rise and apply in sections. (5) Further, the nonvolatile semiconductor device of one aspect of the present invention is a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor memory device, which is formed of a first transistor of a MOS structure formed on a semiconductor substrate. And a second gate of a floating gate type, and configured by a standard CMOS process, the non-volatile semiconductor memory device is configured to be near the drain of the second transistor when storing charge to the floating gate Generating hot electrons, and injecting a charge to the floating gate, or applying a high voltage to the floating gate, and injecting a charge into the floating gate using a tunneling current of Fowler-Norweg; and storing the floating gate a charge, a high voltage is applied between the drain of the second transistor and the floating gate, and the charge stored by the floating gate is discharged by the FN current; as an arrangement of the components of the non-volatile semiconductor memory element, A rectangular crystal forming portion is provided in a case where the first direction on the semiconductor substrate is indicated in the lower direction and the second direction is orthogonal to the first direction in the left-right direction. In this vertical direction, the first In-type diffusion layer that serves as the drain of the first transistor, the first gate region that forms the channel of the first transistor, and the source of the first transistor are also disposed. a second n-type diffusion layer that serves as a drain of the second transistor, a second gate region that forms a channel of the second transistor, and a third n-type diffusion layer that serves as a source; the first metal wiring is used for the electricity The left side or the right side of the crystal forming portion is disposed in parallel with the transistor forming portion and is separated from the surface of the semiconductor substrate by a predetermined distance, and is connected to the drain of the first transistor by a contact; the square polycrystalline layer is attached The left-right direction is formed so that a portion thereof faces the gate region portion of the first transistor, and serves as a gate of the first transistor; and a square-depleted channel is implanted on the semiconductor substrate, in the-16-201010062 The left side of the transistor forming portion is formed in the left-right direction with a predetermined width and depth; the square floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and is disposed at the left end side region and the pass The injected surface faces oppositely, and the region on the right end side faces the second gate region of the second transistor; the fourth n-type diffusion layer is adjacent to the left side of the channel injection, and has a predetermined width and The depth is formed in the left-right direction and serves as a connection terminal to the control gate wiring. The gate wiring is controlled so as to face the floating gate in a horizontal direction from a predetermined distance from the surface of the semiconductor substrate. The contact is connected to the 411th type diffusion layer; the second metal wiring is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the third n-type diffusion layer which is the source of the second transistor. At the same time, the contact is connected to the 3rd-type diffusion layer; and the sub-contact is used to be the side of the first metal wiring on the semiconductor substrate and to be the square of the gate of the first transistor. The position on the upper side of the polysilicon layer suppresses an increase in voltage of a region of the semiconductor substrate on which the memory cell is formed. Q (6) Further, the nonvolatile semiconductor memory device according to one aspect of the present invention is a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor memory device, which is formed of a first transistor of a MOS structure formed on a semiconductor substrate. And a second gate of a floating gate type, and configured by a standard CMOS process, the non-volatile semiconductor memory device is configured to be near the drain of the second transistor when storing charge to the floating gate Generating hot electrons, and injecting a charge to the floating gate, or applying a high voltage to the floating gate, and injecting a charge into the floating gate using a tunneling current of Fowler-Nordheim; and storing the floating gate by erasing the floating gate The charge of the second transistor 汲-17- 201010062
極和浮動閘極之間施加高電壓，而利用FN電流放出該浮 動閘極所儲存的電荷；作爲該非揮發性半導體記憶元件之 構成部分的布置，在以上下方向表示該半導體基板上的第 1方向，並以左右方向表示和該第1方向正交之第2方向 的情況，具備有：方形的電晶體形成部，係在該上下方向 依序配置：成爲該第1電晶體之汲極的第In型擴散層、形 成第1電晶體之通道的第1閘極區域部、是第1電晶體之 源極並亦成爲第2電晶體之汲極的第2n型擴散層、形成第 2電晶體之通道的第2閘極區域部、以及成爲源極的第3n 型擴散層；第1金屬配線，係在該電晶體形成部的左側或 右側，配置成和該電晶體形成部平行而且從半導體基板表 面隔著既定之距離，同時利用接點和該第1電晶體之汲極 連接；方形的多晶矽層，係在左右方向形成爲一部分和該 第1電晶體之閘極區域部相對向，並成爲該第1電晶體之 閘極；η型井，係在該半導體基板上，在該電晶體形成部 的左側，以既定之寬度和深度在左右方向所形成；方形的 浮動閘極，係在左右方向配置成和該半導體基板表面相對 向，同時配置成其左端部側的區域和該η型井的表面相對 向，而且右端部側的區域和該第2電晶體的該第2閘極區 域部相對向；Ρ型擴散層，係和該η型井之與該浮動閘極 相對向之區域的左側相鄰，並以既定之寬度和深度在左右 方向形成，同時成爲對控制閘極配線的連接端子；控制閘 極配線，係從該半導體基板表面隔著既定之距離在左右方 向配置成和該浮動閘極相對向，同時利用接點和該Ρ型擴 散層連接；第2金屬配線，係從該半導體基板表面隔著既 -18- 201010062 定之距離在左右方向配置成和成爲該第2電晶體之源極的 第3n型擴散層相對向，同時利用接點和該第3η型擴散層 連接；第7η型擴散層，係用以對該η型井供給所要之電位 的η型擴散層，並在該η型井的表面上，在該ρ型擴散層 的上側，而且該第In型擴散層之左側區域的既定位置，以 既定之寬度和深度形成；以及第3金屬配線，係配置成和 該電晶體形成部平行而且從半導體基板表面隔著既定之距 離，同時利用接點和該第7η型擴散層連接。 〇 (7)又，本發明之一形態的非揮發性半導體記憶元件，亦 可在對該浮動閘極儲存電荷時，對該第1電晶體的閘極施 加第1高電壓，並對汲極施加第2電壓；對該第2電晶體 的控制閘極施加第3電壓，並對源極施加0V的電壓；在該 第2電晶體的汲極附近產生熱電子，並對該浮動閘極注 入；同時在拭除該浮動閘極所儲存的電荷時，對該第1電 晶體的閘極施加第4電壓，並對該汲極施加第5電壓；對 該第2電晶體的控制閘極施加0V，並將源極設爲開路，或 Q 施加比該第4電壓或該第5電壓更小的第6電壓；藉由對 該第2電晶體的汲極和浮動閘極之間施加高電場，而使從 浮動閘極向汲極放出電荷。 (8) 又，本發明之一形態的非揮發性半導體記憶元件，亦 可在對該浮動閘極儲存電荷時，使施加於該第2電晶體之 控制閘極的第3電壓分段地上昇並施加。 (9) 又，本發明之一形態的非揮發性半導體記憶元件，亦 可將該第3金屬配線所施加的電壓設爲和該控制閘極的電 壓相等或更大。 -19- 201010062 (10)又，本發明之一形態的非揮發性半導體記憶元件，是 於半導體基板上以標準CMOS製程所構成之浮動閘極型的 1層多晶矽非揮發性記憶元件，在以上下方向表示該半導 體基板上的第1方向，並以左右方向表示和該第1方向正 交之第2方向的情況，具備有：方形的電晶體形成部，係 在該上下方向依序配置：成爲電晶體之汲極的第In型擴散 層、形成電晶體之通道的閘極區域部、以及成爲電晶體之 源極的第2n型擴散層；第1金屬配線，係在該電晶體形成 部的左側或右側，配置成和該電晶體形成部平行而且從半 β 導體基板表面隔著既定之距離，同時利用接點和該電晶體 之汲極連接；方形的η型井，係在該半導體基板上，在該 電晶體形成部的左側，以既定之寬度和深度在左右方向所 形成；方形的浮動閘極，係在左右方向配置成和該半導體 基板表面相對向，同時配置成其左端部側的區域和該η型 井的表面相對向，而且右端部側的區域和該閘極區域部相 對向；Ρ型擴散層，係和該η型井之與該浮動閘極相對向 之區域的左側相鄰，並以既定之寬度和深度在左右方向形 Q 成，同時成爲對控制閘極配線的連接端子；控制閘極配線， 係從該半導體基板表面隔著既定之距離在左右方向配置成 和該浮動閘極相對向，同時利用接點和該Ρ型擴散層連 接；以及第2金屬配線，係從該半導體基板表面隔著既定 之距離在左右方向配置成和該第2ri型擴散層相對向，同時 利用接點和該第2η型擴散層連接。 (1 1)又，本發明之一形態的非揮發性半導體記憶元件，是 於半導體基板上以標準CMOS製程所構成之浮動閘極型的 -20- 201010062 1層多晶矽非揮發性記憶元件，在以上下方向表示該半導 體基板上的第1方向，並以左右方向表示和該第1方向正 交之第2方向的情況，具備有：方形的電晶體形成部，係 在該上下方向依序配置：成爲電晶體之汲極的第In型擴散 層、形成電晶體之通道的閘極區域部、以及成爲電晶體之 源極的第2ri型擴散層；第1金屬配線，係在該電晶體形成 部的左側或右側，配置成和該電晶體形成部平行而且從半 導體基板表面隔著既定之距離，同時利用接點和該電晶體 〇之汲極連接；方形之空乏型通道注入，係在該半導體基板 上，在該電晶體形成部的左側，以既定之寬度和深度在左 右方向所形成；方形的浮動閘極，係在左右方向配置成和 該半導體基板表面相對向，同時配置成左端部側的區域和 該通道注入的表面相對向，而且右端部側的區域和該閘極 區域部相對向；第3n型擴散層，係和該通道注入的左側相 鄰，並以既定之寬度和深度在左右方向形成，同時成爲對 該控制閘極配線的連接端子：控制閘極配線，係從該半導 Q 體基板表面隔著既定之距離在左右方向配置成和該浮動閘 極相對向，同時利用接點和該第3ri型擴散層連接；以及第 2金屬配線，係從該半導體基板表面隔著既定之距離在左 右方向配置成和成爲該電晶體之源極的第2n型擴散層相 對向，同時利用接點和該第2η型擴散層連接。 (12)又，本發明之一形態的非揮發性半導體記憶元件，亦 可該非揮發性半導體記憶元件係以ΜΤΡ構成；在儲存該浮 動閘極所儲存之電荷時，對該電晶體的控制閘極施加第1 電壓，對汲極施加第2電壓，並對該源極施加0V的電壓； -21- 201010062 在該電晶體的汲極附近產生熱電子，並對該浮動閘極注入 該熱電子；同時在對該浮動閘極拭除電荷時，具備有：放 出部’係作爲第1拭除部，並對該電晶體的控制閘極施加 0V的電壓，對該汲極施加第3電壓，並將該源極設爲開路， 或施加比該第3電壓更小的第4電壓，藉由對汲極和浮動 閘極之間施加高電場，而利用Fowler - Nordheim的穿隧電 流放出該浮動閘極的電荷；及注入部，係作爲在該第1拭 除部執行後進行的第2拭除部，並對該電晶體的控制閘極 施加0V或比該第3電壓更小的第5電壓，對該汲極施加該 @ 第3電壓，並對該源極施加0V的電壓，在該電晶體的汲極 附近產生熱電子，並對該浮動閘極在既定時間內注入該熱 電子。 (13) 又，本發明之一形態的非揮發性半導體記憶元件，亦 可該非揮發性半導體記憶元件係以OTP構成，並構成爲： 在對該浮動閘極儲存電荷時，對該電晶體的控制閘極施加 第1電壓，對汲極施加第2電壓，並對該源極施加0V的電 壓；在該電晶體的汲極附近產生熱電子，並對該浮動閘極 Q 注入該熱電子。 (14) 又，本發明之一形態的非揮發性半導體記憶元件，是 於半導體基板上以標準CMOS製程所構成之浮動閘極型的 1層多晶矽非揮發性記憶元件，在以上下方向表示該半導 體基板上的第1方向，並以左右方向表示和該第1方向正 交之第2方向的情況，具備有：方形的電晶體形成部，係 在該上下方向依序配置：成爲電晶體之汲極的第In型擴散 層、形成電晶體之通道的閘極區域部、以及成爲電晶體之 -22- 201010062 源極的第2η型擴散層；第1金靥配線，係在該電晶體形成 部的左側或右側，配置成和該電晶體形成部平行而且從半 導體基板表面隔著既定之距離，同時利用接點和該電晶體 之汲極連接；η型井，係在該半導體基板上，在該電晶體 形成部的左側，以既定之寬度和深度在左右方向所形成； 方形的浮動閘極，係在左右方向配置成和該半導體基板表 面相對向，同時配置成其左端部側的區域和該η型井的表 面相對向，而且右端部側的區域和該閘極區域部相對向；ρ Ο 型擴散層，係和該η型井之與該浮動閘極相對向之區域的 左側相鄰，並以既定之寬度和深度在左右方向形成，同時 成爲對控制閘極配線的連接端子；控制閘極配線，係從該 半導體基板表面隔著既定之距離在左右方向配置成和該浮 動閘極相對向，同時利用接點和該Ρ型擴散層連接；第2 金屬配線，係從該半導體基板表面隔著既定之距離在左右 方向配置成和該第2η型擴散層相對向，同時利用接點和該 第2η型擴散層連接；第4η型擴散層，係用以對該η型井 Q 供給所要之電位的η型擴散層，在該η型井的表面上，在 該Ρ型擴散層的上側，而且該第In型擴散層之左側區域的 既定位置，以既定之寬度和深度形成；以及第3金屬配線， 係配置成和該電晶體形成部平行而且從半導體基板表面隔 著既定之距離，同時利用接點和該第4n型擴散層連接。 (15)又，本發明之一形態的非揮發性半導體記憶元件，亦 可該非揮發性半導體記憶元件係以OTP構成，並構成爲： 在對該浮動閘極儲存電荷時，對該電晶體的控制閘極施加 第1電壓，對汲極施加第2電壓，並對該源極施加0V的電 -23- 201010062 壓；在該電晶體的汲極附近產生熱電子，並對該浮動閘極 注入該熱電子。 (1 6)又，本發明之一形態的非揮發性半導體記憶元件，亦 可該非揮發性半導體記憶元件係以MTP構成；在儲存該浮 動閘極所儲存之電荷時，對該電晶體的控制閘極施加第1 電壓，對汲極施加第2電壓，並對該源極施加0V的電壓； 在該電晶體的汲極附近產生熱電子，並對該浮動閘極注入 該熱電子；同時在對該浮動閘極拭除電荷時，具備有：放 出部，係作爲第1拭除部，並對該電晶體的控制閘極施加 ® 〇V的電壓，對該汲極施加第3電壓，並將該源極設爲開路， 或施加比該第3電壓更小的第4電壓，藉由對汲極和浮動 閘極之間施加高電場，而利用Fowler— Nordheim的穿險電 流放出該浮動閘極的電荷；及注入部，係作爲在該第1拭 除部執行後進行的第2拭除部，並對該電晶體的控制閘極 施加0V或比該第3電壓更小的第5電壓，對該汲極施加該 第3電壓，並對該源極施加0V，在該電晶體的汲極附近產 生熱電子，並對該浮動閘極在既定時間內注入該熱電子。 〇 (17) 又，本發明之一形態的非揮發性半導體記憶元件，亦 可將施加於該第3金屬配線的電壓設定成和該控制閘極的 電壓相等或更大。 (18) 又，本發明之一形態的非揮發性半導體記憶胞元，其 由形成於半導體基板上之複數個MOS電晶體所構成，並具 有用以選擇該記憶胞元的選擇閘極、和用以控制記憶內容 的控制閘極，該非揮發性半導體記憶胞元具有：複數個浮 動閘極型電晶體，係由共用的該控制閘極控制，同時彼此 -24- 201010062 並列地連接；及選擇電晶體，係和該複數個浮動閘極型電 晶體串列地連接，並和該選擇閘極連接；該複數個浮動閘 極型電晶體和該選擇電晶體是在該半導體基板上直線狀地 排列，而該複數個浮動閘極型電晶體的各汲極是由直線狀 的金屬配線所連接。 (19)又，本發明之一形態的非揮發性半導體記憶胞元，亦 可在該控制閘極和複數個該浮動閘極型電晶體的各浮動閘 極之間所形成的複數個電容器是使用同一 η型井所形成。 ❹ (2 0)又，本發明之一形態的非揮發性半導體記憶胞元，亦 可在該控制閘極和複數個該浮動閘極型電晶體的各浮動閘 極之間所形成的複數個電容器是使用同一 η型擴散層所形 成。 (21)又，本發明之一形態的非揮發性半導體記憶胞元，其 由以和在半導體基板上形成邏輯電路之CMOS電晶體一樣 的製程所構成之MOS電晶體所構成，該非揮發性半導體記 憶胞元具有：選擇電晶體，係將汲極和該第1端子連接， Q 而閘極被施加選擇信號；及並列地設置之複數個記憶元 件，係浮動閘極型的1層多晶矽電晶體，汲極和該選擇電 晶體的源極連接，而源極和第2端子連接；在對·該複數個 記憶元件寫入資料的情況，根據該選擇信號，而使該選擇 電晶體變成導通（〇n)，並對該第1端子施加第1電壓，對 該第2端子施加比第1電壓低的電壓而進行寫入；在對該 複數個記憶元件拭除資料的情況，根據該選擇信號，而使 該選擇電晶體變成導通，對該第1端子施加比該第1電壓 高的電壓’並將該第2端子設爲開路，或根據該選擇信號， -25- 201010062 而使該選擇電晶體變成不導通（off)，並對該第2端子施加 比該第1電壓高的電壓而進行拭除。A high voltage is applied between the pole and the floating gate, and the charge stored in the floating gate is discharged by the FN current; and the arrangement as a constituent part of the non-volatile semiconductor memory element indicates the first on the semiconductor substrate in the upper and lower directions. In the case of indicating the second direction orthogonal to the first direction in the left-right direction, the rectangular transistor-forming portion is disposed in the vertical direction in order to become the drain of the first transistor. The first in-type diffusion layer, the first gate region portion forming the channel of the first transistor, the second n-type diffusion layer which is the source of the first transistor and also the drain of the second transistor, and the second electrode a second gate region of the channel of the crystal and a third n-type diffusion layer serving as a source; and the first metal wiring is disposed on the left side or the right side of the transistor forming portion in parallel with the transistor forming portion and The surface of the semiconductor substrate is connected to the drain of the first transistor by a predetermined distance; the square polysilicon layer is formed in a part of the left-right direction and faces the gate region of the first transistor. And forming the gate of the first transistor; the n-type well is formed on the semiconductor substrate on the left side of the transistor forming portion in a predetermined width and depth in the left-right direction; the square floating gate is Arranged to face the surface of the semiconductor substrate in the left-right direction while being disposed such that the region on the left end side thereof faces the surface of the n-type well, and the region on the right end side and the second gate of the second transistor The zonal diffusion layer is adjacent to the left side of the n-type well opposite to the floating gate, and is formed in the left-right direction with a predetermined width and depth, and serves as a control gate wiring. a connection terminal; the control gate wiring is disposed in a horizontal direction from the surface of the semiconductor substrate so as to face the floating gate at a predetermined distance, and is connected to the 扩散-type diffusion layer by a contact; the second metal wiring is The surface of the semiconductor substrate is disposed in a horizontal direction at a distance of from -18 to 201010062 so as to face the third n-type diffusion layer serving as a source of the second transistor, and the contact point and the third portion are used. An n-type diffusion layer is connected to the n-type diffusion layer for supplying the n-type well with a desired potential, and on the surface of the n-type well, on the upper side of the p-type diffusion layer, and The predetermined position of the left side region of the first In-type diffusion layer is formed with a predetermined width and depth, and the third metal wiring is disposed in parallel with the transistor forming portion and is separated from the surface of the semiconductor substrate by a predetermined distance. The junction is connected to the 7th n-type diffusion layer. Further, the non-volatile semiconductor memory device according to one aspect of the present invention may apply a first high voltage to the gate of the first transistor and store the drain when the charge is stored in the floating gate. Applying a second voltage, applying a third voltage to the control gate of the second transistor, applying a voltage of 0 V to the source, generating hot electrons near the drain of the second transistor, and injecting the floating gate Simultaneously, when the charge stored in the floating gate is erased, a fourth voltage is applied to the gate of the first transistor, and a fifth voltage is applied to the drain; and the control gate of the second transistor is applied. 0V, and the source is set to open circuit, or Q applies a sixth voltage smaller than the fourth voltage or the fifth voltage; by applying a high electric field between the drain of the second transistor and the floating gate , so that the charge is discharged from the floating gate to the drain. (8) Further, in the nonvolatile semiconductor memory device according to the aspect of the present invention, when the charge is stored in the floating gate, the third voltage applied to the control gate of the second transistor may be stepwisely increased. And applied. (9) Further, in the nonvolatile semiconductor memory device according to the aspect of the invention, the voltage applied to the third metal wiring may be equal to or greater than the voltage of the control gate. -19- 201010062 (10) Further, the non-volatile semiconductor memory device according to one aspect of the present invention is a floating gate type 1-layer polysilicon non-volatile memory device formed by a standard CMOS process on a semiconductor substrate, The lower direction indicates the first direction on the semiconductor substrate, and the second direction orthogonal to the first direction is indicated in the left-right direction. The rectangular transistor-forming portion is disposed in the vertical direction. a first in-type diffusion layer that becomes a drain of the transistor, a gate region portion that forms a channel of the transistor, and a second n-type diffusion layer that serves as a source of the transistor; and the first metal wiring is formed in the transistor formation portion The left side or the right side is disposed in parallel with the transistor forming portion and is separated from the surface of the semi-β conductor substrate by a predetermined distance, and is simultaneously connected by a junction and a drain of the transistor; a square n-type well is attached to the semiconductor The substrate is formed on the left side of the transistor forming portion in a left-right direction with a predetermined width and depth; the square floating gate is disposed in the left-right direction and the surface of the semiconductor substrate In the opposite direction, the area on the left end side thereof is opposite to the surface of the n-type well, and the area on the right end side and the gate area are opposite; the 扩散 type diffusion layer is the same as the n type well The floating gate is adjacent to the left side of the region, and is formed in the left and right direction by a predetermined width and depth, and serves as a connection terminal for controlling the gate wiring; and the control gate wiring is separated from the surface of the semiconductor substrate. The predetermined distance is disposed in the left-right direction so as to face the floating gate, and is connected to the 扩散-type diffusion layer by the contact; and the second metal wiring is disposed in the left-right direction from the surface of the semiconductor substrate with a predetermined distance therebetween. The second RI type diffusion layer is opposed to the second ri type diffusion layer, and is connected to the second n type diffusion layer by a contact. (1) Further, the non-volatile semiconductor memory device according to one aspect of the present invention is a floating gate type -20-201010062 1-layer polycrystalline germanium non-volatile memory element which is formed on a semiconductor substrate by a standard CMOS process. The lower direction indicates the first direction on the semiconductor substrate, and the second direction orthogonal to the first direction is indicated in the left-right direction. The rectangular transistor-forming portion is provided in the vertical direction. : a first In-type diffusion layer that becomes a drain of a transistor, a gate region portion that forms a channel of the transistor, and a second ri-type diffusion layer that serves as a source of the transistor; and the first metal wiring is formed in the transistor The left side or the right side of the portion is disposed in parallel with the transistor forming portion and is separated from the surface of the semiconductor substrate by a predetermined distance, and is simultaneously connected by a contact and a drain of the transistor ;; The semiconductor substrate is formed on the left side of the transistor forming portion in a left-right direction with a predetermined width and depth; the square floating gate is disposed in the left-right direction and the semiconductor The surface of the substrate is opposed to each other, and the region on the left end side is opposite to the surface on which the channel is implanted, and the region on the right end side and the gate region are opposed to each other; the third n-type diffusion layer is coupled to the left side of the channel. Adjacent to each other, it is formed in the left-right direction with a predetermined width and depth, and serves as a connection terminal for the control gate wiring: the gate wiring is arranged in the left-right direction from the surface of the semi-conductive Q-substrate via a predetermined distance. And the floating gate is opposed to each other, and the contact is connected to the third ri type diffusion layer; and the second metal wiring is disposed in the left-right direction from the surface of the semiconductor substrate via a predetermined distance and becomes the transistor. The second n-type diffusion layer of the source is opposed to each other, and is connected to the second n-type diffusion layer by a contact. (12) Further, in the non-volatile semiconductor memory device of one aspect of the present invention, the non-volatile semiconductor memory device may be formed of germanium; and when the charge stored in the floating gate is stored, the gate of the transistor is controlled. Applying a first voltage to the pole, applying a second voltage to the drain, and applying a voltage of 0 V to the source; -21- 201010062 generating hot electrons near the drain of the transistor, and injecting the hot electron to the floating gate At the same time, when the charge is erased to the floating gate, the discharge portion is provided as a first erase portion, and a voltage of 0 V is applied to the control gate of the transistor, and a third voltage is applied to the drain. And setting the source to an open circuit or applying a fourth voltage smaller than the third voltage, and applying a high electric field between the drain and the floating gate, and using Fowler-Norway's tunneling current to discharge the floating The electric charge of the gate; and the injection portion is a second wiping portion that is performed after the first wiping portion is executed, and applies 0 V to the control gate of the transistor or 5th smaller than the third voltage. Voltage, the @3 voltage is applied to the drain, and Applying a voltage of 0V electrode, hot electrons generated in the vicinity of the drain of the transistor, and the electrode injecting hot electrons to the floating gate within a predetermined time. (13) In the nonvolatile semiconductor memory device according to the aspect of the invention, the nonvolatile semiconductor memory device may be configured by an OTP, and configured to: when storing a charge on the floating gate, the transistor The control gate applies a first voltage, applies a second voltage to the drain, applies a voltage of 0 V to the source, generates hot electrons near the drain of the transistor, and injects the hot electrons into the floating gate Q. (14) Further, the nonvolatile semiconductor memory device according to one aspect of the present invention is a floating gate type one-layer polycrystalline germanium nonvolatile memory device which is formed by a standard CMOS process on a semiconductor substrate, and is expressed in the upper and lower directions. In the first direction on the semiconductor substrate, the second direction orthogonal to the first direction is indicated in the left-right direction, and the rectangular transistor-forming portion is disposed in the vertical direction in order to form a transistor. a first In-type diffusion layer of a drain, a gate region portion forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the -22-201010062 of the transistor; the first metal wiring is formed in the transistor The left side or the right side of the portion is disposed in parallel with the transistor forming portion and is separated from the surface of the semiconductor substrate by a predetermined distance, and is connected to the drain of the transistor by a contact; the n-type well is mounted on the semiconductor substrate. a left side of the transistor forming portion is formed in a left-right direction with a predetermined width and depth; and a square floating gate is disposed to face the surface of the semiconductor substrate in the left-right direction. At the same time, the region on the left end side thereof is opposite to the surface of the n-type well, and the region on the right end side and the gate region portion are opposite each other; the p Ο type diffusion layer is associated with the floating of the n-type well The gate is adjacent to the left side of the region, and is formed in the left-right direction with a predetermined width and depth, and serves as a connection terminal for controlling the gate wiring; the gate wiring is controlled from the surface of the semiconductor substrate by a predetermined distance Arranged to face the floating gate in the left-right direction and connected to the 扩散-type diffusion layer by a contact; the second metal wiring is disposed in the left-right direction from the surface of the semiconductor substrate at a predetermined distance and the second η The diffusion layer is opposed to each other and is connected to the second n-type diffusion layer by a contact; the fourth n-type diffusion layer is used to supply the n-type diffusion layer to the n-type well Q at the desired potential, in the n-type well a surface on the upper side of the 扩散-type diffusion layer, and a predetermined position of a left side region of the first In-type diffusion layer is formed with a predetermined width and depth; and a third metal wiring is disposed in the transistor shape And the parallel portion separated a predetermined distance from the semiconductor substrate surface, while using the second contacts and the connection type diffusion layer 4n. (15) Further, in the nonvolatile semiconductor memory device according to one aspect of the present invention, the nonvolatile semiconductor memory device may be configured by an OTP, and configured to: when storing a charge on the floating gate, the transistor The control gate applies a first voltage, applies a second voltage to the drain, and applies a voltage of 0 V to the source -23-201010062; generates hot electrons near the drain of the transistor, and injects the floating gate The hot electron. (16) Further, in the non-volatile semiconductor memory device according to one aspect of the present invention, the non-volatile semiconductor memory device may be composed of MTP; and the control of the transistor may be performed when storing the charge stored in the floating gate. Applying a first voltage to the gate, applying a second voltage to the drain, and applying a voltage of 0 V to the source; generating hot electrons near the drain of the transistor, and injecting the hot electron into the floating gate; When the floating gate is erased, the discharge portion is provided as a first erasing portion, and a voltage of 〇V is applied to the control gate of the transistor, and a third voltage is applied to the drain. The source is set to be open, or a fourth voltage smaller than the third voltage is applied, and a high electric field is applied between the drain and the floating gate, and the floating gate is discharged by Fowler-Norwey's through-current. The electric charge of the pole; and the injection portion is a second wiping portion that is performed after the first wiping portion is executed, and applies a voltage of 0 V or a fifth voltage smaller than the third voltage to the control gate of the transistor. Applying the third voltage to the drain and applying 0V to the source The drain of the transistor generating hot electrons in the vicinity, and the floating gate is injected into the hot electrons within a predetermined time. Further, in the nonvolatile semiconductor memory device according to the aspect of the invention, the voltage applied to the third metal wiring may be set to be equal to or greater than the voltage of the control gate. (18) Further, the nonvolatile semiconductor memory cell according to one aspect of the present invention comprises a plurality of MOS transistors formed on a semiconductor substrate, and has a selection gate for selecting the memory cell, and a control gate for controlling the memory content, the non-volatile semiconductor memory cell having: a plurality of floating gate type transistors controlled by a common control gate and simultaneously connected to each other at -24-201010062; and selecting a transistor connected in series with the plurality of floating gate type transistors and connected to the selection gate; the plurality of floating gate type transistors and the selection transistor being linearly on the semiconductor substrate Arranged, and the respective drains of the plurality of floating gate type transistors are connected by linear metal wiring. (19) Further, in the nonvolatile semiconductor memory cell of one aspect of the present invention, a plurality of capacitors formed between the control gate and the plurality of floating gates of the plurality of floating gate transistors are Formed using the same n-type well. ❹ (20) Further, the non-volatile semiconductor memory cell of one aspect of the present invention may also form a plurality of non-volatile semiconductor memory cells between the control gate and a plurality of floating gates of the plurality of floating gate transistors. The capacitor is formed using the same n-type diffusion layer. (21) Further, a nonvolatile semiconductor memory cell according to an aspect of the present invention is constituted by a MOS transistor formed by a process similar to a CMOS transistor in which a logic circuit is formed on a semiconductor substrate, the nonvolatile semiconductor The memory cell has: a transistor selected to connect the drain terminal to the first terminal, Q and a gate to which a selection signal is applied; and a plurality of memory elements arranged in parallel, a floating gate type 1-layer polysilicon transistor The drain is connected to the source of the selected transistor, and the source is connected to the second terminal. When the data is written to the plurality of memory elements, the selected transistor is turned on according to the selection signal ( 〇n), applying a first voltage to the first terminal, applying a voltage lower than the first voltage to the second terminal, and writing the data to the second terminal; and selecting the signal according to the selection signal And the selection transistor is turned on, and a voltage higher than the first voltage is applied to the first terminal, and the second terminal is opened, or the selection signal is -25-201010062. crystal The body is turned off, and a voltage higher than the first voltage is applied to the second terminal to be erased.
(2 2)又，本發明之一形態的非揮發性半導體記憶胞元，亦 可在對該複數個記憶元件寫入資料的情況，和在該複數個 記憶元件的汲極和源極之間流動的通道電流同時產生係屬 具有高能量之電子的熱電子，並對該記憶元件的浮動閘極 注入所產生之熱電子；在對該複數個記憶元件拭除資料的 情況，和在該複數個記憶元件的汲極或源極、與該半導體 基板之間流動的頻帶•頻帶間電流同時產生係屬具有高能 量之電洞的熱電洞，並對該記憶元件的浮動閘極注入所產 生之熱電洞。(2) Further, the non-volatile semiconductor memory cell of one aspect of the present invention may also be in the case of writing data to the plurality of memory elements, and between the drain and the source of the plurality of memory elements. The flowing channel current simultaneously generates hot electrons belonging to electrons having high energy, and injects the generated hot electrons into the floating gate of the memory element; in the case of erasing the data for the plurality of memory elements, and in the plural The drain or source of the memory element, the band-to-band current flowing between the semiconductor substrate, and the thermoelectric hole of the high-energy hole are simultaneously generated, and the floating gate of the memory element is injected. Thermal hole.
(23)又，本發明之一形態的非揮發性半導體記憶胞元，亦 可該複數個記憶元件由第1記憶元件和第2記憶元件所構 成；並具備有：電晶體形成部，係向第1方向依序串列地 配置：形成該選擇電晶體之汲極的第In型擴散層、形成該 選擇電晶體之閘極的第1多晶矽、形成該選擇電晶體之源 極及該第1記憶元件之汲極的第2ri型擴散層、形成該第1 記憶元件之浮動閘極的第2多晶矽、形成該第1記憶元件 之源極及該第2記憶元件之源極的第3n型擴散層、形成該 第2記憶元件之浮動閘極的第3多晶矽、以及形成該第2 記憶元件之汲極的第4ιι型擴散層；第1金屬配線，係經由 接點而和該第In型擴散層連接，並配置在對該第1方向垂 直的方向；第2金屬配線，係經由接點而和各個該第2n型 擴散層及該第4η型擴散層連接，並配置在和該第1方向相 同的方向；以及第3金屬配線，係經由接點而和該第3η型 -26- 201010062 擴散層連接，並配置在對該第1方向垂直的方向。 (24)又，本發明之一形態的非揮發性半導體記憶胞元，亦 可該複數個記憶元件由第1記憶元件、第2記憶元件以及 第3記憶元件所構成；並具備有：電晶體形成部，係向第 1方向依序串列地配置：形成該選擇電晶體之汲極的第In 型擴散層、形成該選擇電晶體之閘極的第1多晶矽、形成 該選擇電晶體之源極及該第1記憶元件之汲極的第2n型擴 散層、形成該第1記憶元件之浮動閘極的第2多晶矽、形 Ο 成該第1記憶元件之源極及該第2記憶元件之源極的第3η 型擴散層、形成該第2記憶元件之浮動閘極的第3多晶矽、 形成該第2記憶元件之汲極及該第3記憶元件之汲極的第 4η型擴散層、形成該第3記憶元件之浮動閘極的第4多晶 矽、以及形成該第3記憶元件之源極的第5η型擴散層；第 1金屬配線，係經由接點而和該第In型擴散層連接，並配 置在對該第1方向垂直的方向；第2金屬配線，係經由接 點而和各個該第2η型擴散層及該第4n型擴散層連接，並 〇 配置在和該第1方向相同的方向；第3金屬配線，係經由 接點而和該第3η型擴散層連接，並配置在對該第1方向垂 直的方向；以及第4金屬配線，係經由接點而和該第5η型 擴散層連接，並配置在對該第1方向垂直的方向。 (2 5)又，本發明之—形態的非揮發性半導體記憶裝置’其 在字元線和資料線之交點將係屬浮動閘極型之1層多晶矽 非揮發性半導體記憶元件的各個記憶胞元排列成陣列狀而 構成，而該記憶胞元由形成於半導體基板上之MOS構造的 第1電晶體、和浮動閘極型之第2電晶體所構成，並以標 -27- 201010062 準CMOS製程構成，該記憶胞元構成爲：在對該浮動閘極 儲存電荷時，在該第2電晶體的汲極附近產生熱電子，並 對該浮動閘極注入電荷，或對該浮動閘極施加高電壓，而 利用Fowler- Nordheim的穿隧電流對該浮動閘極注入電 荷；及在拭除該浮動閘極所儲存的電荷時，對該第2電晶 體的汲極和浮動閘極之間施加高電壓，而利用該Fowler-Nordheim的穿隧電流放出該浮動閘極所儲存的電荷；該非 揮發性半導體記憶裝置配置成由將該記憶胞元在各列之行 方向按照1位元組或字元單位等之既定位元數的行單位進 © 行行選擇的記憶胞元方塊所構成；同時具備有：複數條位 元線，係沿著列方向共同連接各該記憶胞元之第1電晶體 的汲極；選擇閘極配線，是在各該記憶胞元方塊所設置之 選擇閘極配線，並沿著行方向共同連接記億胞元之係屬第 1電晶體之閘極的選擇閘極；控制閘極配線，是在各該記 憶胞元方塊所設置之控制閘極配線，並沿著行方向共同連 接記億胞元之係靥第2電晶體之閘極的控制閘極；源極 線，是在行方向按照該行單位所選擇之各行選擇範圍內所 © 設置的源極線，並共同連接該行選擇範圍內之所有的列之 各記憶胞元之第2電晶體的源極；列解碼器，係接受位址 信號，並輸出選擇該記憶胞元的列選擇信號；第1位準挪 移電路（first level shift circuit)，係將從該列解碼器所輸 出之信號變換成施加於該選擇閘極的第1電壓信號；第2 位準挪移電路，係將從該列解碼器所輸出之信號變換成施 加於該控制閘極的第2電壓信號；行解碼器，係接受位址 信號，並輸出按照該行單位選擇該記憶胞元的行選擇信 -28- 201010062 號；第3位準挪移電路，係將從該行解碼器所輸出之行選 擇信號變換成第3電壓信號；選擇電路，是配置於各該記 憶胞元方塊，同時對所選擇之記憶胞元方塊內的電晶體施 加閘極電壓的選擇電路，並具有：第1傳輸閘極電晶體 (transfer gate transistor)，係將從該第3位準挪移電路所 輸出之行選擇信號作爲閘極輸入，並向選擇閘極傳輸第1 位準挪移電路的輸出信號；及第2傳輸閘極電晶體，係將 從該第3位準挪移電路所輸出之行選擇信號作爲閘極輸 ❹ 入，並向控制閘極傳輸該第2位準挪移電路的輸出信號； 行選擇電晶體，係將從該第3位準挪移電路所輸出之行選 擇信號作爲閘極輸入，並選擇該行單位之記憶胞元的位元 線；該行單位之位元數的資料輸出入線，係經由該行選擇 電晶體而和由該行選擇電晶體所選擇之該行單位的位元線 連接；資料輸入變換電路，係在接受該行單位的位元數之 寫入資料的輸入信號並進行資料的寫入及資料的拭除時， 輸出透過該資料輸出入線而施加於該第1電晶體之汲極的 〇 第4電壓信號；以及感測放大電路，係將該資料輸出入線 所讀出之記憶胞元的資料放大並向外部輸出。 (2 6)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線之交點將係饜浮動閘極型之1層多晶矽 非揮發性半導體記憶元件的各個記憶胞元排列成陣列狀而 構成，而該記憶胞元由形成於半導體基板上之M0S構造的 第1電晶體、和浮動閘極型之第2電晶體所構成，並以標 準CMOS製程構成，該記憶胞元構成爲：在對該浮動閘極 儲存電荷時，在該第2電晶體的汲極附近產生熱電子，並 -29- 201010062 對該浮動閘極注入電荷，或對該浮動閘極施加高電壓，而 利用Fowler - Nordheim的穿險電流對該浮動閘極注入電 荷；及在拭除該浮動閘極所儲存的電荷時，對該第2電晶 體的汲極和浮動閘極之間施加高電壓，而利用該Fowler-Nordheim的穿隧電流放出該浮動閘極所儲存的電荷；該非 揮發性半導體記憶裝置配置成由將該記憶胞元在各列之行 方向按照1位元組或字元單位等之既定位元數的行單位進 行行選擇的記憶胞元方塊所構成；同時具備有：複數條位 元線，係沿著列方向共同連接各該記憶胞元之第1電晶體 © 的汲極；選擇閘極配線，係沿著行方向共同連接各該記憶 胞元之係屬第1電晶體之閘極的選擇閘極；控制閘極配 線，是在各該記憶胞元方塊所設置之控制閘極配線，並沿 著行方向共同連接記憶胞元之係屬第2電晶體之閘極的控 制閘極；源極線，是在行方向按照該行單位所選擇之各行 選擇範圍內所設置的源極線，並共同連接該行選擇範圍內 之所有的列之各記憶胞元之第2電晶體的源極；列解碼 器，係接受位址信號，並輸出選擇該記憶胞元的列選擇信 © 號；第1位準挪移電路，係將從該列解碼器所輸出之信號 變換成施加於該選擇閘極的第1電壓信號；第2位準挪移 電路，係將從該列解碼器所輸出之信號變換成施加於該控 制閘極的第2電壓信號；行解碼器，係接受位址信號，並 輸出按照該行單位選擇該記憶胞元的行選擇信號；第3位 準挪移電路，.係將從該行解碼器所輸出之行選擇信號變換 成第3電壓信號；選擇電路，是配置於各該記憶胞元方塊， 同時對所選擇之記憶胞元方塊內的電晶體施加閘極電壓的 -30- 201010062 選擇電路，並具有傳輸閘極電晶體，其將從該第3位準挪 移電路所輸出之行選擇信號作爲閛極輸入，並向控制閘極 傳輸該第2位準挪移電路的輸出信號；行選擇電晶體，係 將從該第3位準挪移電路所輸出之行選擇信號作爲閘極輸 入，並選擇該行單位之位元數之記憶胞元的位元線；行單 位之位元數的資料輸出入線，係經由該行選擇電晶體而和 由該行選擇電晶體所選擇之該行單位的位元線連接；資料 輸入變換電路，係在接受該行單位的位元數之寫入資料的 〇 輸入信號並進行資料的寫入及資料的拭除時，輸出透過該 資料輸出入線而施加於該第1電晶體之汲極的第4電壓信 號；以及感測放大電路，係將該資料輸出入線所讀出之記 憶胞元的資料放大並向外部輸出。 (2 7)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線之交點將係屬浮動閘極型之1層多晶矽 非揮發性半導體記憶元件的各個記憶胞元排列成陣列狀而 構成，而該記憶胞元由形成於半導體基板上之MOS構造的 Q 第1電晶體、和浮動閘極型之第2電晶體所構成，並以標 準CMOS製程構成，該記憶胞元構成爲：在對該浮動閘極 儲存電荷時，在該第2電晶體的汲極附近產生熱電子，並 對該浮動閘極注入電荷，或對該浮動閘極施加高電壓，而 利用Fowler—Nordheim的穿隧電流對該浮動閘極注入電 荷；及在拭除該浮動閘極所儲存的電荷時，對該第2電晶 體的汲極和浮動閘極之間施加高電壓，而利用該Fowler-Nordheim的穿隧電流放出該浮動閘極所儲存的電荷；該非 揮發性半導體記憶裝置配置成由將該記憶胞元在各列之行 -31- 201010062 方向按照1位元組或字元單位等之既定位元數的行單位進 行行選擇的記憶胞元方塊所構成；同時具備有：複數條位 元線，係沿著列方向共同連接各該記憶胞元之第1電晶體 的汲極；選擇閘極配線，係沿著行方向共同連接各該記憶 胞元之係屬第1電晶體之閘極的選擇閘極；控制閘極配 線，是在各該記憶胞元方塊所設置之控制閘極配線，並沿 著行方向共同連接記憶胞元之係屬第2電晶體之閘極的控 制閘極；源極線，是在行方向按照該行單位所選擇之各行 選擇範圍內所設置的源極線，並共同連接該行選擇範圍內 © 之所有的列之各記憶胞元之第2電晶體的源極；列解碼 器，係接受位址信號，並輸出選擇該記憶胞元的列選擇信 號；第1位準挪移電路，係將從該列解碼器所輸出之信號 變換成施加於該選擇閘極的第1電壓信號；行解碼器，係 接受位址信號，並輸出按照該行單位選擇該記憶胞元的行 選擇信號；第3位準挪移電路，係將從該行解碼器所輸出 之選擇信號變換成第3電壓；第2位準挪移電路，係將從 該行解碼器所輸出之行選擇信號變換成第2電壓的信號； 選擇電路，是配置於各該記憶胞元方塊，同時對所選擇之 記憶胞元方塊內的電晶體施加閘極電壓的選擇電路，並具 有傳輸閘極電晶體，其將從該第2位準挪移電路所輸出之 行選擇信號作爲閘極輸入，並向控制閘極傳輸該第1位準 挪移電路的輸出信號；行選擇電晶體，係將從該第3位準 挪移電路所輸出之行選擇信號作爲閘極輸入，並選擇該行 單位之位元數之記憶胞元的位元線；該行單位之位元數的 資料輸出入線，係經由該行選擇電晶體而和由該行選擇電 -32- 201010062 晶體所選擇之行單位的位元線連接；資料輸入變換電路， 係在接受該行單位的位元數之寫入資料的輸入信號並進行 資料的寫入及資料的拭除時，輸出透過該資料輸出入線而 施加於該第1電晶體之汲極的第4電壓信號；以及感測放 大電路，係將該資料輸出入線所讀出之記憶胞元的資料放 大並向外部輸出。 (2 8)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線之交點將係屬浮動閘極型之1層多晶矽 〇非揮發性半導體記憶元件的各個記憶胞元排列成陣列狀而 構成，而該記憶胞元由形成於半導體基板上之MOS構造的 第1電晶體、和浮動閘極型之第2電晶體所構成，並以標 準CMOS製程構成，該記憶胞元構成爲：在對該浮動閘極 儲存電荷時，在該第2電晶體的汲極附近產生熱電子，並 對該浮動閘極注入電荷，或對該浮動閘極施加高電壓，而 利用 Fowler- Nordheim的穿隧電流對該浮動閘極注入電 荷；及在拭除該浮動閘極所儲存的電荷時，對該第2電晶 Q 體的汲極和浮動閘極之間施加高電壓，而利用該Fowler-Nordheim的穿隧電流放出該浮動閘極所儲存的電荷；該非 揮發性半導體記憶裝置配置成由將該記憶胞元在各列之行 方向按照1位元組或字元單位等之既定位元數的行單位進 行行選擇的記憶胞元方塊所構成；同時具備有：複數條位 元線，係沿著列方向共同連接各該記憶胞元之第1電晶體 的汲極；選擇閘極配線，係沿著行方向共同連接各該記憶 胞元之係屬第1電晶體之閘極的選擇閘極；控制閘極配 線，是在各該記憶胞元方塊所設置之控制閘極配線，並沿 -33- 201010062 著行方向共同連接記憶胞元之係屬第2電晶體之閘極的控 制閘極；源極線，是在行方向按照該行單位所選擇之各行 選擇範圍內所設置的源極線，並共同連接該行選擇範圍內 之所有的列之各記憶胞元之第2電晶體的源極；列解碼 器，係接受位址信號，並輸出選擇該記憶胞元的列選擇信 號；第1位準挪移電路，係將從該列解碼器所輸出之信號 變換成施加於該選擇閘極的第1電壓信號；行解碼器，係 接受位址信號，並輸出按照該行單位選擇該記憶胞元的行 選擇信號：第2位準挪移電路，係將從該行解碼器所輸出 © 之選擇信號變換成施加於該行選擇電晶體之閘極的第2電 壓；第3位準挪移電路，係將從該行解碼器所輸出之行選 擇信號變換成第3電壓信號；選擇電路，是配置於各該記 憶胞元方塊，同時對所選擇之記億胞元方塊內的電晶體施 加閘極電壓的選擇電路，並具有反相器，其將從該第2位 準挪移電路所輸出之信號作爲電源電壓，將該第1位準挪 移電路的輸出信號作爲輸入信號，並向控制閘極輸出輸出 信號；行選擇電晶體，係將從該第3位準挪移電路所輸出 Q 之行選擇信號作爲閘極輸入，並選擇該行單位之記憶胞元 的位元線；該行單位之位元數的資料輸出入線，係經由該 行選擇電晶體而和由該行選擇電晶體所選擇之該行單位的 位元線連接；資料輸入變換電路，係在接受該行單位的位 元數之寫入資料的輸入信號並進行資料的寫入及資料的拭 除時，輸出透過該資料輸出入線而施加於該第1電晶體之 汲極的第4電壓信號；以及感測放大電路，係將該資料輸 出入線所讀出之記憶胞元的資料放大並向外部輸出。 -34- 201010062 (2 9)又’本發明之一形態的非揮發性半導體記憶裝置，其 將係屬浮動閘極型之1層多晶矽非揮發性半導體記憶元件 的記憶胞元排列成陣列狀而構成，而該記憶胞元由形成於 半導體基板上之MOS構造的第1電晶體、和浮動閘極型之 第2電晶體所構成，並以標準CMOS製程構成，作爲該記 憶胞元之構成部分的布置，在以上下方向表示該半導體基 板上的第1方向，並以左右方向表示和該第1方向正交之 第2方向的情況，具備有：方形的電晶體形成部，係在該 Ο 上下方向依序配置：成爲該第1電晶體之汲極的第In型擴 散層、形成第1電晶體之通道的第1閘極區域部、是第1 電晶體之源極並亦成爲第2電晶體之汲極的第2n型擴散 層、形成第2電晶體之通道的第2閘極區域部、以及成爲 源極的第3n型擴散層·.第1金屬配線，係在該電晶體形成 部的左側或右側，配置成和該電晶體形成部平行而且從半 導體基板表面隔著既定之距離，同時利用接點和該第1電 晶體之汲極連接；方形的多晶矽層，係在左右方向形成爲 〇 —部分和該第1電晶體之閘極區域部相對向，並成爲該第 1電晶體之閘極；方形的η型井，係在該半導體基板上， 在該電晶體形成部的左側，以既定之寬度和深度在左右方 向所形成；方形的浮動閘極，係在左右方向配置成和該半 導體基板表面相對向，同時配置成其左端部側的區域和該 η型井的表面相對向，而且右端部側的區域和該第2電晶 體的該第2閘極區域部相對向；ρ型擴散層，係和該η型 井之與該浮動閘極相對向之區域的左側相鄰，並以既定之 寬度和深度在左右方向形成，同時成爲對控制閘極配線的 -35- 201010062(23) In the non-volatile semiconductor memory cell according to the aspect of the invention, the plurality of memory elements may be composed of the first memory element and the second memory element, and the transistor forming portion may be provided The first direction is arranged in series: an In-type diffusion layer forming a drain of the selected transistor, a first polysilicon forming a gate of the selected transistor, a source forming the selected transistor, and the first a second ri diffusion layer that is a drain of the memory element, a second polysilicon that forms a floating gate of the first memory element, and a third n-type diffusion that forms a source of the first memory element and a source of the second memory element a layer, a third polysilicon forming a floating gate of the second memory element, and a fourth iv type diffusion layer forming a drain of the second memory element; the first metal wiring is diffused via the contact and the first In type The layers are connected and arranged in a direction perpendicular to the first direction; the second metal wiring is connected to each of the second n-type diffusion layer and the fourth n-type diffusion layer via a contact, and is disposed in the first direction The same direction; and the third metal wiring, The second contacts and the diffusion layer -26-201010062 3η type connector, and arranged in a direction perpendicular to the first direction. (24) Further, in the nonvolatile semiconductor memory cell according to the aspect of the invention, the plurality of memory elements may be composed of the first memory element, the second memory element, and the third memory element; and the transistor is provided with: a transistor The forming portion is arranged in series in the first direction: an In-type diffusion layer forming a drain of the selected transistor, a first polysilicon forming a gate of the selective transistor, and a source forming the selective transistor And a second n-type diffusion layer of the first and second memory elements a third n-type diffusion layer of a source, a third polysilicon forming a floating gate of the second memory element, a fourth n-type diffusion layer forming a drain of the second memory element, and a drain of the third memory element, forming a fourth polysilicon of the floating gate of the third memory element and a fifth n-type diffusion layer forming a source of the third memory element; and the first metal wiring is connected to the first in-type diffusion layer via a contact; And arranged in the direction perpendicular to the first direction; the second gold The wiring is connected to each of the second n-type diffusion layer and the fourth n-type diffusion layer via a contact, and is disposed in the same direction as the first direction; the third metal wiring is connected via the contact The third n-type diffusion layer is connected and arranged in a direction perpendicular to the first direction; and the fourth metal wiring is connected to the fifth n-type diffusion layer via a contact, and is disposed in a direction perpendicular to the first direction . (2) Further, the non-volatile semiconductor memory device of the present invention has a memory cell of a floating gate type one-layer polycrystalline non-volatile semiconductor memory device at the intersection of the word line and the data line. The cells are arranged in an array, and the memory cells are composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and are labeled -27-201010062 quasi-CMOS In the process configuration, the memory cell is configured to generate hot electrons near the drain of the second transistor when the charge is stored on the floating gate, and inject a charge to the floating gate or apply the floating gate High voltage, using Fowler-Norway's tunneling current to inject charge into the floating gate; and when erasing the charge stored in the floating gate, applying between the drain of the second transistor and the floating gate High voltage, and the Fowler-Nordheim tunneling current is used to discharge the charge stored by the floating gate; the non-volatile semiconductor memory device is configured to follow the 1-bit or word of the memory cell in the direction of each column Unit And the row unit of the positioning element is formed by the memory cell block selected by the row row; and has a plurality of bit line lines connected to the first transistor of each of the memory cells along the column direction. Selecting the gate wiring is a selection gate wiring provided in each of the memory cell blocks, and is connected in the row direction to the selection gate of the gate of the first transistor belonging to the cell; The control gate wiring is a control gate wiring provided in each memory cell block, and is connected to the control gate of the gate of the second transistor in the row direction in the row direction; the source line Is a source line set in the row direction according to the row selection range selected by the row unit, and is commonly connected to the source of the second transistor of each memory cell of all the columns in the row selection range; The column decoder receives the address signal and outputs a column selection signal for selecting the memory cell; the first level shift circuit converts the signal output from the column decoder to be applied to The first voltage signal of the selected gate The second level shifting circuit converts the signal output from the column decoder into a second voltage signal applied to the control gate; the row decoder receives the address signal and outputs the line according to the row unit. The row selection signal of the memory cell is -28-201010062; the third bit quasi-migration circuit converts the row selection signal outputted from the row decoder into a third voltage signal; the selection circuit is disposed in each of the memories a cell block, at the same time, a selection circuit for applying a gate voltage to the transistor in the selected memory cell block, and having: a first transfer gate transistor, which is to be shifted from the third bit The row selection signal outputted by the circuit is used as a gate input, and the output signal of the first level shifting circuit is transmitted to the selection gate; and the second transmission gate transistor is output from the third level shifting circuit The row selection signal is used as the gate input, and the output signal of the second level shifting circuit is transmitted to the control gate; the row selection transistor is used as the gate selection signal outputted from the third level shifting circuit. Inputting and selecting a bit line of the memory cell of the row unit; the data output line of the row unit is selected by the row to select the transistor and the row unit selected by the row to select the transistor The bit line connection; the data input conversion circuit is configured to receive the input signal of the data input in the row unit of the row and write the data and erase the data, and the output is applied to the data through the data input and output line. The fourth voltage signal of the drain of the first transistor; and the sense amplifier circuit amplifies the data of the memory cell read out from the data input line and outputs it to the outside. (2) Further, in a nonvolatile semiconductor memory device according to an aspect of the present invention, at the intersection of a word line and a data line, each memory cell of a floating gate type one-layer polycrystalline non-volatile semiconductor memory element is used. The cells are arranged in an array, and the memory cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process. The cell is configured to generate hot electrons near the drain of the second transistor when the charge is stored on the floating gate, and to inject charge to the floating gate or apply high to the floating gate -29-201010062 Voltage, which is injected into the floating gate using Fowler-Norway's safe current; and high voltage between the drain and the floating gate of the second transistor when the charge stored in the floating gate is erased Voltage, and the Fowler-Nordheim tunneling current is used to discharge the charge stored by the floating gate; the non-volatile semiconductor memory device is configured to follow the 1-bit or character of the memory cell in the direction of each column single And a memory cell block that performs row selection by arranging the row units of the number of elements; and has a plurality of bit lines, which are connected to the first transistor of each of the memory cells in the column direction. The gate wiring is connected to the selection gate of the gate of the first transistor which is connected to each memory cell in the row direction; the control gate wiring is set in each memory cell block. Controlling the gate wiring, and connecting the control gates of the gates of the second transistor belonging to the memory cells in the row direction; the source lines are selected in the row direction according to the row selected by the row unit a source line that is connected to the source of the second transistor of each memory cell of all columns in the row selection range; the column decoder accepts the address signal and outputs the selected memory cell Column selection signal ©; the first bit quasi-migration circuit converts the signal output from the column decoder into a first voltage signal applied to the selection gate; the second level shift circuit is from the column The signal output by the decoder is transformed into a a second voltage signal of the control gate; the row decoder receives the address signal, and outputs a row selection signal for selecting the memory cell according to the row unit; the third bit shifting circuit, the system will be from the row The row selection signal outputted by the decoder is converted into a third voltage signal; the selection circuit is disposed in each of the memory cell blocks, and simultaneously applies a gate voltage to the transistor in the selected memory cell block -30- 201010062 Selecting a circuit and having a transmission gate transistor that uses a row selection signal output from the third level shifting circuit as a drain input and transmits an output signal of the second level shifting circuit to the control gate; Selecting a transistor is a row selection signal outputted from the third level shifting circuit as a gate input, and selecting a bit line of the memory cell of the row unit number of the row unit; The data input and output line is connected to the bit line of the row unit selected by the row selection transistor through the row selection transistor; the data input conversion circuit is configured to accept the number of bits of the row unit. When the input signal of the material is input and the data is erased, the fourth voltage signal applied to the drain of the first transistor through the data input and output line is output; and the sense amplifier circuit is The data of the memory cell read out from the data input line is amplified and output to the outside. (2) Further, a nonvolatile semiconductor memory device according to an aspect of the present invention, which is a memory cell of a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor memory element at an intersection of a word line and a data line The cells are arranged in an array, and the memory cell is composed of a Q first crystal having a MOS structure formed on a semiconductor substrate and a second transistor having a floating gate type, and is configured by a standard CMOS process. The memory cell is configured to generate hot electrons near the drain of the second transistor when the charge is stored on the floating gate, and to inject a charge to the floating gate or apply a high voltage to the floating gate. Applying a charge to the floating gate using a tunneling current of Fowler-Nordheim; and applying a high voltage between the drain of the second transistor and the floating gate when erasing the charge stored by the floating gate Using the Fowler-Nordheim tunneling current to discharge the charge stored by the floating gate; the non-volatile semiconductor memory device is configured to follow the 1-bit or word of the memory cell in the direction of each column -31-201010062 Yuan A memory cell block that performs row selection by a row unit that locates a number of elements, and a plurality of bit lines that are connected to the first transistor of each memory cell along the column direction. The gate wiring is connected to the selection gate of the gate of the first transistor which is connected to each memory cell in the row direction; the control gate wiring is set in each memory cell block. Controlling the gate wiring, and connecting the control gates of the gates of the second transistor belonging to the memory cells in the row direction; the source lines are selected in the row direction according to the row selected by the row unit a source line is provided, and is connected to the source of the second transistor of each memory cell of all the columns in the row selection range; the column decoder accepts the address signal and outputs the selected memory cell The column selection signal; the first level shifting circuit converts the signal output from the column decoder into a first voltage signal applied to the selection gate; the row decoder receives the address signal and outputs the signal according to The line unit selects the memory The row selection signal of the cell; the third bit shifting circuit converts the selection signal outputted from the row decoder into a third voltage; and the second level shifting circuit is a line output from the row decoder The selection signal is converted into a signal of the second voltage; the selection circuit is a selection circuit disposed in each of the memory cell blocks and applying a gate voltage to the transistor in the selected memory cell block, and has a transmission gate electrode a crystal, which uses a row selection signal output from the second level shifting circuit as a gate input, and transmits an output signal of the first level shifting circuit to the control gate; The row selection signal output by the 3-bit quasi-migration circuit is used as the gate input, and the bit line of the memory cell of the row unit number of the row unit is selected; the data output line of the row unit number of the row unit is via the row Selecting the transistor and connecting with the bit line of the row unit selected by the row selected by the line - 32- 201010062 crystal; the data input conversion circuit is input signal inputting the data of the number of bits in the row unit When data is written and data is erased, a fourth voltage signal applied to the drain of the first transistor through the data input and output line is output; and a sense amplifier circuit is outputted from the data input line. The data of the memory cell is amplified and output to the outside. (2) Further, a nonvolatile semiconductor memory device according to one aspect of the present invention, which is a memory of a floating gate type one-layer polycrystalline germanium non-volatile semiconductor memory element at an intersection of a word line and a data line The cells are arranged in an array, and the memory cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process. The memory cell is configured to generate hot electrons near the drain of the second transistor when the charge is stored on the floating gate, and to inject a charge to the floating gate or apply a high voltage to the floating gate. Applying a charge to the floating gate using a tunneling current of Fowler-Norway; and applying a high voltage between the drain of the second transistor Q and the floating gate when erasing the charge stored in the floating gate And using the Fowler-Nordheim tunneling current to discharge the charge stored by the floating gate; the non-volatile semiconductor memory device is configured to be in the order of 1 byte or character by the memory cell in the direction of each column Wait for The row unit of the positioning element is composed of a memory cell block for performing row selection; and at the same time, there are: a plurality of bit lines, which are connected to the drain of the first transistor of each memory cell along the column direction; The pole wiring is connected to the selection gates of the gates of the first transistor in the memory cell in the row direction; the control gate wiring is the control gate wiring provided in each memory cell block. And along the -33- 201010062 direction of the line connecting the memory cell is the control gate of the gate of the second transistor; the source line is in the row direction according to the row selected by the row unit a source line that is connected to the source of the second transistor of each memory cell of all columns in the row selection range; the column decoder accepts the address signal and outputs the selected memory cell a column selection signal; the first bit shifting circuit converts a signal output from the column decoder into a first voltage signal applied to the selection gate; and the row decoder receives the address signal and outputs the signal according to the Row unit selects the memory Cell row selection signal: the second bit quasi-migration circuit converts the selection signal outputted from the row decoder into a second voltage applied to the gate of the row selection transistor; the third bit shift circuit Converting the row selection signal outputted from the row decoder into a third voltage signal; the selection circuit is disposed in each of the memory cell blocks, and simultaneously applies a gate to the selected transistor in the cell a pole voltage selection circuit having an inverter that uses a signal output from the second level shifting circuit as a power supply voltage, and uses an output signal of the first level shifting circuit as an input signal to the control gate Output output signal; row selection transistor, the row selection signal outputted from the third level shifting circuit is used as the gate input, and the bit line of the memory cell of the row unit is selected; The data output of the element is input to the line via the row, and is connected to the bit line of the row unit selected by the row selection transistor; the data input conversion circuit is in the number of bits accepting the row unit When an input signal of the data is written, data is written, and data is erased, a fourth voltage signal applied to the drain of the first transistor through the data input and output line is output; and the sense amplifier circuit is The data of the memory cell read out by the data input and output line is amplified and output to the outside. -34- 201010062 (2 9) A non-volatile semiconductor memory device according to one aspect of the present invention, wherein memory cells of a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor memory device are arranged in an array The memory cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process as a component of the memory cell. In the case where the first direction on the semiconductor substrate is indicated in the upper and lower directions, and the second direction orthogonal to the first direction is indicated in the left-right direction, a rectangular transistor forming portion is provided. Arranged in the vertical direction: the first In-type diffusion layer that is the drain of the first transistor, the first gate region that forms the channel of the first transistor, and the source of the first transistor are also the second The second n-type diffusion layer of the drain of the transistor, the second gate region portion forming the channel of the second transistor, and the third n-type diffusion layer serving as the source are formed in the transistor. Left or right side of the department, configured as and The transistor forming portions are parallel and are separated from the surface of the semiconductor substrate by a predetermined distance, and are connected to the drain of the first transistor by a contact; the square polycrystalline layer is formed in the left-right direction as a 〇-portion and the first electric The gate region of the crystal faces oppositely and becomes the gate of the first transistor; the square n-type well is on the semiconductor substrate, and has a predetermined width and depth on the left side of the transistor forming portion. The direction is formed; the square floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and is disposed such that a region on the left end side thereof faces the surface of the n-type well, and a region on the right end side and The second gate region of the second transistor is opposed to each other; the p-type diffusion layer is adjacent to a left side of a region of the n-type well facing the floating gate, and has a predetermined width and depth Formed in the left and right direction, and at the same time becomes the control gate wiring -35- 201010062
連接端子；控制閘極配線，係從該半導體基板表面隔著既 定之距離在左右方向配置成和該浮動閘極相對向，同時利 用接點和該p型擴散層連接；以及第2金屬配線，係從該 半導體基板表面隔著既定之距離在左右方向配置成和成爲 該第2電晶體之源極的第3n型擴散層相對向，同時利用接 點和該第3n型擴散層連接；同時在各該記憶胞元的配置， 將彼此共用該η型井並左右對稱地配置之2個記憶胞元； 及對該左右對稱地配置之2個記憶胞元，彼此共用該第2 金屬配線並在下方向對稱地配置之2個記憶胞元之合計4 個記憶胞元作爲配置的基本單位；在左右方向平行地排列 配置，同時在上下方向亦平行地排列配置成爲該配置之基 本單位的4個記憶胞元。a connection terminal; the control gate wiring is disposed in a horizontal direction from the surface of the semiconductor substrate so as to face the floating gate at a predetermined distance, and is connected to the p-type diffusion layer by a contact; and the second metal wiring; The surface of the semiconductor substrate is disposed in a horizontal direction with respect to a third n-type diffusion layer serving as a source of the second transistor, and is connected to the third n-type diffusion layer by a contact; Arrangement of the memory cells, the two memory cells in which the n-type wells are shared and symmetrically arranged; and the two memory cells arranged symmetrically to the left and right share the second metal wiring and Four memory cells of the two memory cells arranged symmetrically are the basic units of the arrangement; they are arranged in parallel in the left-right direction, and four memories which are the basic units of the arrangement are arranged in parallel in the vertical direction. Cell.
(30)又，本發明之一形態的非揮發性半導體記憶裝置，其 將係靥浮動閘極型之1層多晶矽非揮發性半導體記憶元件 的記憶胞元排列成陣列狀而構成，而該記憶胞元由形成於 半導體基板上之MOS構造的第1電晶體、和浮動閘極型之 第2電晶體所構成，並以標準CMOS製程構成，作爲該記 憶胞元之構成部分的布置，在以上下方向表示該半導體基 板上的第1方向，並以左右方向表示和該第1方向正交之 第2方向的情況，具備有：方形的電晶體形成部，係在該 上下方向依序配置：成爲該第1電晶體之汲極的第In型擴 散層、形成第1電晶體之通道的第1閘極區域部、是第1 電晶體之源極並亦成爲第2電晶體之汲極的第2n型擴散 層、形成第2電晶體之通道的第2閘極區域部、以及成爲 源極的第3n型擴散層；第1金屬配線’係在該電晶體形成 -36- 201010062 部的左側或右側，配置成和該電晶體形成部平行而且從半 導體基板表面隔著既定之距離，同時利用接點和該第1電 晶體之汲極連接：方形的多晶矽層，係在左右方向形成爲 一部分和該第1電晶體之閘極區域部相對向，並成爲該第 1電晶體之閘極；方形之空乏型通道注入，係在該半導體 基板上，在該電晶體形成部的左側，以既定之寬度和深度 在左右方向所形成；方形的浮動閘極，係在左右方向配置 成和該半導體基板表面相對向，同時配置成左端部側的區 〇域和該通道注入的表面相對向，而且右端部側的區域和該 第2電晶體的該第2閘極區域部相對向；第4η型擴散層， 係和該通道注入的左側相鄰，並以既定之寬度和深度在左 右方向形成，同時成爲對該控制閘極配線的連接端子；控 制閘極配線，係從該半導體基板表面隔著既定之距離在左 右方向配置成和該浮動閘極相對向，同時利用接點和該第 4η型擴散層連接；以及第2金屬配線，係從該半導體基板 表面隔著既定之距離在左右方向配置成和成爲該第2電晶 Q 體之源極的第3η型擴散層相對向，同時利用接點和該第 3η型擴散層連接；同時在各該記憶胞元的配置，將彼此共 用成爲對該控制閘極配線之連接端子的第4η型擴散層並 左右對稱地配置之2個記憶胞元、及對該左右對稱地配置 之2個記憶胞元，彼此共用該第2金屬配線並在下方向對 稱地配置之2個記憶胞元之合計4個記憶胞元作爲配置的 基本單位；在上下方向平行地排列配置，同時在上下方向 亦平行地排列配置成爲該配置之基本單位的4個記憶胞 元。 -37- 201010062 (31)又，本發明之一形態的非揮發性半導體記憶裝置，其 將係屬浮動閘極型之1層多晶矽非揮發性半導體記億元件 的記憶胞元排列成陣列狀而構成，而該記憶胞元由形成於 半導體基板上之MOS構造的第1電晶體、和浮動閘極型之 第2電晶體所構成，並以標準CMOS製程構成，作爲該記 憶胞元之構成部分的布置，在以上下方向表示該半導體基 板上的第1方向，並以左右方向表示和該第1方向正交之 第2方向的情況，具備有：方形的電晶體形成部，係在該 上下方向依序配置：成爲該第1電晶體之汲極的第In型擴 © 散層、形成第1電晶體之通道的第1閘極區域部、是第1 電晶體之源極並亦成爲第2電晶體之汲極的第2η型擴散 層、形成第2電晶體之通道的第2閘極區域部、以及成爲 源極的第3η型擴散層；第1金屬配線，係在該電晶體形成 部的左側或右側，配置成和該電晶體形成部平行而且從半 導體基板表面隔著既定之距離，同時利用接點和該第1電 晶體之汲極連接；方形的多晶矽層，係在左右方向形成爲 一部分和該第1電晶體之閘極區域部相對向，並成爲該第 © 1電晶體之閘極；方形之第1及第2空乏型通道注入，係 在該半導體基板上，在該電晶體形成部的左側及右側，以 既定之寬度和深度在左右方向所形成；方形的浮動閘極， 係在左右方向配置成和該半導體基板表面相對向，同時配 置成其左端部側的區域和該第1通道注入的表面相對向， 而且其中央部分的區域和成爲該第2電晶體之汲極的該第 2η型擴散層相對向，右端部側的區域和該第2通道注入的 表面相對向；第5η型擴散層，係和該第1通道注入的左側 -38- 201010062 相鄰，以既定之寬度和深度在左右方向所形成，並成爲控 制閘極；第6n型擴散層，係和該第2通道注入的右側相鄰， 以既定之寬度和深度在左右方向所形成，並成爲控制閘 極；控制閘極配線，是從該半導體基板表面隔著既定之距 離在左右方向配置成和該浮動閘極相對向，同時連接用以 對浮動閘極賦與電位之控制閘極的控制閘極配線，並一部 分和該浮動閘極相對向，同時利用接點和該第1及第2n型 擴散層連接；以及第2金屬配線，係從該半導體基板表面 〇 隔著既定之距離在左右方向配置成和成爲該第2電晶體之 源極的第3ri型擴散層相對向，同時利用接點和該第3η型 擴散層連接；同時在各該記憶胞元的配置，在左右方向將 記憶胞元排列成彼此共用成爲該控制閘極的第5及第6η型 擴散層；同時對該在左右方向所排列的記憶胞元，共用該 第2金屬配線，並在下方向對稱地排列記憶胞元。 (32)又，本發明之一形態的非揮發性半導體記憶裝置，其 將係屬浮動閘極型之1層多晶矽非揮發性半導體記憶元件 Q 的記憶胞元排列成陣列狀而構成，而該記憶胞元由形成於 半導體基板上之MOS構造的第1電晶體、和浮動閘極型之 第2電晶體所構成，並以標準CMOS製程構成，作爲該記 憶胞元之構成部分的布置，在以上下方向表示該半導體基 板上的第1方向，並以左右方向表示和該第1方向正交之 第2方向的情況，具備有：方形的電晶體形成部，係在該 上下方向依序配置：成爲該第1電晶體之汲極的第In型擴 散層、形成第1電晶體之通道的第1閘極區域部、是第1 電晶體之源極並亦成爲第2電晶體之汲極的第2n型擴散 -39- 201010062 層、形成第2電晶體之通道的第2閘極區域部、以及成爲 源極的第3η型擴散層；第1金屬配線，係在該電晶體形成 部的左側或右側，配置成和該電晶體形成部平行而且從半 導體基板表面隔著既定之距離，同時利用接點和該第1電 晶體之汲極連接；方形的多晶矽層，係在左右方向形成爲 一部分和該第1電晶體之閘極區域部相對向，並成爲該第 1電晶體之閘極；方形之第1及第2空乏型通道注入，係 . 在該半導體基板上，在該電晶體形成部的左側及右側，以 既定之寬度和深度在左右方向所形成；方形的浮動閘極， ❹ 係在左右方向配置成和該半導體基板表面相對向，同時配 置成其左端部側的區域和該第1通道注入的表面相對向， 而且其中央部分的區域和該第2電晶體的該第2閘極區域 相對向，右端部側的區域和該第2通道注入的表面相對 向；第5η型擴散層，係和該第1通道注入的左側相鄰，以 既定之寬度和深度在左右方向所形成，並成爲控制閘極； 第6η型擴散層，係和該第2通道注入的右側相鄰，以既定 之寬度和深度在左右方向所形成，並成爲控制閘極；控制 © 閘極配線，是從該半導體基板表面隔著既定之距離在左右 方向配置成和該浮動閘極相對向，同時連接用以對浮動閘 極賦與電位之控制閘極的控制閘極配線，一部分和該浮動 閘極相對向，同時利用接點和該第1及第2型擴散層連接； 第2金饜配線，係從該半導體基板表面隔著既定之距離在 左右方向配置成和成爲該第2電晶體之源極的第3η型擴散 層相對向，同時利用接點和該第3η型擴散層連接；以及副 接點，係用以在是該半導體基板上之該第1金屬配線的側 -40- 201010062 方，而且成爲該第1電晶體的閘極之方形的多晶政層之上 側的位置，抑制形成該記憶胞元之半導體基板的區域之電 壓的上昇；同時在各該記憶胞元的配置，在左右方向將記 憶胞元排列成彼此共用成爲該控制閘極的第5及第6ri型擴 散層；同時對該在左右方向所排列的2個記憶胞元，共用 該第2金屬配線，並在下方向對稱地排列記憶胞元。 (3 3)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將係屬浮動閘極型之1層多晶砂 〇 非揮發性半導體記憶元件的各個記憶胞元排列成陣列狀而 構成，而該記憶胞元由形成於半導體基板上之MOS構造的 第1電晶體、和浮動閘極型之第2電晶體所構成，並以標 準CMOS製程構成，該記憶胞元構成爲：在對該浮動閘極 儲存電荷時，在該第2電晶體的汲極附近產生熱電子，並 對該浮動閘極注入電荷，或對該浮動閘極施加高電壓，而 利用Fowler— Nordheim的穿隧電流對該浮動閘極注入電 荷；及在拭除該浮動閘極所儲存的電荷時，對該第2電晶 Q 體的汲極和浮動閘極之間施加高電壓，而利用該Fowler-Nordheim的穿隧電流放出該浮動閘極所儲存的電荷；該非 揮發性半導體記憶裝置配置成由將該記憶胞元在各列之行 方向按照1位元組或字元單位等之既定位元數的行單位進 行行選擇的記憶胞元方塊所構成；同時具備有：複數條位 元線，係沿著列方向共同連接各記憶胞元之第1電晶體的 汲極：複數條選擇閘極配線，係沿著行方向共同連接各記 憶胞元之係屣第1電晶體之閘極的選擇閘極；複數條控制 閘極配線，係沿著行方向共同連接各記憶胞元之係屬第2 -41- 201010062(30) A nonvolatile semiconductor memory device according to one aspect of the present invention, wherein the memory cells of the one-layer polysilicon nonvolatile semiconductor memory device of the floating gate type are arranged in an array, and the memory is configured The cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process, and is arranged as a component of the memory cell. The lower direction indicates the first direction on the semiconductor substrate, and the second direction orthogonal to the first direction is indicated in the left-right direction. The rectangular transistor-forming portion is disposed in the vertical direction. The first In-type diffusion layer that serves as the drain of the first transistor, and the first gate region that forms the channel of the first transistor are the source of the first transistor and also serve as the drain of the second transistor. a second n-type diffusion layer, a second gate region portion forming a channel of the second transistor, and a third n-type diffusion layer serving as a source; the first metal wiring ′ is formed on the left side of the transistor-36-201010062 portion Or right, configured to and The crystal forming portions are parallel and are separated from the surface of the semiconductor substrate by a predetermined distance, and are connected to the drain of the first transistor by a contact: a square polycrystalline germanium layer is formed in a portion in the left-right direction and a gate of the first transistor. The pole region portion faces the gate of the first transistor; the square void channel is implanted on the semiconductor substrate, and the left side of the transistor is formed with a predetermined width and depth in the left and right direction. Formed; a square floating gate disposed in the left-right direction so as to face the surface of the semiconductor substrate, and configured to face the region on the left end side and the surface to be injected in the channel, and the region on the right end side and the first portion The second gate region of the second transistor is opposed to each other; the fourth n-type diffusion layer is adjacent to the left side of the channel injection, and is formed in the left-right direction with a predetermined width and depth, and serves as the control gate wiring. The connection terminal; the control gate wiring is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the floating gate at a predetermined distance; The contact is connected to the fourth n-type diffusion layer; and the second metal interconnection is arranged in the left-right direction from the surface of the semiconductor substrate at a predetermined distance and is a third n-type diffusion which is a source of the second electro-crystal Q body. The layers are opposed to each other, and are connected to the third n-type diffusion layer by a contact; and at the same time, the arrangement of the memory cells is shared by the fourth n-type diffusion layer of the connection terminal of the control gate wiring and symmetrically left and right. Two memory cells arranged, and two memory cells arranged symmetrically to the left and right, and a total of four memory cells in which the second metal wirings are shared with each other and symmetrically arranged in the lower direction are arranged The basic unit is arranged in parallel in the vertical direction, and four memory cells which are the basic units of the arrangement are arranged in parallel in the vertical direction. Further, in a nonvolatile semiconductor memory device according to one aspect of the present invention, memory cells of a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor device are arranged in an array. The memory cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process as a component of the memory cell. In the case where the first direction on the semiconductor substrate is indicated in the lower direction, and the second direction orthogonal to the first direction is indicated in the left-right direction, a rectangular transistor forming portion is provided. The direction is sequentially arranged: the first In-type diffusion layer which is the drain of the first transistor, the first gate region which forms the channel of the first transistor, and the source of the first transistor a second n-type diffusion layer having a drain of the transistor, a second gate region forming a channel of the second transistor, and a third n-type diffusion layer serving as a source; and the first metal wiring is formed in the transistor Left or right side of the department, configured as and The transistor forming portion is parallel and connected to the surface of the semiconductor substrate by a predetermined distance, and is connected to the drain of the first transistor by a contact; the square polycrystalline layer is formed in a portion in the left-right direction and the first transistor. The gate region is opposed to each other and serves as a gate of the first transistor; the first and second recessed channels of the square are implanted on the semiconductor substrate on the left and right sides of the transistor forming portion. The predetermined width and depth are formed in the left-right direction; the square floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and the region on the left end side thereof is opposite to the surface to be implanted in the first channel And the region of the central portion and the second n-type diffusion layer which is the drain of the second transistor face each other, and the region on the right end side faces the surface on which the second channel is implanted; and the fifth n-type diffusion layer It is adjacent to the left side -38-201010062 of the first channel injection, and is formed in the left and right direction with a predetermined width and depth, and becomes a control gate; a 6n-type diffusion layer, and the second pass The right side of the channel injection is adjacent to each other, and is formed in the left-right direction with a predetermined width and depth, and becomes a control gate; the gate wiring is controlled from the surface of the semiconductor substrate in a left-right direction with a predetermined distance and the floating gate a control gate line for connecting a control gate of the floating gate to the potential gate, and a portion of the gate gate opposite to the floating gate, and connecting the first and second n-type diffusion layers by using the contact point And the second metal wiring is disposed so as to face the third ri type diffusion layer which is a source of the second transistor from the surface of the semiconductor substrate with a predetermined distance therebetween, and the contact point and the first 3η-type diffusion layer connection; at the same time, in the arrangement of the memory cells, the memory cells are arranged in the left-right direction to be the 5th and 6th n-type diffusion layers which are the control gates; and are arranged in the left-right direction The memory cells share the second metal wiring and align the memory cells symmetrically in the lower direction. (32) A nonvolatile semiconductor memory device according to one aspect of the present invention, wherein the memory cells of the floating gate type one-layer polysilicon nonvolatile semiconductor memory device Q are arranged in an array, and the memory cell The memory cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process, and is arranged as a component of the memory cell. The lower direction indicates the first direction on the semiconductor substrate, and the second direction orthogonal to the first direction is indicated in the left-right direction. The rectangular transistor-forming portion is provided in the vertical direction. The first In-type diffusion layer that becomes the drain of the first transistor, the first gate region that forms the channel of the first transistor, the source of the first transistor, and also the drain of the second transistor a second n-type diffusion-39-201010062 layer, a second gate region portion forming a channel of the second transistor, and a third n-type diffusion layer serving as a source; the first metal wiring is formed in the transistor formation portion Left or right, configured as and The transistor forming portions are parallel and connected from the surface of the semiconductor substrate by a predetermined distance, and are connected to the drain of the first transistor by a contact; the square polycrystalline layer is formed in a portion in the left-right direction and the first transistor. The gate region is opposed to each other and serves as a gate of the first transistor; and the first and second hollow channels of the square are implanted on the semiconductor substrate on the left and right sides of the transistor forming portion. The predetermined width and depth are formed in the left-right direction; the square floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and the region on the left end side thereof is opposite to the surface in which the first channel is implanted. And the region of the central portion and the second gate region of the second transistor face each other, and the region on the right end side faces the surface on which the second channel is implanted; the fifth n-type diffusion layer is The left side adjacent to the one channel injection is formed in the left and right direction with a predetermined width and depth, and becomes a control gate; the sixth n type diffusion layer is adjacent to the right side of the second channel injection, The predetermined width and depth are formed in the left-right direction and become the control gate. The control © gate wiring is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the floating gate at a predetermined distance, and is connected at the same time. The control gate wiring for the control gate of the floating gate and the potential is opposite to the floating gate, and is connected to the first and second diffusion layers by the contact; the second metal wiring is The surface of the semiconductor substrate is disposed in a horizontal direction with respect to a third n-type diffusion layer serving as a source of the second transistor, and is connected to the third n-type diffusion layer by a contact; and a sub-connection The point is used to prevent the formation of the upper side of the polycrystalline layer of the square of the gate of the first transistor, on the side of the first metal wiring on the semiconductor substrate -40 to 201010062. The voltage of the region of the semiconductor substrate of the memory cell rises; at the same time, in the arrangement of the memory cells, the memory cells are arranged in the left-right direction to be the fifth and sixth ri type which are shared with each other as the control gate. Powder layer; the same time arranged in the horizontal direction of the memory cell element 2, that share the second metal wiring, and the memory cell element are arranged symmetrically in the downward direction. (3) Further, a non-volatile semiconductor memory device according to one aspect of the present invention, which is a floating gate type one-layer polycrystalline silicon germanium non-volatile semiconductor memory element at an intersection of a word line and a data line Each memory cell is arranged in an array, and the memory cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process. The memory cell is configured to generate hot electrons near the drain of the second transistor when the charge is stored on the floating gate, and inject a charge to the floating gate or apply a high voltage to the floating gate And applying a charge to the floating gate using a tunneling current of Fowler-Norwegian; and applying a charge between the drain of the second transistor Q and the floating gate when erasing the charge stored in the floating gate High voltage, and the Fowler-Nordheim tunneling current is used to discharge the charge stored by the floating gate; the non-volatile semiconductor memory device is configured to follow the 1-bit or word of the memory cell in the direction of each column Unit of the unit, etc. The row unit of the positioning element is composed of a memory cell block for performing row selection; and at the same time, there are: a plurality of bit line lines, which are connected to the drain of the first transistor of each memory cell along the column direction: a plurality of strips are selected The gate wiring is connected to the selection gate of the gate of the first transistor in the row direction of each memory cell; the plurality of control gate wirings are connected to each memory cell in the row direction Dependent 2 -41- 201010062
電晶體之閘極的控制閘極；源極線，是在行方向按照該行 單位所選擇之各行選擇範圍內所設置的源極線，並共同連 接該行選擇範圍內之所有的列之各記憶胞元之第2電晶體 的源極；列解碼器，係接受位址信號，並輸出選擇該記憶 胞元的列選擇信號；第1位準挪移電路，係將從該列解碼 器所輸出之信號施加於該選擇閘極的信號變換成第1電 壓；第2位準挪移電路，係將從該列解碼器所輸出之信號 施加於該控制閘極的信號變換成第2電壓；行解碼器，係 接受位址信號，並輸出按照該行單位選擇該記憶胞元的行 選擇信號：第3位準挪移電路，係將從該行解碼器所輸出 之行選擇信號變換成第3電壓的行選擇信號；行選擇電晶 體，係將從該第3位準挪移電路所輸出之行選擇信號作爲 閘極輸入，並選擇該行單位之,記憶胞元的位元線；該行單 位之位元數的資料輸出入線，係經由該行選擇電晶體而和 由該行選擇電晶體所選擇之該行單位的位元線連接；資料 輸入變換電路，係在接受該行單位的位元數之寫入資料的 輸入信號並進行資料的寫入及資料的拭除時，輸出透過該 資料輸出入線而施加於該第1電晶體之汲極的第4電壓信 號；以及感測放大電路，係將該資料輸出入線所讀出之記 憶胞元的資料放大並向外部輸出。 (34) 又，本發明之一形態的非揮發性半導體記憶裝置， 其在字元線和資料線的交點將係屬浮動閘極型之1層多晶 矽非揮發性半導體記億元件的各個記憶胞元排列成陣列狀 而構成，而該記憶胞元由形成於半導體基板上之MOS構造 的第1電晶體、和浮動閘極型之第2電晶體所構成，並以 -42- 201010062 標準CMOS製程構成，該記憶胞元構成爲：在對該浮動閘 極儲存電荷時，在該第2電晶體的汲極附近產生熱電子， 並對該浮動閘極注入電荷，或對該浮動閘極施加高電壓， 而利用 Fowler— Nordheim的穿隧電流對該浮動閘極注入 電荷；及在拭除該浮動閘極所儲存的電荷時，對該第2電 晶體的汲極和浮動閘極之間施加高電壓，而利用該Fowler -Nordheim的穿隧電流放出該浮動閘極所儲存的電荷；該 非揮發性半導體記憶裝置配置成由將該記億胞元在行方向 Ο 分割成既定之位元數k(k 21)個，並在行方向具有η位元 (η 2 1)之寬度的該k個記憶胞元方塊所構成；並具備有： 複數條位元線，係沿著列方向共同連接各記憶胞元之第1 電晶體的汲極；複數條選擇閘極配線，係沿著行方向共同 連接各記憶胞元之係屬第1電晶體之閘極的選擇閘極；複 數條控制閘極配線，係沿著行方向共同連接各記憶胞元之 係屬第2電晶體之閛極的控制閘極；列解碼器，是在各列 所設置之列解碼器，並接受位址信號，產生選擇該記憶胞 Q 元的列選擇信號；第1位準挪移電路，係將從該列解碼器 所輸出之信號變換成施加於該選擇閘極之第1電壓信號； 第2位準挪移電路，係將從該列解碼器所輸出之信號變換 成施加於該控制閘極的第2電壓信號；η個行解碼器，是 對應於在該記憶胞元方塊之行方向的位元數η而設置的行 解碼器，並輸出從各該記憶胞元方塊選擇1個記憶胞元的 行選擇信號；第3位準挪移電路，係將從該行解碼器所輸 出之行選擇信號變換成第3電壓的行選擇信號；行選擇電 晶體，是對應於各個該記憶胞元方塊所設置之η位元單位 -43- 201010062 的行選擇電晶體，將從該第3位準挪移電路所輸出之第3 電壓信號作爲閘極輸入，從各該記憶胞元方塊選擇1個記 憶胞元的位元線，並選擇合計k位元的記憶胞元；k位元 之資料輸出入線，係經由該行選擇電晶體而和由該行選擇 電晶體所選擇之k位元的位元線連接；資料輸入變換電 路，係在接受k位元單位之寫入資料的輸入信號並進行資 料的寫入及資料的拭除時，輸出透過該資料輸出入線而施 加於該第1電晶體之汲極的第4電壓信號；以及感測放大 電路，係將該資料輸出入線所讀出之記憶胞元的資料放大 Θ 並向外部輸出。 (35)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將係屬浮動閘極型之1層多晶矽 非揮發性半導體記憶元件的各個記憶胞元排列成陣列狀而 構成，而該記憶胞元由形成於半導體基板上之MOS構造的 第1電晶體、和浮動閘極型之第2電晶體所構成，並以標 準CMOS製程構成，各該記憶胞元是該（6)項所記載之非揮 發性半導體記憶元件，並由具有用以對η型井施加所要之 © 電壓的第7η型擴散層和第3金屬配線的非揮發性半導體記 憶元件所構成，同時該非揮發性半導體記憶裝置配置成由 將該記憶胞元在各列之行方向按照1位元組或字元單位等 之既定位元數的行單位進行行選擇的記憶胞元方塊所構 成；同時具備有：複數條位元線，係沿著列方向共同連接 各該記憶胞元之第1電晶體的汲極；選擇閘.極配線，係沿 著行方向共同連接各該記憶胞元之係屬第1電晶體之閘極 的選擇閘極；控制閘極配線，是在各該記憶胞元方塊所設 -44- 201010062 置之控制閘極配線，並沿著行方向共同連接記憶胞元之係 屬第2電晶體之閘極的控制閘極；源極線，是在行方向按 照該行單位所選擇之各行選擇範圍內所設置的源極線，並 共同連接該行選擇範圍內之所有的列之各記憶胞元之第2 電晶體的源極；列解碼器，係接受位址信號，並輸出選擇 該記憶胞元的列選擇信號；第1位準挪移電路，係將從該 列解碼器所輸出之信號變換成施加於該選擇閘極的第1電 壓信號；行解碼器，係接受位址信號，並輸出按照該行單 Ο 位選擇該記憶胞元的行選擇信號；第3位準挪移電路，係 將從該行解碼器所輸出之選擇信號變換成第3電壓；第2 位準挪移電路，係將從該列解碼器所輸出之行選擇信號變 換成第2電壓信號；選擇電路，是配置於各該記憶胞元方 塊，同時對所選擇之記億胞元方塊內的電晶體施加閘極電 壓的選擇電路，並具有傳輸閘極電晶體，其將第1位準挪 移電路的輸出信號作爲汲極輸入，並將從該第2位準挪移 電路所輸出之行選擇信號的電壓作爲閘極輸入，向該控制 〇 閘極傳輸該第1位準挪移電路的輸出信號或因應於該行選 擇信號之電壓的電壓；行選擇電晶體，係將從該第3位準 挪移電路所輸出之行選擇信號作爲閘極輸入，並選擇該行 單位的位元數之記億胞元的位元線；該行單位之位元數的 資料輸出入線，係經由該行選擇電晶體而和由該行選擇電 晶體所選擇之行單位的位元線連接；資料輸入變換電路， 係在接受該行單位的位元數之寫入資料的輸入信號並進行 資料的寫入及資料的拭除時，輸出透過該資料輸出入線而 施加於該第1電晶體之汲極的第4電壓信號；以及感測放 -45- 201010062 大電路，係將該資料輸出入線所讀出之記憶胞元的資料放 大並向外部輸出。 (36) 又，本發明之一形態的非揮發性半導體記憶裝置，其 將係屬浮動閘極型之1層多晶矽非揮發性半導體記憶元件 的記憶胞元排列成陣列狀而構成，而該記憶胞元由形成於 半導體基板上之MOS構造的第1電晶體、和浮動閘極型之 第2電晶體所構成，並以標準CMOS製程構成，各該記憶 胞元是該（6)項所記載之非揮發性半導體記憶元件，並由具 有用以對η型井施加所要之電壓的第7n型擴散層和第3金 © 屬配線的非揮發性半導體記憶元件所構成，同時在各該記 憶胞元的配置，將彼此共用該η型井並左右對稱地配置之 2個記憶胞元；及對該左右對稱地配置之2個記憶胞元， 彼此共用該第2金屬配線並在下方向對稱地配置之2個記 憶胞元之合計4個記憶胞元作爲配置的基本單位；在左右 方向平行地排列配置，同時在上下方向亦平行地排列配置 成爲該配置之基本單位的4個記憶胞元。The gate of the gate of the transistor; the source line is the source line set in the row selection direction of each row selected in the row direction, and is connected to all the columns in the row selection range a source of the second transistor of the memory cell; the column decoder receives the address signal and outputs a column selection signal for selecting the memory cell; the first level shifting circuit is output from the column decoder The signal applied to the selection gate is converted into a first voltage, and the second level shifting circuit converts a signal applied from the output of the column decoder to the control gate into a second voltage; Receiving an address signal, and outputting a row selection signal for selecting the memory cell according to the row unit: the third bit shifting circuit converts the row selection signal outputted by the row decoder into the third voltage Row selection signal; row selection transistor, the row selection signal outputted from the third level shifting circuit is used as a gate input, and the bit line of the memory cell is selected in the row unit; Metadata output The input line is connected to the bit line of the row unit selected by the row selection transistor through the row selection transistor; the data input conversion circuit is inputting the data input in the number of bits accepting the row unit When the signal is written and the data is erased, the fourth voltage signal applied to the drain of the first transistor through the data input and output line is output, and the sense amplifier circuit outputs the data to the line. The data of the read memory cell is amplified and output to the outside. (34) Further, in the nonvolatile semiconductor memory device according to one aspect of the present invention, at the intersection of the word line and the data line, each of the memory cells of the floating gate type polycrystalline germanium nonvolatile semiconductor device The cells are arranged in an array, and the memory cells are composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and are manufactured in a standard CMOS process of -42-201010062. The memory cell is configured to generate hot electrons near the drain of the second transistor when the charge is stored on the floating gate, and inject a charge to the floating gate or apply a high voltage to the floating gate Voltage, and Fowler-Norway's tunneling current is used to inject charge into the floating gate; and when the charge stored in the floating gate is erased, a high voltage is applied between the drain and the floating gate of the second transistor. a voltage, and the Fowler-Nordheim tunneling current is used to discharge the charge stored by the floating gate; the non-volatile semiconductor memory device is configured to divide the cell in the row direction into a predetermined number of bits k ( k 21 And consisting of the k memory cell blocks having a width of η bits (η 2 1) in the row direction; and having: a plurality of bit lines connecting the memory cells in the column direction The first gate of the first transistor; the plurality of gate gates are connected to each other, and the gates of the first transistor are connected to each memory cell in the row direction; the plurality of control gate wirings are Connecting the memory cells in the row direction to the control gate of the second transistor of the second transistor; the column decoder is a column decoder set in each column, and accepts the address signal to generate the selected memory. a column selection signal of a cell Q element; the first bit shifting circuit converts a signal output from the column decoder into a first voltage signal applied to the selection gate; and a second level shift circuit The signal output by the column decoder is converted into a second voltage signal applied to the control gate; the n row decoders are line decodings corresponding to the number of bits η in the row direction of the memory cell block. And outputting a memory cell from each of the memory cell blocks The row selection signal; the third bit shifting circuit is a row selection signal that converts the row selection signal outputted from the row decoder into a third voltage; the row selection transistor corresponds to each of the memory cell blocks. The row selection transistor of the set η bit unit -43-201010062, the third voltage signal outputted from the third bit shifting circuit is used as a gate input, and one memory cell is selected from each of the memory cell blocks. a bit line, and select a memory cell with a total of k bits; the data output line of the k bit is selected via the row to select a transistor and is connected to the bit line of the k bit selected by the row selection transistor The data input conversion circuit is configured to receive the input signal of the data written in the k-bit unit and write the data and erase the data, and output the drain electrode applied to the first transistor through the data input and output line. The fourth voltage signal; and the sense amplifying circuit is a data amplification Θ of the memory cell read out by the data input and output to the external output. (35) Further, in a nonvolatile semiconductor memory device according to an aspect of the present invention, at the intersection of a word line and a data line, each memory cell of a floating gate type one-layer polycrystalline non-volatile semiconductor memory element is used. The memory cells are formed by an array of first crystals of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and are configured by a standard CMOS process, each of which is composed of the memory. The cell is the non-volatile semiconductor memory element described in the item (6), and is a nonvolatile semiconductor memory element having a 7th n-type diffusion layer and a third metal wiring for applying a desired voltage to the n-type well. The non-volatile semiconductor memory device is configured such that the memory cell is selected by row cells in which the memory cell is selected in a row unit of a 1-bit group or a character unit in the row direction of each column. And having a plurality of bit lines, which are connected to the drains of the first transistors of the memory cells in the column direction; the gates are selected to be connected in the row direction. The cell is the gate of the gate of the first transistor; the gate is controlled, and the gate wiring is set in the memory cell block -44- 201010062, and is common along the row direction. The connection gate is the control gate of the gate of the second transistor; the source line is the source line set in the row selection direction selected by the row unit in the row direction, and the row is connected in common Selecting the source of the second transistor of each memory cell in all the columns in the range; the column decoder accepts the address signal and outputs a column selection signal for selecting the memory cell; the first level shifting circuit, Converting the signal output from the column decoder into a first voltage signal applied to the selection gate; the row decoder accepting the address signal and outputting the row of the memory cell according to the row unit a selection signal; the third bit quasi-migration circuit converts the selection signal output from the row decoder into a third voltage; and the second level shift circuit converts the row selection signal output from the column decoder into Second voltage signal; selection circuit, a selection circuit disposed in each of the memory cell blocks and applying a gate voltage to the selected transistor in the cell, and having a transmission gate transistor, which outputs the output signal of the first level shifting circuit As a drain input, a voltage of a row selection signal output from the second level shifting circuit is used as a gate input, and an output signal of the first level shifting circuit is transmitted to the control gate or in response to the row Selecting the voltage of the voltage of the signal; selecting the transistor from the row, the row selection signal outputted from the third level shifting circuit is used as the gate input, and selecting the bit of the cell of the row unit a line; the data output line of the row unit of the row unit is connected to the bit line of the row unit selected by the row selection transistor by the row selection transistor; the data input conversion circuit is accepted by the line When the input signal of the data is written into the data and the data is erased, the fourth voltage signal applied to the drain of the first transistor through the data input and output line is output; -45-201010062 large discharge sensing circuit, the data lines into the data output line of the memory cell is read out membered amplified output to the outside. (36) A nonvolatile semiconductor memory device according to one aspect of the present invention, wherein memory cells of a floating gate type one-layer polycrystalline germanium nonvolatile semiconductor memory device are arranged in an array, and the memory is configured The cell is composed of a first transistor of a MOS structure formed on a semiconductor substrate and a second transistor of a floating gate type, and is configured by a standard CMOS process, and each of the memory cells is recorded in the item (6). The non-volatile semiconductor memory element is composed of a non-volatile semiconductor memory element having a 7n-type diffusion layer and a third gold-type wiring for applying a desired voltage to the n-type well, and simultaneously in each of the memory cells In the arrangement of the elements, two memory cells in which the n-type wells are shared with each other and symmetrically arranged; and two memory cells arranged symmetrically to the left and right sides share the second metal wiring and are symmetrically arranged in the lower direction The total of four memory cells are the basic unit of the arrangement; they are arranged in parallel in the left-right direction, and are arranged in parallel in the vertical direction, and are arranged in four units which are the basic units of the arrangement. Memory cell.
(37) 又，本發明之一形態的非揮發性半導體記憶裝置，其 Q 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀，而構成記憶胞元陣 列’該記憶胞元作爲OTP，並構成爲在對該浮動閘極儲存 電荷時，對該電晶體的控制閘極施加第1電壓，對汲極施 加第2電壓，並對該源極施加〇V的電壓；在該電晶體的汲 極附近產生熱電子，並對該浮動閘極注入該熱電子；該非 揮發性半導體記憶裝置配置複數個記憶胞元方塊，其根據 -46 - 201010062 行位址η位元（η 2 1)和i〇位元（io 2 1)的輸出入I/O位元 數，而將該記憶胞元陣列在行方向按照該行位址η位元單 位，分割成該I/O位元數而構成；並具備有：複數條位元 線，係沿著列方向共同連接各該記憶胞元之電晶體的汲 極；字元線，是在各列所設置之字元線，並沿著行方向共 同連接該記憶胞元之電晶體的控制閘極；源極線，係共同 連接各記憶胞元之電晶體的源極；列解碼器，是在各列所 設置之列解碼器，接受位址信號並產生選擇該記億胞元的 〇 列選擇信號；第1位準挪移電路，係將從各該解碼器所輸 出之列選擇信號變換成施加於該字元線之第1信號電壓的 信號；η個行解碼器，是對應於在該記憶胞元方塊之行方 向的位元數η所設置的行解碼器，並輸出從各該記憶胞元 方塊選擇1個記憶胞元的行選擇信號；第2位準挪移電路， 係將從該行解碼器所輸出之行選擇信號變換成第2信號電 壓的信號；行選擇電晶體，是對各該記憶胞元方塊所設置 之η位元單位的行選擇電晶體，將從該第2位準挪移電路 〇 所輸出之第2信號電壓作爲閘極輸入，並從各記憶胞元方 塊選擇1個記憶胞元的位元線，以選擇該I/O位元數的記 憶胞元；該I/O位元數的資料輸出入線，係經由該行選擇 電晶體而和由該行選擇電晶體所選擇之該I/O位元數的位 元線連接；寫入控制電路，係在接受該I/O位元數之寫入 資料的輸入信號，並進行資料的寫入及資料的拭除時，輸 出透過該料輸出入線而施加於該電晶體之汲極的第3電壓 信號；以及感測放大電路，係將該資料輸出入線所讀出之 記億胞元的資料放大並向外部輸出。 -47- 201010062(37) Further, in a nonvolatile semiconductor memory device according to one aspect of the present invention, Q is a layer of a floating gate type which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each memory cell of the polycrystalline non-volatile memory element is arranged in an array, and constitutes a memory cell array 'the memory cell as an OTP, and is configured to control the transistor when the charge is stored on the floating gate Applying a first voltage to the pole, applying a second voltage to the drain, applying a voltage of 〇V to the source; generating hot electrons near the drain of the transistor, and injecting the hot electron into the floating gate; the non-volatile The semiconductor memory device is configured with a plurality of memory cell blocks, which are input into the number of I/O bits according to the output of the -46 - 201010062 row address η bit (η 2 1) and the i 〇 bit (io 2 1). Configuring the memory cell array in the row direction according to the row address η bit unit, and dividing into the I/O bit number; and having: a plurality of bit lines connected together in the column direction The drain of the transistor of the memory cell; the word line is a line of characters arranged in each column, and jointly connecting the control gates of the transistors of the memory cells along the row direction; the source lines are the sources of the transistors commonly connected to the memory cells; the column decoder, Is a column decoder set in each column, accepting an address signal and generating a queue selection signal for selecting the cell; the first level shifting circuit converts the column selection signal output from each decoder a signal applied to the first signal voltage of the word line; n row decoders are row decoders corresponding to the number of bits η in the row direction of the memory cell block, and are outputted from each The memory cell block selects a row selection signal of one memory cell; the second bit quasi-migration circuit converts the row selection signal outputted from the row decoder into a signal of the second signal voltage; the row selects the transistor, Selecting a transistor for each of the n-bit units of the memory cell block, and outputting the second signal voltage outputted from the second-level shift circuit 作为 as a gate input, and selecting from each memory cell block a bit line of a memory cell, Selecting the memory cell of the I/O bit number; the data of the I/O bit number is input to the line, and the selected transistor is selected by the row and the I/O bit selected by the row selection transistor The number of bit lines are connected; the write control circuit is an input signal for writing data of the I/O bit number, and when the data is written and the data is erased, the output is output through the material input line. A third voltage signal applied to the drain of the transistor; and a sense amplifier circuit that amplifies the data of the cells of the cell read out from the data input line and outputs it to the outside. -47- 201010062
(3 8)又’本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀，而構成記憶胞元陣 列，該記憶胞元作爲OTP，並構成爲在對該浮動閘極儲存 電荷時，對該電晶體的控制閘極施加第1電壓，對汲極施 加第2電壓，並對該源極施加〇V的電壓；在該電晶體的汲 極附近產生熱電子，並對該浮動閘極注入該熱電子；該非 揮發性半導體記憶裝置配置複數個記憶胞元方塊，其按照 i〇位元（i〇 2 1)之輸出入I/O位元數的單位，在行方向分割 該記憶胞元陣列而構成；並具備有：複數條位元線，係沿 著列方向共同連接各該記憶胞元之電晶體的汲極；字元 線，是在各列所設置之字元線，並沿著行方向共同連接該 記憶胞元之電晶體的控制閘極；源極線，係共同連接各記 憶胞元之電晶體的源極；列解碼器，是在各列所設置之列 解碼器，接受位址信號並產生選擇該記憶胞元的列選擇信 號；第1位準挪移電路，係將從各該解碼器所輸出之列選 擇信號變換成施加於該字元線之第1信號電壓的信號；行 解碼器，係接受位址信號並輸出在行方向按照該I/O位元 數的單位選擇該記憶胞元的行選擇信號；第2位準挪移電 路，係將從該行解碼器所輸出之選擇信號變換成第2信號 電壓；行選擇電晶體，是對各該記憶胞元方塊所設置之該 I/O位元數的單位的行選擇電晶體，將從該第2位準挪移電 路所輸出之第2信號電壓作爲閘極輸入，並從所選擇的記 憶胞元方塊選擇該I/O位元數之記憶胞元的位元線；該1/0 -48- 201010062 位元數的資料輸出入線，係經由該行選擇電晶體而和由該 行選擇電晶體所選擇之該I/O位元數的位元線連接；寫入 控制電路，係在接受該I/O位元數之寫入資料的輸入信號， 並進行資料的寫入及資料的拭除時，輸出透過該資料輸出 入線而施加於該第1電晶體之汲極的第3電壓信號；以及 感測放大電路，係將該資料輸出入線所讀出之記憶胞元的 資料放大並向外部輸出。 (3 9)又，本發明之一形態的非揮發性半導體記憶裝置，其 〇 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀，而構成記憶胞元陣 列，該記憶胞元係以MTP構成，並構成爲：在對該浮動閘 極儲存電荷時，執行在MOS電晶體的汲極附近產生熱電 子’並對該浮動閘極注入該熱電子的步驟；及在對該浮動 閘極拭除電荷時，執行：第1步驟，係利用Fowler-Nordheim的穿隧電流將電荷注入該浮動閘極；及第2步 〇 驟’係在執行該第1步驟後，在電晶體的汲極附近產生熱 電子’並對該浮動閘極在既定時間內注入該熱電子。 (4 0)又’本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀，而構成記憶胞元陣 列’該記憶胞元係以MTP構成，並構成爲：在對該浮動閘 極儲存電荷時’在MOS電晶體的汲極附近產生熱電子，並 對該浮動閘極注入該熱電子；同時在對該浮動閘極拭除電 -49- 201010062 荷時，在利用Fowler— Nordheim的穿險電流將電荷注入該 浮動閘極後，在電晶體的汲極附近產生熱電子，並對該浮 動閘極在既定時間內注入該熱電子；同時該非揮發性半導 體記憶裝置配置複數個記憶胞元方塊，其根據行位址η位 元（η2 1)和io位元（iogl)的輸出入I/O位元數，而將該記 憶胞元陣列在行方向按照該行位址η位元單位，分割成該 I/O位元數而構成；並具備有：複數條位元線，係沿著列方 向共同連接各該記憶胞元之電晶體的汲極；字元線，是在 各列所設置之字元線，並沿著行方向共同連接該記憶胞元 © 之電晶體的控制閘極；源極線，是在各列所設置之源極線， 並沿著行方向共同連接該記憶胞元之電晶體的源極；開關 用電晶體，係設置於各該源極線，並用以選擇將該源極線 接地成GND或設爲開路；列解碼器，是在各列所設置之列 解碼器，接受位址信號並產生選擇該記憶胞元的列選擇信 號，選擇該列選擇信號的電壓位準，並施加於該字元線， 同時輸出使該開關用電晶體變成導通、不導通的控制信 號；η個行解碼器，是對應於在該記憶胞元方塊之行方向 〇 的位元數η所設置的行解碼器，並輸出從各該記憶胞元方 塊選擇1個記憶胞元的行選擇信號；第2位準挪移電路， 係將從該行解碼器所輸出之行選擇信號變換成第2信號電 壓的信號；行選擇電晶體，是對各該記憶胞元方塊所設置 之η位元單位的行選擇電晶體，將從該第2位準挪移電路 所輸出之行選擇信號作爲閘極輸入，並從各記憶胞元方塊 選擇1個記憶胞元的位元線，以選擇該I/O位元數的記憶 胞元；該I/O位元數的資料輸出入線，係經由該行選擇電 -50- 201010062 晶體而和由該行選擇電晶體所選擇之該ι/ο位元數的{立$ 線連接；寫入控制電路，係在接受該I/O位元數之寫人資 料的輸入信號，並進行資料的寫入及資料的拭除時，輸出 透過該資料輸出入線而施加於該電晶體之汲極的第3電壓 信號；以及感測放大電路，係將該資料輸出入線所讀出之 記憶胞元的資料放大並向外部輸出。 (41) 又，本發明之一形態的非揮發性半導體記憶裝置，亦 可該列解碼器具備有：寫入模式，係將2位元之第丨或第 ❹ 2寫入控制信號作爲控制輸入，並因應於該第1或第2寫 入控制信號的値，而在對記憶胞元寫入資料時，向該字元 線輸出第1信號電壓，以使該開關用電晶體變成導通；第 1拭除模式，係在拭除記憶胞元的資料時，向該字元線輸 出0V，並輸出使該開關用電晶體變成不導通的信號；以及 第2拭除模式，係在拭除記憶胞元的資料時，向該字元線 輸出0V，並輸出使該開關用電晶體變成導通的信號。(3) A non-volatile semiconductor memory device according to one aspect of the present invention, which is a layer of a floating gate type which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each memory cell of the polycrystalline non-volatile memory element is arranged in an array to form an array of memory cells, the memory cell being an OTP, and configured to control a gate of the transistor when the charge is stored on the floating gate Applying a first voltage to the pole, applying a second voltage to the drain, applying a voltage of 〇V to the source; generating hot electrons near the drain of the transistor, and injecting the hot electron into the floating gate; the non-volatile The semiconductor memory device is configured with a plurality of memory cell blocks, which are formed by dividing the memory cell array in the row direction according to the output of the i-bit (i〇2 1) into the I/O bit number unit; There is: a plurality of bit lines, which are connected to the drains of the transistors of the memory cells along the column direction; the word lines are the word lines arranged in the columns, and are commonly connected along the row direction. Control of the transistor of memory cells a gate; a source line is a source of a transistor that commonly connects each memory cell; a column decoder is a column decoder set in each column, accepts an address signal and generates a column selection for selecting the memory cell. a signal; a first level shifting circuit converts a column selection signal output from each of the decoders into a signal applied to a first signal voltage of the word line; and the row decoder receives the address signal and outputs the signal The row direction selects a row selection signal of the memory cell according to the unit of the number of I/O bits; the second bit shifting circuit converts the selection signal outputted by the row decoder into a second signal voltage; The transistor is a row selection transistor for each unit of the number of I/O bits provided in each memory cell block, and the second signal voltage output from the second level shifting circuit is used as a gate input. And selecting, from the selected memory cell block, a bit line of the memory cell of the I/O bit number; the data of the 1/0 -48-201010062 bit number is input into the line, and the transistor is selected through the row. And the number of I/O bits selected by the row to select the transistor The bit line is connected; the write control circuit is configured to receive the input signal of the data written by the I/O bit number, and when the data is written and the data is erased, the output is applied to the data input and output line. The third voltage signal of the drain of the first transistor; and the sense amplifier circuit amplify the data of the memory cell read by the data input and output to the outside. (3) Further, a nonvolatile semiconductor memory device according to an aspect of the present invention is characterized in that a floating gate type of a standard CMOS process is formed on a semiconductor substrate at an intersection of a word line and a data line. Each of the memory cells of the polycrystalline non-volatile memory element is arranged in an array to form an array of memory cells, the memory cell being composed of MTP, and configured to perform MOS when storing charge on the floating gate a step of generating a hot electron near the drain of the transistor and injecting the hot electron to the floating gate; and performing a first step of using a tunneling current of Fowler-Nordheim when the charge is erased from the floating gate A charge is injected into the floating gate; and a second step is to generate a hot electron near the drain of the transistor after performing the first step and to inject the hot electron for the floating gate for a predetermined time. (4) A non-volatile semiconductor memory device according to one aspect of the present invention, which is a layer of a floating gate type which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each memory cell of the polycrystalline non-volatile memory element is arranged in an array, and constitutes a memory cell array. The memory cell is composed of MTP and is configured to: when storing charge on the floating gate, 'in the MOS transistor The hot electrons are generated near the drain and the hot electrons are injected into the floating gate; and when the floating gate is erased -49- 201010062, the charge is injected into the floating gate using the Fowler-Norway safe current. After the pole, hot electrons are generated near the drain of the transistor, and the hot gate is injected into the floating gate for a predetermined time; and the non-volatile semiconductor memory device is configured with a plurality of memory cell blocks according to the row address η The output of the bit (η2 1) and the io bit (iogl) enters the number of I/O bits, and the memory cell array is divided into the I/O bits in the row direction according to the row address η bit unit. Composed of yuan; and The utility model has a plurality of bit lines, which are connected to the drains of the transistors of the memory cells in the column direction; the word lines are the word lines arranged in the columns, and are connected together along the row direction. The control gate of the transistor of the memory cell ©; the source line is a source line disposed in each column, and the source of the transistor of the memory cell is commonly connected along the row direction; the transistor for switching Is set in each of the source lines, and is used to select the source line to be grounded to GND or to be an open circuit; the column decoder is a column decoder set in each column, accepting the address signal and generating the selected memory a column selection signal of the cell, selecting a voltage level of the column selection signal, and applying to the word line, and simultaneously outputting a control signal for turning the transistor into conduction and non-conduction; n row decoders are corresponding a row decoder set in the bit number η of the memory cell block, and outputting a row selection signal for selecting one memory cell from each of the memory cell blocks; a second bit shifting circuit, Is the line that will be output from the row decoder The signal is converted into a signal of the second signal voltage; the row selection transistor is a row selection transistor of η bit units set for each of the memory cell blocks, and the output from the second level shifting circuit is outputted. Selecting a signal as a gate input, and selecting a bit line of one memory cell from each memory cell block to select a memory cell of the I/O bit number; and outputting the data of the I/O bit number into the line By selecting the electric -50-201010062 crystal through the row and the {$$ line connection of the ι/ο bit number selected by the row selection transistor; the write control circuit accepts the I/O bit The input signal of the digital data of the digital data, and the writing of the data and the erasing of the data, outputting the third voltage signal applied to the drain of the transistor through the data input and output line; and the sensing and amplifying circuit, The data of the memory cell read out by the data input and output is amplified and output to the outside. (41) In the nonvolatile semiconductor memory device according to the aspect of the present invention, the column decoder may include a write mode in which a 2-bit third or second write control signal is used as a control input. And in response to the first or second write control signal, when the data is written to the memory cell, the first signal voltage is output to the word line, so that the switching transistor becomes conductive; 1 erasing mode, when erasing the data of the memory cell, outputting 0V to the word line, and outputting a signal for making the switch transistor non-conductive; and the second erasing mode is erasing the memory In the case of the cell data, 0 V is output to the word line, and a signal for turning the switching transistor into conduction is output.
(42) 又，本發明之一形態的非揮發性半導體記憶裝置，其 Q 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀，而構成記憶胞元陣 列，該記憶胞元係以MTP構成，並構成爲：在對該浮動閘 極儲存電荷時，在MOS電晶體的汲極附近產生熱電子，並 對該浮動閘極注入該熱電子；同時在對該浮動閘極拭除電 荷時，在利用Fowler— Nordheim的穿險電流將電荷注入該 浮動閘極後，在電晶體的汲極附近產生熱電子，並對該浮 動閘極在既定時間內注入該熱電子；同時該非揮發性半導 -51- 201010062 體記憶裝置配置複數個記憶胞元方塊，其將io位元（io 2 1) 的輸出入I/O位元數作爲單位，並在行方向分割該記憶胞 元陣列而構成；並具備有：複數條位元線，係沿著列方向 共同連接各該記憶胞元之電晶體的汲極；字元線，是在各 列所設置之字元線，並沿著行方向共同連接該記憶胞元之 電晶體的控制閘極；源極線，是在各列所設置之源極線， 並沿著行方向共同連接該記憶胞元之電晶體的源極；開關 用電晶體，係設置於各該源極線，並用以選擇將該源極線 接地成GND或設爲開路；列解碼器，是在各列所設置之列 © 解碼器，接受位址信號並產生選擇該記憶胞元的列選擇信 號，選擇該列選擇信號的電壓位準，並施加於該字元線， 同時輸出使該開關用電晶體變成導通、不導通的控制信 號；行解碼器，係接受位址信號並輸出在行方向按照該I/O 位元數的單位選擇該記憶胞元的行選擇信號；第2位準挪 移電路，係將從該行解碼器所輸出之行選擇信號變換成第 2信號電壓；行選擇電晶體，是在各該記憶胞元方塊所設 置之該I/O位元數的單位的行選擇電晶體，將從該第2位 Q 準挪移電路所輸出之第2信號電壓作爲閘極輸入，並從所 選擇之記憶胞元方塊選擇該I/O位元數之記憶胞元的位元 線；該I/O位元數的資料輸出入線，係經由該行選擇電晶 體而和由該行選擇電晶體所選擇之該I/O位元數的位元線 連接；寫入控制電路，係在接受該I/O位元數之寫入資料 的輸入信號並進行資料的寫入及資料的拭除時，輸出透過 該資料輸出入線而施加於該記憶胞元之電晶體的汲極之第 4電壓信號；以及感測放大電路’係將該資料輸出入線所 -52- 201010062 讀出之記憶胞元的資料放大並向外部輸出。 (43) 又’本發明之一形態的非揮發性半導體記憶裝置，亦 可該列解碼器具備有：寫入模式，係將2位元之第1或第 2寫入控制信號作爲控制輸入，並因應於該第1或第2寫 入控制信號的値，而在對記憶胞元寫入資料時，向該字元 線輸出第1信號電壓，以使該開關用電晶體變成導通；第 1拭除模式，係在拭除記憶胞元的資料時，向該字元線輸 出0V，並輸出使該開關用電晶體變成不導通的信號；以及 Ο 第2拭除模式，係在拭除記憶胞元的資料時，向該字元線 輸出0V，並輸出使該開關用電晶體變成導通的信號。 (44) 又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀，而構成記憶胞元陣 列，該記億胞元係以MTP構成，並構成爲：在對該浮動閘 極儲存電荷時，在MOS電晶體的汲極附近產生熱電子，並 〇 對該浮動閘極注入該熱電子；同時在對該浮動閘極拭除電 荷時，在利用Fowler— Nordheim的穿隧電流將電荷注入該 浮動閘極後，在電晶體的汲極附近產生熱電子，並對該浮 動閘極在既定時間內注入該熱電子；同時該非揮發性半導 體記憶裝置配置複數個記憶胞元方塊，其根據行位址η位 元（η 2 1)和io位元（iogl)的輸出入I/O位元數，而將該記 憶胞元陣列在行方向按照該行位址η位元單位，分割成該 I/O位元數而構成；並具備有：複數條位元線，係沿著列方 向共同連接各該記憶胞元之電晶體的汲極；字元線，是在 -53- 201010062(42) Further, in the nonvolatile semiconductor memory device according to one aspect of the present invention, Q is a layer of a floating gate type which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each memory cell of the polycrystalline non-volatile memory element is arranged in an array to form an array of memory cells, the memory cell being composed of MTP, and configured to: when storing charge on the floating gate, in the MOS transistor A hot electron is generated near the drain and the hot electron is injected into the floating gate; and when the charge is erased from the floating gate, after the charge is injected into the floating gate using Fowler-Norwey's through-current, A hot electron is generated near the drain of the transistor, and the hot gate is injected into the floating gate for a predetermined time; and the non-volatile semiconductor-51100100 memory device is configured with a plurality of memory cell blocks, which will be io-bit The output of the element (io 2 1) is in units of I/O bits, and is divided into the memory cell array in the row direction; and is provided with: a plurality of bit lines, which are connected together in the column direction. Remember Recalling the drain of the transistor of the cell; the word line is the word line set in each column, and is connected to the control gate of the transistor of the memory cell along the row direction; the source line is The source lines of each column are connected to the source of the transistor of the memory cell in the row direction; the switching transistor is disposed on each of the source lines, and is used to select the source line to be grounded GND or set to open; the column decoder is a column set decoder in each column, accepts the address signal and generates a column select signal for selecting the memory cell, selects the voltage level of the column select signal, and Applying to the word line, simultaneously outputting a control signal for turning the switch transistor into conduction and non-conduction; and the row decoder accepting the address signal and outputting the line in the row direction according to the unit of the number of I/O bits. a row selection signal of the memory cell; the second bit shifting circuit converts the row selection signal outputted from the row decoder into a second signal voltage; and the row selection transistor is set in each of the memory cell blocks Row selection of the unit of the number of I/O bits a transistor, wherein the second signal voltage outputted from the second bit Q quasi-shift circuit is used as a gate input, and the bit line of the memory cell of the I/O bit number is selected from the selected memory cell block The data output line of the I/O bit number is connected to the bit line of the I/O bit number selected by the row selection transistor through the row selection transistor; the write control circuit is When accepting the input signal of the written data of the I/O bit number, and writing the data and erasing the data, outputting the drain of the transistor applied to the memory cell through the data input and output line 4 voltage signal; and the sense amplifier circuit 'outputs the data into the line -52- 201010062 The data of the read memory cell is amplified and output to the outside. (43) In the non-volatile semiconductor memory device according to one aspect of the present invention, the column decoder may include a write mode in which a first or second write control signal of two bits is used as a control input. And in response to the first or second write control signal, when the data is written to the memory cell, the first signal voltage is output to the word line, so that the switching transistor becomes conductive; The erase mode is to output 0V to the word line when the data of the memory cell is erased, and output a signal for making the switch transistor non-conductive; and Ο the second erase mode is to erase the memory In the case of the cell data, 0 V is output to the word line, and a signal for turning the switching transistor into conduction is output. (44) A nonvolatile semiconductor memory device according to one aspect of the present invention, which is a floating gate type one-layer polysilicon which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each memory cell of the non-volatile memory element is arranged in an array to form an array of memory cells, which is composed of MTP, and is configured to: when storing charge on the floating gate, in the MOS transistor Thermal electrons are generated near the drain, and the hot electrons are injected into the floating gate; and when the charge is erased to the floating gate, after the charge is injected into the floating gate using Fowler-Norway's tunneling current, Producing hot electrons near the drain of the transistor, and injecting the hot electrons into the floating gate for a predetermined time; and the non-volatile semiconductor memory device is configured with a plurality of memory cell blocks according to the row address η bit ( The output of η 2 1) and io bit (iogl) enters the number of I/O bits, and the memory cell array is divided into the number of I/O bits in the row direction according to the row address η bit unit And have A plurality of bit bar lines, each of the drain lines commonly connected memory transistors of the cells of the electrode in the column direction; word lines, in -53-201010062
各列所設置之字元線，並沿著行方向共同連接該記憶胞元 之電晶體的控制閘極；源極線，是在成對之每2列所設置 之源極線，並沿著行方向共同連接該2列記憶胞元之電晶 體的源極；開關用電晶體，是在各該源極線所設置之2個 開關用電晶體，即第1開關用電晶體，係根據來自該成對 之2個列解碼器之一方的信號而選擇將該源極線接地成 GND或設爲開路；及第2開關用電晶體，係根據來自該成 對之2個列解碼器之另一方的信號而選擇將該源極線接地 成GND或設爲開路；列解碼器，是在各列所設置之列解碼 器，接受位址信號並產生選擇該記憶胞元的列選擇信號， 選擇該列選擇信號的電壓位準，並施加於該字元線，同時 以2個構成對，從一方輸出使該第1開關用電晶體變成導 通、不導通的控制信號，並從另一方輸出使該第2開關用 電晶體變成導通、不導通的控制信號；η個行解碼器，是 對應於在該記憶胞元方塊之行方向的位元數η所設置的行 解碼器，並輸出從各該記憶胞元方塊選擇1個記憶胞元的 行選擇信號；第2位準挪移電路，係將從該行解碼器所輸 出之行選擇信號變換成第2信號電壓的信號；行選擇電晶 體，是對各該記憶胞元方塊所設置之η位元單位的行選擇 電晶體，將從該第2位準挪移電路所輸出之第2信號電壓 作爲閘極輸入，並從各記憶胞元方塊選擇1個記憶胞元的 位元線，以選擇該I/O位元數的記憶胞元；該I/O位元數 的資料輸出入線，係經由該行選擇電晶體而和由該行選擇 電晶體所選擇之該I/O位元數的位元線連接；寫入控制電 路，係在接受該I/O位元數之寫入資料的輸入信號並進行 -54- 201010062 資料的寫入及資料的拭除時，輸出透過該資料輸出入線而 施加於該電晶體之汲極的第3電壓信號；以及感測放大電 路，係將該資料輸出入線所讀出之記憶胞元的資料放大並 向外部輸出。 (45)又’本發明之一形態的非揮發性半導體記憶裝置，亦 可該列解碼器具備有：寫入模式，係在對記憶胞元寫入資 料時’在係屬所選擇之列解碼器的情況，對該字元線輸出 第1信號電壓，同時使對應於該列解碼器的該開關用電晶 0體變成導通；第1拭除模式，係在拭除記憶胞元的資料時， 在係屬所選擇之列解碼器的情況，向該字元線輸出0V，並 輸出使對應於該列解碼器之該開關用電晶體變成不導通的 信號’同時在係屬非選擇之列解碼器的情況，向該字元線 輸出既定之電壓信號，並輸出使對應於該列解碼器之該開 關用電晶體變成不導通的信號；以及第2拭除模式，係在 拭除記憶胞元的資料時，在係羼所選擇之列解碼器的情 況’向該字元線輸出0V，並輸出使對應於該列解碼器之該 Ο開關用電晶體變成導通的信號，而且在係屬非選擇之列解 碼器的情況，向該字元線輸出0V，同時輸出使對應於該列 解碼器之該開關用電晶體變成不導通的信號。 (4 6)又’本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之丨層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀，而構成記憶胞元陣 列’該記憶胞元係以MTP構成，並構成爲：在對該浮動閘 極儲存電荷時’在MOS電晶體的汲極附近產生熱電子，並 -55- 201010062 對該浮動閘極注入該熱電子；同時在對該浮動閘極拭除電 荷時，在利用Fowler— Nordheim的穿隧電流將電荷注入該 浮動閘極後，在電晶體的汲極附近產生熱電子，並對該浮 動閘極在既定時間內注入該熱電子；同時該非揮發性半導 體記憶裝置配置複數個記憶胞元方塊，其按照io位元 (io 2 1)的輸出入I/O位元數的單位，在行方向分割該記憶 胞元陣列而構成；並具備有：複數條位元線，係沿著列方 向共同連接各該記憶胞元之電晶體的汲極；字元線，是在 各列所設置之字元線，並沿著行方向共同連接該記憶胞元 © 之電晶體的控制閘極；源極線，是在成對之每2列所設置 之源極線，並沿著行方向共同連接該2列記憶胞元之電晶 體的源極；開關用電晶體，是在各該源極線所設置之2個 開關用電晶體，即第1開關用電晶體，係根據來自該成對 之2個列解碼器之一方的信號而選擇將該源極線接地成 GND或設爲開路；及第2開關用電晶體，係根據來自該成 對之2個列解碼器之另一方的信號而選擇將該源極線接地 成GND或設爲開路；列解碼器，是在各列所設置之列解碼 Q 器，接受位址信號並產生選擇該記憶胞元的列選擇信號， 選擇該列選擇信號的電壓位準，並施加於字元線，同時以 2個構成對，從一方輸出使該第1開關用電晶體變成導通、 不導通的控制信號，並從另一方輸出使該第2開關用電晶 體變成導通、不導通的控制信號；行解碼器，係接受位址 信號並輸出在行方向按照該I/O位元數的單位選擇該記憶 胞元的行選擇信號；第2位準挪移電路，係將從該行解碼 器所輸出之選擇信號變換成第2信號電壓；行選擇電晶 -56- 201010062 體，是在各該記憶胞元方塊所設置之該I/O位元數的單位 的行選擇電晶體，將從該第2位準挪移電路所輸出之第2 信號電壓作爲閘極輸入，並從所選擇之記憶胞元方塊選擇 該I/O位元數之記憶胞元的位元線；該I/O位元數的資料 輸出入線，係經由該行選擇電晶體而和由該行選擇電晶體 所選擇之該I/O位元數的位元線連接；寫入控制電路，係 在接受該I/O位元數之寫入資料的輸入信號並進行資料的 寫入及資料的拭除時，輸出透過該資料輸出入線而施加於 Ο 該第1電晶體之汲極的第4電壓信號；以及感測放大電路， 係將該資料輸出入線所讀出之記憶胞元的資料放大並向外 部輸出。 (4 7)又，本發明之一形態的非揮發性半導體記憶裝置，亦 可該列解碼器具備有：寫入模式，係在對記憶胞元寫入資 料時，在係屬所選擇之列解碼器的情況，對該字元線輸出 第1信號電壓，同時使對應於該列解碼器的該開關用電晶 體變成導通；第1拭除模式，係在拭除記憶胞元的資料時， Ο 在係屬所選擇之列解碼器的情況，向該字元線輸出ον，並 輸出使對應於該列解碼器之該開關用電晶體變成不導通的 信號，同時在係屬非選擇之列解碼器的情況，向該字元線 輸出既定之電壓信號，並輸出使對應於該列解碼器之該開 關用電晶體變成不導通的信號；以及第2拭除模式，係在 拭除記憶胞元的資料時，在係屬所選擇之列解碼器的情 況，向該字元線輸出0V，並輸出使對應於該列解碼器之該 開關用電晶體變成導通的信號，同時在係屬非選擇之列解 碼器的情況，向該字元線輸出0V，同時輸出使對應於該列 -57- 201010062 解碼器之該開關用電晶體變成不導通的信號。 (48)又’本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀而構成，作爲該記憶胞 元之構成部分的布置，在以上下方向表示該半導體基板上 的第1方向，並以左右方向表示和該第1方向正交之第2 方向的情況’具備有：方形的電晶體形成部，係在該上下 方向依序配置：成爲電晶體之汲極的第In型擴散層、形成 0 電晶體之通道的閘極區域部、以及成爲電晶體之源極的第 2n型擴散層；第1金屬配線，係在該電晶體形成部的左側 或右側，配置成和該電晶體形成部平行而且從半導體基板 表面隔著既定之距離，同時利用接點和該電晶體之汲極連 接；方形的η型井，係在該半導體基板上，在該電晶體形 成部的左側，以既定之寬度和深度在左右方向所形成；方 形的浮動閘極，係在左右方向配置成和該半導體基板表面 相對向，同時配置成其左端部側的區域和該η型井的表面 @ 相對向，而且右端部側的區域和該閘極區域部相對向；ρ 型擴散層，係和該η型井之與該浮動閘極相對向之區域的 左側相鄰，並以既定之寬度和深度在左右方向形成，同時 成爲對控制閘極配線的連接端子；控制閘極配線，係從該 半導體基板表面隔著既定之距離在左右方向配置成和該浮 動閘極相對向，同時利用接點和該Ρ型擴散層連接；以及 第2金屬配線，係從該半導體基板表面隔著既定之距離在 左右方向配置成和成爲該電晶體之源極的第2η型擴散層 -58- 201010062 相對向，同時利用接點和該第2η型擴散層連接；同時在各 該記憶胞元的配置，將彼此共用該η型井並左右對稱地配 置之2個記憶胞元；及對該左右對稱地配置之2個記憶胞 元，彼此共用該第2金屬配線並在下方向對稱地配置之2 個記憶胞元之合計4個記憶胞元作爲配置的基本單位；在 左右方向平行地排列配置，同時在上下方向亦平行地排列 配置成爲該構成之基本單位的4個記憶胞元。 (4 9)又，本發明之一形態的非揮發性半導體記憶裝置，其 Ο 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀而構成，作爲該記憶胞 元之構成部分的布置，在以上下方向表示該半導體基板上 的第1方向，並以左右方向表示和該第1方向正交之第2 方向的情況，具備有：方形的電晶體形成部，係在該上下 方向依序配置：成爲電晶體之汲極的第In型擴散層、形成 電晶體之通道的閘極區域部、以及成爲電晶體之源極的第 〇 2ri型擴散層；第1金靥配線，係在該電晶體形成部的左側 或右側，配置成和該電晶體形成部平行而且從半導體基板 表面隔著既定之距離，同時利用接點和該電晶體之汲極連 接；方形之空乏型通道注入，係在該半導體基板上，在該 電晶體形成部的左側，以既定之寬度和深度在左右方向所 形成；方形的浮動閘極，係在左右方向配置成和該半導體 基板表面相對向，同時配置成左端部側的區域和該通道注 入的表面相對向，而且右端部側的區域和該電晶體的該閘 極區域部相對向；第3n型擴散層，係和該通道注入的左側 -59- 201010062Each of the column of word lines is disposed, and is connected to the control gate of the transistor of the memory cell along the row direction; the source line is a source line disposed in each of two pairs of pairs, and along The source of the transistor of the two columns of memory cells is connected in the row direction; the transistor for switching is two transistors for switching in the source line, that is, the transistor for the first switch, based on Selecting one of the pair of two column decoders to select the source line to be grounded to GND or to be an open circuit; and the second switching transistor to be based on the other pair of column decoders One of the signals is selected to ground the source line to GND or to be an open circuit; the column decoder is a column decoder provided in each column, receives the address signal and generates a column selection signal for selecting the memory cell, and selects The voltage level of the column selection signal is applied to the word line, and two pairs are formed, and a control signal for turning on the first switching transistor is turned on and off, and is output from the other side. The second switching transistor becomes conductive and non-conductive a signal; n row decoders, which are row decoders corresponding to the number of bits η in the row direction of the memory cell block, and output row selection for selecting one memory cell from each of the memory cell blocks a signal; a second quasi-migration circuit is a signal for converting a row selection signal outputted from the row decoder into a second signal voltage; and a row selection transistor is an n-bit set for each of the memory cell blocks The row selection transistor of the unit selects the second signal voltage outputted from the second level shifting circuit as a gate input, and selects a bit line of one memory cell from each memory cell block to select the I a memory cell of the number of O/O bits; the data of the I/O bit number is input to the line, and the bit is selected by the row and the bit of the I/O bit selected by the row is selected by the row. The line connection; the write control circuit is configured to receive the input signal of the data of the I/O bit number and perform the writing of the data and the data erasing of -54-201010062, and the output is applied through the data input and output line. a third voltage signal at the drain of the transistor; and sensing Large circuit, the read data lines of the data input and output lines of the memory cell element amplifies and outputs to the outside. (45) In the non-volatile semiconductor memory device according to one aspect of the present invention, the column decoder may be provided with a write mode, which is to decode the data selected in the system when the data is written to the memory cell. In the case of the device, the first signal voltage is output to the word line, and the switch crystal cell corresponding to the column decoder is turned on; the first erasing mode is when the data of the memory cell is erased. In the case of a selected column decoder, 0V is output to the word line, and a signal for causing the switching transistor corresponding to the column decoder to become non-conductive is outputted while being in a non-selected state. In the case of a decoder, a predetermined voltage signal is output to the word line, and a signal for causing the switching transistor corresponding to the column decoder to become non-conductive is output; and a second erasing mode is performed to erase the memory cell. In the case of the metadata of the element, in the case of the selected decoder of the system, '0 V is output to the word line, and a signal for turning on the transistor for the switch corresponding to the column decoder is output, and is In the case of a non-selected column decoder, The word line outputs 0V, while the output power so that the crystal switch corresponding to the column decoder of the signal becomes nonconductive. (4) A non-volatile semiconductor memory device according to one aspect of the present invention, which is a floating gate type layer formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each memory cell of the polycrystalline non-volatile memory element is arranged in an array, and constitutes a memory cell array. The memory cell is composed of MTP and is configured to: when storing charge on the floating gate, 'in the MOS transistor A hot electron is generated near the drain, and -55-201010062 injects the hot electron to the floating gate; and when the charge is erased from the floating gate, a charge is injected into the floating gate using a tunneling current of Fowler-Norweenheim After the pole, hot electrons are generated near the drain of the transistor, and the hot gate is injected into the floating gate for a predetermined time; and the non-volatile semiconductor memory device is configured with a plurality of memory cell blocks according to the io bit ( The unit of the output of the io 2 1) is divided into the unit of the number of I/O bits, and the memory cell array is divided in the row direction; and the plurality of bit lines are provided, and the memory is connected in the column direction. The drain of the transistor of the element; the word line is the word line set in each column, and is connected to the control gate of the transistor of the memory cell © in the row direction; the source line is in a source line for each of the two columns, and a source of the transistor of the two columns of memory cells are connected in the row direction; the switching transistor is two switches provided in each of the source lines The transistor, that is, the first switching transistor, is selected to ground the source line to GND or open circuit based on a signal from one of the pair of two column decoders; and the second switching transistor According to the signal from the other of the pair of two column decoders, the source line is selected to be grounded to GND or to be an open circuit; the column decoder is to decode the Q set in each column and accept The address signal generates a column selection signal for selecting the memory cell, selects a voltage level of the column selection signal, applies it to the word line, and forms a pair of two, and outputs the first switching transistor from one side. Becomes a conduction, non-conducting control signal, and outputs the second from the other side The transistor is turned into a non-conducting control signal; the row decoder receives the address signal and outputs a row selection signal for selecting the memory cell in the row direction according to the number of the I/O bit number; the second bit The quasi-migration circuit converts the selection signal outputted from the decoder of the row into a second signal voltage; the row selects the crystal-56-201010062 body, which is the I/O bit set in each memory cell block. The row of the number of cells selects the transistor, and the second signal voltage output from the second level shifting circuit is used as a gate input, and the memory cell of the I/O bit number is selected from the selected memory cell block. a bit line of the element; the data output line of the I/O bit number is connected to the bit line of the I/O bit number selected by the row selection transistor via the row selection transistor; The control circuit is configured to receive an input signal of the I/O bit number and write the data and erase the data, and the output is applied to the first transistor through the data input and output line. The fourth voltage signal of the drain; and the sense amplifier circuit Line feed data into the read output of the memory cell element and an enlarged portion outwardly outputs. (4) Further, in the nonvolatile semiconductor memory device according to the aspect of the present invention, the column decoder may be provided with a write mode, which is selected in the system when writing data to the memory cell. In the case of the decoder, the first signal voltage is output to the word line, and the switching transistor corresponding to the column decoder is turned on; the first erasing mode is when the data of the memory cell is erased. Ο In the case of a selected column decoder, ον is output to the word line, and a signal for causing the switching transistor corresponding to the column decoder to become non-conductive is output, and is in a non-selection column In the case of a decoder, a predetermined voltage signal is output to the word line, and a signal for causing the switching transistor corresponding to the column decoder to become non-conductive is output; and a second erasing mode is performed to erase the memory cell. In the case of the metadata of the element, in the case of the decoder selected by the column, 0 V is output to the word line, and a signal for turning the transistor for the switch corresponding to the column decoder into conduction is output, and at the same time Select the case of the decoder To the word line output 0V, while the output of the corresponding the switch -57- to the column decoder of the electric crystal 201,010,062 signal becomes nonconductive. (48) A non-volatile semiconductor memory device according to one aspect of the present invention, which is a floating gate type one-layer polysilicon which is formed on a semiconductor substrate in a standard CMOS process at an intersection of a word line and a data line. Each of the memory cells of the non-volatile memory element is arranged in an array, and the arrangement of the constituent elements of the memory cell indicates the first direction on the semiconductor substrate in the upper and lower directions, and is expressed in the left-right direction. In the case of the second direction orthogonal to the one direction, a rectangular transistor forming portion is disposed in the vertical direction in order to form an In-type diffusion layer which is a drain of the transistor and a channel which forms a 0-crystal. a gate region portion and a second n-type diffusion layer serving as a source of the transistor; the first metal wiring is disposed on the left side or the right side of the transistor forming portion in parallel with the transistor forming portion and from the surface of the semiconductor substrate A joint is connected to the drain of the transistor through a predetermined distance; a square n-type well is on the semiconductor substrate, on the left side of the transistor forming portion, with a predetermined The width and the depth are formed in the left-right direction; the square floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and is disposed such that the region on the left end side thereof faces the surface @ of the n-type well, and The region on the right end side and the gate region portion face each other; the p-type diffusion layer is adjacent to the left side of the region of the n-type well opposite to the floating gate, and is in the left and right direction with a predetermined width and depth And forming a connection terminal for controlling the gate wiring; and controlling the gate wiring from the surface of the semiconductor substrate so as to face the floating gate in a horizontal direction with a predetermined distance therebetween, and using the contact and the Ρ type The second metal wiring is disposed so as to be opposed to the second n-type diffusion layer-58-201010062 which is a source of the transistor in a horizontal direction from a surface of the semiconductor substrate with a predetermined distance therebetween. a point is connected to the second n-type diffusion layer; and at the same time, in the arrangement of the memory cells, two memory cells which are mutually shared with the n-type well and symmetrically arranged; and Two memory cells arranged symmetrically to the right, and the total of four memory cells of the two memory cells that are symmetrically arranged in the lower direction are shared as the basic unit of arrangement; and are arranged in parallel in the left-right direction. At the same time, four memory cells which are the basic units of the configuration are arranged in parallel in the vertical direction. (4) Further, a nonvolatile semiconductor memory device according to an aspect of the present invention is characterized in that a floating gate type of a standard CMOS process is formed on a semiconductor substrate at an intersection of a word line and a data line. Each of the memory cells of the polycrystalline non-volatile memory element is arranged in an array, and the arrangement of the constituent elements of the memory cell indicates the first direction on the semiconductor substrate in the upper and lower directions, and represents the sum in the left-right direction. In the second direction orthogonal to the first direction, a rectangular transistor forming portion is provided in the vertical direction, and an In-type diffusion layer which serves as a drain of the transistor and a channel for forming a transistor are disposed in this order. a gate region portion and a second ri2ri type diffusion layer that serves as a source of the transistor; and the first metal ridge wiring is disposed on the left side or the right side of the transistor forming portion in parallel with the transistor forming portion and The semiconductor substrate surface is separated by a predetermined distance, and the junction is connected to the gate of the transistor; a square-shaped channel is implanted on the semiconductor substrate at the transistor forming portion. The side is formed in the left-right direction with a predetermined width and depth; the square floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and the region disposed on the left end side and the surface injecting the channel are opposed to each other. And the region on the right end side and the gate region portion of the transistor are opposite; the third n-type diffusion layer, and the left side of the channel injection - 59- 201010062
相鄰，並以既定之寬度和深度在左右方向形成，同時成爲 對該控制閘極配線的連接端子；控制閘極配線，係從該半 導體基板表面隔著既定之距離在左右方向配置成和該浮動 閘極相對向，同時利用接點和該第3n型擴散層連接；以及 第2金屬配線，係從該半導體基板表面隔著既定之距離在 左右方向配置成和成爲該電晶體之源極的第2n型擴散層 相對向，同時利用接點和該第2n型擴散層連接；同時在各 該記憶胞元的配置，將左右對稱地配置成彼此共用成爲該 控制閘極之連接端子的第3n型擴散層之2個記憶胞元、及 對該左右對稱地配置之2個記憶胞元，彼此共用該第2金 屬配線並在下方向對稱地配置之2個記憶胞元之合計4個 記憶胞元作爲配置的基本單位；在左右方向平行地排列配 置，同時在上下方向亦平行地排列配置成爲該構成之基本 單位的4個記憶胞元。Adjacent, and formed in the left-right direction with a predetermined width and depth, and as a connection terminal to the control gate wiring, the gate wiring is arranged in the left-right direction from the surface of the semiconductor substrate via a predetermined distance. The floating gate is opposed to each other, and the contact is connected to the third n-type diffusion layer; and the second metal wiring is disposed in the left-right direction from the surface of the semiconductor substrate at a predetermined distance and serves as a source of the transistor. The second n-type diffusion layer is opposed to each other, and is connected to the second n-type diffusion layer by a contact; and at the same time, the arrangement of the memory cells is symmetrically arranged to be the third to be the connection terminal of the control gate. Two memory cells of the type of diffusion layer and two memory cells of the two memory cells symmetrically arranged in the left and right, sharing the second metal wiring and symmetrical in the lower direction, the total of four memory cells The basic unit of the arrangement is arranged in parallel in the left-right direction, and four memory cells which are the basic units of the configuration are arranged in parallel in the vertical direction.
(5 0)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀而構成，作爲該記憶胞 元之構成部分的布置，在以上下方向表示該半導體基板上 的第1方向，並以左右方向表示和該第1方向正交之第2 方向的情況，具備有：方形的電晶體形成部，係在該上下 方向依序配置：成爲電晶體之汲極的第In型擴散層、形成 電晶體之通道的閘極區域部、以及成爲電晶體之源極的第 2n型擴散層；第1金屬配線，係在該電晶體形成部的左側 或右側’配置成和該電晶體形成部平行而且從半導體基板 -60- 201010062 表面隔著既定之距離，同時利用接點和該電晶體之汲極連 接；方形之空乏型通道注入，係在該半導體基板上，在該 電晶體形成部的左側，以既定之寬度和深度在左右方向所 形成；浮動閘極，係在左右方向配置成和該半導體基板表 面相對向，同時配置成左端部側的區域和該通道注入的表 面相對向，而且右端部側的區域和該電晶體的該閘極區域 部相對向；第3n型擴散層，係和該通道注入的左側相鄰， 並以既定之寬度和深度在左右方向形成，同時成爲對該控 Ο 制閘極配線的連接端子；控制閘極配線，係從該半導體基 板表面隔著既定之距離在左右方向配置成和該浮動閘極相 對向’同時利用接點和該第3η型擴散層連接；以及第2金 屬配線，係從該半導體基板表面隔著既定之距離在左右方 向配置成和成爲該電晶體之源極的第2η型擴散層相對 向，同時利用接點和該第2η型擴散層連接；同時在各該記 憶胞元的配置，將左右對稱地配置成彼此共用成爲該控制 閘極之連接端子的第3ri型擴散層之2個記憶胞元、及對該 Ο 左右對稱地配置之2個記憶胞元，彼此共用該第2金屬配 線並在下方向對稱地配置之2個記憶胞元之合計4個記憶 胞元作爲配置的基本單位；在左右方向平行地排列配置， 同時在上下方向亦平行地排列配置成爲該構成之基本單位 的4個記億胞元。 (51)又’本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀而構成，作爲該記憶胞 -61- 201010062 元之構成部分的布置，在以上下方向表示該半導體基板上 的第1方向，並以左右方向表示和該第1方向正交之第2 方向的情況，具備有：方形的電晶體形成部，係在該上下 方向依序配置：成爲電晶體之汲極的第In型擴散層、形成 電晶體之通道的閘極區域部、以及成爲電晶體之源極的第 2n型擴散層；第1金屬配線，係在該電晶體形成部的左側 或右側，配置成和該電晶體形成部平行而且從半導體基板 表面隔著既定之距離，同時利用接點和該電晶體之汲極連 接；方形之空乏型通道注入，係在該半導體基板上，在該 © 電晶體形成部的左側，以既定之寬度和深度在左右方向所 形成；浮動閘極，是在左右方向配置成和該半導體基板表 面相對向，同時配置成左端部側的區域和該通道注入的表 面相對向，而且右端部側的區域和該電晶體的該閘極區域 部相對向之方形的浮動閛極，並配置成在和該通道注入的 表面相對向之左端部的區域具備有方形的面積擴張部；第 3n型擴散層，係和該通道注入的左側相鄰，並以既定之寬 度和深度在左右方向形成，同時成爲對該控制閘極配線的 〇 連接端子；控制閘極配線，係從該半導體基板表面隔著既 定之距離在左右方向配置成和該浮動閘極相對向’同時利 用接點和該第3η型擴散層連接；以及第2金龎配線’係從 該半導體基板表面隔著既定之距離在左右方向配置成和成 爲該電晶體之源極的第2η型擴散層相對向’同時利用接點 和該第2η型擴散層連接；同時在各該記憶胞元的配置’將 2個記憶胞元左右對稱地配置成彼此共用成爲該控制閘極 之連接端子的第3η型擴散層’並對該左右對稱地配置之2 -62- 201010062 個記憶胞元，在上方向對稱地配置記憶胞元，將這4個記 憶胞元作爲單位，在左右方向排列成記憶胞元陣列；同時 在上下方向平行地排列配置在該左右方向所排列的記憶胞 元陣列。 (5 2)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記億胞元排列成陣列狀，而構成記憶胞元陣 Ο 列，各該記憶胞元是該（14)項所記載之非揮發性半導體記 憶元件，並由具有用以對η型井施加所要之電壓的第4ri型 擴散層和第3金屬配線的非揮發性半導體記憶元件所構 成，同時該非揮發性半導體記憶裝置配置複數個記憶胞元 方塊，其根據行位址η位元（n g 1)和io位元（io 2 1)的輸出 入I/O位元數，而將該記憶胞元陣列在行方向按照該行位 址η位元單位，分割成該I/O位元數而構成；並具備有： 複數條位元線，係沿著列方向共同連接各該記憶胞元之電 〇 晶體的汲極；字元線，是在各列所設置之字元線，並沿著 行方向共同連接該記憶胞元之電晶體的控制閘極；源極 線，係共同連接各記憶胞元之電晶體的源極；列解碼器， 是在各列所設置之列解碼器，接受位址信號並產生選擇該 記憶胞元的列選擇信號；第1位準挪移電路，係將從各該 列解碼器所輸出之列選擇信號變換成施加於該字元線之第 1信號電壓的信號；η個行解碼器，是對應於在該記憶胞元 方塊之行方向的位元數η所設置的行解碼器，並輸出從各 該記憶胞元方塊選擇1個記憶胞元的行選擇信號；第2位 -63- 201010062(50) Further, a nonvolatile semiconductor memory device according to an aspect of the present invention is a layer of a floating gate type which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each of the memory cells of the polycrystalline non-volatile memory device is arranged in an array, and the arrangement of the constituent elements of the memory cell indicates the first direction on the semiconductor substrate in the upper and lower directions, and is expressed in the left-right direction. In the case where the first direction is orthogonal to the second direction, the rectangular transistor forming portion is disposed in the vertical direction in order to form an In-type diffusion layer which is a drain of the transistor and a channel for forming the transistor. a gate region portion and a second n-type diffusion layer serving as a source of the transistor; the first metal wiring is disposed on the left side or the right side of the transistor forming portion in parallel with the transistor forming portion and from the semiconductor substrate - 60- 201010062 The surface is separated by a predetermined distance, and the junction is connected to the gate of the transistor; a square-shaped channel is implanted on the semiconductor substrate to form the transistor. The left side of the portion is formed in the left-right direction with a predetermined width and depth; the floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and the region disposed on the left end side and the surface injecting the channel are opposed to each other. And the region on the right end side faces the gate region portion of the transistor; the third n-type diffusion layer is adjacent to the left side of the channel injection, and is formed in the left-right direction with a predetermined width and depth, and becomes a connection terminal for controlling the gate wiring; and controlling the gate wiring from the surface of the semiconductor substrate at a predetermined distance in the left-right direction so as to face the floating gate while using the contact and the third n-type The second metal wiring is disposed in a horizontal direction from the surface of the semiconductor substrate so as to face the second n-type diffusion layer serving as a source of the transistor from the surface of the semiconductor substrate, and the contact point and the first The 2n-type diffusion layer is connected; at the same time, in the arrangement of the memory cells, the 3rd type which is symmetrically arranged left and right to be the connection terminal of the control gate is shared Two memory cells of the diffusion layer and two memory cells arranged symmetrically with respect to each other, and a total of four memory cells of the two memory cells that share the second metal wiring and are symmetrically arranged in the lower direction The basic unit of the arrangement is arranged in parallel in the left-right direction, and four cells in the basic unit of the configuration are arranged in parallel in the vertical direction. (51) A non-volatile semiconductor memory device according to one aspect of the present invention, which is a floating gate type one-layer polysilicon which is formed on a semiconductor substrate by a standard CMOS process at an intersection of a word line and a data line. Each of the memory cells of the non-volatile memory element is arranged in an array, and the arrangement of the constituent elements of the memory cell-61-201010062 represents the first direction on the semiconductor substrate in the upper and lower directions, and is in the left-right direction. In the case of the second direction orthogonal to the first direction, a rectangular transistor forming portion is disposed in the vertical direction, and an In-type diffusion layer that serves as a drain of the transistor and a transistor are formed. a gate region portion of the channel and a second n-type diffusion layer serving as a source of the transistor; and the first metal wiring is disposed on the left side or the right side of the transistor forming portion in parallel with the transistor forming portion and The surface of the semiconductor substrate is separated by a predetermined distance, and the junction is connected to the gate of the transistor; the square-shaped channel is implanted on the semiconductor substrate, and the transistor is formed. The left side of the portion is formed in the left-right direction with a predetermined width and depth; the floating gate is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and the region disposed on the left end side and the surface injecting the channel are opposed to each other. And the region on the right end side and the gate region of the transistor are opposite to the square floating fins, and are arranged to have a square area expansion portion in a region opposite to the left end portion of the surface implanted with the channel The 3n-type diffusion layer is adjacent to the left side of the channel injection, and is formed in the left-right direction with a predetermined width and depth, and serves as a connection terminal for the control gate wiring; the control gate wiring is from the The surface of the semiconductor substrate is disposed so as to face the floating gate in a horizontal direction with a predetermined distance therebetween, and is connected to the third n-type diffusion layer by a contact; and the second metal wiring is spaced from the surface of the semiconductor substrate. The distance is arranged in the left-right direction so as to face the second n-type diffusion layer which is the source of the transistor, and the contact point and the second n-type diffusion layer are simultaneously used. At the same time, in the arrangement of the memory cells, the two memory cells are symmetrically arranged in a left-right symmetric manner to share the third n-type diffusion layer which serves as a connection terminal of the control gate, and the left and right symmetrically arranged 2 - 62- 201010062 memory cells, in which the memory cells are symmetrically arranged in the upper direction, and the four memory cells are arranged as a unit in the left-right direction as a memory cell array; and are arranged in parallel in the vertical direction in the vertical direction. Arranged array of memory cells. (5 2) Further, a nonvolatile semiconductor memory device according to one aspect of the present invention is a layer of a floating gate type which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line. Each of the cells of the polycrystalline non-volatile memory element is arranged in an array to form a memory cell array, each of the memory cells being the non-volatile semiconductor memory element recited in the item (14), and having a fourth RI type diffusion layer for applying a desired voltage to the n-type well and a non-volatile semiconductor memory element of the third metal wiring, wherein the non-volatile semiconductor memory device is configured with a plurality of memory cell blocks according to the row position The output of the address η bit (ng 1) and the io bit (io 2 1) enters the number of I/O bits, and the memory cell array is segmented into the row direction according to the row address η bit unit The number of I/O bits is composed of: a plurality of bit lines, which are connected to the drains of the cells of the memory cells in the column direction; the word lines are set in the columns. Word line and connect the memory together in the row direction The control gate of the transistor of the cell; the source line is the source of the transistor that commonly connects the memory cells; the column decoder is a column decoder set in each column, accepts the address signal and generates a selection a column selection signal of the memory cell; the first bit shifting circuit converts the column selection signal outputted from each of the column decoders into a signal applied to the first signal voltage of the word line; n rows of decoding And a row decoder corresponding to the number of bits η in the row direction of the memory cell block, and outputting a row selection signal for selecting one memory cell from each of the memory cell blocks; the second bit - 63- 201010062
準挪移電路，係將從該行解碼器所輸出之行選擇信號變換 成第2信號電壓的信號；行選擇電晶體，是對各該記億胞 元方塊所設置之η位元單位的行選擇電晶體，將從該第2 位準挪移電路所輸出之第2信號電壓作爲閘極輸入，並從 各記憶胞元方塊選擇1個記憶胞元的位元線，以選擇該I/O 位元數的記憶胞元；該I/O位元數的資料輸出入線，係經 由該行選擇電晶體而和由該行選擇電晶體所選擇之該I/O 位元數的位元線連接；寫入控制電路，係在接受該I/O位 元數之寫入資料的輸入信號，並進行資料的寫入及資料的 拭除時，輸出透過該資料輸出入線而施加於該電晶體之汲 極的第3電壓信號；以及感測放大電路，係將該資料輸出 入線所讀出之記憶胞元的資料放大並向外部輸出。The quasi-migration circuit converts the row selection signal outputted from the row decoder into a signal of the second signal voltage; the row selection transistor is a row selection of η-bit units set for each of the cells of the cell a transistor, wherein a second signal voltage outputted from the second level shifting circuit is used as a gate input, and a bit line of one memory cell is selected from each memory cell block to select the I/O bit. a number of memory cells; the data output line of the I/O bit number is selected via the row selection transistor and the bit line of the I/O bit number selected by the row selection transistor; The input control circuit is configured to receive the input signal of the data written in the I/O bit number, and when the data is written and the data is erased, the output is applied to the drain of the transistor through the data input and output line. The third voltage signal; and the sensing amplifying circuit amplifies the data of the memory cell read out by the data input and output to the outside.
(53)又，本發明之一形態的非揮發性半導體記憶裝置，其 在字元線和資料線的交點將在半導體基板上以標準CMOS 製程所構成之係屬浮動閘極型之1層多晶矽非揮發性記憶 元件的各個記憶胞元排列成陣列狀而構成，各該記憶胞元 是該（14)項所記載之非揮發性半導體記憶元件，並由具有 用以對η型井施加所要之電壓的第4η型擴散層和第3金屬 配線的非揮發性半導體記憶元件所構成，同時在各該記憶 胞元的配置，將彼此共用該η型井並左右對稱地配置之2 個記憶胞元；及對該左右對稱地配置之2個記憶胞元，彼 此共用該第2金靥配線並在下方向對稱地配置之2個記憶 胞元之合計4個記憶胞元作爲配置的基本單位；在左右方 向平行地排列配置，同時在上下方向亦平行地排列配置成 爲該構成之基本單位的4個記憶胞元。 -64 - 201010062 (5 4)又，本發明之一形態的非揮發性半導體記憶裝置，係 具有排列成複數個格子狀的非揮發性半導體記憶胞元，其 由形成於半導體基板上的複數個MOS電晶體所構成，並具 有用以選擇該記憶胞元的選擇閘極、及用以控制記憶內容 的控制閘極，各該非揮發性半導體記憶胞元具有：複數個 浮動閘極型電晶體，係由共用之該控制閘極控制，同時彼 此並列地連接；及選擇電晶體，係和該複數個浮動閘極型 電晶體串列地連接，並和該選擇閘極連接；該複數個浮動 〇閘極型電晶體和該選擇電晶體是在該半導體基板上直線狀 地排列，而該複數個浮動閘極型電晶體的各汲極是由直線 狀的金屬配線所連接，而且在該控制閘極和複數個該浮動 閘極型電晶體的各浮動閘極之間所形成之複數個電容器是 形成於同一η型擴散層內；在複數個非揮發性半導體記憶 胞元共用該η型擴散層。 (55)又，本發明之一形態的非揮發性半導體記憶裝置，係 具有排列成複數個格子狀的非揮發性半導體記憶胞元，其 〇 由形成於半導體基板上的複數個MOS電晶體所構成，並具 有用以選擇該記憶胞元的選擇閘極、及用以控制記憶內容 的控制閘極，各該非揮發性半導體記憶胞元具有：複數個 浮動閘極型電晶體，係由共用之該控制閘極控制，同時彼 此並列地連接；及選擇電晶體，係和該複數個浮動閘極型 電晶體串列地連接，並和該選擇閘極連接；該複數個浮動 閘極型電晶體和該選擇電晶體是在該半導體基板上直線狀 地排列，該複數個浮動閘極型電晶體的各汲極是由直線狀 的金屬配線所連接；具備有解碼器，其具有輸出部，向既 -65- 201010062 定之該控制閘極輸 胞元之位址信號解 元的寫入信號所產 (56) 又，本發明之 可該解碼器因應於 該輸出部的輸出電 (57) 又，本發明之 具有由 MOS電晶 胞元，而該MOS電 之CMOS電晶體相 體記憶胞元具有： 接，而閘極被施加 元件，是浮動閘極 擇電晶體的源極連 數個記憶元件寫入 選擇電晶體變成導 該第2端子施加比 該複數個記憶元件 使該選擇電晶體變 電壓高的電壓，將 從該複數個記憶元 而使該選擇電晶體 1電壓低的電壓而 係將該非揮發性半 極線，係對各行共 出根據已將指定該非揮發性半導體記憶 碼的信號、及該非揮發性半導體記憶胞 生之控制信號。 一形態的非揮發性半導體記憶裝置，亦 該寫入信號，在拭除資料時和讀出時將 壓設爲0V。 —形態的非揮發性半導體記憶裝置，其 體所構成之複數個非揮發性半導體記憶 晶體以和在半導體基板上形成邏輯電路 ©(53) Further, in a nonvolatile semiconductor memory device according to an aspect of the present invention, a floating gate type one-layer polysilicon which is formed by a standard CMOS process on a semiconductor substrate at an intersection of a word line and a data line Each of the memory cells of the non-volatile memory element is arranged in an array, and each of the memory cells is a non-volatile semiconductor memory element recited in the item (14), and has a function for applying a desired type to the n-type well. The fourth n-type diffusion layer of the voltage and the non-volatile semiconductor memory element of the third metal wiring are arranged, and in the arrangement of the memory cells, the two n-type wells are shared by the n-type well and symmetrically arranged. And a total of four memory cells of the two memory cells that are symmetrically arranged in the left-right direction and that share the second metal wire and are symmetrically arranged in the lower direction as the basic unit of the arrangement; The directions are arranged in parallel, and four memory cells which are the basic units of the configuration are arranged in parallel in the vertical direction. Further, a nonvolatile semiconductor memory device according to one aspect of the present invention has a plurality of non-volatile semiconductor memory cells arranged in a plurality of lattices, which are formed by a plurality of non-volatile semiconductor memory cells formed on a semiconductor substrate. The MOS transistor is configured to have a selection gate for selecting the memory cell and a control gate for controlling the memory content, each of the non-volatile semiconductor memory cells having: a plurality of floating gate type transistors; Controlled by the shared control gates while being connected in parallel with each other; and selecting a transistor connected in series with the plurality of floating gate type transistors and connected to the selection gate; the plurality of floating turns The gate type transistor and the selection transistor are linearly arranged on the semiconductor substrate, and the respective drains of the plurality of floating gate type transistors are connected by linear metal wiring, and the control gate is a plurality of capacitors formed between the poles and the plurality of floating gates of the floating gate type transistor are formed in the same n-type diffusion layer; in the plurality of non-volatile semiconductors Membered cells share the η-type diffusion layer. (55) Further, a nonvolatile semiconductor memory device according to an aspect of the present invention has a plurality of lattice-shaped nonvolatile semiconductor memory cells arranged in a plurality of MOS transistors formed on a semiconductor substrate. Constructing, and having a selection gate for selecting the memory cell and a control gate for controlling the memory content, each of the non-volatile semiconductor memory cells having: a plurality of floating gate type transistors, shared by The control gates are controlled while being connected in parallel with each other; and the transistor is selected to be connected in series with the plurality of floating gate type transistors and connected to the selection gate; the plurality of floating gate type transistors And the selection transistor is linearly arranged on the semiconductor substrate, and each of the plurality of floating gate type transistors is connected by a linear metal wiring; and a decoder having an output portion And -65-201010062, which is determined by the write signal of the address signal of the control gate cell (56). Moreover, the decoder of the present invention can respond to the output of the output ( 57) Further, the present invention has a MOS transistor, and the MOS transistor of the MOS transistor has a junction, and the gate is applied with a component, which is a source connection of the floating gate transistor. The plurality of memory elements are written to the selection transistor, and the second terminal is applied with a voltage higher than the plurality of memory elements to change the voltage of the selection transistor, and the voltage of the selection transistor 1 is lowered from the plurality of memory elements. The voltage is the non-volatile half-pole line, and the control signals corresponding to the non-volatile semiconductor memory code and the non-volatile semiconductor memory are separately generated for each row. A non-volatile semiconductor memory device of the type also writes a signal, and sets the voltage to 0V when erasing data and reading. a non-volatile semiconductor memory device in which a plurality of non-volatile semiconductor memory crystals are formed to form a logic circuit on a semiconductor substrate.
同的製程構成，該複數個非揮發性半導 選擇電晶體，係將汲極和該第1端子連 選擇信號；及並列地設置之複數個記憶 型的1層多晶矽電晶體，其汲極和該選 接，而源極和第2端子連接；在對該複 資料的情況，根據該選擇信號，而使該 通，並對該第1端子施加第1電壓，對 該第1電壓低的電壓而進行寫入；在對 Q 拭除資料的情況，根據該選擇信號，而 成導通，並對該第1端子施加比該第1 該第2端子設爲開路而進行拭除；及在 件讀出資料的情況，根據該選擇信號， 變成導通，並對該第2端子施加比該第 進行讀出；並具備有：記憶胞元陣列， 導體記憶胞元配置成陣列狀；複數條汲 同連接該複數個非揮發性半導體記憶胞 -66- 201010062 元的該汲極端子；複數個行選擇閘極，係和各個該複數條 汲極線連接；資料輸出入線，係經由該複數個行選擇聞極 而和該複數條汲極線連接；感測放大電路，係將該資料輸 出入線所讀出之該非揮發性半導體記憶胞元的資料放大並 向外部輸出；複數條選擇閘極線，係對各列共同連接該複 數個非揮發性半導體記憶胞元所具有之該選擇電晶體的閘 極：複數條源極線係對各列共同連接該複數個非揮發性半 導體記憶胞元的該源極端子；以及控制部，係根據從外部 Ο所輸入之選擇記億區域的位址信號及表示動作的命令信 號，而切換該行選擇閘的導通及不導通，並對該複數條選 擇閘極線及該複數條源極線施加電壓。 (5 8)又，本發明之一形態的非揮發性半導體記憶裝置，亦 可具備有和該複數條源極線之全部連接的源極驅動器：在 對該複數個非揮發性半導體記憶胞元全部一起進行拭除的 情況，該控制部對該複數個非揮發性半導體記憶胞元之該 複數條選擇閘極線的全部施加使該選擇電晶體變成不導通 〇 的電壓，而該源極驅動器施加比該第1電壓低的電壓。 (5 9)又，本發明之一形態的非揮發性半導體記憶裝置，亦 可將該複數個非揮發性半導體記憶胞元按照列單位分成複 數個方塊；具備有複數個和該複數個方塊各自的源極線連 接的源極驅動器；在進行對複數列之該非揮發性半導體記 憶胞元進行拭除之方塊拭除的情況，該控制部對該複數個 非揮發性半導體記憶胞元之該複數條選擇閘極線的全部施 加使該選擇電晶體變成不導通的電壓，而該複數個源極驅 動器施加比該第1電壓低的電壓。 -67- 201010062 (6 0)又，本發明之一形態的非揮發性半導體記憶裝置，其 配置複數個由MOS電晶體所構成的非揮發性半導體記憶 胞元而構成，而該MOS電晶體以和在半導體基板上形成邏 輯電路之CMOS電晶體相同的製程構成，該非揮發性半導 體記憶胞元具有：選擇電晶體，係將汲極和該第1端子連 接，而閘極被施加選擇信號；及並列地設置之第1記憶元 件及第2記憶元件，係浮動閘極型的1層多晶矽電晶體， 汲極和該選擇電晶體的源極連接，而源極和第2端子連 接；並具備有：電晶體形成部，係朝向第1方向依序串列 © 地配置：形成該選擇電晶體之汲極的第In型擴散層、形成 該選擇電晶體之閘極的第1多晶矽、形成該選擇電晶體之 源極及該第1記憶元件之汲極的第2η型擴散層、形成該第 1記憶元件之浮動閘極的第2多晶矽、形成該第1記億元 件之源極及該第2記憶元件之源極的第3η型擴散層、形成 該第2記憶元件之浮動閘極的第3多晶矽、以及形成該第 2記憶元件之汲極的第4η型擴散層；第1金屬配線，係經 由接點而和該第In型擴散層連接，並配置在對該第1方向 〇 垂直的方向；第2金靥配線，係經由接點而分別和該第2n 型擴散層及第4n型擴散層連接，並配置在和該第1方向相 同的方向；以及第3金靥配線，係經由接點而和該第3n型 擴散層連接，並配置在對該第1方向垂直的方向；同時在 該複數個非揮發性半導體記憶胞元的配置，將彼此共用該 第In型擴散層及該第1金屬配線，並對該第！金屬配線在 該第1方向對稱地配置的2個該非揮發性記憶胞元作爲配 置的基本單位；將該配置的基本單位排列配置成陣列狀； -68- 201010062 在和該第1方向垂直的方向相鄰之非揮發性半導體記憶胞 元的該第1多晶矽及該第3金屬配線各自在和該第1方向 垂直的方向直線狀地連接。 (61)又，本發明之一形態的非揮發性半導體記憶裝置，其 配置複數個由MOS電晶體所構成的非揮發性半導體記憶 胞元而構成，而該MOS電晶體以和在半導體基板上形成邏 輯電路之CMOS電晶體相同的製程構成，該非揮發性半導 體記憶胞元具有：選擇電晶體，係將汲極和該第1端子連 Ο 接，而閘極被施加選擇信號；及並列地設置之第1記億元 件、第2記憶元件以及第3記憶元件，係浮動閘極型的1 層多晶矽電晶體，汲極和該選擇電晶體的源極連接，而源 極和第2端子連接；該非揮發性半導體記憶胞元在構成部 分的布置上具備有：電晶體形成部，係朝向第’1方向依序 串列地配置：形成該選擇電晶體之汲極的第In型擴散層、 形成該選擇電晶體之閘極的第1多晶矽、形成該選擇電晶 體之源極及該第1記憶元件之汲極的第2n型擴散層、形成 〇 該第1記憶元件之浮動閘極的第2多晶矽、形成該第1記 憶元件之源極及該第2記憶元件之源極的第3n型擴散層、 形成該第2記憶元件之浮動閘極的第3多晶矽、形成該第 2記憶元件之汲極及該第3記憶元件之汲極的第4η型擴散 層、形成該第3記憶元件之浮動閘極的第4多晶矽、以及 形成該第3記憶元件之源極的第5η型擴散層；第1金屬配 線’係經由接點而和該第In型擴散層連接，並配置在對該 第1方向垂直的方向第2金靥配線，係經由接點而分別 和該第2n型擴散層及第4n型擴散層連接，並配置在和該 -69- 201010062 第1方向相同的方向；第3金屬配線，係經由接點而和該 第3n型擴散層連接，並配置在對該第1方向垂直的方向； 以及第4金屬配線，係經由接點而和該第5ri型擴散層連 接，並配置在對該第1方向垂直的方向；同時在該非揮發 性半導體記憶胞元的配置，將共用該第In型擴散層及該第 1金屬配線，並對該第1金屬配線在該第1方向對稱地配 置，而且共用該第5n型擴散層及該第4金屬配線，並對該 第4金屬配線在該第1方向對稱地配置的複數個該非揮發 性半導體記憶胞元作爲行；在對該第1方向垂直的方向平 © 行地排列該行，而將該非揮發性半導體記憶胞元配置成陣 列狀；該行具備有第5金屬配線，其和各個該行所包含之 該非揮發性半導體記憶胞元所具備的該第1金屬配線連 接，並沿著該行而在該第1方向配置；在對該第1方向垂 直的方向相鄰之該非揮發性半導體記憶胞元的該第1多晶 矽、該第3金屬配線以及該第4金靥配線各自在對該第1 方向垂直的方向直線狀地連接。 【發明之效果】 〇 在本發明之非揮發性半導體記憶元件及非揮發性半導 體記憶裝置，能以標準邏輯元件的CMOS製程實現非揮發 性記憶體，同時可緊密地配置面積變大的電容器（在浮動閘 極和半導體基板表面所形成之電容器），並使記憶胞元及記 憶胞元陣列的面積變成最小限度。 又，本發明之非揮發性半導體記憶元件及非揮發性半 導體記憶裝置，能以標準邏輯元件的CMOS製程實現非揮 發性記憶體，同時可提供1層多晶矽構成的OTP (One Time -70- 201010062 P r 〇 g r am m ab 1 e R Ο Μ)及 MTP(Multi Time Programmable ROM)。 又，在非揮發性半導體記憶元件，可緊密地配置面積 變大的電容器（在浮動閘極和半導體基板表面所形成之電 容器），並使面積變成最小限度。因而，可使記憶胞元及記 憶胞元陣列的面積變成最小限度。 又，若依據本發明，在使用將複數個浮動閘極型電晶 體並列地連接而構成非揮發性半導體記憶胞元的情況，可 Ο 易於得到適合1層多晶矽製程的布置。因此，例如以標準 邏輯元件的CMOS製程可實現具有可靠性的非揮發性半導 體記憶胞元及裝置，可得到例如易於或便宜地實現邏輯元 件混載記憶體。 又，若依據本發明，使用標準CMOS製程，可實現小 的配置面積而且提高記憶保持之可靠性的非揮發性半導體 記憶胞元及使用該記憶胞元的非揮發性半導體記憶裝置， 並可易於或便宜地實現邏輯元件混載記憶體。 〇 【實施方式】 以下，參照附加圖面，說明本發明之實施形態。 [第1實施形態] 第1A圖〜第1E圖係本發明之第1實施形態之非揮發 性半導體記憶元件的構成圖，係表示EEPROM胞元之例子 的圖。此外，在以下的說明，有時將「非揮發性半導體記 憶元件」僅稱爲「記億胞元」。 第1A圖表示EEPROM胞元的平面圖。第1B圖表示等 價電路圖，第1C圖表示沿著第1A圖之A10— A10’的剖 -71- 201010062 面圖，第ID圖表示沿著B10-B10’的剖面圖，第1E圖 表示沿著C 1 0 — C 1 0 ’的剖面圖。 此EEPROM胞元如第1B圖的等價電路圖所示，由電 晶體T101 (第1電晶體）、電晶體T102(第2電晶體）以及電 容器C101所構成，並具有汲極D100、源極S100、選擇閘 極SG100、控制閘極CG100以及浮動閘極FG10(^C101是 控制閘極CG100和浮動閘極FG100之間的電容器。 在構造上，在第1A圖〜第1E圖，1001是p型半導體 基板，1002是形成於p型半導體基板1001上的η型井 © (n-well)，1003是構成第1電晶體Τ101的MOS電晶體（第 1閘極區域部），1004是構成第2電晶體T102的浮動閘極 型電晶體（第2閘極區域部），1〇〇5是構成電晶體T101之汲 極的η型汲極擴散層，1〇〇6是電晶體T101的源極，亦成 爲電晶體Τ102之汲極的η型擴散層，1007是成爲電晶體 Τ102之源極的η型擴散層，1008是成爲電晶體Τ101之閘 極的多晶矽層，1009是成爲電晶體Τ102之浮動閘極的多 晶矽層’並成爲電容器C101的一端。1010是連接擴散層 Q 1 0 05和金屬配線1012的接點，1012是用以拉出電晶體 Τ101之汲極D100的金屬配線，1〇13是用以拉出浮動閘極 型電晶體Τ102之源極S1 〇〇的金屬配線，1014是電容器 C101’1015是ρ型擴散層，並成爲電容器cl01的另一端。 1016是連接p型擴散層ι〇15和控制閘極配線（金屬配 線）1019的接點，1017是形成於η型井1〇〇2上的η型擴散 層’ 1018是連接η型擴散層1〇17和控制閘極配線（金屬配 線）1019的接點，1019是成爲控制閘極配線的金屬配線， -72- 201010062 1 020是分離用絕緣氧化膜》 此記憶胞元的特徵如圖所示，在縱向（在圖面上爲上下 方向）配置電晶體形成部1030，其包含有電晶體T101之η 型擴散層1005、是電晶體Τ101的源極並亦成爲Τ1 02之汲 極的η型擴散層1006、以及成爲電晶體Τ102之源極的η 型擴散層1007等。又，成爲位元線之記憶胞元之汲極的金 屬配線1012亦在縱向配置。而，在橫向（在圖面上爲左右 方向）配置成爲選擇閘極的多晶矽層1〇〇8、及控制閘極配線 Ο (金屬配線）1019，又，緊密地配置面積變大之電容器 C101(由 1002、1009、1014、1015、1016 等所構成），使記 憶胞元的面積變成最小限度。 第2Α圖及第2Β圖係用以說明第1 Α圖〜第1Ε圖所示 之記憶胞元的動作圖。以下，參照第2A圖及第2B圖，說 明其動作。 關於對記憶胞元的寫入，有2種方式。第1種方法是 藉熱電子注入的寫入方式。作爲寫入1—1，對選擇閘極 Q SG100施加8V，對控制閘極CG100施加3~8V，對汲極D100 施加5V，對源極S100施加0V。對汲極及閘極施加高電壓， 爲了在後述的飽和區域進行動作，而在汲極附近對空乏層 施加高電壓，產生熱電子，其被注入浮動閘極。因爲注入 電子，所以表面上電晶體T 1 02的臨限値變高。 在拭除的情況，預先對選擇閘極SG100偏壓至10V， 對控制閘極CG100偏壓至0V，對汲極D100偏壓至8V， 對源極S100偏壓至開路（open)或約2V。在此狀態，對汲 極和浮動鬧極之間施加局電場，而Fowler — Nordheim的穿 73- 201010062 隧電流（以下簡稱爲FN電流）流動，從浮動閘極向汲極放出 電子，而表面上看起來臨限値降低》 關於讀出，對選擇閘極SG100施加3〜5V，對控制閘極 CG100施加0V，對汲極D100施加IV，對源極S100施加 0V時，若是寫入狀態（臨限値爲正），電流不會流動，而判 斷爲“ 〇” 。若是拭除狀態（臨限値爲負），電流流動，而判 斷爲“ 1” 。 第3A圖係表示第1 A〜第1E圖所示之記憶胞元之電晶 體T1 02的特性圖，作爲僅電晶體T1 02的特性，表示VCG © —Id特性。第3B圖係表示第1A圖所示之記憶胞元之電晶 體T102的構成圖。 起始的臨限値是約IV。進行寫入時，因爲電子被注入 浮動閘極內，所以如圖所示，顯示表面上臨限値升高至3V 的特性。又，拭除時，顯示表面上臨限値下降至- 2V的特 性。 在此，將該寫入電壓設爲3~8V，是因爲電晶體T102 被過度拭除時，如後述所示，浮動閘極帶正電，所以在寫 ❹ 入時，若將控制閘極CG 100設爲太高的電壓，就進入非飽 和區域，難產生熱電子，而具有寫入特性變差的問題。 在此情況，如後述所示，可採用步升寫入方式，其在 過度拭除狀態時，將控制閘極CG 100的電壓設定成稍低， 若要寫入，和寫入量合倂，而使控制閘極CG 100的電壓逐 漸升高。 如此，在第1實施形態所示之本發明的非揮發性半導 體記憶元件，在對浮動閘極1 009儲存電荷時，對第1電晶 -74- 201010062 體ΤΙ 01的閘極施加第1高電壓（例如8V)，對汲極施加第2 高電壓（例如5V)，對第2電晶體T102的控制閘極CG100 施加第3高電壓（3~8V)，對源極S100施加“ 0” V的電壓， 藉此，在第2電晶體T102之汲極附近產生熱電子，並注入 浮動閘極1009。又，在拭除浮動閘極1009所儲存之電荷 時，對第1電晶體T101的選擇閘極SG100施加第4髙電 壓（例如10V)，對汲極施加第5高電壓（例如8V)，對第2 電晶體T102的控制閘極CG100施加“0” V，使源極S100 Ο 變成開路，或施加第6高電壓（例如2V)，藉此，對第2電 晶體T102之汲極附和浮動閘極之間施加高電場，而使從浮 動閘極向汲極放出電荷。 因而，除了可緊密地配置面積變大之電容器（在浮動閘 極和半導體基板表面所形成之電容器）使面積變成最小限 度之效果以外，還可易於對浮動閘極儲存電荷及從浮動閘 極放出電荷。 第4A圖係表示第1A圖〜第1E圖所示之記憶胞元之電 〇 晶體T101及T102的特性圖，表示將電晶體T101及T102 串接的特性。第4B圖係表示第1A圖所示之記憶胞元之電 晶體T1 01及T1 02的構成圖。 在此情況，讀出時，因爲控制閘極 CG100是 「CG10 0 = 0V」，所以若T102之臨限値的起始値爲約IV， VSG- Id特性（記憶胞元的特性）是電流幾乎不流動之狀 態。進行寫入時，電流完全不流動。在拭除時（拭除狀態 時），因爲T 1 02總是導通狀態，所以作爲記憶胞元特性， 和控制閘極CG 100的電壓成正比的電流流動。 -75- 201010062 此外，將寫入亦以FN電流進行的情況設爲寫入方式1 —2。在此情況，若對選擇閘極SG100施加5V，對控制閘 極CG100施加15V，對汲極D100施加0V，對源極S100 設爲開路或施加0V，則對通道和浮動閘極間施加高電壓， 而注入電子。 第5A圖表示此記憶p元之耦合系統的等價電路。第 5B圖係表示第5A圖之記憶胞元的構成圖。若浮動閘極之 狀態爲起始狀態（中性狀態），因爲此系統之總電荷爲零， 所以若(VCG100 — VFG100)xC100(FC100) + (VSubl00 - 〇 VFG100)xC100(FB100) + (VD100-VFG100)xC100(FD100) +The same process composition, the plurality of non-volatile semi-conducting selective crystals, wherein the drain electrode and the first terminal are connected with a selection signal; and a plurality of memory-type 1-layer polycrystalline germanium transistors arranged side by side, the drain and In the case of the selective connection, the source is connected to the second terminal; in the case of the complex data, the pass is made according to the selection signal, and the first voltage is applied to the first terminal, and the voltage lower than the first voltage is applied. Writing is performed; when the data is erased from Q, the data is turned on according to the selection signal, and the first terminal is opened to be erased than the first terminal and the second terminal is opened; and the reading is performed. When the data is output, the selection signal is turned on, and the second terminal is applied to read the second terminal; and the memory cell array is arranged, and the conductor memory cells are arranged in an array; the plurality of connections are connected The plurality of non-volatile semiconductor memory cells - 66 - 201010062 yuan of the 汲 terminal; a plurality of rows of select gates, and each of the plurality of 汲 线 line connection; data output into the line, through the plurality of lines of choice Extremely and plural a line connection; a sense amplifying circuit that amplifies the data of the non-volatile semiconductor memory cell read out by the data input and output to the outside; and selects a plurality of gate lines to connect the plurality of columns in common a non-volatile semiconductor memory cell having a gate of the selected transistor: a plurality of source lines are connected to the source terminal of the plurality of non-volatile semiconductor memory cells; and a control unit Switching the conduction and non-conduction of the row selection gate according to the address signal of the input area and the command signal indicating the operation input from the external port, and selecting the gate line and the plurality of source lines for the plurality of lines Apply voltage. (5) Further, the non-volatile semiconductor memory device according to one aspect of the present invention may further include a source driver connected to all of the plurality of source lines: in the plurality of non-volatile semiconductor memory cells In the case where all are erased together, the control unit applies a voltage to the plurality of select gate lines of the plurality of non-volatile semiconductor memory cells to make the selected transistor a non-conducting voltage, and the source driver A voltage lower than the first voltage is applied. (5) Further, in the non-volatile semiconductor memory device of one aspect of the present invention, the plurality of non-volatile semiconductor memory cells may be divided into a plurality of blocks in column units; and the plurality of non-volatile semiconductor memory cells are provided a source driver connected to the source line; in the case of performing a block erase of the non-volatile semiconductor memory cell of the plurality of columns, the control portion of the plurality of non-volatile semiconductor memory cells All of the strip selection gate lines cause the select transistor to become a non-conducting voltage, and the plurality of source drivers apply a lower voltage than the first voltage. Further, a nonvolatile semiconductor memory device according to an aspect of the present invention is configured by arranging a plurality of nonvolatile semiconductor memory cells composed of MOS transistors, and the MOS transistor is configured by And a process of forming the same circuit as the CMOS transistor forming the logic circuit on the semiconductor substrate, the non-volatile semiconductor memory cell having: selecting the transistor, connecting the drain to the first terminal, and applying a selection signal to the gate; and The first memory element and the second memory element which are arranged in parallel are a floating gate type one-layer polysilicon transistor, the drain is connected to the source of the selection transistor, and the source is connected to the second terminal; The transistor forming portion is arranged in series with the first direction: an In-type diffusion layer forming a drain of the selected transistor, and a first polysilicon forming a gate of the selected transistor, forming the selection a second n-type diffusion layer of a source of the transistor and a drain of the first memory element, a second polysilicon forming a floating gate of the first memory element, a source forming the first memory element, and the second Memory component a third n-type diffusion layer of a source, a third polysilicon forming a floating gate of the second memory element, and a fourth n-type diffusion layer forming a drain of the second memory element; the first metal wiring is via a contact And connected to the first In-type diffusion layer, and arranged in a direction perpendicular to the first direction ;; the second metal wiring is connected to the second n-type diffusion layer and the fourth n-type diffusion layer via contacts, respectively. And arranged in the same direction as the first direction; and the third metal wiring is connected to the third n-type diffusion layer via a contact, and is disposed in a direction perpendicular to the first direction; and at the same time The arrangement of the non-volatile semiconductor memory cells shares the first In-type diffusion layer and the first metal wiring with each other, and the first! Two non-volatile memory cells arranged symmetrically in the first direction in the metal wiring are used as a basic unit of arrangement; the basic unit arrangement of the arrangement is arranged in an array; -68-201010062 is perpendicular to the first direction The first polysilicon and the third metal wiring of the adjacent non-volatile semiconductor memory cells are linearly connected in a direction perpendicular to the first direction. (61) Further, a nonvolatile semiconductor memory device according to an aspect of the present invention is configured by arranging a plurality of non-volatile semiconductor memory cells composed of MOS transistors, and the MOS transistors are on a semiconductor substrate Forming the same process of the CMOS transistor forming the logic circuit, the non-volatile semiconductor memory cell having: selecting the transistor, connecting the drain terminal and the first terminal, and applying a selection signal to the gate; and setting in parallel The first billion element, the second memory element, and the third memory element are floating gate type one-layer polysilicon transistors, the drain is connected to the source of the selection transistor, and the source is connected to the second terminal; The non-volatile semiconductor memory cell includes, in the arrangement of the constituent portions, a transistor forming portion which is arranged in series in the '1 direction, and forms an In-type diffusion layer which forms a drain of the selected transistor, and is formed. Selecting a first polysilicon of a gate of the transistor, a second n-type diffusion layer forming a source of the selective transistor and a drain of the first memory element, and forming a floating gate of the first memory element a polysilicon, a third n-type diffusion layer forming a source of the first memory element and a source of the second memory element, a third polysilicon forming a floating gate of the second memory element, and a second memory element forming the second memory element a fourth n-type diffusion layer having a drain and a drain of the third memory element, a fourth polysilicon forming a floating gate of the third memory element, and a fifth n-type diffusion layer forming a source of the third memory element; The first metal wiring is connected to the first In-type diffusion layer via a contact, and is disposed in a second metal wiring in a direction perpendicular to the first direction, and is connected to the second n-type diffusion layer via a contact. The fourth n-type diffusion layer is connected and arranged in the same direction as the first direction of the -69-201010062; the third metal wiring is connected to the third n-type diffusion layer via the contact, and is disposed in the first direction The fourth metal wiring is connected to the fifth ri type diffusion layer via a contact, and is disposed in a direction perpendicular to the first direction; and the nonvolatile semiconductor memory cell is disposed in common. The first In type diffusion layer and the first metal And arranging the first metal wiring symmetrically in the first direction, and sharing the fifth n-type diffusion layer and the fourth metal wiring, and arranging the fourth metal wiring symmetrically in the first direction The non-volatile semiconductor memory cells are arranged as rows; the rows are arranged in a line perpendicular to the first direction, and the non-volatile semiconductor memory cells are arranged in an array; the row is provided with a fifth metal wiring, And connecting to the first metal wiring included in the non-volatile semiconductor memory cell included in each row, and arranged in the first direction along the row; adjacent to the direction perpendicular to the first direction The first polysilicon, the third metal wiring, and the fourth metal wiring of the nonvolatile semiconductor memory cell are linearly connected in a direction perpendicular to the first direction. [Effects of the Invention] In the non-volatile semiconductor memory device and the non-volatile semiconductor memory device of the present invention, non-volatile memory can be realized by a CMOS process of a standard logic element, and a capacitor having a large area can be closely arranged ( The capacitor formed on the floating gate and the surface of the semiconductor substrate) minimizes the area of the memory cell and the memory cell array. Moreover, the non-volatile semiconductor memory device and the non-volatile semiconductor memory device of the present invention can realize non-volatile memory in a CMOS process of standard logic components, and can provide OTP composed of one-layer polysilicon (One Time -70- 201010062) P r 〇gr am m ab 1 e R Ο Μ) and MTP (Multi Time Programmable ROM). Further, in the nonvolatile semiconductor memory element, a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate) can be closely arranged, and the area can be minimized. Thus, the area of the memory cell and the memory cell array can be minimized. Further, according to the present invention, in the case where a plurality of floating gate type electric crystals are connected in parallel to form a nonvolatile semiconductor memory cell, an arrangement suitable for a one-layer polysilicon process can be easily obtained. Thus, for example, a non-volatile semiconductor memory cell and device having reliability can be realized by a CMOS process of standard logic elements, for example, it is easy or inexpensive to implement logic element mixed memory. Moreover, according to the present invention, a non-volatile semiconductor memory cell having a small configuration area and improving the reliability of memory retention and a non-volatile semiconductor memory device using the memory cell can be realized by using a standard CMOS process, and can be easily Or logically implement a logical component to mix memory. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to additional drawings. [First Embodiment] Fig. 1A to Fig. 1E are diagrams showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, showing an example of an EEPROM cell. In addition, in the following description, the "non-volatile semiconductor memory element" may be simply referred to as "the billion cell". Figure 1A shows a plan view of an EEPROM cell. 1B is an equivalent circuit diagram, and FIG. 1C is a cross-sectional view taken along line A-A10' of FIG. 1A-71-201010062, and the ID diagram is a cross-sectional view along B10-B10'. A cross-sectional view of C 1 0 - C 1 0 '. The EEPROM cell is composed of a transistor T101 (first transistor), a transistor T102 (second transistor), and a capacitor C101 as shown in the equivalent circuit diagram of FIG. 1B, and has a drain D100 and a source S100. Select gate SG100, control gate CG100, and floating gate FG10 (^C101 is a capacitor between control gate CG100 and floating gate FG100. In construction, in 1A to 1E, 1001 is p-type The semiconductor substrate 1002 is an n-type well (n-well) formed on the p-type semiconductor substrate 1001, 1003 is an MOS transistor (first gate region portion) constituting the first transistor Τ101, and 1004 is a second structure. The floating gate type transistor (second gate region portion) of the transistor T102, 1〇〇5 is an n-type drain diffusion layer constituting the drain of the transistor T101, and 1〇〇6 is the source of the transistor T101. Also, it is an n-type diffusion layer which is a drain of the transistor Τ102, 1007 is an n-type diffusion layer which becomes a source of the transistor Τ102, 1008 is a polysilicon layer which becomes a gate of the transistor Τ101, and 1009 is a transistor Τ102. The polysilicon layer of the floating gate 'and becomes one end of the capacitor C101. 1010 is a connection diffusion layer The junction of Q 1 0 05 and metal wiring 1012, 1012 is the metal wiring for pulling out the drain D100 of the transistor Τ101, and the 1〇13 is for pulling out the source S1 of the floating gate type transistor Τ102. The metal wiring 1014 is a capacitor C101'1015 which is a p-type diffusion layer and becomes the other end of the capacitor cl01. 1016 is a contact connecting the p-type diffusion layer ι15 and the control gate wiring (metal wiring) 1019, 1017 is The n-type diffusion layer '1018 formed on the n-type well 1〇〇2 is a contact connecting the n-type diffusion layer 1〇17 and the control gate wiring (metal wiring) 1019, and 1019 is a metal wiring which becomes a control gate wiring. -72- 201010062 1 020 is an insulating oxide film for separation. The characteristics of this memory cell are as shown in the figure. The transistor forming portion 1030 is disposed in the vertical direction (upward and downward in the drawing), and includes a transistor T101. The n-type diffusion layer 1005 is an n-type diffusion layer 1006 which is also a source of the transistor 101 and also serves as a drain of the transistor 102, and an n-type diffusion layer 1007 which becomes a source of the transistor 102. Further, it becomes a bit line. The metal wiring 1012 of the memory cell is also arranged in the vertical direction. Further, in the lateral direction (the left and right directions on the drawing), the polysilicon layer 1〇〇8 which is a gate is selected, and the gate wiring Ο (metal wiring) 1019 is controlled, and the capacitor C101 having a large area is closely arranged. (consisting of 1002, 1009, 1014, 1015, 1016, etc.), the area of memory cells is minimized. The second diagram and the second diagram are diagrams for explaining the operation of the memory cells shown in the first to the first diagrams. Hereinafter, the operation will be described with reference to Figs. 2A and 2B. There are two ways to write to memory cells. The first method is a write method by hot electron injection. As write 1-1, 8V is applied to the selection gate Q SG100, 3 to 8V is applied to the control gate CG100, 5V is applied to the drain D100, and 0V is applied to the source S100. A high voltage is applied to the drain and the gate, and a high voltage is applied to the depletion layer in the vicinity of the drain in order to operate in a saturation region to be described later, and hot electrons are generated, which are injected into the floating gate. Because of the injection of electrons, the threshold 电 of the transistor T 1 02 on the surface becomes high. In the case of erasing, the selection gate SG100 is biased to 10V in advance, the control gate CG100 is biased to 0V, the drain D100 is biased to 8V, and the source S100 is biased to open or about 2V. . In this state, a local electric field is applied between the drain and the floating pole, and Fowler — Nordheim's 73-201010062 tunneling current (hereinafter referred to as FN current) flows, and the electrons are discharged from the floating gate to the drain, and on the surface. It seems that the readout is about 3 to 5V for the selection gate SG100, 0V for the control gate CG100, IV for the drain D100, and 0V for the source S100, if it is the write state (Pro The limit is positive), the current does not flow, and it is judged as “〇”. If it is erased (the threshold is negative), the current flows and the judgment is "1". Fig. 3A is a characteristic diagram showing the crystal cell T1 02 of the memory cell shown in Figs. 1A to 1E, and shows the VCG © -Id characteristic as the characteristic of only the transistor T1 02. Fig. 3B is a view showing the configuration of the crystal cell T102 of the memory cell shown in Fig. 1A. The initial threshold is about IV. When writing is performed, since electrons are injected into the floating gate, as shown in the figure, the characteristic of the display surface is raised to 3V. Also, when erasing, the characteristic of the surface is lowered to -2V. Here, the write voltage is set to 3 to 8 V. When the transistor T102 is excessively erased, as will be described later, the floating gate is positively charged. Therefore, when the write is in progress, the gate CG is controlled. When 100 is set to a voltage that is too high, it enters an unsaturated region, and it is difficult to generate hot electrons, and there is a problem that writing characteristics are deteriorated. In this case, as will be described later, a step-up writing method may be employed in which the voltage of the control gate CG 100 is set to be slightly lower in the over-erased state, and the writing and the writing amount are combined. The voltage of the control gate CG 100 is gradually increased. As described above, in the nonvolatile semiconductor memory device of the present invention shown in the first embodiment, when the charge is stored in the floating gate 1 009, the first gate is applied to the gate of the first transistor -74 - 201010062 body ΤΙ 01. A voltage (for example, 8 V) applies a second high voltage (for example, 5 V) to the drain, a third high voltage (3 to 8 V) to the control gate CG100 of the second transistor T102, and a "0" V to the source S100. The voltage is thereby generated by generating hot electrons near the drain of the second transistor T102 and injecting the floating gate 1009. When the charge stored in the floating gate 1009 is erased, a fourth voltage (for example, 10 V) is applied to the selection gate SG100 of the first transistor T101, and a fifth high voltage (for example, 8 V) is applied to the drain. The control gate CG100 of the second transistor T102 applies "0" V to turn the source S100 Ο into an open circuit or a sixth high voltage (for example, 2 V), whereby the drain of the second transistor T102 is attached to the floating gate. A high electric field is applied between the poles to discharge charge from the floating gate to the drain. Therefore, in addition to the effect of tightly arranging a capacitor having a large area (a capacitor formed on the floating gate and the surface of the semiconductor substrate) to minimize the area, it is also easy to store and discharge the charge from the floating gate. Charge. Fig. 4A is a characteristic diagram showing the electric crystals T101 and T102 of the memory cells shown in Figs. 1A to 1E, showing the characteristics in which the transistors T101 and T102 are connected in series. Fig. 4B is a view showing the configuration of the transistors T1 01 and T1 02 of the memory cells shown in Fig. 1A. In this case, at the time of reading, since the control gate CG100 is "CG10 0 = 0V", if the starting 値 of the threshold T of T102 is about IV, the VSG-Id characteristic (characteristic of the memory cell) is almost current. The state of no flow. When writing, the current does not flow at all. At the time of erasing (when the state is erased), since T 1 02 is always in an on state, as a memory cell characteristic, a current proportional to the voltage of the gate CG 100 is controlled to flow. -75- 201010062 In addition, the case where the write is also performed with the FN current is set to the write mode 1-2. In this case, if 5V is applied to the selection gate SG100, 15V is applied to the control gate CG100, 0V is applied to the drain D100, and the source S100 is set to be open or 0V is applied, a high voltage is applied between the channel and the floating gate. While injecting electrons. Fig. 5A shows an equivalent circuit of the coupling system of this memory p-element. Fig. 5B is a view showing the configuration of the memory cell of Fig. 5A. If the state of the floating gate is the initial state (neutral state), because the total charge of this system is zero, if (VCG100 - VFG100)xC100(FC100) + (VSubl00 - 〇VFG100)xC100(FB100) + (VD100 -VFG100)xC100(FD100) +
(VS 1 00 - VFG1 00)xC100(FS100) = 0C、 (FC 1 00) + C 1 00(FB 100) + C100(FS100) = CT100(總和），貝IJ VFG100 = VCG100xC100(FC100)/CTlO0 + VSubl00xC10 0(FB100)/CT100 + VD100xC100(FD100)/CT100 + VS100xC10 0(FS100)/CT100 在此，若 C100(FD100)=C100(FS100)=0 ' VSubl00=(VS 1 00 - VFG1 00)xC100(FS100) = 0C, (FC 1 00) + C 1 00 (FB 100) + C100(FS100) = CT100 (sum), Bay IJ VFG100 = VCG100xC100(FC100)/CTlO0 + VSubl00xC10 0(FB100)/CT100 + VD100xC100(FD100)/CT100 + VS100xC10 0(FS100)/CT100 Here, if C100(FD100)=C100(FS100)=0 'VSubl00=
vsioo=o ，則 Q VFG100 = VCG100xC100(FC100)/{C100(FC100) + C100( FB 1 00)} 在此，若 C100(FC100)/{C100(FC100) + C100(FB100)} =a 100(耦合比），則 VFG100=a 100xVCG100。 —般，設定成a 100与0.6。 此外，電晶體T101相當於上述之第1電晶體，電晶體 T102相當於上述之第2電晶體。又，η型擴散層1005相當 -76- 201010062 於上述之成爲第1電晶體的汲極之第In型擴散層，η型擴 散層1006相當於上述之第2η型擴散層，η型擴散層1007 相當於上述之第3η型擴散層。又，在MOS電晶體1003之 第In型擴散層1005和第2η型擴散層1006之間的區域相 當於上述之第1閘極區域部，在浮動閘極型電晶體1〇〇4之 第2η型擴散層1 006和第3η型擴散層1 007之間的區域相 當於上述之第2閘極區域部。又，金屬配線1012相當於上 述之第1金屬配線，多晶矽層1〇〇8相當於上述的多晶矽 Ο 層，金屬配線1013於上述之第2金屬配線（在第2實施形 態~第12實施形態亦相同）。 又，在對浮動閘極儲存電荷時（寫入時），第2Β圖之動 作表所示之選擇閘極SG100的電壓“8” V相當於上述之 施加於第1電晶體之閘極的第1高電壓，汲極D1 00的電壓 “ 5 ” V相當於上述之施加於汲極的第2電壓，控制閘極 CG100的電壓"3〜8” V相當於上述之施加於控制閘極的 第3電壓。又，在拭除對浮動閘極的電荷時，選擇閘極SG100 〇 的電壓“10” ν相當於上述之施加於第1電晶體之閘極的 第4電壓，汲極D1 00的電壓“ 8” V相當於上述之施加於 第1電晶體之汲極的第5電壓，源極S100的電壓“2” V 相當於上述之施加於第2電晶體之源極的第6電壓。 而，在半導體基板表面上的第1方向（在第1Α圖上爲 上下方向），配置形成第1電晶體和第2電晶體的電晶體形 成部1030。此電晶體形成部1030由上依序配置：成爲第1 電晶體Τ101之汲極的第In型擴散層1005、形成第1電晶 體之通道的第1閘極區域部1〇〇3(第1擴散層1005和第2 -77- 201010062 擴散層1006之中間的區域）、是第1電晶體T101的源極並 亦成爲第2電晶體之汲極的第2ιι型擴散層1 006、形成第2 電晶體T102之通道的第2閘極區域部（第2擴散層1〇〇5和 第3擴散層1007之中間的區域）、以及成爲源極的第3n 型擴散層1 007。 在此電晶體形成部1030的左側，在上下方向配置第1 金屬配線1012。 此金屬配線1012從半導體基板表面隔著既定之距離 配置成和電晶體形成部1030平行，又，金屬配線1012利 ® 用接點和第1電晶體的汲極（第In型擴散層1005)連接。 又，在左右方向形成多晶矽層1008,使其和第1電晶體T101 的第1閘極區域部相對向。 在電晶體形成部1030的左側，以既定之寬度和深度在 左右方向所形成方形的η型井1002。方形的浮動閘極1009 在左右方向配置成和半導體基板表面相對向，同時配置成 其左端部側的區域和η型井1002的表面相對向，且右端部 側的區域和第2電晶體的第2閘極區域部（第2η型擴散層 Q 1 006和第3η型擴散層1 007之中間的通道形成區域）相對 向。 在η型井1 0 02的左側，在左右方向形成ρ型擴散層 1015，其和與此η型井1002的浮動閘極1009相對向之區 域的左側相鄰，並具有既定之寬度和深度。此ρ型擴散層 1 〇 1 5和控制閘極配線1 〇 1 9利用接點1 0 1 6連接。此控制閘 極配線1019從半導體基板表面隔著既定之距離在左右方 向配置成和浮動閘極100 9相對向，又，利用接點1016和 -78- 201010062 P型擴散層1015連接。第2金屬配線1013從半導體基板 表面隔著既定之距離在左右方向配置成和成爲第2電晶體 T102之源極的第3n型擴散層1007相對向，此第2金屬配 線1013利用接點1011和第3n型擴散層1007連接。 如此，在第1實施形態所示之本發明的非揮發性半導 體記憶元件，作爲非揮發性半導體記憶元件之構成，在上 下方向配置形成第1電晶體T101及第2電晶體T102的電 晶體形成部，在此電晶體形成部的左側，配置和第1電晶 〇體之汲極連接的金屬配線（位元線），又，在左右方向（橫向） 配置第1電晶體的閘極層及和第2電晶體之源極連接的金 屬配線。又，將η型井配置於電晶體形成部的左側，在左 右方向將浮動閘極配置成和此η型井的表面及第2電晶體 的第2閘極區域部（第2η型擴散層和第3η型擴散層之中間 的通道形成區域）相對向，在左右方向亦配置和對此浮動閘 極賦與電位之控制閘極端子連接的控制閘極配線。 因而，以標準邏輯元件的CMOS製程可實現非揮發性 〇 記憶體，同時可緊密地配置面積變大的電容器（在浮動閘極 和半導體基板表面所形成之電容器），使面積變成最小限 度。 · 此外，在第1A圖所示之第1實施形態，雖然金屬配線 1012配置於電晶體形成部1 03 0的左側，但是亦可配置於 正上或右側。 [第2實施形態] 第6圖係表示本發明之第2實施形態的非揮發性半導 體記憶裝置的構成圖。第6圖所示的例子是將本發明之非 -79- 201010062 揮發性半導體記憶元件（記憶胞元）裝入陣列（記憶胞元陣 列）之EEPROM的例子。 在第6圖所示之記憶胞元陣列的構成，採用10- 100〜 10 - 107之8位元構成，將記憶胞元Mill — 0~M1 1 1 — 7、~、Vsioo=o , then Q VFG100 = VCG100xC100(FC100)/{C100(FC100) + C100( FB 1 00)} Here, if C100(FC100)/{C100(FC100) + C100(FB100)} =a 100( Coupling ratio), then VFG100=a 100xVCG100. Generally, it is set to a 100 and 0.6. Further, the transistor T101 corresponds to the first transistor described above, and the transistor T102 corresponds to the second transistor described above. Further, the n-type diffusion layer 1005 corresponds to -76-201010062 as the first In-type diffusion layer which becomes the drain of the first transistor, and the n-type diffusion layer 1006 corresponds to the above-described second n-type diffusion layer, and the n-type diffusion layer 1007 It corresponds to the above-described third n-type diffusion layer. Further, a region between the In-type diffusion layer 1005 and the second n-type diffusion layer 1006 of the MOS transistor 1003 corresponds to the first gate region portion described above, and the second gate of the floating gate transistor 1〇〇4 The region between the type diffusion layer 1 006 and the third n-type diffusion layer 1 007 corresponds to the second gate region described above. Further, the metal wiring 1012 corresponds to the first metal wiring described above, the polysilicon layer 1〇〇8 corresponds to the above polysilicon layer, and the metal wiring 1013 is to the second metal wiring (in the second embodiment to the twelfth embodiment) the same). Further, when the charge is stored in the floating gate (at the time of writing), the voltage "8" V of the selection gate SG100 shown in the operation table of the second drawing corresponds to the above-described gate applied to the first transistor. 1 high voltage, the voltage of the drain D1 00 "5" V corresponds to the above-mentioned second voltage applied to the drain, and the voltage of the control gate CG100 "3~8" V is equivalent to the above-mentioned application to the control gate The third voltage. Further, when the charge to the floating gate is erased, the voltage "10" ν of the gate SG100 选择 is selected to correspond to the fourth voltage applied to the gate of the first transistor, and the drain D1 00 The voltage "8" V corresponds to the fifth voltage applied to the drain of the first transistor, and the voltage "2" V of the source S100 corresponds to the sixth voltage applied to the source of the second transistor. On the other hand, in the first direction on the surface of the semiconductor substrate (in the vertical direction on the first side view), the transistor forming portion 1030 in which the first transistor and the second transistor are formed is disposed. The transistor forming portion 1030 is placed on the substrate. Sequence configuration: an In-type diffusion layer 1005 which becomes a drain of the first transistor Τ101, and forms a first transistor The first gate region 1〇〇3 of the channel (the region between the first diffusion layer 1005 and the second-77-201010062 diffusion layer 1006) is the source of the first transistor T101 and also serves as the second transistor. The second type of diffusion layer 1 006 of the drain, the second gate region portion (the region between the second diffusion layer 1〇〇5 and the third diffusion layer 1007) forming the channel of the second transistor T102, and The third n-type diffusion layer 1 007 of the source is disposed on the left side of the transistor forming portion 1030. The first metal wiring 1012 is disposed in the vertical direction. The metal wiring 1012 is disposed to form a transistor from a surface of the semiconductor substrate with a predetermined distance therebetween. The portion 1030 is parallel, and the metal wiring 1012 is connected to the drain of the first transistor (the In-type diffusion layer 1005). The polysilicon layer 1008 is formed in the left-right direction to form the first transistor T101. The first gate region is opposed to each other. On the left side of the transistor forming portion 1030, a square n-type well 1002 is formed in the left-right direction with a predetermined width and depth. The square floating gate 1009 is arranged in the left-right direction and the semiconductor. The surface of the substrate is opposite, and is configured as its The region on the end side faces the surface of the n-type well 1002, and the region on the right end side and the second gate region of the second transistor (the second n-type diffusion layer Q 1 006 and the third n-type diffusion layer 1 007) In the middle of the n-type well 1 0 02, a p-type diffusion layer 1015 is formed in the left-right direction, which is opposite to the left side of the region opposite to the floating gate 1009 of the n-type well 1002. Adjacent, and has a predetermined width and depth. The p-type diffusion layer 1 〇1 5 and the control gate wiring 1 〇1 9 are connected by a contact 1 0 16 . The control gate wiring 1019 is disposed to face the floating gate 100 9 in the left-right direction from the surface of the semiconductor substrate with a predetermined distance, and is connected by the contact 1016 and the -78-201010062 P-type diffusion layer 1015. The second metal wiring 1013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the third n-type diffusion layer 1007 which is the source of the second transistor T102, and the second metal interconnection 1013 uses the contact 1011 and The 3n-type diffusion layer 1007 is connected. As described above, in the nonvolatile semiconductor memory device of the present invention shown in the first embodiment, the transistor forming the first transistor T101 and the second transistor T102 is formed in the vertical direction as a configuration of the nonvolatile semiconductor memory device. a metal wiring (bit line) connected to the drain of the first transistor, and a gate layer of the first transistor in the left-right direction (lateral direction) and the left side of the transistor forming portion. A metal wiring connected to the source of the second transistor. Further, the n-type well is disposed on the left side of the transistor forming portion, and the floating gate is disposed in the left-right direction with the surface of the n-type well and the second gate region portion of the second transistor (the second n-type diffusion layer and The channel forming region in the middle of the third n-type diffusion layer is opposed to each other, and the control gate wiring to which the control gate terminal of the potential is applied to the floating gate is also disposed in the left-right direction. Therefore, a non-volatile memory can be realized in a CMOS process of standard logic elements, and a capacitor having a large area (a capacitor formed on the floating gate and the surface of the semiconductor substrate) can be closely arranged to minimize the area. Further, in the first embodiment shown in Fig. 1A, the metal wiring 1012 is disposed on the left side of the transistor forming portion 1300, but may be disposed on the upper side or the right side. [Second Embodiment] Fig. 6 is a view showing the configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. The example shown in Fig. 6 is an example of incorporating the non-79-201010062 volatile semiconductor memory device (memory cell) of the present invention into an EEPROM of an array (memory cell array). The memory cell array shown in Fig. 6 is constructed by using 8-100 to 10 - 107 octaves, and the memory cells Mill_0~M1 1 1-7, ~,
Mlml — 0~Mlml — 7集中，而構成記憶胞元陣列1100 —卜 如此，以8位元單位集中，而構成至1100-n爲止。此外， 將8位元單位之記憶胞元（例如Ml 11— 0〜Ml 11- 7)稱爲記 憶胞元方塊。 從記憶胞元Ml 1 1 _ 0至Ml 1 1 - 7(8位元單位之記憶胞 〇 元方塊）各自共同連接選擇閘極SG100、控制閘極CG100 以及源極S1 00，並各自和選擇閘極配線SG 111、控制閘極 配線CG111以及源極線S101連接。其他的記憶胞元亦一 樣，記憶胞元Mlml— 0〜Mlml-7(8位元單位之記憶胞元 方塊）各自和選擇閘極配線SGlml、控制閘極配線CGlml 以及源極線S101連接，記憶胞元Mlln— 0~Μ11η-7各自 和選擇閘極配線SGI In、控制閘極配線CGI In以及源極線 S10n連接，記憶胞元Mlmn—0~Mlmn — 7各自和選擇蘭極 配線SGlmn、控制閘極配線CGlmn以及源極線S10n連接。 另一方面，根據列位址而進行選擇輸出之列解碼器 1 200— 1〜1 200-m被設定成選擇記憶胞元的選擇閘極 SG100和控制閘極CG100。列解碼器1200— 1由以下之元 件所構成，列解碼電路1 20 1，係接受列位址信號並輸出選 擇；反相器1202，係接受此列解碼電路1201的輸出並輸 出反相信號；以及位準挪移電路1 203、位準挪移電路 1205,係各自將反相器1202、N AND電路1202的輸出各自 -80- 201010062 變換成高電壓VP101、VP102。位準挪移電路1203、1205 的輸出經由選擇電路1300 — 11和選擇閘極配線SG111及 控制閘極配線C G 1 1 1連接。 選擇電路1300 - 11由以下之元件所構成，傳輸閘極電 晶體1301，係接受來自後述之行解碼器的選擇信號，並向 選擇閘極SG100傳輸位準挪移電路1 203的輸出；電晶體 1302，係在不選擇行解碼器時，將選擇閘極SG100設定成 GND(OV);電晶體1 303，係向控制閘極CG100傳輸位準挪 Ο 移電路1205的輸出；以及電晶體1304，係不選擇行解碼 器時，將控制閘極CG100設定成GND。在電晶體1301、 1 3 03，輸入行解碼電路的輸出信號 COL101，在電晶體 1 3 02、1 3 04，輸入行解碼器輸出的反相信號COLB101。 另一方面，設置根據行位址所選擇之行解碼器1 40 0-1〜1400-n，行解碼器1400-l~1400-n由根據行位址而選 擇輸出的解碼電路1401、反相器14 02以及將反相器14 02 的輸出變換成高電壓 VP103的位準挪移電路1 403所構 © 成。位準挪移電路1403的輸出是上述的信號COL101，反 相器1402的輸出是上述的信號COLB101。 此外，記憶胞元Ml 1 1 — 0〜記憶胞元Mlml— 0的汲極 和位元線BIT101 — 0連接，記憶胞元Ml 1 1 — 7〜記憶胞元 Mlml-7的汲極和位元線BIT101-7連接。位元線BIT101 —0〜BIT101 - 7各自和根據行解碼電路的輸出信號 COL101所選擇的行選擇電晶體C101-0〜C101-7連接， 行選擇電晶體C101-0〜C101— 7的另一端各自和資料輸 出入線 Datal0O~DatalO7 連接。 81 - 201010062 資料輸出入線DatalOO〜Datal07和資料輸入變換電路 1 500連接，其接受寫入資料輸入信號Dinl00~Dinl07，並 輸出寫入、拭除所需的高電壓信號VP104。又，資料輸出 入線Datal00~Datal07和將讀出資料放大並向外部輸出的 感測放大器1 600 — 0〜1600 — 7連接，並輸出輸出資料 DoutlOO〜Doutl07。關於記憶胞元陣列noo — n，亦進行一 樣的連接。 其次，說明此記憶體的動作。 例如，假設選擇記憶胞元Mill— 0~M 111— 7之8位元 © 的記憶胞元方塊。說明寫入動作。根據列位址而選擇列解 碼器1200 — 1。根據列位址而選擇列解碼電路1201，輸出 “1” 。反相器1202的輸出變成“〇” ，位準挪移電路1203 輸出VP1 01 (例如8 V)。另一方面，寫入時，因爲寫入信號 W 1 0 0爲“ 1 ” ，所以N AN D電路1 2 0 4變成“ 0 ” ，而位準 挪移電路1205輸出VP102(例如5V)。 又，根據行位址而選擇行解碼器1400- 1，解碼電路 1401輸出“ 1” ，反相器1402输出“ 0” ，位準挪移電路 〇 1403 以 COL101 信號輸出 VP103(例如 10V)。又，COLB101 輸出“0”（0V)。選擇電路1300 - 11使電晶體1301、1303 變成導通，並使電晶體1302、1304變成不導通，對選擇閘 極配線SG111供給位準挪移電路1203的輸出VP101(8V)， 對控制閘極配線CG111供給位準挪移電路1 205的輸出 VP102(5V)。 此時’寫入資料輸入信號Dinl00~Dinl07經由資料輸 入變換電路1 500，對資料輸出入線DatalOO〜Datal07供給 -82 - 201010062 寫入電壓VP 104(例如5V)。在此，若輸入Din 100= “ 0”（寫 入）、Din 100= “ 1”（禁止寫入），則資料輸出入線Data 100 變成「Datal00 = 5V」，因爲行選擇電晶體C101—0〜C101 —7變成導通，所以對位元線BIT101— 0施加5V，對BIT101 一 7施加0V。因此，對記憶胞元Ml 1 1 - 0寫入資料“ 0” ， 而臨限値變高。又，記憶胞元Mill - 7變成資料“1”（禁 止寫入），而臨限値依然低。 另一方面，行解碼器1400-11變成非選擇，因爲輸出 Ο 信號 COLlOn 變成 “〇”（0V)、COLB10n 變成 “1” ，所以 選擇電路1300 — In〜1300 — mn變成非選擇，而記憶胞元陣 列1100-n變成非選擇狀態。又，列解碼器1200-m亦變 成非選擇，因爲位準挪移電路1203、1 205的輸出變成 “ 0”（0V)，所以 Mlml — 0~Mlml—7 變成非選擇。 在此，關於寫入，若在拭除時進行過度拭除，因爲電 晶體T1 02在非飽和區域進行動作，所以初期具有難寫入的 問題。在此情況，寫入時，將控制閘極CG100的電壓（VP102) 〇 設爲最初的3V，接著3.5V、4.0V.....寫入複數次，只要 每次使VP 102的電壓逐步上昇，就可總是使在飽和區域進 行動作，結果，可達成高速寫入。 第7圖係表示電源電壓控制電路之構成圖。 在第7圖所示之電源電壓控制電路1700,〗70丨是電源 昇壓電路’由振還器（oscillator)、充電栗、電壓檢測電路 等（都未圖示）所構成。將外部電源VCC 10 0(例如3 V)作爲電 源，進行內部昇壓，而輸出VPP100(例如i〇V)。 電壓輸出電路1702由電壓檢測電路和穩壓器（都未圖 -83- 201010062 示）所構成，接受高電壓VPP100,並作爲輸出，供給VP 101、 VP102、VP103、VP104的記憶胞元所需的電壓。 第8八圖~第8C圖係表示寫入時之電壓VP102和寫入 信號Write以及控制閘極CG 100的信號波形圖。如圖所示， 電壓VP102從3V以IV步級，升高爲4V、5V、6V，並重 複輸入寫入信號 Write»每次接受此寫入信號Write的邊 緣，將寫入電壓升一級後，向控制閘極CG 100輸出。 在拭除時，因爲列解碼器1200 — 1之位準挪移電路 1 203 的輸出爲 VPIOI(IOV)、信號 W100 爲 “ 0”，所以 NAND © 電路1 204變成“1” ，位準挪移電路1 205變成“0”（0V)。 行解碼電路之輸出信號COL 101輸出VP 103(12V)，資 料輸出入線Datal00~Datal07經由資料輸入變換電路1500 而輸出VP104(8V)。又，拭除控制信號EB100變成“0” ， 記憶胞元陣列1100 — 1~1100— η中的電晶體1101~1~1101 —η變成不導通。結果，在記憶胞元Mill — 0~ Mill - 7，Mlml — 0~Mlml — 7 is concentrated, and constitutes a memory cell array 1100. Therefore, it is concentrated in 8-bit units and formed up to 1100-n. Further, a memory cell of an 8-bit unit (e.g., Ml 11 - 0 to Ml 11 - 7) is referred to as a memory cell block. From the memory cells Ml 1 1 _ 0 to Ml 1 1 - 7 (the memory cell block of the 8-bit unit) are respectively connected to the selection gate SG100, the control gate CG100, and the source S1 00, and the respective gates The pole wiring SG 111, the control gate wiring CG111, and the source line S101 are connected. The other memory cells are also the same, and the memory cells Mlml-0~Mlml-7 (the memory cell block of the 8-bit unit) are respectively connected to the selection gate wiring SGlml, the control gate wiring CGlml, and the source line S101, and the memory The cells Mlln_0~Μ11η-7 are respectively connected to the selection gate wiring SGI In, the control gate wiring CGI In, and the source line S10n, and the memory cells Mlmn_0~Mlmn-7 are respectively selected and the blue-pole wiring SGlmn is controlled. The gate wiring CGlmn and the source line S10n are connected. On the other hand, the column decoders 1 200-1 to 1 200-m which perform selection output based on the column address are set to select the selection gate SG100 of the memory cell and the control gate CG100. The column decoder 120-1 is composed of the following elements, the column decoding circuit 1 1 1 receives the column address signal and outputs the selection; the inverter 1202 receives the output of the column decoding circuit 1201 and outputs an inverted signal; And the level shifting circuit 1 203 and the level shifting circuit 1205 convert the respective outputs of the inverter 1202 and the N AND circuit 1202 to the high voltages VP101 and VP102. The outputs of the level shifting circuits 1203 and 1205 are connected to the selection gate wiring SG111 and the control gate wiring C G 1 1 1 via the selection circuits 1300-11. The selection circuits 1300 - 11 are composed of the following elements, the transmission gate transistor 1301 receives the selection signal from the row decoder described later, and transmits the output of the level shift circuit 1 203 to the selection gate SG100; the transistor 1302 When the row decoder is not selected, the selection gate SG100 is set to GND (OV); the transistor 1 303 transmits the output of the level shifting circuit 1205 to the control gate CG100; and the transistor 1304 is When the row decoder is not selected, the control gate CG100 is set to GND. In the transistors 1301, 103, the output signal COL101 of the line decoding circuit is input, and in the transistors 1 3 02, 1 3 04, the inverted signal COLB101 output from the row decoder is input. On the other hand, the row decoders 1400-1 1400-n selected according to the row address are set, and the row decoders 140-1 to 1400-n are selected by the decoding circuit 1401 which is output according to the row address. The device 14 02 and the level shifting circuit 1 403 that converts the output of the inverter 14 02 into the high voltage VP103 are constructed. The output of the level shift circuit 1403 is the above-described signal COL101, and the output of the inverter 1402 is the above-described signal COLB101. In addition, the memory cell Ml 1 1 - 0 ~ memory cell Mlml - 0 of the drain and bit line BIT101 - 0 connected, memory cell Ml 1 1 - 7 ~ memory cell Mlml-7 of the bungee and bit Line BIT101-7 is connected. The bit lines BIT101_0 to BIT101-7 are each connected to the row selection transistors C101-0 to C101-7 selected according to the output signal COL101 of the row decoding circuit, and the other ends of the row selection transistors C101-0 to C101-7 are selected. They are connected to the data input lines Datal0O~DatalO7. 81 - 201010062 Data output line DatalOO~Datal07 and data input conversion circuit 1 500 are connected, which accepts the data input signals Dinl00~Dinl07, and outputs the high voltage signal VP104 required for writing and erasing. Further, the data output lines Datal00 to Datal07 are connected to the sense amplifiers 1 600 - 0 to 1600 - 7 which amplify the read data and output to the outside, and output the output data DoutlOO to Doutl07. Regarding the memory cell array noo-n, the same connection is also made. Next, the action of this memory will be described. For example, suppose that the memory cell block of the 8-bit © of the memory cell Mill_0~M 111-7 is selected. Explain the write action. The column decoder 1200-1 is selected based on the column address. The column decoding circuit 1201 is selected in accordance with the column address, and "1" is output. The output of the inverter 1202 becomes "〇", and the level shifting circuit 1203 outputs VP1 01 (for example, 8 V). On the other hand, at the time of writing, since the write signal W 1 0 0 is "1", the N AN D circuit 1 2 0 4 becomes "0", and the level shift circuit 1205 outputs VP 102 (for example, 5 V). Further, the row decoder 140-1 is selected in accordance with the row address, the decoding circuit 1401 outputs "1", the inverter 1402 outputs "0", and the level shift circuit 〇 1403 outputs VP103 (for example, 10 V) as a COL101 signal. Also, COLB101 outputs "0" (0V). The selection circuits 1300 - 11 turn on the transistors 1301, 1303 and make the transistors 1302, 1304 non-conductive, and supply the selection gate wiring SG111 to the output VP101 (8V) of the level shift circuit 1203, and the control gate wiring CG111 The output VP 102 (5 V) of the level shifting circuit 1 205 is supplied. At this time, the write data input signals Dinl00 to Dinl07 are supplied to the data input/output lines Data100 to Datal07 via the data input conversion circuit 1500, and the write voltage VP 104 (for example, 5 V) is supplied to the data input lines Data1 to Datal07. Here, if Din 100 = "0" (write) and Din 100 = "1" (write prohibited), the data input/output line Data 100 becomes "Datal00 = 5V" because the row selects the transistor C101-0~ C101-7 becomes conductive, so 5V is applied to bit line BIT101-0, and 0V is applied to BIT101-7. Therefore, the data "0" is written to the memory cell M1 1 1 - 0, and the threshold 値 becomes high. Also, the memory cell Mill-7 becomes the data "1" (forbidden writing), and the threshold is still low. On the other hand, the row decoder 1400-11 becomes non-selection because the output Ο signal COLlOn becomes "〇" (0V) and COLB10n becomes "1", so the selection circuit 1300 - In 1300 - mn becomes non-selection, and the memory cell The meta array 1100-n becomes a non-selected state. Further, the column decoder 1200-m also becomes non-selected because the output of the level shifting circuits 1203, 1 205 becomes "0" (0 V), so Mlml - 0 - Mlml - 7 becomes non-selected. Here, regarding the writing, if the erasing is performed at the time of erasing, since the transistor T1 02 operates in the unsaturated region, there is a problem that it is difficult to write at the beginning. In this case, at the time of writing, the voltage of the control gate CG100 (VP102) 〇 is set to the first 3V, and then 3.5V, 4.0V, . . . is written a plurality of times, as long as the voltage of the VP 102 is gradually stepped each time. When it rises, it is always possible to operate in a saturated region, and as a result, high-speed writing can be achieved. Fig. 7 is a view showing the configuration of a power supply voltage control circuit. In the power supply voltage control circuit 1700 shown in Fig. 7, the power supply boosting circuit is constituted by an oscillator, a charging pump, a voltage detecting circuit, and the like (all not shown). The external power supply VCC 10 0 (for example, 3 V) is used as a power source for internal boosting, and VPP100 (for example, i〇V) is output. The voltage output circuit 1702 is composed of a voltage detecting circuit and a voltage regulator (both not shown in FIG. 83-201010062), and receives a high voltage VPP100 and supplies it as an output to the memory cells of the VP 101, VP102, VP103, and VP104. Voltage. Fig. 8 to Fig. 8C show signal waveform diagrams of the voltage VP102 at the time of writing, the write signal Write, and the control gate CG 100. As shown in the figure, the voltage VP102 rises from 4V in IV steps to 4V, 5V, 6V, and repeats the input write signal Write» each time accepts the edge of the write signal Write, after the write voltage is increased by one level, Output to the control gate CG 100. At the time of erasing, since the output of the level shifting circuit 1 203 of the column decoder 1200-1 is VPIOI (IOV) and the signal W100 is "0", the NAND © circuit 1 204 becomes "1", and the level shifting circuit 1 205 becomes "0" (0V). The output signal COL 101 of the row decoding circuit outputs VP 103 (12 V), and the data input lines Datal00 to Datal07 output VP 104 (8 V) via the data input conversion circuit 1500. Further, the erasing control signal EB100 becomes "0", and the transistors 1101 to 1 to 1101 - η in the memory cell array 1100 - 1 to 1100 - η become non-conductive. As a result, in the memory cell Mill — 0~ Mill - 7,
對選擇閘極SG100施加「SG100=10V」，對控制閘極CG100 施加「CG10 0 = OV」，對位元線「BIT101-0 〜BIT101 - 7」 Q 施加8V，源極S101變成開路，結果被拭除。 讀出時，從位準挪移電路1203輸出VP1 02(3 V)，因爲 信號 W 1 0 0變成“ 0 ” ，所以位準挪移電路1 2 0 5輸出 “0”（0V)。對資料輸出入線Datal00~Datal07，自感測放 大器1600 — 0~1 6 00 — 7施加位元線預充電電壓IV，若記憶 胞元M111-0是寫入狀態（不導通），且若位元線BIT101-〇是IV、記憶胞元Mill— 7是拭除狀態（導通）’則電流流 動，而位元線BIT101— 7及資料輸出入線Data 107的位準 -84- 201010062 下降’感測放大器1600-0~1600 — 7檢測此電壓差，而輸 出 Dout 10 0= “0” 、Doutl07= “1” 。 此外，高電壓VP101、 VP102、 VP103、 VP104亦可由 未圖示之內部的電源電路（充電泵+電壓檢測電路+穩壓器 等所構成）供給，亦可由外部電源供給。 此外，在第6圖，位準挪移電路1 2 03相當於上述之第 1位準挪移電路，位準挪移電路1 20 5相當於上述之第2位 準挪移電路，位準挪移電路1 40 3相當於上述之第3位準挪 © 移電路。又，傳輸閘極電晶體1301相當於上述之第1傳輸 閘極電晶體，傳輸閘極電晶體1 3 03相當於上述之第2傳輸 閘極電晶體。 而，在第2實施形態所示之非揮發性半導體記憶裝 置，配置成由將記憶胞元對各列在行方向以1位元組單位 (例如記憶胞元Mill- 7)被進行行選擇之8位元 單位的記憶胞元方塊所構成。又，沿著列方向利用位元線 BIT101 - 0~ ΒΙΤΙΟη— 7共同連接各記憶胞元 Mill — 〇 0〜Mlmn-7之第1電晶體T101的汲極。 又，對各記憶胞元方塊，沿著行方向利用選擇閘極配 線SGlll~SGlln共同連接記憶胞元之係靥第1電晶體T101 的閘極的選擇閘極SG100，沿著行方向利用控制閘極配線 CG1 11〜CGlln共同連接記憶胞元之係屬第2電晶體T102 的閘極的控制閘極CG100。 又，在行方向以1位元組單位所選擇之各行選擇範圍 內設置源極線S101〜SlOn，該行選擇範圍內之所有的列之 各各記憶胞元之第 2電晶體的源極各自利用源極線 -85- 201010062 S101~S10n共同連接》列解碼器1200- 1〜1200-m接受位 址信號，並輸出選擇記憶胞元的列選擇信號。第1位準挪 移電路1203將從列解碼器1200 -l~1200 -m所輸出之信 號變換成施加於選擇閘極SG100之第1電壓VP101的信 號。第2位準挪移電路12 05將從列解碼器1200-1-12 00 -m所輸出之信號變換成施加於該控制閘極CG 100之第2 電壓VP102的信號。 行解碼器1400— 1〜1400—η接受位址信號，並輸出以 1位元組單位選擇記憶胞元的行選擇信號。第3位準挪移 © 電路1403將從行解碼器所輸出之行選擇信號變換成第3電 壓VP103的信號。 選擇電路1300 - 11〜1300-ml由以下之元件所構成， 第1傳輸閘極電晶體130卜係將從第3位準挪移電路1403 所輸出之行選擇信號VP 103作爲閘極輸入，並向選擇閘極 SG100傳輸位準挪移電路1203的輸出信號VP101;第2傳 輸閘極電晶體1303,係將從第3位準挪移電路所輸出之行 選擇信號VP 103作爲閘極輸入，並向選擇閘極SG1 00傳輸 Q 第2位準挪移電路1205的輸出信號VP102。 行選擇電晶體，例如行選擇電晶體C101-0-C 101-7 將從第3位準挪移電路1 40 3所輸出之行選擇信號VP103 作爲閘極輸入，並選擇1位元組單位之記憶胞元的位元 線。在由此行選擇電晶體C101— 0〜C 101—7所選擇之1位 兀組的位兀線BIT101— 0〜BIT101— 7，經由該行選擇電晶 體，而連接1位元組的資料輸出入線Data 100〜Data 107。 又，資料輸入變換電路1 5 00在接受1位元組單位之寫 -86- 201010062 入資料Din 100~Din 107的輸入信號，並進行資料的寫入及 資料的拭除時，輸出透過該資料輸出入線Data 1〇〇〜Data 107 及位元線而施加於第1電晶體之汲極的第4電壓信號 VP104。又，在讀出資料時，利用感測放大器1600— 〇~1600 -7將資料輸出入線DatalOO〜Datal07所讀出之記憶胞元 的資料放大並向外部輸出。 如此，在本發明之第2實施形態的非揮發性半導體記 憶裝置，以將記憶胞元在行方向以1位元組單位（例如Mill Ο — 0〜Mill — 7)進行行選擇的方式配置記憶胞元方塊。又， 利用位元線共同連接各記憶胞元之第1電晶體的汲極，在 各記憶胞元方塊，在行方向共同連接選擇閘極SG100，在 行方向共同連接控制閘極CG1 00。又，將從行列解碼器所 輸出之列選擇信號施加於選擇閘極SG 100的信號變換成第 1電壓VP1 01，將從列選擇信號施加於控制閘極CG 100的 信號變換成第2電壓VP 102。而，在所選擇之記憶胞元方 塊的選擇電路，利用第1傳輸閘極電晶體向選擇閘極SG 100 〇 傳輸第1電壓VP101，並利用第2傳輸閘極電晶體向控制 閘極CG100傳輸第2電壓VP 102。又，將利用行選擇電晶 體所選擇之1位元組的位元線和1位元組的資料輸出入線 連接，再透過此資料輸出入線而對記憶胞元寫入和讀出資 料。 因而，使用本發明之非揮發性半導體記憶元件，可構 成非揮發性半導體記憶裝置。因而，以標準邏輯元件的 CMOS製程可實現非揮發性記憶體，同時可緊密地配置面 積變大的電容器（在浮動閘極和半導體基板表面所形成之 -87- 201010062 電容器），使面積變成最小限度。 [第3實施形態] 第9圖係表示本發明之第3實施形態的非揮發性半導 體記憶裝置的構成圖，是使用本發明之非揮發性半導體記 憶元件（記憶胞元）構成記憶胞元陣列之EEPROM的例子》"SG100=10V" is applied to the selection gate SG100, "CG10 0 = OV" is applied to the control gate CG100, 8V is applied to the bit line "BIT101-0 to BIT101 - 7" Q, and the source S101 becomes an open circuit, and the result is Erase. At the time of reading, VP1 02 (3 V) is output from the level shifting circuit 1203. Since the signal W 1 0 0 becomes "0", the level shifting circuit 1 2 0 5 outputs "0" (0 V). For the data input and output line Datal00~Datal07, the bit line precharge voltage IV is applied from the sense amplifier 1600 — 0~1 6 00 — 7 , if the memory cell M111-0 is in the write state (non-conducting), and if the bit is Line BIT101-〇 is IV, memory cell Mill-7 is erased state (conducting), then current flows, and bit line BIT101-7 and data output line Data 107 level -84- 201010062 drop 'sensing amplifier 1600-0~1600 — 7 detects this voltage difference, and the output Dout 10 0=“0” and Doutl07=“1”. Further, the high voltages VP101, VP102, VP103, and VP104 may be supplied from an internal power supply circuit (charge pump + voltage detecting circuit + voltage regulator or the like) (not shown) or may be supplied from an external power source. In addition, in FIG. 6, the level shifting circuit 1 2 03 is equivalent to the first level shifting circuit described above, and the level shifting circuit 1 205 is equivalent to the second level shifting circuit described above, and the level shifting circuit 1 40 3 It is equivalent to the above-mentioned third-order quasi-shifting circuit. Further, the transfer gate transistor 1301 corresponds to the first transfer gate transistor described above, and the transfer gate transistor 133 corresponds to the second transfer gate transistor described above. Further, in the nonvolatile semiconductor memory device shown in the second embodiment, the memory cells are arranged in rows in a 1-bit unit (for example, memory cells Mill-7) in the row direction. The 8-bit unit memory cell block is composed. Further, the drains of the first transistors T101 of the memory cells Mill_ 〇 0 to Mlmn-7 are connected in common in the column direction by the bit lines BIT101 - 0~ ΒΙΤΙΟ η-7. Further, for each memory cell block, the gate electrode selection gate SG100 of the first transistor T101 of the memory cell is connected in common in the row direction by the selection gate wirings SG111 to SGlln, and the gate is used along the row direction. The pole wirings CG1 to CG11n are connected to the control gate CG100 of the gate of the second transistor T102, which is connected to the memory cell. Further, the source lines S101 to S1On are set in the row selection direction selected by the 1-bit unit in the row direction, and the source of the second transistor of each of the memory cells in all the columns in the row selection range is selected. The source decoder -85-201010062 S101~S10n are commonly connected. The column decoders 1200-1 to 1200-m accept the address signals and output the column selection signals for selecting the memory cells. The first-order quasi-shift circuit 1203 converts the signal output from the column decoders 120-1 to 1200-m into a signal applied to the first voltage VP101 of the selection gate SG100. The second level shift circuit 12 05 converts the signal output from the column decoders 1200-1-12 00 -m into a signal applied to the second voltage VP102 of the control gate CG 100. The row decoders 140-1 to 1400-n accept the address signals and output a row selection signal for selecting the memory cells in units of 1 byte. The third bit shifting © circuit 1403 converts the row select signal output from the row decoder into the signal of the third voltage VP103. The selection circuits 1300 - 11 to 1300-ml are composed of the following elements, and the first transmission gate transistor 130 is used as a gate input from the row selection signal VP 103 output from the third level shift circuit 1403, and The output signal VP101 of the gate SG100 transmission level shifting circuit 1203 is selected; the second transmission gate transistor 1303 is used as a gate input from the row selection signal VP 103 outputted by the third level shifting circuit, and is selected as a gate. The pole SG1 00 transmits the output signal VP102 of the Q second level shifting circuit 1205. The row selection transistor, for example, the row selection transistor C101-0-C 101-7, uses the row selection signal VP103 output from the third bit shifting circuit 1403 as a gate input, and selects a memory of one byte unit. The bit line of the cell. In this row, the bit lines BIT101-0~BIT101-7 of the 1-bit group selected by the transistors C101-0~C 101-7 are selected, and the transistor is selected via the row, and the data output of the 1-bit group is connected. Enter data line 100 to Data 107. Moreover, the data input conversion circuit 1 500 receives the input signal of the data Din 100~Din 107 when writing 1-86-unit units, and writes the data and erases the data. The fourth voltage signal VP104 applied to the drain of the first transistor is input to the data lines Data1 to Data 107 and the bit lines. Further, when reading data, the data of the memory cells read out by the data output lines Data1OO to Datal07 are amplified by the sense amplifiers 1600 - 〇 1600 -7 -7 and output to the outside. As described above, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, the memory cells are arranged in a row in a 1-bit unit (for example, Mill Ο 0 to Mill -7) in the row direction. Cell box. Further, the drains of the first transistors of the respective memory cells are connected in common by the bit lines, and the selection gates SG100 are commonly connected in the row direction in the memory cell blocks, and the control gates CG1 00 are connected in the row direction. Further, the signal from which the column selection signal output from the row and column decoder is applied to the selection gate SG 100 is converted into the first voltage VP1 01, and the signal applied from the column selection signal to the control gate CG 100 is converted into the second voltage VP. 102. And, in the selection circuit of the selected memory cell block, the first transmission gate transistor transmits the first voltage VP101 to the selection gate SG 100 ,, and transmits the second transmission gate transistor to the control gate CG100 by using the second transmission gate transistor. The second voltage VP 102. Further, the bit line of the 1-bit group selected by the row selection transistor and the data output line of the 1-bit group are connected, and the data is written and read through the data input line. Thus, a non-volatile semiconductor memory device can be constructed using the non-volatile semiconductor memory device of the present invention. Therefore, the non-volatile memory can be realized by the CMOS process of the standard logic element, and the capacitor with a large area (the -87-201010062 capacitor formed on the surface of the floating gate and the semiconductor substrate) can be closely arranged to minimize the area. limit. [Third Embodiment] Fig. 9 is a view showing a configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention, in which a memory cell array is constructed using the nonvolatile semiconductor memory device (memory cell) of the present invention. EEPROM example"
第9圖所示之記憶胞元陣列和第6圖所示之記憶胞元 陣列在構成上的相異點是，省略第6圖所示之選擇電路 1 3 00 - 1 1中之傳輸閘極電晶體1301和開關用電晶體 1 302，而僅由傳輸閘極電晶體1 3 03和開關用電晶體1304 所構成，例如，將選擇閘極配線SG111~ SGlln進行共用 化，並作爲選擇閘極配線SG101。其他和第6圖所示之非 揮發性半導體記憶裝置的構成相同，對相同的構成部分附 加相同的符號，並省略重複說明。The difference between the memory cell array shown in FIG. 9 and the memory cell array shown in FIG. 6 is that the transmission gate in the selection circuit 1 3 00 - 1 1 shown in FIG. 6 is omitted. The transistor 1301 and the switching transistor 1 302 are composed only of the transmission gate transistor 103 and the switching transistor 1304. For example, the selection gate wirings SG111 to SG11n are shared and used as a selection gate. Wiring SG101. The other components are the same as those of the non-volatile semiconductor memory device shown in Fig. 6, and the same reference numerals will be given to the same components, and overlapping description will be omitted.
此EEPROM因爲以1位元組單位（8位元）進行寫入、 拭除，所以爲了避免電壓應力作用於所選擇之記憶胞元以 外者，基本上，以8位元單位（記憶胞元Ml 1 1 — 0〜Ml 1 1 -8等）在電路上進行分離。 在第9圖所示之例子，例如已選擇記憶胞元Μ 1 1 1 — 0〜Μ111-7，因爲選擇閘極配線SG101變成高電壓，所以 對記憶胞元Μ11η-0~Μ11η — 7的選擇閘極電晶體Τ101施 加電壓應力，但是因爲行解碼器1400 - ！！爲非選擇，所以 行選擇電晶體Cl On — 0〜C 10η— 7變成不導通，而對位元線 ΒΙΤΙΟη— 0〜ΒΙΤ10η-7不會施加電壓，結果，對成爲記憶 部之電晶體T102的汲極不會施加電壓，又，因爲電晶體 T 102的控制閘極CG 100爲非選擇，所以不會被施加電壓應 -88- 201010062 力。若依據本構成，因爲可減少選擇電路1300— 11的元件 數，所以可縮小記憶胞元配置上的面積。 此外，在第9圖，位準挪移電路1 20 3相當於上述的第 1位準挪移電路，位準挪移電路1 2 0 5相當於上述的第2位 準挪移電路，位準挪移電路1 403相當於上述的第3位準挪 移電路。 而，在第3實施形態所示之本發明的非揮發性半導體 記憶裝置，作爲其構成，配置成由將記憶胞元對各列在行 Ο 方向以1位元組單位（例如記憶胞元Ml 1 1 - 0〜Ml 1 1 - 7)被 進行行選擇之8位元單位的記憶胞元方塊所構成。又，沿 著列方向利用位元線BIT101— 0~ BIT10n-7共同連接各 記憶胞元Ml 1 1 — 0~Mlmn— 7之第1電晶體T101的汲極。 而，沿著行方向利用選擇閘極配線SG101共同連接記 憶胞元之係屬第1電晶體T101的閘極的選擇閘極SG100。 又，對各記憶胞元方塊，沿著行方向利用控制閘極配線 CGI 1 1~ CGI In共同連接記憶胞元之係屬第2電晶體T102 〇 的閘極的控制閘極CG100。 又，在行方向以1位元組單位所選擇之各行選擇範圍 內設置源極線S101~S10n，該行選擇範圍內之所有的列之 各各記億胞元之第 2電晶體的源極各自利用源極線 S101~S10n共同連接。列解碼器1200 — 1〜1200-m接受位 址信號，並輸出選擇記憶胞元的列選擇信號。第1位準挪 移電路1203將從列解碼器1200— l~1200~m所輸出之信 號變換成施加於選擇閘極SG100之第1電壓VP101的信 號。第2位準挪移電路1205將從列解碼器12〇〇 —卜^⑻ -89- 201010062 一 m所輸出之信號變換成施加於該控制閘極CGI 00之第2 電壓VP102的信號。 行解碼器1 400— l~1 400—n接受位址信號，並輸出以 1位元組單位選擇記憶胞元的行選擇信號。第3位準挪移 電路1403將從行解碼器所輸出之行選擇信號變換成第3電 壓VP103的信號。 選擇電路1 300 -ll~1 300 -ml具有傳輸閘極電晶體 13 03，其將第1位準挪移電路1203的輸出信號VP101直 接向選擇閘極SG100傳輸，同時將從第3位準挪移電路所 ❹ 輸出之行選擇信號VP 103作爲閘極輸入，將第2位準挪移 電路1205的輸出信號VP102向控制閘極CG100傳輸。 行選擇電晶體，例如行選擇電晶體C101— 0〜C101二7 將從第3位準挪移電路1 403所輸出之行選擇信號VP103 作爲閘極輸入，並選擇1位元組單位之記憶胞元的位元 線。在由此行選擇電晶體C101- 0〜C 101 — 7所選擇之1位 元組的位元線BIT101 - 0〜BIT101 — 7，經由該行選擇電晶 體，而連接1位元組的資料輸出入線Data 100〜Data 107。 © 又，資料輸入變換電路15〇〇在接受1位元組單位之寫 入資料Din 100〜Din 107的輸入信號，並進行資料的寫入及 資料的拭除時，輸出透過該資料輸出入線Data 100〜Data 107 及位元線而施加於第 1電晶體之汲極的第 4電壓信號 VP 104。又，在讀出資料時，利用感測放大器1600 — 〇~ 1600 一7將資料輸出入線DatalOO〜Datal07所讀出之記憶胞元 的資料放大並向外部輸出。 如此，在第3實施形態所示之本發明的非揮發性半導 -90- 201010062 體記憶裝置，將從列解碼器所輸出之列選擇信號變換成施 加於選擇閘極SG100之第1電壓VP101的信號，並將列選 擇信號變換成施加於該控制閘極CG 100之第2電壓VP 102 的信號。而，關於選擇閘極信號，將第1電壓VP101直接 向各列之記憶胞元方塊內的選擇閘極SG 100傳輸，但是關 於控制閘極信號，只向所選擇之記憶胞元方塊傳送。在此 情況，利用選擇電路內的傳輸閘極電晶體，向控制閘極 CG100傳輸第2電壓VP102。 〇 因而，使用本發明之非揮發性半導體記憶元件，可構 成非揮發性半導體記憶裝置，同時可減少選擇電路的元件 數，而可更縮小記憶胞元配置上的面積。 [第4實施形態] 第10圖係表示本發明之第4實施形態的非揮發性半導 體記憶裝置的構成圖，是表示記憶胞元陣列之構成圖。 第1 0圖所示之記憶胞元陣列和第6圖所示之記憶胞元 陣列在構成上的相異點爲|變更對控制閘極選擇性地供給 〇 電壓之選擇電路 1300 — 11〜1300 - In、及變更列解碼器 1200- 1-1200— m 與行解碼器 1400 — 1 〜1400-n。即，變 更列解碼器1200 — 1〜1200-m，刪除第6圖所示的反相器 12 02及 N AND電路 1205，一倂刪除選擇電路 1300 — 11~1300 — In中的電晶體1301、1302。反之，對行解碼器 1400-l~1400-n追加NAND電路1404及位準挪移電路 1405 ° 而且，在行解碼器1400-l~1400-n，輸出利用位準 挪移電路1405變換成第2電壓VP102(例如4V)之信號的行 -91- 201010062 選擇信號 COLlOla〜COLlOna 。 此行選擇信號 COL101a~COL10na 成爲選擇電路 1300 - 11~1300— ln 中之 傳輸閘極電晶體13 03的閘極輸入信號。 又，從行解碼器1 400 — 1〜1 400 — η中的NAND電路 1404輸出行選擇信號COL101aB~COL10naB(邏輯和信號 COLlOla-COLlOna 相反的信號）。此行選擇信號 COLlOlaB 〜COLlOnaB 成爲選擇電路 1 3 0 〇 - 1 1 ~ 1 3 0 0 - 1 η 中之開關用電晶體1304的閘極輸入信號，根據此行選擇信 號COL101aB~COL10naB，使非選擇列之開關用電晶體1 3 04 Ο 變成導通。 又，從行解碼器1400 — 1-1400— η向行選擇電晶體 C101-0~C101—7.....C10n — 0 〜C10n—7 的閘極輸入利 用位準挪移電路1403變換成第3電壓VP103(例如10V)之 行選擇信號 COLlOlb〜COLlOnb。根據此行選擇信號 COLlOlb-COLlOnb > 使行選擇電晶體 C 1 0 1 - 0〜C 1 0 1 — 7、…、C 1 0 η 一 0〜C10n — 7變成開、關。 將位準挪移電路1405的電源設爲VP102,將位準挪移 Q 電路1403的電源設爲VP103。位準挪移電路1405的輸出 控制列解碼器之位準挪移電路1203的輸出，並控制對控制 閘極CG100供給的電壓。即，位準挪移電路1203的輸出 電壓VP101 (例如8V)經由傳輸閘極電晶體1303而供給控制 閘極 CG111。此時，供給控制閘極CG111的電壓，在 「VP101>VP102(信號 COLlOla 的電壓）+ Vth(電晶體 1303 的臨限値）的情況， 成爲「VCG111= VP102— Vth」。例如，若 VP101 = 8V、 -92- 201010062 VP102 = 4V、Vth(1 3 03)=l V，則 VCG100 =3V。此時，若 VP102 = 5V，貝IJ VCG100 =4V > 若 VP102 = 6V，貝lj VCG100 =5V，在寫入時，可對控制閘極CGI 1 1施加步升電壓。 此外，在第10圖，位準挪移電路1203相當於上述的 第1位準挪移電路，位準挪移電路1 40 5相當於上述的第2 位準挪移電路，位準挪移電路1 403相當於上述的第3位準 挪移電路。 而且，在第4實施形態所示之本發明的非揮發性半導 Λ U 體記憶裝置，作爲其構成，配置成由將記憶胞元對各列在 行方向以1位元組單位（例如記憶胞元Ml 1 1 — 0〜Ml 1 1 - 7) 被進行行選擇之8位元單位的記憶胞元方塊所構成。又， 沿著列方向利用位元線BIT101-0~ BIT10n-7共同連接 各記憶胞元Mill— 0〜Mlllmn — 7之第1電晶體T101的汲 極。 而，沿著行方向利用選擇閘極配線SG1 01共同連接記 憶胞元之係屬第1電晶體T101的閘極的選擇閘極SG100。 〇 又，對各記憶胞元方塊，沿著行方向利用控制閘極配線 CG111〜CGlln共同連接記憶胞元之係屬第2電晶體T102 的閘極的控制閘極CG100。 又，在行方向以1位元組單位所選擇之各行選擇範圍 內設置源極線S101~S10n，該行選擇範圍內之所有的列之 各各記憶胞元之第2電晶體的源極利用源極線S101-S1 On 共同連接。列解碼器1200-l~1200-m接受位址信號，並 輸出選擇記憶胞元的列選擇信號。第1位準挪移電路12 03 將從列解碼器1200 - l~1200-m所輸出之信號變換成施加 -93- 201010062 於選擇閛極SGI 00之第1電壓VP101的信號。行解碼器 1400- 1〜1400— η接受位址信號，並輸出以1位元組單位 選擇記憶胞元的行選擇信號。第2位準挪移電路1405將從 行解碼器1 400 - 1 -1 400 - 11所輸出之行選擇信號變換成第 2電壓VP 102的信號。第3位準挪移電路1403將從行解碼 器所輸出之行選擇信號變換成第3電壓VP 103的信號》Since the EEPROM is written and erased in 1-bit units (8 bits), in order to prevent voltage stress from acting on the selected memory cell, basically, in 8-bit units (memory cell M1) 1 1 — 0 to Ml 1 1 -8, etc.) Separate on the circuit. In the example shown in Fig. 9, for example, the memory cells Μ 1 1 1 - 0 to Μ 111-7 have been selected, since the selection gate wiring SG101 becomes a high voltage, the selection of the memory cells Μ11η-0~Μ11η-7 The gate transistor 101 applies a voltage stress, but because of the row decoder 1400-! ! For non-selection, the row selection transistor Cl On — 0 to C 10η—7 becomes non-conducting, and no voltage is applied to the bit line ΒΙΤΙΟη—0~ΒΙΤ10η-7, and as a result, the transistor T102 which becomes the memory portion is not applied. The drain does not apply a voltage, and since the control gate CG 100 of the transistor T 102 is not selected, the voltage is not applied -88- 201010062. According to this configuration, since the number of components of the selection circuits 1300-11 can be reduced, the area on the memory cell configuration can be reduced. Further, in Fig. 9, the level shifting circuit 1 203 corresponds to the first level shifting circuit described above, and the level shifting circuit 1 2 0 5 corresponds to the second level shifting circuit described above, and the level shifting circuit 1 403 It is equivalent to the third level shifting circuit described above. In the nonvolatile semiconductor memory device of the present invention shown in the third embodiment, the memory cell is arranged in a 1-bit unit in the row direction (for example, the memory cell M1). 1 1 - 0 to Ml 1 1 - 7) A memory cell block of an 8-bit unit selected for row selection. Further, the drains of the first transistor T101 of the memory cells M1 1 1 - 0 to Mlmn-7 are connected in common in the column direction by the bit lines BIT101 - 0 to BIT10n - 7 . On the other hand, the selection gate SG101 of the first transistor T101 is connected to the memory cell in the row direction by the selection gate wiring SG101. Further, for each of the memory cell blocks, the control gate CG100 of the gate of the second transistor T102 〇 is connected to the memory cell by the control gate wirings CGI 1 1 to CGI In in the row direction. Further, the source lines S101 to S10n are set in each row selection range selected by one byte unit in the row direction, and the source of the second transistor of each of the cells of all the columns in the row selection range is selected. The source lines S101 to S10n are connected in common. The column decoder 1200 - 1 to 1200-m accepts the address signal and outputs a column selection signal for selecting the memory cell. The first-order quasi-shift circuit 1203 converts the signal output from the column decoders 1200-1 to 1200~m into a signal applied to the first voltage VP101 of the selection gate SG100. The second level shifting circuit 1205 converts the signal output from the column decoder 12(b)-89-201010062-m into a signal applied to the second voltage VP102 of the control gate CGI00. The row decoder 1 400 - l~1 400 - n accepts the address signal and outputs a row selection signal for selecting the memory cell in 1-bit units. The third bit shifting circuit 1403 converts the row selection signal output from the row decoder into a signal of the third voltage VP103. The selection circuit 1 300 -11~1 300 -ml has a transmission gate transistor 133, which directly transmits the output signal VP101 of the first level shifting circuit 1203 to the selection gate SG100, and simultaneously shifts the circuit from the third level. The output row selection signal VP 103 is used as a gate input, and the output signal VP102 of the second level shift circuit 1205 is transmitted to the control gate CG100. The row selection transistor, for example, the row selection transistor C101-0~C101 2, uses the row selection signal VP103 output from the third bit shift circuit 1 403 as a gate input, and selects a memory cell of 1 byte unit. Bit line. In this row, the 1-bit tuple bit lines BIT101 - 0 to BIT101 - 7 selected by the transistors C101 - 0 - C 101 - 7 are selected, and the transistor is selected via the row, and the 1-byte data output is connected. Enter data line 100 to Data 107. © In addition, the data input conversion circuit 15 receives the input signal of the data Din 100 to Din 107 in the 1-bit unit, and writes the data and erases the data. 100 to Data 107 and bit lines are applied to the fourth voltage signal VP 104 of the drain of the first transistor. Further, when data is read, the data of the memory cells read out by the data output lines Data1OO to Datal07 are amplified by the sense amplifiers 1600 - 〇 1600 - 7 and output to the outside. As described above, in the nonvolatile semiconducting-90-201010062 bulk memory device of the present invention shown in the third embodiment, the column selection signal output from the column decoder is converted into the first voltage VP101 applied to the selection gate SG100. The signal is converted into a signal applied to the second voltage VP 102 of the control gate CG 100. On the other hand, regarding the selection of the gate signal, the first voltage VP101 is directly transmitted to the selection gate SG 100 in the memory cell block of each column, but the control gate signal is transmitted only to the selected memory cell block. In this case, the second voltage VP102 is transmitted to the control gate CG100 by using the transfer gate transistor in the selection circuit. Thus, by using the non-volatile semiconductor memory device of the present invention, a non-volatile semiconductor memory device can be constructed while reducing the number of components of the selection circuit and reducing the area on the memory cell configuration. [Fourth Embodiment] Fig. 10 is a view showing a configuration of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention, and is a view showing a configuration of a memory cell array. The difference between the memory cell array shown in FIG. 10 and the memory cell array shown in FIG. 6 is a selection circuit 1300-11-1300 that selectively supplies a threshold voltage to the control gate. - In, and change column decoders 1200- 1-1200-m and row decoders 1400-1 to 1400-n. That is, the column decoders 1200-1 to 1200-m are changed, the inverters 12 02 and the N AND circuits 1205 shown in FIG. 6 are deleted, and the transistors 1301 in the selection circuits 1300 - 11 - 1300 - In are deleted. 1302. On the other hand, the NAND circuit 1404 and the level shifting circuit 1405 are added to the row decoders 140-1 to 1400-n. Further, in the row decoders 140-1 to 1400-n, the output is converted into the second voltage by the level shifting circuit 1405. The line of the VP102 (eg 4V) signal -91- 201010062 selects the signal COLlOla~COLlOna. The row selection signal COL101a~COL10na becomes the gate input signal of the transmission gate transistor 13 03 in the selection circuit 1300 - 11~1300 - ln. Further, the row selection signals COL101aB to COL10naB (signals opposite to the logical sum signal COL1Ola-COLlOna) are output from the NAND circuit 1404 in the row decoders 1400-1 to 1400-n. The row selection signal COL1OlaB to COLLOnaB becomes the gate input signal of the switching transistor 1304 in the selection circuit 1 3 0 〇-1 1 ~ 1 3 0 0 - 1 η, and the signal COL101aB~COL10naB is selected according to the row to make non-selection The column switches the transistor 1 3 04 Ο to become conductive. Further, the gate input from the row decoder 1400 - 1-1400 - η to the row selection transistors C101-0 - C101 - 7 . . . C10n - 0 to C10n - 7 is converted into the first by the level shift circuit 1403. 3 voltage selection signal COLlOlb~COLlOnb of VP103 (for example, 10V). According to this row selection signal COLlOlb-COLlOnb > causes the row selection transistor C 1 0 1 - 0 to C 1 0 1 - 7, ..., C 1 0 η 0 to C10n - 7 to turn on and off. The power supply of the level shifting circuit 1405 is set to VP102, and the power of the level shifting Q circuit 1403 is set to VP103. The output of the level shifting circuit 1405 controls the output of the level shifting circuit 1203 of the column decoder and controls the voltage supplied to the control gate CG100. That is, the output voltage VP101 (e.g., 8V) of the level shifting circuit 1203 is supplied to the control gate CG111 via the transmission gate transistor 1303. At this time, the voltage supplied to the control gate CG111 becomes "VCG111 = VP102 - Vth" in the case of "VP101> VP102 (voltage of the signal COL1Ola) + Vth (the threshold of the transistor 1303). For example, if VP101 = 8V, -92- 201010062 VP102 = 4V, Vth(1 3 03) = l V, then VCG100 = 3V. At this time, if VP102 = 5V, Bay IJ VCG100 = 4V > If VP102 = 6V, Bayer lj VCG100 = 5V, when writing, the step-up voltage can be applied to the control gate CGI 1 1 . Further, in Fig. 10, the level shifting circuit 1203 corresponds to the above-described first level shifting circuit, and the level shifting circuit 154 is equivalent to the above-described second level shifting circuit, and the level shifting circuit 1 403 is equivalent to the above. The third position of the quasi-shift circuit. Further, the nonvolatile semi-conductive U-body memory device of the present invention shown in the fourth embodiment is configured such that the memory cell pairs are arranged in a row in a 1-bit unit (for example, memory). The cells M1 1 1 - 0 to M1 1 1 - 7) are composed of memory cell blocks of 8-bit units selected for row selection. Further, the drains of the first transistor T101 of the memory cells Mill_0 to Mlllmn-7 are connected in common in the column direction by the bit lines BIT101-0 to BIT10n-7. On the other hand, the selective gate SG100 of the gate of the first transistor T101 is connected in common by the selection gate wiring SG1 01 in the row direction. Further, for each memory cell block, the control gate CG100 of the gate of the second transistor T102 is connected to the memory cell by the control gate wirings CG111 to CG11n in the row direction. Further, the source lines S101 to S10n are set in the row selection direction selected by the 1-bit unit in the row direction, and the source of the second transistor of each of the memory cells in all the columns in the row selection range is utilized. The source lines S101-S1 On are connected in common. The column decoders 120-1 to 1200-m receive the address signals and output column selection signals for selecting memory cells. The first level shift circuit 12 03 converts the signal output from the column decoders 1200 - l to 1200-m into a signal of -93 - 201010062 for selecting the first voltage VP101 of the drain SGI 00. The row decoder 1400-1 1400 - η accepts the address signal and outputs a row selection signal for selecting the memory cell in 1-bit units. The second level shifting circuit 1405 converts the line selection signal output from the row decoder 1 400 - 1 -1 400 - 11 into the signal of the second voltage VP 102. The third bit shifting circuit 1403 converts the row selection signal output from the row decoder into the signal of the third voltage VP 103"
選擇電路1 300 — 1 1〜1 300 — ml將第1位準挪移電路 1203的輸出信號VP101直接向選擇閘極SG100傳輸，同時 將從第2位準挪移電路1405所輸出之行選擇信號VP 102 作爲閘極輸入，將第2位準挪移電路1 4 0 5的輸出信號 VP1 02和第2傳輸閘極電晶體1303的臨限値Vth之差的信 號（VP102— Vth)向控制閘極CG100傳輸。The selection circuit 1 300 - 1 1 to 1 300 - ml transmits the output signal VP101 of the first level shifting circuit 1203 directly to the selection gate SG100 while the row selection signal VP 102 output from the second level shifting circuit 1405 As the gate input, the signal (VP102_Vth) of the difference between the output signal VP1 02 of the second level shifting circuit 1 4 0 5 and the threshold 値Vth of the second transmission gate transistor 1303 is transmitted to the control gate CG100. .
行選擇電晶體，例如行選擇電晶體C101— 0〜C 101— 7 將從第3位準挪移電路1 403所輸出之行選擇信號VP103 作爲閘極輸入，並選擇1位元組單位之記憶胞元的位元 線。在由此行選擇電晶體C101— 0〜C101— 7所選擇之1位 元組的位元線BIT101— 0〜BIT101— 7，經由該行選擇電晶 體’而連接1位元組的資料輸出入線DatalOO〜Datal07。 又，資料輸入變換電路1500在接受1位元組單位之寫 入資料Din 100~Din 107的輸入信號，並進行資料的寫入及 資料的拭除時，輸出透過該資料輸出入線DatalOO〜Datal07 及位元線而施加於第1電晶體之汲極的第4電壓信號 VP104»又，在讀出資料時，利用感測放大器1600_0〜1600 —7將資料輸出入線DatalOO〜Datal07所讀出之記億胞元 的資料放大並向外部輸出。 -94- 201010062 如此，在第4實施形態所示之本發明的非揮發性半導 體記憶裝置，將從列解碼器所輸出之列選擇信號施加於選 擇閘極SG100的信號變換成第1電壓VP 101的信號，並將 行選擇信號所輸出之行選擇信號變換成第2電壓VP 102的 信號。而，在選擇電路，將第1電壓VP101直接向選擇閘 極SG1 00傳輸，同時利用將第2電壓VP1 02的行選擇信號 作爲閘極輸入的第2傳輸閘極電晶體，將由第2電壓VP102 和第2傳輸閘極電晶體的臨限値Vth所決定的電壓（例如 〇 VP102— Vth)向控制閘極CG100傳輸。 因而，使用本發明之非揮發性半導體記憶元件，可構 成非揮發性半導體記憶裝置，同時可減少閘極電壓選擇電 路的元件數，而可更縮小記憶胞元配置上的面積。又，藉 由控制第2電壓VP1 02的位準，而在寫入時，可對控制閘 極施加步升電壓。 [第5實施形態] 第11圖係表示本發明之第5實施形態的非揮發性半導 0 體記憶裝置的構成圖，係表示記憶胞元陣列之構成圖。 第11圖所示之非揮發性半導體記憶裝置（記憶胞元陣 列）和第1 0圖所不之第4實施形態的記憶胞元陣列在構成 上的相異點爲，變更選擇電路1300 — 11〜1300 - In之構成。 在第11圖所示的例子，替代第10圖所示的傳輸閘極 電晶體1303及開關用電晶體1304,而將位準挪移電路1405 的輸出（VP102:信號COLlOla)作爲電源，並設置由PMOS 電晶體13 10和NMOS電晶體1311所構成之反相器，將其 輸出作爲控制閘極CG111的信號。又，設置將位準挪移電 -95- 201010062 路1403的輸出信號COLlOlaB作爲閘極輸入的NMOS電晶 體1312。其他的構成係和第10圖所示的記憶胞元陣列一 樣。 在此電路，可根據VP102的電壓而直接控制CG111的 電壓。即，要使控制閘極CG111步升至3V、4V、5V，只 要使VP102步升至3V、4V、5V即可。 如此，第5實施形態所示的非揮發性半導體記憶裝 置，除了使用第11圖所示的選擇電路以外，係和第10圖 所示的電路一樣，作爲其構成，配置成由將記憶胞元對各 ® 列在行方向以1位元組單位（例如記憶胞元Μ 1 1 1 — 0 ~ Μ 1 1 1 -7)被進行行選擇之8位元單位的記憶胞元方塊所構成。 又，沿著列方向利用位元線BIT 101 - 0〜BIT 10η — 7共同連 接各記憶胞元Mlll-0~Mlmn— 7之第1電晶體Τ101的汲 極。 而，沿著行方向利用選擇閘極配線SG101共同連接記 憶胞元之係靥第1電晶體T101的閘極的選擇閘極SG100。 又，對各記憶胞元方塊，沿著行方向利用控制閘極配線 Q CGI 1 1〜CGI In共同連接記憶胞元之係屬第2電晶體T102 的閘極的控制閘極CG100。 又，在行方向以1位元組單位所選擇之各行選擇範圍 內設置源極線S101〜S10n，該行選擇範圍內之所有的列之 各各記憶胞元之第 2電晶體的源極各自利用源極線 S101~S10n共同連接。列解碼器1200 — l~1200-m接受位 址信號，並輸出選擇記憶胞元的列選擇信號。第1位準挪 移電路1203將從列解碼器1200- l~1200—m所輸出之信 -96- 201010062 號變換成施加於選擇閘極SGI 00之第1電壓VP 101的信 號。行解碼器1400-l~1400-n接受位址信號，並輸出以 1位元組單位選擇記憶胞元的行選擇信號。 第2位準挪移電路1 405將從行解碼器1 400 - 1 ~1400 一 η所輸出之行選擇信號變換成第2電壓VP 102的信號。 第3位準挪移電路1 403將從行解碼器所輸出之行選擇信號 變換成第3電壓VP103的信號。 選擇電路 1300- 11~1300 - ml將第 1位準挪移電路 Ο 1203的輸出信號VP 101直接向選擇閘極SG100傳輸，同時 將從第2位準挪移電路140 5所輸出之行選擇信號VP102 作爲電源電壓，將從第2位準挪移電路1 40 5所輸出之行選 擇信號VP102向控制閘極CG100傳輸。 行選擇電晶體，例如行選擇電晶體C101-0〜C101-7 將從第3位準挪移電路1 403所輸出之行選擇信號VP103 作爲閘極輸入，並選擇1位元組單位之記憶胞元的位元 線。在由此行選擇電晶體C101- 0〜C101 — 7所選擇之1位 Ο 元組的位元線BIT101 — 0〜BIT101 - 7，經由該行選擇電晶 體’而連接1位元組的資料輸出入線Data 100〜Datal07。 又，資料輸入變換電路1 5 00在接受1位元組單位之寫 入資料Din 100〜Din 107的輸入信號，並進行資料的寫入及 資料的拭除時，輸出透過該資料輸出入線Data 100〜Data 107 及位元線而施加於第1電晶體之汲極的第4電壓信號 VP104。又，在讀出資料時，利用感測放大器1600— 〇~ 1600 將資料輸出入線DatalOO〜Datal07所讀出之記憶胞元 的資料放大並向外部輸出。 -97- 201010062 如此，在第5實施形態所示之本發明的非揮發性半導 體記憶裝置，將從列解碼器所輸出之列選擇信號變換成第 1電壓VP101的信號，並將此第1電壓VP101直接向各記 憶胞元方塊的選擇閘極SG 100傳輸。又，在所選擇之記憶 胞元方塊的選擇電路，利用將從行選擇信號所產生之第2 電壓VP102作爲電源電壓的反相器，將第1電壓VP101作 爲輸入信號，並向控制閘極CG100傳輸該反相器輸出 VP 1 02。 因而，使用本發明之非揮發性半導體記憶元件，可構 © 成非揮發性半導體記憶裝置，同時可減少選擇電路的元件 數，而可更縮小記憶胞元配置上的面積。又，藉由控制第 2電壓VP 102的位準，而在寫入時，可對控制閘極施加步 升電壓。 [第6實施形態] 第12圖係表示本發明之第6實施形態的非揮發性半導 體記憶裝置的構成圖，係表示記憶胞元的布置配置。 在第12圖所示的記憶胞元陣列，是表示第1A圖〜第 Q 1 E圖所示之記憶胞元單元的配置例的圖。如第1 2圖所示， 使控制閘極配線CG111、CG121、CG131、…在橫向通過， 使位元線BIT101、 BIT102、 BIT103、…在縱向通過，在上 下左右對稱地配置第1A圖〜第1E圖的記憶胞元單元，彼 此共用η型井上的電容器，以縮小面積。 例如，在上側2段所排列的記憶胞元，共用源極S 1 0 1， 在源極S101的上側所排列之各記憶胞元之電晶體Τ101的 選擇閘極SG100(多晶矽層1〇〇8)和共用的選擇閘極配線（多 -98- 201010062 晶矽配線）SG111連接。又，各記憶胞元之電晶體ΤΙ 02的 控制閘極CG100所連接的控制閘極配線1019和共用的控 制閘極配線（金屬配線）CG111連接。一樣地，電晶體Τ1 02 的第2金屬配線1013和共用的源極線S101連接。在共用 之源極線S 1 0 1的下側所排列之各記憶胞元之電晶體Τ 1 0 1 的選擇閘極 SG 100和共用的選擇閘極配線（多晶矽配 線）SG1 2 1連接，各記憶胞元之電晶體Τ1 02的控制閘極 CG100和共用的控制閛極配線（金屬配線）CG121連接。又， €) 關於在下側之2段所排列的記憶胞元，亦成爲相同的布置 配置。 藉由進行這種布置配置，而消除在半導體基板上之浪 費的空空間，使成爲高效率的配置。又，在特性上，亦成 爲在面積上最佳的配置。 如此，在第12圖所示之非揮發性半導體記憶裝置的各 記憶胞元是第1Α圖〜第1Ε圖所示的記憶胞元，第1Α圖〜 第1 Ε圖所示的記憶胞元如上述所示，如以下所示般布置構 Ο 成部分。即，參照第1Α圖〜第1Ε圖，在半導體基板表面 上之第1方向（在第1Α圖爲上下方向），配置形成第1電晶 體Τ101和第2電晶體Τ102的電晶體形成部1030。此電晶 體形成部1030，由上依序配置：成爲第1電晶體Τ101之 汲極的第In型擴散層1 〇〇5、形成第1電晶體之通道的第1 閘極區域部（第1擴散層1005和第2擴散層1006之中間的 區域）、是第1電晶體T101的源極並亦成爲第2電晶體之 汲極的第2n型擴散層1006、形成第2電晶體T102之通道 的第2閘極區域部（第2擴散層1005和第3擴散層1007 -99- 201010062 之中間的區域）、以及成爲源極的第3n型擴散層1007。 在此電晶體形成部1030的左側，在上下方向配置第1 金屬配線1012。此金屬配線1012從半導體基板表面隔著 既定之距離配置成和電晶體形成部1030平行，又，金靥配 線1012利用接點和第1電晶體的汲極（第in型擴散層 1005)連接。又，在左右方向形成多晶矽層1〇〇8，使其和第 1電晶體的閘極區域部相對向》 在電晶體形成部1030的左側，以既定之寬度和深度在 左右方向所形成方形的η型井1002。方形的浮動閘極1〇〇9 在左右方向配置成和半導體基板表面相對向，同時配置成 其左端部側的區域和η型井1002的表面相對向，而且右端 部側的區域和第2電晶體的第2閘極區域部（第2η型擴散 層1 006和第3η型擴散層1 007之中間的通道形成區域）相 對向。 在η型井1002的左側’在左右方向形成ρ型擴散層 1015，其和與此η型井1002的浮動閘極1009相對向之區 域的左側相鄰，並具有既定之寬度和深度。此ρ型擴散層 1 〇 1 5和控制閘極配線1 0 1 9利用接點1 0 1 6連接。此控制閘 極配線1019從半導體基板表面隔著既定之距離在左右方 向配置成和浮動閘極1009相對向，又，利用接點1〇16和 Ρ型擴散層1015連接。 第2金屬配線1013從半導體基板表面隔著既定之距離 在左右方向配置成和成爲第2電晶體Τ102之源極的第3η 型擴散層1007相對向，此第2金屬配線1013利用接點1011 和第3η型擴散層1 007連接。 201010062 而且，在第12圖所示的非揮發性半導體記憶裝置，將 2個記憶胞元和2個記憶胞元之合計4個記億胞元作爲配 置的基本單位，在左右方向平行地排列配置，同時在上下 方向亦平行地排列配置成爲此配置之基本單位的4個記憶 胞元，而該2個記憶胞元使彼此共用η型井1002，並左右 對稱地配置第1八圖~第1Ε圖所示的記憶胞元，該2個非 揮發性半導體記憶元件對該左右對稱地配置之2個記憶胞 元，使彼此共用金屬配線1〇13(共用的源極線S101)，並在 ® 下方向對稱地配置， 如此，在第6實施形態所示之本發明的非揮發性半導 體記憶裝置，在各記憶胞元的配置，將2個記憶胞元和2 個記憶胞元之合計4個記憶胞元作爲配置的基本單位，在 左右及上下方向亦平行地排列配置成爲此基本單位的4個 記憶胞元，而該2個記憶胞元使彼此共用第1A圖〜第1E 圖所示之記憶胞元的η型井，並左右對稱地配置，該2個 非揮發性半導體記憶元件對該左右對稱地配置之2個記憶 〇胞元，在下方向對稱地配置。因而，根據本發明，可緊密 地配置非揮發性半導體記憶元件，並可使非揮發性半導體 記憶裝置的面積變成最小限度。 此外，在第12圖所示之第6實施形態，雖然在記憶胞 元（由位元線BIT 102和選擇閘極配線SGI 1 1所選擇的記億 胞元），將金屬配線1012配置於電晶體形成部1030的左 側，但是配置於正上或右側亦一樣。其中，在本例，配置 於右側時，因爲記憶胞元尺寸由金屬配線1 〇 1 2的間隔所決 定，所以有記憶胞元尺寸變成稍大的情況。 -101- 201010062 [第7實施形態] 第13A圖及第13B圖表示本發明之第7實施形態的非 揮發性半導體記憶元件之構成的圖，是表示記憶胞元之構 成。 第13A圖是平面圖’第13B圖是沿著B10—B10，的 剖面圖。在所圖示的記憶胞元，因爲作成省略η.型井，並 設置NMOS電容器，所以將Ρ型擴散層1015變更成η型擴 散層1015’ （第4ιι型擴散層）。因爲電容器1〇14成爲NMOS 電容器，所以在電容器1014的閘極下進行空乏型（D 一型 ❹ depletion— type)的 通道注入1021，使反相層總是存在，而 使可高效率地進行耦合。對標準CMOS製程，雖然需要D 型的通道注入，但是因爲是追加注入步驟，所以對總步驟 只是微增，不會成爲製程之繁雜性的負擔。 第13A圖及第13B圖所示的記憶胞元和第ία圖〜第 1E圖所示之記憶胞元在構成上的相異點，是省略第ία圖 所示的η型井（n—We 11)2，並將ρ型擴散層1〇15變更成η 型擴散層1015’ ，替代地設置第13Β圖所示的空乏型 〇 (depletion— type)通道注入1021。即，第1Α圖〜第1Ε圖所 示之電晶體形成部1030中之成爲第1電晶體T101之汲極 的第In型擴散層1005、形成第1電晶體τιοί之通道的閘 極區域部1〇〇3(第In型擴散層1 005和第2n型擴散層1006 之中間的區域）、是電晶體T101的源極，亦成爲電晶體T102 之汲極的第2η型擴散層1006、形成第2電晶體T102之通 道的閘極區域部1〇〇4(第2η型擴散層1〇〇5和第3η型擴散 層1 00 7之中間的區域）以及成爲源極之第3η型擴散層1007 -102- 201010062 的配置是相同，又，關於多晶矽層1008、金屬配線1012、 1013、控制閘極配線等亦一樣。又，由第1B圖所示之電晶 體T101和電晶體T1 02所形成之等價電路亦相同。因而， 對相同的構成部分附加相同的符號，並省略重複說明。 如此，在第13A圖及第13B圖所示的記憶胞元，對第 1A圖〜第1E圖所示之記憶胞元，省略η型井，而可更加發 揮面積縮小效果。 此外，在第7實施形態，電晶體Τ1 01相當於上述的第 Ο 1電晶體，電晶體Τ102相當於上述的第2電晶體。又，η 型擴散層1005相當於上述之成爲第1電晶體之汲極的第 In型擴散層，η型擴散層1 006相當於上述的第2η型擴散 層，η型擴散層1007相當於上述的第3η型擴散層，η型擴 散層1015’相當於上述的第4η型擴散層。又，金屬配線 1012相當於上述的第1金靥配線，多晶矽層1 00 8相當於 上述的多晶矽層，金屬配線1013相當於上述的第2金屬配 線。 Ο 而，在半導體基板表面上的第1方向（在圖上爲上下方 向），配置形成第1電晶體Τ101和第2電晶體Τ102的電晶 體形成部1030。此電晶體形成部1030由上依序配置：成 爲第1電晶體Τ101之汲極的第In型擴散層1005、形成第 1電晶體之通道的閘極區域部1 003 (第1擴散層1005和第2 擴散層1006之中間的區域）、是第1電晶體T101的源極並 亦成爲第2電晶體之汲極的第2η型擴散層1006、形成第2 電晶體Τ102之通道的閘極區域部1004(第2擴散層1005 和第3擴散層1007之中間的區域）、以及成爲源極的第3η -103- 201010062 型擴散層1007。 在此電晶體形成部1030的左側，在上下方向配置金屬 配線1012。此金屬配線1012從半導體基板表面隔著既定 之距離配置成和電晶體形成部1030平行，又，金屬配線 1012利用接點1010和第1電晶體的汲極（第In型擴散層 1005)連接。又，在左右方向形成多晶矽層1008，使其和第 1電晶體T101的閘極區域部相對向。The row selection transistor, for example, the row selection transistor C101-0~C101-7, selects the row selection signal VP103 outputted from the third bit shift circuit 1403 as a gate input, and selects a memory cell of 1 byte unit. The bit line of the yuan. In this row, the 1-bit tuple bit lines BIT101-0~BIT101-7 selected by the transistors C101-0~C101-7 are selected, and the 1-bit data output line is connected via the row selecting the transistor' DatalOO~Datal07. Moreover, the data input conversion circuit 1500 receives the input signal of the write data Din 100~Din 107 in one byte unit, and performs data writing and data erasing, and outputs the data through the data input lines Data100~Datal07 and The fourth voltage signal VP104» applied to the drain of the first transistor in the bit line, and when the data is read, the data is outputted to the line DatalOO~Datal07 by the sense amplifiers 1600_0~1600-7. The cell data is amplified and output to the outside. In the nonvolatile semiconductor memory device of the present invention shown in the fourth embodiment, the signal applied from the column selection signal output from the column decoder to the selection gate SG100 is converted into the first voltage VP 101. The signal is converted into a signal of the second voltage VP 102 by the row selection signal outputted by the row selection signal. In the selection circuit, the first voltage VP101 is directly transmitted to the selection gate SG1 00, and the second transmission gate transistor is used as the gate input signal of the second voltage VP1 02, and the second voltage VP102 is used. The voltage determined by the threshold 値Vth of the second transfer gate transistor (for example, 〇VP102_Vth) is transmitted to the control gate CG100. Thus, by using the non-volatile semiconductor memory device of the present invention, a non-volatile semiconductor memory device can be constructed while reducing the number of components of the gate voltage selection circuit and reducing the area on the memory cell configuration. Further, by controlling the level of the second voltage VP1 02, a step-up voltage can be applied to the control gate at the time of writing. [Fifth Embodiment] Fig. 11 is a view showing a configuration of a nonvolatile semiconducting memory device according to a fifth embodiment of the present invention, and is a view showing a configuration of a memory cell array. The difference between the non-volatile semiconductor memory device (memory cell array) shown in Fig. 11 and the memory cell array of the fourth embodiment shown in Fig. 10 is the change selection circuit 1300-11. ~1300 - In composition. In the example shown in FIG. 11, instead of the transmission gate transistor 1303 and the switching transistor 1304 shown in FIG. 10, the output of the level shifting circuit 1405 (VP102: signal COL10a) is used as a power source, and is set by An inverter constituted by the PMOS transistor 13 10 and the NMOS transistor 1311 outputs the signal as a signal for controlling the gate CG111. Further, an NMOS transistor 1312 which is a gate input is provided by shifting the output signal COL1OlaB of the path 1403 to 201010062. The other components are the same as those of the memory cell array shown in Fig. 10. In this circuit, the voltage of the CG111 can be directly controlled according to the voltage of the VP102. That is, to raise the control gate CG111 to 3V, 4V, 5V, it is only necessary to raise the VP102 step to 3V, 4V, 5V. As described above, the nonvolatile semiconductor memory device according to the fifth embodiment is configured such that the memory cell is arranged in the same manner as the circuit shown in FIG. 10 except that the selection circuit shown in FIG. 11 is used. It is composed of memory cell blocks of 8-bit units in which row rows are selected in 1-bit units (for example, memory cells Μ 1 1 1 - 0 ~ Μ 1 1 1 -7) in the row direction. Further, the anodes of the first transistor Τ101 of the respective memory cells M111 to Mlmn-7 are connected in common in the column direction by the bit lines BIT 101 - 0 to BIT 10 η - 7. Further, the selection gate SG100 of the gate of the first transistor T101 of the memory cell is connected in common by the selection gate wiring SG101 in the row direction. Further, for each of the memory cell blocks, the control gate CG100 of the gate of the second transistor T102 is connected in common by the control gate wirings Q CGI 1 1 to CGI In in the row direction. Further, source lines S101 to S10n are provided in each row selection range selected by one byte unit in the row direction, and the source of the second transistor of each of the memory cells in all the columns in the row selection range is selected. The source lines S101 to S10n are connected in common. The column decoder 1200 - l ~ 1200-m accepts the address signal and outputs a column selection signal for selecting the memory cell. The first-order shift circuit 1203 converts the signal -96-201010062 output from the column decoders 1200-l~1200-m into a signal applied to the first voltage VP101 of the selection gate SGI00. The row decoders 140-1 to 1400-n accept the address signals and output a row selection signal for selecting the memory cells in units of 1 byte. The second level shifting circuit 1 405 converts the row selection signal output from the row decoders 1 400 - 1 to 1400 - η into the signal of the second voltage VP 102. The third bit shift circuit 1 403 converts the row select signal output from the row decoder into a signal of the third voltage VP103. The selection circuit 1300- 11~1300 - ml transmits the output signal VP 101 of the first level shifting circuit Ο 1203 directly to the selection gate SG100, and simultaneously selects the line selection signal VP102 outputted from the second level shifting circuit 140 5 as The power supply voltage is transmitted from the row selection signal VP102 outputted from the second level shifting circuit 1405 to the control gate CG100. The row selection transistor, for example, the row selection transistors C101-0 to C101-7, uses the row selection signal VP103 output from the third bit shift circuit 1 403 as a gate input, and selects a memory cell of 1 byte unit. Bit line. In this row, the bit lines BIT101 - 0 to BIT101 - 7 of the 1-bit unit selected by the transistors C101 - 0 to C101 - 7 are selected, and the data output of the 1-bit group is connected via the row selecting the transistor ' Enter data line 100~Datal07. Moreover, the data input conversion circuit 1 500 receives the input signal of the write data Din 100 to Din 107 in one byte unit, and performs data writing and data erasing, and outputs the data through the data input and output line Data 100. The data 107 and the bit line are applied to the fourth voltage signal VP104 of the drain of the first transistor. Further, when data is read, the data of the memory cells read by the data output lines Data1OO to Datal07 are amplified by the sense amplifiers 1600 - 〇 1600 and output to the outside. In the nonvolatile semiconductor memory device of the present invention shown in the fifth embodiment, the column selection signal output from the column decoder is converted into a signal of the first voltage VP101, and the first voltage is applied. The VP 101 transmits directly to the selection gate SG 100 of each memory cell block. Further, in the selection circuit of the selected memory cell block, the first voltage VP101 is used as an input signal by using the second voltage VP102 generated from the row selection signal as an input voltage, and is directed to the control gate CG100. The inverter output VP 1 02 is transmitted. Thus, by using the non-volatile semiconductor memory device of the present invention, it is possible to construct a non-volatile semiconductor memory device while reducing the number of components of the selection circuit and reducing the area on the memory cell configuration. Further, by controlling the level of the second voltage VP 102, a stepping voltage can be applied to the control gate at the time of writing. [Fourth embodiment] Fig. 12 is a view showing a configuration of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention, showing an arrangement of memory cells. The memory cell array shown in Fig. 12 is a view showing an arrangement example of memory cell units shown in Figs. 1A to 1H1E. As shown in Fig. 12, the control gate wirings CG111, CG121, CG131, ... are passed in the lateral direction, and the bit lines BIT101, BIT102, BIT103, ... are passed in the vertical direction, and the first to fourth views are arranged symmetrically in the vertical direction. The memory cell unit of Fig. 1E shares a capacitor on the n-type well to reduce the area. For example, in the memory cells arranged in the upper two segments, the common source S 1 0 1 , the selection gate SG100 of the transistor 101 of each memory cell arranged on the upper side of the source S101 (polycrystalline layer 1〇〇8) ) Connected to the shared selection gate wiring (multi-98- 201010062 wafer wiring) SG111. Further, the control gate wiring 1019 to which the control gate CG100 of the transistor 各 02 of each memory cell is connected is connected to the common control gate wiring (metal wiring) CG111. Similarly, the second metal wiring 1013 of the transistor Τ102 is connected to the common source line S101. The selection gate SG 100 of the transistor Τ 1 0 1 of each memory cell arranged on the lower side of the shared source line S 1 0 1 is connected to the common selection gate wiring (polysilicon wiring) SG1 2 1 , each The control gate CG100 of the transistor Τ102 of the memory cell is connected to the common control gate wiring (metal wiring) CG121. Also, €) The memory cells arranged in the two segments on the lower side are also in the same arrangement. By performing such an arrangement, the empty space on the semiconductor substrate is eliminated, making it an efficient arrangement. Also, in terms of characteristics, it is also the best configuration in terms of area. As described above, each of the memory cells of the nonvolatile semiconductor memory device shown in FIG. 12 is a memory cell shown in the first to the first drawing, and the memory cell shown in the first to the first is as shown in FIG. As shown above, the components are arranged as shown below. In other words, referring to the first to first drawings, the transistor forming portion 1030 in which the first transistor 101 and the second transistor 102 are formed is disposed in the first direction on the surface of the semiconductor substrate (in the vertical direction in the first drawing). The transistor forming portion 1030 is disposed in order from the top, the first inversion layer 1 成为5 which is the drain of the first transistor 101, and the first gate region in which the channel of the first transistor is formed (first a region between the diffusion layer 1005 and the second diffusion layer 1006), a source of the first transistor T101, and a second n-type diffusion layer 1006 that also serves as a drain of the second transistor, and a channel for forming the second transistor T102. The second gate region portion (the region between the second diffusion layer 1005 and the third diffusion layer 1007-99-201010062) and the third n-type diffusion layer 1007 serving as the source. On the left side of the transistor forming portion 1030, the first metal wiring 1012 is disposed in the vertical direction. The metal wiring 1012 is disposed in parallel with the transistor forming portion 1030 from the surface of the semiconductor substrate at a predetermined distance, and the metal wiring 1012 is connected to the drain of the first transistor (the first in-type diffusion layer 1005) by a contact. Further, the polysilicon layer 1〇〇8 is formed in the left-right direction so as to face the gate region portion of the first transistor, and a square shape is formed in the left-right direction with a predetermined width and depth on the left side of the transistor forming portion 1030. Η-type well 1002. The square floating gate 1〇〇9 is disposed to face the surface of the semiconductor substrate in the left-right direction while being disposed such that the region on the left end side thereof faces the surface of the n-type well 1002, and the region on the right end side and the second electric portion The second gate region portion of the crystal (the channel formation region between the second n-type diffusion layer 1 006 and the third n-type diffusion layer 1 007) faces each other. On the left side of the n-type well 1002, a p-type diffusion layer 1015 is formed in the left-right direction adjacent to the left side of the region opposite to the floating gate 1009 of the n-type well 1002, and has a predetermined width and depth. The p-type diffusion layer 1 〇 15 and the control gate wiring 1 0 1 9 are connected by a contact 1 0 16 . The control gate wiring 1019 is disposed to face the floating gate 1009 in the left-right direction with a predetermined distance from the surface of the semiconductor substrate, and is connected to the 扩散-type diffusion layer 1015 by the contact 1〇16. The second metal wiring 1013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the third n-type diffusion layer 1007 which is the source of the second transistor Τ102, and the second metal wiring 1013 uses the contact 1011 and The third n-type diffusion layer 1 007 is connected. 201010062 Further, in the nonvolatile semiconductor memory device shown in Fig. 12, a total of four memory cells and two memory cells are arranged as a basic unit of arrangement, and are arranged in parallel in the left-right direction. At the same time, four memory cells which are the basic units of the arrangement are arranged in parallel in the vertical direction, and the two memory cells share the n-type well 1002 with each other, and the first eight figures to the first one are arranged symmetrically left and right. In the memory cell shown in the figure, the two non-volatile semiconductor memory elements share the two memory cells symmetrically arranged to each other, and share the metal wiring 1〇13 (the common source line S101) with each other, and In the non-volatile semiconductor memory device of the present invention shown in the sixth embodiment, in the arrangement of the memory cells, the total of two memory cells and two memory cells are four. As the basic unit of the arrangement, the memory cells are arranged in parallel in the left and right and up and down directions, and the four memory cells are arranged in parallel with each other, and the two memory cells share the first picture 1 to the first picture. Memory cell η-type well, and symmetrically arranged, the two non-volatile semiconductor memory device of symmetrically disposed about the two square memory cell element, are arranged symmetrically in the downward direction. Thus, according to the present invention, the non-volatile semiconductor memory device can be closely arranged and the area of the non-volatile semiconductor memory device can be minimized. Further, in the sixth embodiment shown in Fig. 12, the metal wiring 1012 is placed in the memory cell (the cell line selected by the bit line BIT 102 and the gate line SGI 1 1). The left side of the crystal forming portion 1030 is the same as that disposed on the upper side or the right side. In this case, in the case of being arranged on the right side, since the memory cell size is determined by the interval of the metal wiring 1 〇 1 2, the memory cell size becomes slightly larger. [Embodiment 7] FIG. 13A and FIG. 13B are views showing the configuration of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention, and showing the configuration of a memory cell. Fig. 13A is a plan view. Fig. 13B is a cross-sectional view taken along B10-B10. In the memory cell shown, because η is omitted. Since the NMOS capacitor is provided in the well, the 扩散-type diffusion layer 1015 is changed to the n-type diffusion layer 1015' (the fourth iv type diffusion layer). Since the capacitor 1〇14 becomes an NMOS capacitor, a channel injection 1021 of a depletion type is performed under the gate of the capacitor 1014, so that the inversion layer is always present, so that coupling can be performed efficiently. . For standard CMOS processes, D-type channel injection is required, but because of the additional injection step, the total steps are only slightly increased, and it does not become a burden of the complexity of the process. The memory cell shown in Figs. 13A and 13B and the memory cell shown in Fig. 1A to Fig. 1E are different in composition, and the n-type well shown in Fig. 11) 2, and the p-type diffusion layer 1〇15 is changed to the n-type diffusion layer 1015', and a depletion-type channel injection 1021 shown in Fig. 13 is instead provided. In other words, the first In-type diffusion layer 1005 which is the drain of the first transistor T101 and the gate region 1 which forms the channel of the first transistor τιί, in the transistor forming portion 1030 shown in the first to the first drawings. 〇〇3 (a region between the first in-type diffusion layer 1 005 and the second n-type diffusion layer 1006), a source of the transistor T101, and a second n-type diffusion layer 1006 which is also a drain of the transistor T102. 2 gate region portion 1〇〇4 of the channel of the transistor T102 (a region between the second n-type diffusion layer 1〇〇5 and the third n-type diffusion layer 1 00 7) and a third n-type diffusion layer 1007 serving as a source The configuration of -102-201010062 is the same, and the same applies to the polysilicon layer 1008, the metal wirings 1012 and 1013, the control gate wiring, and the like. Further, the equivalent circuit formed by the transistor T101 and the transistor T1 02 shown in Fig. 1B is also the same. Therefore, the same components are denoted by the same reference numerals, and the repeated description is omitted. As described above, in the memory cells shown in Figs. 13A and 13B, the n-type well is omitted for the memory cells shown in Figs. 1A to 1E, and the area reduction effect can be further enhanced. Further, in the seventh embodiment, the transistor Τ101 corresponds to the above-described first 电1 transistor, and the transistor Τ102 corresponds to the above-described second transistor. Further, the n-type diffusion layer 1005 corresponds to the above-described first In-type diffusion layer which is the drain of the first transistor, the n-type diffusion layer 1 006 corresponds to the above-described second n-type diffusion layer, and the n-type diffusion layer 1007 corresponds to the above The third n-type diffusion layer and the n-type diffusion layer 1015' correspond to the above-described fourth n-type diffusion layer. Further, the metal wiring 1012 corresponds to the above-described first metal wiring, the polysilicon layer 1 00 8 corresponds to the above-described polysilicon layer, and the metal wiring 1013 corresponds to the above-described second metal wiring. Further, in the first direction (upward and downward in the drawing) on the surface of the semiconductor substrate, the electric crystal forming portion 1030 in which the first transistor 101 and the second transistor 102 are formed is disposed. The transistor forming portion 1030 is disposed in order from the top, the first inversion layer 1005 which is the drain of the first transistor 101, and the gate region 1003 in which the channel of the first transistor is formed (the first diffusion layer 1005 and The region between the second diffusion layer 1006) is the second n-type diffusion layer 1006 which is the source of the first transistor T101 and also serves as the drain of the second transistor, and the gate region where the channel of the second transistor 102 is formed. The portion 1004 (the region between the second diffusion layer 1005 and the third diffusion layer 1007) and the third η-103-201010062 diffusion layer 1007 serving as the source. On the left side of the transistor forming portion 1030, the metal wiring 1012 is disposed in the vertical direction. The metal wiring 1012 is disposed in parallel with the transistor forming portion 1030 from the surface of the semiconductor substrate at a predetermined distance, and the metal wiring 1012 is connected to the drain of the first transistor (the first in-type diffusion layer 1005) by the contact 1010. Further, the polysilicon layer 1008 is formed in the left-right direction so as to face the gate region portion of the first transistor T101.
又，在電晶體形成部1 03 0的左側，以既定之寬度和深 度在左右方向所形成方形的空乏型（depletion— type)通道 注入1021。方形的浮動閘極1009在左右方向配置成和半 導體基板表面相對向，同時配置成其左端部側的區域和通 道注入1021相對向，而且右端部側的區域和第2電晶體的 第2閘極區域部1 004(第2n型擴散層1 006和第3η型擴散 層1 007之中間的通道形成區域）相對向。Further, on the left side of the transistor forming portion 101 0, a depletion-type channel 1011 formed in a square shape with a predetermined width and depth in the left-right direction is injected. The square floating gate 1009 is disposed in the left-right direction so as to face the surface of the semiconductor substrate, and is disposed such that the region on the left end side thereof faces the channel injection 1021, and the region on the right end side and the second gate of the second transistor. The region portion 1 004 (the channel formation region between the 2nd n-type diffusion layer 1 006 and the 3rd n-type diffusion layer 1 007) faces each other.
在通道注入1 02 1的左側，以和通道注入1 02 1相鄰的 方式在左右方向形成η型擴散層1015’ ，此η型擴散層 1 0 1 5 ’和控制閘極配線1 0 1 9利用接點1 0 1 6連接。控制閘 極配線1019從半導體基板表面隔著既定之距離在左右方 向配置成和浮動閘極1009相對向，又，利用接點1〇16和 η型擴散層1015’連接。第2金屬配線1013從半導體基板 表面隔著既定之距離在左右方向配置成和成爲第2電晶體 Τ102之源極的第3η型擴散層1 007相對向，此金屬配線 1013利用接點1011和第3η型擴散層1007連接。 如此，在第7實施形態所示之本發明的非揮發性半導 體記憶元件，作爲非揮發性半導體記憶元件之布置’在上 -104- 201010062 下方向（縱向）配置形成第1電晶體T101及第2電晶體ΤΙ 02 的電晶體形成部1 030，在此電晶體形成部1 030的左側， 配置和第1電晶體之汲極連接的金屬配線（位元線），又， 在左右方向（橫向）配置第1電晶體的閘極層（多晶矽層 1 〇〇8)及和第2電晶體Τ1 02之源極連接的金屬配線1013。 又，將空乏型通道注入102 1形成於電晶體形成部的左 側，在左右方向將浮動閘極10 09配置成和通道注入1021 的表面及第2閘極區域部（第2η型擴散層1006和第3η型 〇 擴散層1007之中間的通道形成區域）相對向，在左右方向 亦配置和對此浮動閘極賦與電位之控制閘極端子連接的控 制閘極配線1 〇 1 9。 因而，除了可緊密地配置面積變大的電容器（在浮動閘 極和半導體基板表面所形成之電容器），使面積變成最小限 度之效果以外，還對第1人圖~第1Ε圖所示的記憶胞元， 可省略η型井，發揮更大之面積縮小效果。 此外，在第13Α圖及第13Β圖所示之第7實施形態， 〇 雖然金屬配線1012配置於電晶體形成部1030的左側，但 是亦可配置於右側》 [第8實施形態] 第14圖係表示本發明之第8實施形態的非揮發性半導 體記憶裝置的構成圖，表示記憶胞元的布置配置。 在第14圖所示的記憶胞元陣列，是將第13Α圖及第 13Β圖所示之記億胞元單元配置於陣列上。在本例，和第 12圖所示之記憶胞元的布置配置一樣，在圖上對稱地配置 上下左右，可將面積縮小省略η型井的份量。 -105- 201010062 即，作爲記憶胞元，在第14圖，著眼於由位元線BIT 102 和控制閘極配線CGU1所選擇的記憶胞元時，在此記憶胞 元，在半導體基板表面上的第1方向（在圖上爲上下方向）， 配置形成第1電晶體T101和第2電晶體T1 02的電晶體形 成部1 030。 此電晶體形成部1 03 0由上依序配置：成爲第1電晶體 T101之汲極的第In型擴散層1005、形成第1電晶體之通 道的閘極區域部（第1擴散層1 00 5和第2擴散層1006之中 間的區域）、是第1電晶體T101的源極並亦成爲第2電晶 體之汲極的第2n型擴散層1006、形成第2電晶體T102之 通道的閘極區域部（第2擴散層1 005和第3 擴散層1007 之中間的區域）、以及成爲源極的第3n型擴散層1 007。 在此電晶體形成部1030的左側，在上下方向配置第1 金屬配線1012 » 此金屬配線1012從半導體基板表面隔著既定之距離 配置成和電晶體形成部1030平行，又，第1金屬配線1012 利用接點和第1電晶體的汲極（第In型擴散層1005)連接。 又，在左右方向形成多晶矽層1〇〇8,使其和第1電晶體的 閘極區域部相對向。第1金屬配線1012和位元線BIT 102 連接。多晶矽層1008和共用之選擇閘極SG111連接。 又，在電晶體形成部1 030的左側，左右方向形成方形 的空乏型（depletion - type)通道注入（參照第13B圖的通道 注入1021)。方形的浮動閘極1009在左右方向配置成和半 導體基板表面相對向，同時配置成其左端部側的區域和通 道注入的表面相對向，而且右端部側的區域和第2電晶體 -106- 201010062 的第2閘極區域部（第2η型擴散層1006和第3η型擴散層 1007之中間的通道形成區域）相對向。 在通道注入的左側’在左右方向將η型擴散層1〇15’ 形成爲和此通道注入相鄰，此η型擴散層1015’和控制閘 極配線1019利用接點連接。控制鬧極配線1〇19在左右方 向配置成和浮動閘極1009相對向，又，利用接點1016和 η型擴散層1015’連接。第2金屬配線1013在左右方向配 置成和成爲第2電晶體Τ102之源極的第3η型擴散層1〇〇7 Ο 相對向，此金屬配線1013利用接點1011和第3η型擴散層 1 0 07連接。控制閘極配線1019和共用的控制閘極配線 CG111連接，金屬配線1013和共用的源極線S101連接。 而且，將使彼此共用η型井1002並在左右對稱地配置 的2個記憶胞元，及對該左右對稱地配置之2個記憶胞元， 使彼此共用金屬配線1013並在下方向對稱地配置的2個記 億胞元之合計4個記憶胞元作爲配置的基本單位，在左右 方向及上下方向平行地排列配置成爲此基本單位的4個記 ©憶胞元。 因而，可緊密地配置面本發明的非揮發性半導體記憶 元件，並可使非揮發性半導體記憶裝置的面積變成最小限 度。 此外，在第14圖所示之第8實施形態，雖然在成爲基 本之記憶胞元（由位元線ΒΙΤ102和選擇閘極配線SG111所 選擇的記憶胞元），將金屬配線1012配置於電晶體形成部 1030的左側，但是配置於正上或右側亦一樣。其中，在本 例，配置於右側時，因爲記憶胞元尺寸由金靥配線1012的 -107- 201010062 間隔所決定，所以有記憶胞元尺寸變成稍大的情況。 [第9實施形態] 第15圖係表示本發明之第9實施形態的非揮發性半導 體記憶裝置的構成圖，是表示記憶胞元的布置配置。 相對於第13A圖及第13B圖所示的記憶胞元，將浮動 閘極和控制閘極的電容器配置於電晶體T101和T102的左 側，第15圖所示的記憶胞元，分開地配置於電晶體T101 和T 1 0 2的左右。 即，第1空乏型通道注入1021A形成於電晶體形成部 1030的左側，第2空乏型通道注入102 1B形成於電晶體形 成部1 03 0的右側。又，將成爲控制閘極之第5η型擴散層 1015Α設置成和第1通道注入1021 Α的左側相鄰，將成爲 控制閘極之第6n型擴散層101 5B設置成和第2通道注入 1021B的右側相鄰。而且，在左右方向配置浮動閘極1 009， 使浮動閘極1009之兩端部的區域和第1及第2之2個通道 注入1021A及通道注入1021B的表面相對向，而且中央和 第2電晶體的第2閘極區域部（第2n型擴散層1006和第3η 型擴散層1 007之中間的通道形成區域）相對向。 而，在各記憶胞元的配置，在左右方向將記憶胞元排 列成彼此共用成爲控制閘極CG100的第5及第6η型擴散 層1015Α及1015Β。此η型擴散層1015Α及1015Β利用控 制閘極配線1019和控制閘極配線CG111共同連接。又， 對在左右方向所排列之記憶胞元，共用金屬配線1013,在 下方向對稱地排列記憶胞元。 而，在如第1 5圖所示配置記憶胞元的情況，共用源極 -108- 201010062 線S 1 0 1，在上側所排列之各記憶胞元之電晶體τ 1 0 1的選 擇閘極SG100和共用之選擇閘極配線（多晶矽配線）SG1U 連接，各記憶胞元之電晶體T102的控制閘極CG100和共 用之控制閘極配線（金屬配線）CG111連接。一樣地，在下 側所排列之各記憶胞元之電晶體T101的選擇閘極SG100 和共用之選擇閘極配線（多晶矽配線）SG121連接，各記憶 胞元之電晶體T102的控制閘極CG100和共用之控制閘極 配線（金屬配線）CG121連接。 〇 依此方式，浮動閘極之左右對遮罩偏差具有邊限（特性 不變），又，在加工上，亦取得平衡，可消除微細加工時之 圖型相依性》 如此，在第9實施形態所示之本發明的非揮發性半導 體記憶裝置，作爲記憶胞元的布置構成，在圖上在上下方 向（縱向）配置形成第1電晶體T101及第2電晶體T102的 電晶體形成部1 030，在此電晶體形成部的左側，配置和第 1電晶體T101之汲極連接的第1金屬配線1012。此第1 Q 金屬配線1012和共用的位元線BIT1 01連接。 又，在左右方向（橫向）配置第1電晶體T101的閘極層 及和第2電晶體T102之源極連接的第2金屬配線1013。 多晶矽層1008和共用的選擇閘極配線SG111連接。第2 金屬配線1013和共用的源極線S101連接。 又，將第1空乏型通道注入102 1A形成於電晶體形成 部1 03 0的左側，將第2空乏型通道注入102 1B形成於電晶 體形成部1 03 0的右側。又，將成爲對控制閘極配線1019 之連接端子的第5n型擴散層1015A設置成和第1通道注入 -109- 201010062 1021A的左側相鄰，將成爲對控制閘極配線1019之連接端 子的第6ιι型擴散層1015B設置成和第2通道注入1021B 的右側相鄰。 而，在左右方向將浮動閘極1009配置成兩端部的區域 和第1及第2之2個通道注入1021Α及1021Β的表面相對 向，而且中央部和第2電晶體之第2閘極區域部（第2η型 擴散層1006和第3η型擴散層1007之中間的通道形成區域） 相對向，亦在在左右方向配置控制閘極配線1019。此控制 閘極配線1019和共用的控制閘極配線CG111連接。 而’在各記憶胞元的配置，在左右方向將記憶胞元排 列成彼此共用成爲對控制閘極配線1019之連接端子的第5 及第6η型擴散層1〇1 5Α及101 5Β，同時對在左右方向所排 列之記憶胞元’在下方向將記憶胞元對稱地排列成共用第 2金屬配線1013(源極線S101)。 因而’在非揮發性半導體記憶裝置，可配置記憶胞元 陣列，而不會增加記憶胞元的面積。 此外，在第15圖所示的第9實施形態，雖然在記憶胞 元，金屬配線1012金屬配線電晶體形成部1〇3〇的左側， 但是亦可配置於正上或配置於右側。 [第10實施形態] 第10圖係表示本發明之第10實施形態的非揮發性半 導體記憶裝置的構成圖，是追加副接點的例子。 第10圖所示之非揮發性半導體記憶元件和第13A圖 及第13B圖所不之非揮發性半導體記憶元件在構成上的相 異點’是追加第16圖所示的副接點ι〇22與1〇23、及用以 -110- 201010062 取副接點配線1 024與副接點的p型擴散層區域1 025，其 他的構成是和第13A圖及第13B圖所示的非揮發性半導體 記憶元件一樣。因而’對相同的構成部分附加相同的符號， 並省略重複說明。 本發明之記憶胞元的熱電子寫入方式，因爲在飽和區 域使電流流動，所以電流流向基板（基體）。一般，在飽和 區域之基板電流，在經驗上最大是在汲極-源極間流動之 電流的約20%。電流流向基板時，基板記憶胞元附近的基 ® 板電位上昇，而產生誤動作。爲了避免之，需要在記憶胞 元的附近取副接點。 在第16圖所示的例子，是可取得副接點的配置，不會 使記憶胞元的面積增加，面積效果亦大》 如此’在第10實施形態所示之本發明的非揮發性半導 體記憶元件，使用第13A圖及第13B圖所示的非揮發性半 導體記憶元件，在此第13A圖及第13B圖所示的非揮發性 半導體記憶元件，以MOS構造的第1電晶體和具有浮動閘 Ο 極的第2電晶體構成非揮發性半導體記憶元件。 而’作爲其布置配置，在圖上的上下方向（縱向）配置 包含用以形成第1電晶體T101及第2電晶體T102之擴散 層的電晶體形成部1030,在此電晶體形成部1030的左側， 將和第1電晶體之汲極連接的第1金屬配線1012配置成和 該電晶體形成部1030平行（上下方向）。 又’在左右方向（橫向）配置成爲第1電晶體之閘極之 方形的多晶矽層1008、及和第2電晶體T102之源極連接 的第2金屬配線1013。多晶矽層1008和共用的選擇閘極 -111 - 201010062 配線SGI 1 1連接.On the left side of the channel injection 1011, an n-type diffusion layer 1015' is formed in the left-right direction in a manner adjacent to the channel injection 1011, the n-type diffusion layer 1 0 1 5 ' and the control gate wiring 1 0 1 9 Connect with contacts 1 0 1 6 . The control gate wiring 1019 is disposed so as to face the floating gate 1009 in the left-right direction from the surface of the semiconductor substrate with a predetermined distance therebetween, and is connected to the n-type diffusion layer 1015' by the contact 1〇16. The second metal wiring 1013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the third n-type diffusion layer 007 which is the source of the second transistor Τ102, and the metal wiring 1013 uses the contact 1011 and the The 3n-type diffusion layer 1007 is connected. As described above, in the nonvolatile semiconductor memory device of the present invention shown in the seventh embodiment, the arrangement of the nonvolatile semiconductor memory device is configured such that the first transistor T101 and the first transistor are arranged in the downward direction (longitudinal direction) of the upper-104-201010062. 2, the transistor forming portion 1 030 of the transistor ΤΙ 02, on the left side of the transistor forming portion 1 030, and the metal wiring (bit line) connected to the drain of the first transistor, and in the left-right direction (lateral direction) The gate layer (polysilicon layer 1 〇〇 8) of the first transistor and the metal wiring 1013 connected to the source of the second transistor Τ 102 are disposed. Further, the depletion channel injection 102 1 is formed on the left side of the transistor formation portion, and the floating gate electrode 10 09 is disposed in the left and right direction with the surface of the channel injection 1021 and the second gate region portion (the second n-type diffusion layer 1006 and The channel forming region in the middle of the third n-type germanium diffusion layer 1007 is opposed to each other, and the control gate wiring 1 〇1 9 connected to the control gate terminal of the floating gate is also disposed in the left-right direction. Therefore, in addition to the effect that the capacitor having a large area (the capacitor formed on the floating gate and the surface of the semiconductor substrate) can be closely arranged, the area is minimized, and the memory shown in the first figure to the first figure is also used. The cell can omit the n-type well and exert a larger area reduction effect. Further, in the seventh embodiment shown in Fig. 13 and Fig. 13 , the metal wiring 1012 is disposed on the left side of the transistor forming portion 1030, but may be disposed on the right side. [Eighth Embodiment] Fig. 14 A configuration diagram of a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention, showing arrangement of memory cells. In the memory cell array shown in Fig. 14, the cells of the cells shown in Fig. 13 and Fig. 13 are arranged on the array. In this example, as in the arrangement of the memory cells shown in Fig. 12, the upper and lower sides are symmetrically arranged on the drawing, and the area can be reduced to omit the weight of the n-type well. -105- 201010062 That is, as a memory cell, in Fig. 14, focusing on the memory cell selected by the bit line BIT 102 and the control gate line CGU1, the memory cell is on the surface of the semiconductor substrate. In the first direction (upward and downward directions in the drawing), the transistor forming portion 1 030 in which the first transistor T101 and the second transistor T1 02 are formed is disposed. The transistor forming portion 1 0 0 is arranged in order from the top: the In-type diffusion layer 1005 which becomes the drain of the first transistor T101, and the gate region portion which forms the channel of the first transistor (the first diffusion layer 100) a region between the fifth and second diffusion layers 1006), a source of the first transistor T101, a second n-type diffusion layer 1006 that also serves as a drain of the second transistor, and a gate that forms a channel of the second transistor T102. The polar region portion (the region between the second diffusion layer 1 005 and the third diffusion layer 1007) and the third n-type diffusion layer 1 007 serving as the source. The first metal wiring 1012 is disposed on the left side of the transistor forming portion 1030 in the vertical direction. The metal wiring 1012 is disposed in parallel with the transistor forming portion 1030 from the surface of the semiconductor substrate at a predetermined distance, and the first metal wiring 1012 is further disposed. The contact is connected to the drain of the first transistor (the first in-type diffusion layer 1005). Further, the polysilicon layer 1 8 is formed in the left-right direction so as to face the gate region portion of the first transistor. The first metal wiring 1012 is connected to the bit line BIT 102. The polysilicon layer 1008 is connected to the common selection gate SG111. Further, on the left side of the transistor forming portion 1 030, a square depletion-type channel injection is formed in the left-right direction (see the channel injection 1021 of Fig. 13B). The square floating gate 1009 is disposed to face the surface of the semiconductor substrate in the left-right direction while being disposed such that the region on the left end side thereof faces the surface on which the channel is implanted, and the region on the right end side and the second transistor -106 - 201010062 The second gate region portion (the channel formation region between the second n-type diffusion layer 1006 and the third n-type diffusion layer 1007) faces each other. The n-type diffusion layer 1〇15' is formed adjacent to the channel in the left-right direction on the left side of the channel injection, and the n-type diffusion layer 1015' and the control gate wiring 1019 are connected by a contact. The control wiring 1〇19 is disposed to face the floating gate 1009 in the left-right direction, and is connected to the n-type diffusion layer 1015' by the contact 1016. The second metal wiring 1013 is disposed to face the third n-type diffusion layer 1〇〇7 成为 which is the source of the second transistor Τ102 in the left-right direction, and the metal wiring 1013 uses the contact 1011 and the third n-type diffusion layer 10 07 connection. The control gate wiring 1019 is connected to the common control gate wiring CG111, and the metal wiring 1013 is connected to the common source line S101. In addition, two memory cells in which the n-type well 1002 is shared with each other and symmetrically arranged in the left-right direction, and two memory cells that are symmetrically arranged in the left and right are used, and the metal wires 1013 are shared with each other and arranged symmetrically in the lower direction. The four memory cells of the two cells are arranged as the basic unit of the arrangement, and four memory cells which are the basic units are arranged in parallel in the left-right direction and the vertical direction. Thus, the non-volatile semiconductor memory device of the present invention can be closely arranged and the area of the non-volatile semiconductor memory device can be minimized. Further, in the eighth embodiment shown in Fig. 14, the metal wiring 1012 is disposed in the transistor in the basic memory cell (the memory cell selected by the bit line 102 and the gate line SG111). The left side of the portion 1030 is formed, but it is also disposed on the upper side or the right side. However, in this example, when it is placed on the right side, since the memory cell size is determined by the interval of -107 - 201010062 of the gold wire 1012, the memory cell size becomes slightly larger. [Embodiment 9] Fig. 15 is a view showing a configuration of a nonvolatile semiconductor memory device according to a ninth embodiment of the present invention, showing an arrangement arrangement of memory cells. The memory of the floating gate and the control gate is disposed on the left side of the transistors T101 and T102 with respect to the memory cells shown in FIGS. 13A and 13B, and the memory cells shown in FIG. 15 are separately disposed in The left and right of the transistor T101 and T 1 0 2 . That is, the first depletion channel injection 1021A is formed on the left side of the transistor forming portion 1030, and the second depletion channel injection 102 1B is formed on the right side of the transistor forming portion 103. Further, the fifth n-type diffusion layer 1015 that is the control gate is disposed adjacent to the left side of the first channel injection 1021, and the sixth n-type diffusion layer 101 5B that serves as the control gate is disposed to be implanted with the second channel 1021B. Adjacent to the right. Further, the floating gate 1 009 is disposed in the left-right direction such that the region of both ends of the floating gate 1009 and the surfaces of the first and second channels are in contact with the surface of the 1021A and the channel implant 1021B, and the center and the second electrode are opposite to each other. The second gate region portion of the crystal (the channel formation region between the second n-type diffusion layer 1006 and the third n-type diffusion layer 1 007) faces each other. On the other hand, in the arrangement of the memory cells, the memory cells are arranged in the left-right direction to be the fifth and sixth n-type diffusion layers 1015A and 1015A which are used to control the gate CG100. The n-type diffusion layers 1015A and 1015 are commonly connected by the control gate wiring 1019 and the control gate wiring CG111. Further, the memory cells arranged in the left-right direction share the metal wiring 1013, and the memory cells are arranged symmetrically in the lower direction. However, in the case where the memory cells are arranged as shown in FIG. 5, the source-108-201010062 line S 1 0 1 is selected, and the selection gate of the transistor τ 1 0 1 of each memory cell arranged on the upper side is selected. The SG 100 is connected to a common selection gate wiring (polysilicon wiring) SG1U, and the control gate CG100 of the transistor T102 of each memory cell is connected to the common control gate wiring (metal wiring) CG111. Similarly, the selection gate SG100 of the transistor T101 of each memory cell arranged on the lower side is connected to the common selection gate wiring (polysilicon wiring) SG121, and the control gate CG100 of the transistor T102 of each memory cell is shared. The control gate wiring (metal wiring) CG121 is connected. In this way, the left and right of the floating gate have a margin (the characteristic is unchanged) for the mask deviation, and in the processing, the balance is also obtained, which can eliminate the pattern dependence during the micro processing. Thus, in the ninth implementation The non-volatile semiconductor memory device of the present invention has a configuration in which the memory cells are arranged, and the transistor forming portion 1 in which the first transistor T101 and the second transistor T102 are formed in the vertical direction (longitudinal direction) is arranged on the drawing. 030, on the left side of the transistor forming portion, a first metal wiring 1012 that is connected to the drain of the first transistor T101 is disposed. The first Q metal wiring 1012 is connected to the common bit line BIT101. Further, the gate layer of the first transistor T101 and the second metal wiring 1013 connected to the source of the second transistor T102 are arranged in the left-right direction (lateral direction). The polysilicon layer 1008 is connected to the common selection gate wiring SG111. The second metal wiring 1013 is connected to the common source line S101. Further, the first depletion channel injection 102 1A is formed on the left side of the transistor formation portion 100 0 , and the second depletion channel injection 102 1B is formed on the right side of the electromorph formation portion 1 03 0 . Moreover, the fifth n-type diffusion layer 1015A which is a connection terminal for controlling the gate wiring 1019 is provided adjacent to the left side of the first channel injection -109-201010062 1021A, and becomes the connection terminal of the control gate wiring 1019. The 6 ι type diffusion layer 1015B is disposed adjacent to the right side of the second channel injection 1021B. In the left-right direction, the floating gate 1009 is disposed such that the end portions are opposed to the surfaces of the first and second channel injections 1021 and 1021, and the central portion and the second gate region of the second transistor. In the opposing direction (the channel forming region between the second n-type diffusion layer 1006 and the third n-type diffusion layer 1007), the control gate wiring 1019 is also disposed in the left-right direction. This control gate wiring 1019 is connected to the common control gate wiring CG111. On the other hand, in the arrangement of the memory cells, the memory cells are arranged in the left-right direction to become the fifth and sixth n-type diffusion layers 1〇1 5Α and 101 5Β which are connected to the connection terminals of the gate line 1019, and The memory cells arranged in the left-right direction symmetrically arrange the memory cells in the lower direction to share the second metal interconnection 1013 (source line S101). Thus, in a non-volatile semiconductor memory device, a memory cell array can be configured without increasing the area of memory cells. Further, in the ninth embodiment shown in Fig. 15, the metal wiring 1012 is disposed on the left side of the metal wiring transistor forming portion 1〇3〇 in the memory cell, but may be disposed directly above or on the right side. [Tenth embodiment] FIG. 10 is a view showing a configuration of a nonvolatile semiconductor memory device according to a tenth embodiment of the present invention, and is an example in which a sub-contact is added. The difference between the non-volatile semiconductor memory device shown in FIG. 10 and the non-volatile semiconductor memory device shown in FIGS. 13A and 13B is the addition of the sub-contact ι shown in FIG. 22 and 1〇23, and the p-type diffusion layer region 1 025 for the sub-contact wiring 1 024 and the sub-contact for -110-201010062, the other configuration is non-volatile as shown in Figs. 13A and 13B. The same is true for semiconductor memory elements. Therefore, the same components are denoted by the same reference numerals, and the repeated description is omitted. In the hot electron writing mode of the memory cell of the present invention, since current flows in the saturation region, current flows to the substrate (base). Typically, the substrate current in the saturated region is empirically at most about 20% of the current flowing between the drain and source. When a current flows to the substrate, the potential of the base plate near the memory cell of the substrate rises, causing malfunction. In order to avoid this, it is necessary to take a sub-contact in the vicinity of the memory cell. In the example shown in Fig. 16, the arrangement of the sub-contacts is obtained, and the area of the memory cells is not increased, and the area effect is also large. Thus, the non-volatile semiconductor of the present invention shown in the tenth embodiment The memory element uses the non-volatile semiconductor memory element shown in FIGS. 13A and 13B, and the non-volatile semiconductor memory element shown in FIGS. 13A and 13B, the first transistor having the MOS structure and having The second transistor of the floating gate constitutes a non-volatile semiconductor memory element. In the arrangement, the transistor forming portion 1030 including the diffusion layers for forming the first transistor T101 and the second transistor T102 is disposed in the vertical direction (longitudinal direction) on the drawing, where the transistor forming portion 1030 is On the left side, the first metal wiring 1012 connected to the drain of the first transistor is placed in parallel with the transistor forming portion 1030 (vertical direction). Further, a polycrystalline germanium layer 1008 which is a square of the gate of the first transistor and a second metal wiring 1013 which is connected to the source of the second transistor T102 are disposed in the left-right direction (lateral direction). Polycrystalline germanium layer 1008 and shared select gate -111 - 201010062 wiring SGI 1 1 connection.
又，將方形之空乏型通道注入（參照第13B圖所示的通 道注入1021)形成於電晶體形成部1030的左側。而且，在 左右方向將方形的浮動閘極1〇〇9配置成一部分和通道注 入的表面相對向，且該一部分和第2電晶體的第2閘極區 域部（第2ri型擴散層1006和第3n型擴散層1007之中間的 通道形成區域）相對向。在左右方向亦配置用以對此浮動閘 極1 009賦與電位之控制閘極配線1019。此外，在第1金 屬配線1012的左側，而且在成爲第1電晶體T101之閘極 之方形之多晶矽層1 〇 〇 8之上側的位置，設置用以抑制形成 記憶胞元之半導體基板之區域之電壓上昇的副接點1 02 3、 1024以及p型擴散層區域1025。 因而，在非揮發性半導體記憶裝置，除了可減少記憶 胞元之配置面積的效果以外，還可追加副接點，不會增加 記憶胞元的面積。Further, a square void-type channel is implanted (see the channel injection 1021 shown in Fig. 13B) on the left side of the transistor forming portion 1030. Further, the square floating gate 1〇〇9 is disposed in the left-right direction so that a part thereof faces the surface of the channel injection, and the portion and the second gate region of the second transistor (the second ri-type diffusion layer 1006 and the The channel forming region in the middle of the 3n-type diffusion layer 1007 is opposed to each other. A control gate wiring 1019 for applying a potential to the floating gate 1 009 is also disposed in the left-right direction. Further, on the left side of the first metal wiring 1012, and at a position above the square polysilicon layer 1 〇〇 8 which is the gate of the first transistor T101, a region for suppressing formation of the semiconductor substrate of the memory cell is provided. The sub-contacts of the voltage rise are 01 2 3, 1024 and the p-type diffusion layer region 1025. Therefore, in the nonvolatile semiconductor memory device, in addition to the effect of reducing the arrangement area of the memory cells, the sub-contacts can be added without increasing the area of the memory cells.
此外，在第16圖所示之第10實施形態，雖然在記憶 胞元，金屬配線1012配置於電晶體形成部1〇3〇的左側， 但是亦可配置於正上或配置於右側。 [第1 1實施形態] 第1 7圖係表示本發明之第1 1實施形態的非揮發性半 導體記憶裝置的構成圖’是在第15圖所示之記憶胞元的布 置追加副接點的例子》 如第17圖所示’高效率地配置副接點，面積亦不會增 加。 如此’在第17圖所示的非揮發性半導體記憶裝置，在 -112- 201010062 記憶胞元，在圖上的上下方向（縱向）配置形成第1電晶體 T101及第2電晶體T1 02的電晶體形成部1030，在此電晶 體形成部1030的左側，配置和第1電晶體T101之汲極連 接的第1金屬配線1012。此金屬配線1012和共用的位元 線BIT101連接。 又，在左右方向（橫向）配置第1電晶體T101的閘極層 (多矽層1008)、及第2電晶體T102之源極所連接的第2 金屬配線1013。多矽層1008和共用的選擇閘極配線SG111 C) 連接。第2金屬配線1013和共用的源極線S101連接。 又，在電晶體形成部1 03 0的左側，形成第1空乏型通 道注入1021A，在電晶體形成部1 03 0的右側，形成第2空 乏型通道注入1021B。又，將成爲對控制閘極配線1019之 連接端子的第5η型擴散層1015A設置成和第1通道注入 1021Α的左側相鄰，將成爲對控制閘極配線1019之連接端 子的第6ιι型擴散層1015Β設置成和第2通道注入1021Β 的右側相鄰》 〇 而，在左右方向將浮動閘極1009配置成兩端部的區域 和第1及第2之2個通道注入102 1Α及1021Β的表面相對 向，而且中央部和第2電晶體之第2閘極區域部（第2ιι型 擴散層1006和第3η型擴散層1 00 7之中間的通道形成區域） 相對向，亦在在左右方向配置控制閘極配線1019。此控制 閘極配線1019和共用的控制閘極配線CG111連接。 又，在第1金屬配線1012之左側（或右側）的位置，且 在成爲第1電晶體Τ101之閘極之多晶矽層1008之上側的 位置，設置用以抑制形成記憶胞元之半導體基板之區域之 -113- 201010062 電壓上昇的副接點1022、 1023以及p型擴散層區域1025。 而’在各記憶胞元的配置，在圖上的左右方向將記憶 胞元排列成彼此共用成爲控制閘極之連接端子的第5及第 6n型擴散層101 5A及101 5B。又，對在左右方向所排列之 記憶胞元，在圖上的下方向將記憶胞元對稱地排列成共用 第2金屬配線1013。 因而，在非揮發性半導體記憶裝置，除了可減少記憶 胞元之配置面積的效果以外，還可追加副接點，不會增加 記憶胞元的面積。 此外，在第17圖所示之第11實施形態，雖然在各記 憶胞元，金屬配線1012配置於電晶體形成部1030的左側， 但是配置於右側亦相同。在此情況，若使副接點的位置移 至右側之空的空間，可配置，而不會增加面積。 [第12實施形態] 第18圖係表示本發明之第12實施形態的非揮發性半 導體記憶裝置的構成圖。在第18圖所示的例子，以簡化之 EEPROM的例子表示記憶胞元之構造。 在上述之實施形態的例子，雖然表示可應用於保證改 寫次數1萬次以上之EEPROM的例子，但是在最近受到注 目之精密類比電路之微調用的EEPROM ’亦出現改寫次數 只要約10次〜約20次就夠用的用途。在此情況，電壓應力 對非選擇之記憶胞元的影響亦變少。 在第18圖所示的例子’控制閘極CG100亦共用化， 作爲控制閘極配線CG101~CG10m。 例如，在選擇Mill — 0~M111 - 7並進行寫入時，雖然 201010062 在非記憶胞元Mlln— 0~Μ11η— 7,對閘極施加高電壓，但 是因爲行選擇電晶體Cl On — 0~C1 On — 7變成不導通，所以 對汲極不會施加電壓，而不會發生寫入。 如此，第18圖所示之本發明的非揮發性半導體記億裝 置，作爲其構成，配置成由將記憶胞元對各列在行方向以 例如記憶胞元Ml 1 1 — 0-M111 - 7之1位元組單位被進行行 選擇之8位元單位的記憶胞元方塊所構成。又，沿著列方 向利用位元線BIT101— 0~ ΒΙΤΙΟπ — 7共同連接各記憶胞 Ο 元M111-0〜Mill - 7之第1電晶體T101的汲極。 而，沿著行方向利用選擇閘極配線SG1 01共同連接記 憶胞元之係屬第1電晶體T101的閘極的選擇閘極SG100。 又，沿著行方向利用控制閘極配線CG1 0 1共同連接記憶胞 元之係靥第2電晶體T1 02的閘極的控制閘極CG 100。 又，在行方向以1位元組單位所選擇之各行選擇範圍 內設置源極線S101~S1 On，該行選擇範圍內之所有的列之 各各記憶胞元之第 2電晶體的源極各自利用源極線 〇 S101~S10n共同連接。列解碼器1200 — l~1200-m接受位 址信號，並輸出選擇記憶胞元的列選擇信號。第1位準挪 移電路1 203將從列解碼器1 200 — 1〜1 200 -m所輸出之列 選擇信號變換成施加於選擇閘極SG100之第1電壓VP101 的信號。又，第2位準挪移電路1 205將從列解碼器1200 -1〜1 200 — m所輸出之列選擇信號變換成施加於該控制閘 極CG100之第2電壓VP102的信號。 行解碼器1 400— 1 ~1 400- η接受位址信號，並輸出以 1位元組單位選擇記憶胞元的行選擇信號。第3位準挪移 -115- 201010062 電路1403將從行解碼器1400 — 1~1400— η所輸出之行選擇 信號變換成第3電壓VP 103的信號。 行選擇電晶體，例如行選擇電晶體C101-0〜C101-7 將從第3位準挪移電路140 3所輸出之行選擇信號VP103 作爲閘極輸入，並選擇1位元組單位之記憶胞元的位元線 ΒΙΤ101 - 0~ΒΙΤ101 — 7。在由此行選擇電晶體 C101 — 0〜C101— 7所選擇之1位元組的位元線ΒΙΤ101— 0〜ΒΙΤ101 - 7,經由該行選擇電晶體，而連接1位元組的資料輸出入 線 Data 1 00~Datal 00a7 〇 又，資料輸入變換電路1 5 00在接受1位元組單位之寫 入資料DinlOO〜Dinl07的輸入信號，並進行資料的寫入及 資料的拭除時，輸出透過該資料輸出入線Data 100〜Data 107 及位元線而施加於第1電晶體之汲極的第4電壓信號 VP 104。又，在讀出資料時，利用感測放大器1600 — 0-16 00 —7將資料輸出入線DatalOO〜Datal07所讀出之記憶胞元 的資料放大並向外部輸出。 如此，在第1 2實施形態所示之本發明的非揮發性半導 體記憶裝置，將從列解碼器1 200 - 1 ~12〇0- m所輸出之列 選擇信號施加於選擇閘極SG100之信號變換成第1電壓 VP101 ’並向各記憶胞元的選擇閘極SG100輸出。 又，從列解碼器所輸出之列選擇信號變換成第2電壓 VP102，並向各記憶胞元的選擇閘極SG100輸出。即，選 擇閘極SG 100及控制閘極CG1 00都進行共用化。而，利用 行選擇電晶體選擇行方向的記憶胞元。 因而，使用本發明之非揮發性半導體記憶元件，可構 -116- 201010062 成非揮發性半導體記憶裝置，同時可減少選擇電路，而可 更縮小記憶胞元配置上的面積。 [第13實施形態] 可是，在第18圖所示的例子，雖然權宜上以集中成各 位元組之方式配置記憶胞元陣列的單位，但是在本例，選 擇閘極SG 100及控制閘極CG 100都共用設定於各記憶胞 元陣列，尤其不必以位元組單位集中。 例如，在第18圖，因爲藉行解碼器1400-l~1400-n Ο 之行位址的分配是至l〜n的η條，所以亦可採用包含有作 爲第1記憶胞元方塊之記憶胞元Mill— 0~Μ11η— 0、作爲 第2記憶胞元方塊之記憶胞元Μ111-1〜Mlln— 1、作爲第 8記憶胞元方塊之記憶胞元Mill— 7~Μ11η — 7之記憶胞元 群的陣列。在此情況，以分割成8個記憶胞元方塊之方式 配置1位元組份量之記憶胞元的各個。 第19圖係表示本發明之第13實施形態的非揮發性半 導體記憶裝置的構成圖，是在行方向以η位元的位址單位 〇 集中而構成記憶胞元方塊的例子。 在第 19圖所示的例子，資料輸入信號採用 Dinl00~Dinl07(IO-100〜10— 107)的 8 位元構成，記憶胞 元陣列在行方向以η位元及在列方向以m位元的單位，由 分割成8部分的記憶胞元方塊1100-0〜1100— 7所構成。 即，記憶胞元如 Μ111—0~Μ11η— 0.....Mill— 7 〜Mlln -7般，在行方向以η位元的位址單位集中，構成至記憶 胞元方塊 1100— 〇~11〇〇— 7。 沿著行方向利用選擇閘極配線SG101〜SGlOm共同連 -117- 201010062 接各記憶胞元之係屬第1電晶體的閘極之選擇閘極 SG100。又，沿著行方向利用控制閘極配線CG101~CG10m 共同連接各記憶胞元之係屬第2電晶體的閘極之控制閘極 CG100。又，利用源極線S101共同連接各記憶胞元的源極。 列解碼器1200- 1〜1200-m接受位址信號，並輸出選 擇記憶胞元的列選擇信號。第1位準挪移電路1203將從列 解碼器1200 - l~1200—m所輸出之列選擇信號變換成施加 於選擇閘極SG100之第1電壓VP101的信號。又，第2位 準挪移電路1205將從列解碼器1200— 1~1200 - m所輸出 © 之信號變換成施加於該控制閘極CG1 00之第2電壓VP 102 的信號。 行解碼器1400 - 1〜1 400 -n是對應於在記億胞元方塊 之行方向的位元數η所設置之η個行解碼器，並輸出從各 記憶胞元陣列1100— 0〜1100— 7的各個選擇1個記億胞元 的行選擇信號。第3位準挪移電路1403將從行解碼器所輸 出之行選擇信號變換成第3電壓VP103的信號並輸出。 又，對應於8個記憶胞元陣列1 100 - 〇〜1 1〇〇 — 7的各 © 個，而設置η位元單位的行選擇電晶體（C10 1—0〜C 10η ~ 〇.....C1 01 — 7〜Cl On — 7)，此行選擇電晶體將從第3位準 挪移電路1 403所輸出之行選擇信號VP103作爲閘極輸 入，對各記憶胞元陣列1 100 — 0~1 100 - 7選擇1個記憶胞 元的位元線，而選擇合計8位元的記憶胞元。 由此行選擇電晶體所選擇的記憶胞元，經由該行選擇 電晶體，而和資料輸出入線DatalOO〜Datal07連接。又’ 資料輸入變換電路1500在接受1位元組單位之寫入資料輸 -118- 201010062 入信號DinlOO〜Dinl07並進行資料的寫入時，輸出透過該 資料輸出入線Datal00~Datal07而施加於記憶胞元之第1 電晶體之汲極之第4電壓VP 104的信號。又’感測放大器 1 600 - 0〜1 600 - 7將資料輸出入線DatalOO〜Datal07所讀 出之記憶胞元的資料放大並向外部輸出。 根據這種構成，在本發明的非揮發性半導體記憶裝 置，可在行方向以η位元的位址單位集中並構成記憶胞元 方塊。又，在第19圖所示的例子，雖然說明將記憶胞元陣 Ο 列在行方向進行8分割的例子，但是未限定如此，可因應 於輸出入I/O資料的位元數k(k 21)，而將記憶胞元陣列在 行方向分割成任意的k個。 [第14實施形態] 第20八圖~第20F圖係表示本發明之第14實施形態的 非揮發性半導體記憶元件之構成圖，係表示EEPROM胞元 之例子的圖。 第20A圖〜第20F圖所示之非揮發性半導體記憶元件 〇 (記憶胞元）和第1A圖~第1E圖所示非揮發性半導體記憶元 件（記憶胞元）在構成上的相異點，是刪除和控制閘極 CG119連接之η型擴散層1017及接點1018，並和n型井 1002分離，而新設置η型擴散層1026、金屬配線1028、 以及連接η型擴散層1026和金屬配線1 02 8的接點10 27。 以利用此η型擴散層1026和金屬配線1028而對η型井1〇〇2 供給所要之電壓CG Well 10的方式構成。此η型擴散層 1026、接點1027以及金屬配線1028可配置於記憶胞元的 空空間，不會使記憶胞元的面積變大，而刪除第1Α圖〜第 -119- 201010062 1E圖所示之η型擴散層1017、接點1018之面積縮小效果 大。 第20A圖表示第14實施形態之記憶胞元（EEPROM胞 元）的平面圖。第20B圖表示等價電路圖，第20C圖表示沿 著第20A圖之A10— A10’的剖面圖，第20D圖表示沿著 BIO— B10’的剖面圖，第20E圖表示沿著CIO— C10’的 剖面圖，第20F圖表示沿著E10— E10，的剖面圖。 此記憶胞元如第20B圖的等價電路所示，由電晶體 T101、電晶體T102以及電容器C101所構成，並具有汲極 ❹ D100、源極S100、選擇閘極SG100、控制閘極CG100以及 浮動閘極 FG100。C101是控制閘極 CG100和浮動閘極 FG100之間的電容器。 在構造上，在第20A圖〜第20F圖，1001是p型半導 體基板，1002是形成於1上的η型井（n-well)，1003是構 成T101的電晶體，1004是構成電晶體T102的浮動閘極型 電晶體，1005是成爲電晶體T101之汲極的η型汲極擴散 層，1 006是電晶體Τ101的源極，亦成爲電晶體Τ102之汲 ❹ 極的η型擴散層，10 07是成爲電晶體Τ102之源極的η型 擴散層，1008是成爲電晶體Τ101之閘極的多晶矽層，1009 是成爲電晶體Τ102之浮動閘極的多晶矽層，並成爲電容器 C 1 0 1的一端》 1010是連接η型擴散層1005和金屬配線1012的接 點，1011是連接擴散層1007和金靥配線1013的接點，1〇12 是用以拉出電晶體Τ101之汲極D100的金屬配線，1013是 用以拉出浮動閘極型電晶體Τ102的金屬配線，1014是電 -120- 201010062 容器C101，1015是P型擴散層，並成爲電容器C101的另 —端。1016是連接p型擴散層1015和對控制閘極供給電 壓之控制閘極配線（金屬配線）1019的接點，1026是形成於 η型井1002上的η型擴散層，1027是連接n型擴散層1026 和金屬配線102 8的接點。 此記憶胞元之圖面的特徵，是在縱向配置成爲位元線 之記億胞元之汲極的金屬配線1012,在橫向配置成爲選擇 閘極的多晶矽層1008及控制閘極配線1〇19，又，在縱向 Ο 配置對η型井1002供給所要之電壓的金屬配線1〇28。因 而，使記憶胞元的面積變成最小限度。 第21圖係用以說明第20Α圖〜第20F圖所示之記憶胞 元的動作圖。以下，參照第21圖，說明其動作。 關於對記憶胞元的寫入，有2種方式。第1種方法是 藉熱電子注入的寫入方式。作爲寫入1— 1，對選擇閘極 SG100施加8V，對控制閘極CG100施加3~8V，對汲極D100 施加5V，對源極S100施加0V»對汲極及閘極施加高電壓， 〇 爲了在飽和區域進行動作，而在汲極附近對空乏層施加高 電壓，產生熱電子，其被注入浮動閘極。因爲注入電子， 所以表面上電晶體τ 1 02的臨限値變高。 在拭除的情況，預先對選擇閘極SG100偏壓至10V， 對控制閘極CG100偏壓至0V，對汲極D100偏壓至8V， 對源極S100偏壓至開路（open)或約2V。在此狀態，對汲 極D100和浮動閘極FG100之間施加高電壓，而Fowler — Nor dheirn的穿隧電流流動，從浮動閘極向汲極放出電子， 而表面上看起來臨限値降低。 -121- 201010062 關於讀出，對選擇閘極SG100施加3V，對控制閘極 CG100施加0V，對汲極D100施加IV，對源極S100施加 0V時，若是寫入狀態（臨限値爲正），電流不會流動，而判 斷爲“ 〇” ，若是拭除狀態（臨限値爲負），電流流動，而判 斷爲“ 1 ” 。 又，第2種寫入方式是寫入亦使用Fauler—Nordheim 之穿隧電流進行的方法，若對選擇閘極SG100施加8V、對 控制閘極CG100施加15V、對汲極D100施加0V、對源極 S1 00使變成開路或施加約2V，則電子被注入浮動閘極而 成爲寫入狀態。 又，如第21圖的動作所示，在寫入、拭除以及讀出時， 預先使利用接點1027及金屬配線1028對η型井1002供給 的電壓CGWelllO總是變成高電位，以免成爲控制閘極之ρ 型擴散層1015變成正偏壓。 此外，第3A圖所示之記憶胞元之僅電晶體T1 02的特 性（VCG- Id特性）及第4A圖所示之電晶體T101與電晶體 T102的特性（VSG-Id特性），在第20A圖〜第20F圖所示 之第1 4實施形態的記憶胞元亦一樣。 此外，在第20八圖~第20F圖所示之第14實施形態的 非揮發性半導體記憶元件，電晶體T101相當於上述之第1 電晶體，電晶體T1 02相當於上述之第2電晶體。又，η型 擴散層1 005相當於上述之成爲第1電晶體的汲極之第In 型擴散層，η型擴散層1 0 0 6相當於上述之第2η型擴散層， η型擴散層1007相當於上述之第3η型擴散層，η型擴散層 1026相當於上述之第7η型擴散層。又，在MOS電晶體1003 -122- 201010062 之第In型擴散層1005和第2n型擴散層1006之間的區域 相當於上述之第1閘極區域部，在浮動閘極型電晶體10 04 之第2n型擴散層1006和第3n型擴散層1007之間的區域 相當於上述之第2閘極區域部。又，金屬配線1012相當於 上述之第1金屬配線，多晶矽層1〇〇 8相當於上述的多晶矽 層，金靥配線1013於上述之第2金屬配線，金屬配線1028 於上述之第3金屬配線。 又，在對浮動閘極儲存電荷時（寫入時），第21圖之動 ® 作表所示之選擇閘極SG100的電壓“8”V相當於上述之 施加於第1電晶體之閘極的第1高電壓，汲極D1 00的電壓 “ 5 ” V相當於上述之施加於汲極的第2電壓’控制閘極 C G 1 0 0的電壓“ 3 ~ 8 ” V相當於上述之施加於控制閘極的 第3電壓。又，在拭除對浮動閘極的電荷時，選擇閘極SG1 00 的電壓“10” V相當於上述之施加於第1電晶體之閘極的 第4電壓，汲極D100的電壓“8” V相當於上述之施加於 第1電晶體之汲極的第5電壓’源極S100的電壓“2” V Ο 相當於上述之施加於第2電晶體之源極的第6電壓。 而，在半導體基板表面上的第1方向（在第20A圖上爲 上下方向），配置形成第1電晶體和第2電晶體的電晶體形 成部1030。此電晶體形成部1030由上依序配置：成爲第1 電晶體T101之汲極的第In型擴散層1005、形成第1電晶 體之通道的第1閘極區域部（第1擴散層1〇〇5和第2擴散 層1006之中間的區域）、是第1電晶體T101的源極並亦成 爲第2電晶體之汲極的第2ιι型擴散層1 006、形成第2電 晶體T1 02之通道的第2閘極區域部（第2擴散層1 005和第 -123- 201010062 3擴散層1007之中間的區域）、以及成爲源極的第3n型擴 散層1 007。 在此電晶體形成部1030的左側，在上下方向配置第1 金屬配線1012 »Further, in the tenth embodiment shown in Fig. 16, the metal wiring 1012 is disposed on the left side of the transistor forming portion 1〇3〇 in the memory cell, but may be disposed on the right side or on the right side. [Embodiment 1] FIG. 1 is a view showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, in which a sub-contact is added to the arrangement of memory cells shown in FIG. Example: As shown in Figure 17, 'the sub-contacts are arranged efficiently, and the area does not increase. Thus, in the nonvolatile semiconductor memory device shown in Fig. 17, in the memory cell of -112-201010062, the electric power of the first transistor T101 and the second transistor T1 02 are arranged in the vertical direction (longitudinal direction) on the drawing. In the crystal forming portion 1030, a first metal wiring 1012 that is connected to the drain of the first transistor T101 is disposed on the left side of the transistor forming portion 1030. This metal wiring 1012 is connected to the common bit line BIT101. Further, the gate layer (multi-turn layer 1008) of the first transistor T101 and the second metal line 1013 to which the source of the second transistor T102 is connected are disposed in the left-right direction (lateral direction). The multi-layer 1008 is connected to the common selection gate wiring SG111 C). The second metal wiring 1013 is connected to the common source line S101. Further, on the left side of the transistor forming portion 100 0, the first depletion type channel injection 1021A is formed, and on the right side of the transistor forming portion 1 0 0, the second depletion type channel injecting 1021B is formed. Moreover, the fifth n-type diffusion layer 1015A which is a connection terminal for controlling the gate wiring 1019 is provided adjacent to the left side of the first channel injection 1021, and is a sixth type diffusion layer for controlling the connection terminal of the gate wiring 1019. 1015Β is disposed adjacent to the right side of the second channel implant 1021Β, and the floating gate 1009 is disposed in the left-right direction as a region at both ends and the surfaces of the first and second channel implants 102 1Α and 1021Β are opposed to each other. In the center portion and the second gate region portion of the second transistor (the channel forming region between the second iv type diffusion layer 1006 and the third n-type diffusion layer 1007), the control is also arranged in the left-right direction. Gate wiring 1019. This control gate wiring 1019 is connected to the common control gate wiring CG111. Further, at a position on the left side (or the right side) of the first metal wiring 1012, and at a position on the upper side of the polysilicon layer 1008 which is the gate of the first transistor 101, an area for suppressing formation of a semiconductor substrate of a memory cell is provided. -113- 201010062 Sub-contacts 1022, 1023 and p-type diffusion layer region 1025 with voltage rise. On the other hand, in the arrangement of the memory cells, the memory cells are arranged in the left-right direction on the drawing to share the fifth and sixth n-type diffusion layers 1015 and 1015B which are the connection terminals for controlling the gates. Further, the memory cells arranged in the left-right direction are symmetrically arranged in the lower direction of the figure to share the second metal interconnection 1013. Therefore, in the nonvolatile semiconductor memory device, in addition to the effect of reducing the arrangement area of the memory cells, the sub-contacts can be added without increasing the area of the memory cells. Further, in the eleventh embodiment shown in Fig. 17, the metal wiring 1012 is disposed on the left side of the transistor forming portion 1030 in each of the memory cells, but is disposed on the right side. In this case, if the position of the sub-contact is moved to the space on the right side, it can be configured without increasing the area. [Twelfth Embodiment] Fig. 18 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twelfth embodiment of the present invention. In the example shown in Fig. 18, the construction of the memory cell is shown by an example of a simplified EEPROM. In the example of the above-described embodiment, an example of the EEPROM which can be used to ensure the number of times of rewriting is 10,000 times or more. However, the number of rewrites of the EEPROM 'the micro-call of the precision analog circuit which has recently been noticed is also about 10 times to about 20 times is enough for use. In this case, the effect of voltage stress on non-selected memory cells is also reduced. In the example shown in Fig. 18, the control gate CG100 is also shared as the control gate wirings CG101 to CG10m. For example, when Mill_0~M111-7 is selected and written, although 201010062 applies a high voltage to the gate in the non-memory cell Mlln-0~Μ11n-7, because the row selects the transistor Cl On — 0~ C1 On — 7 becomes non-conducting, so no voltage is applied to the drain and no writing occurs. As described above, the nonvolatile semiconductor device of the present invention shown in Fig. 18 has a configuration in which the memory cell pairs are arranged in the row direction, for example, memory cells M1 1 1 - 0 - M111 - 7 The 1-bit unit is composed of memory cell blocks of 8-bit units selected for row selection. Further, the drains of the first transistors T101 of the respective memory cells M111-0 to Mill-7 are connected in common in the column direction by the bit lines BIT101 - 0 - ΒΙΤΙΟ π - 7. On the other hand, the selective gate SG100 of the gate of the first transistor T101 is connected in common by the selection gate wiring SG1 01 in the row direction. Further, the control gate CG 100 of the gate of the second transistor T1 02 of the memory cell is connected in common in the row direction by the control gate wiring CG1 0 1 . Further, source lines S101 to S1 On are set in each row selection range selected by one byte unit in the row direction, and the source of the second transistor of each memory cell of all the columns in the row selection range is selected. Each of the source lines 〇S101 to S10n is connected in common. The column decoder 1200 - l ~ 1200-m accepts the address signal and outputs a column selection signal for selecting the memory cell. The first level shift circuit 1 203 converts the column selection signal output from the column decoders 1 200-1 to 1 200-m into a signal applied to the first voltage VP101 of the selection gate SG100. Further, the second level shifting circuit 1 205 converts the column selection signal output from the column decoders 120-1 to 1 200-m into a signal applied to the second voltage VP102 of the control gate CG100. The row decoder 1 400 - 1 ~ 1 400 - η accepts the address signal and outputs a row selection signal for selecting the memory cell in 1-bit units. The third position shift -115 - 201010062 The circuit 1403 converts the line selection signal output from the row decoders 1400 - 1 to 1400 - η into the signal of the third voltage VP 103. The row selection transistor, for example, the row selection transistors C101-0 to C101-7, uses the row selection signal VP103 output from the third bit shift circuit 140 3 as a gate input, and selects a memory cell of 1 byte unit. The bit line ΒΙΤ101 - 0~ΒΙΤ101-7. In this row, the 1-bit tuple bit line 101_0~ΒΙΤ101-7 selected by the transistors C101-0~C101-7 is selected, and the transistor is selected through the row, and the 1-bit data output line is connected. Data 1 00~Datal 00a7 〇In addition, the data input conversion circuit 1 500 receives the input signal of the data DinlOO~Dinl07 in the 1-bit unit, and writes the data and erases the data. The data is input to the fourth voltage signal VP 104 of the drain of the first transistor from the data lines 100 to 107 and the bit lines. Further, when reading data, the data of the memory cells read out by the data output lines Data1OO to Datal07 are amplified by the sense amplifiers 1600 - 0-16 00 - 7 and output to the outside. As described above, in the nonvolatile semiconductor memory device of the present invention shown in the second embodiment, the column selection signal output from the column decoders 1 200 - 1 to 12 〇 0- m is applied to the signal of the selection gate SG100. It is converted into the first voltage VP101' and output to the selection gate SG100 of each memory cell. Further, the column selection signal output from the column decoder is converted into the second voltage VP102, and is output to the selection gate SG100 of each memory cell. That is, both the selection gate SG 100 and the control gate CG1 00 are shared. Instead, the row selection transistor is used to select the memory cells in the row direction. Thus, by using the non-volatile semiconductor memory device of the present invention, the non-volatile semiconductor memory device can be constructed from -116 to 201010062, and the selection circuit can be reduced, and the area on the memory cell configuration can be further reduced. [Thirteenth Embodiment] However, in the example shown in Fig. 18, the unit of the memory cell array is arranged so as to be concentrated in each of the tuples. However, in this example, the gate SG 100 and the control gate are selected. The CGs 100 are all shared in each memory cell array, and in particular do not have to be concentrated in byte units. For example, in Fig. 18, since the allocation of the row address of the borrow decoders 1400-1 to 1400-n is n to n to n, it is also possible to use the memory including the first memory cell block. Cell Mill_0~Μ11η-0, as the memory cell of the second memory cell block 111-1~Mlln-1, as the memory cell of the memory cell of the eighth memory cell block Mill-7~Μ11η-7 An array of metagroups. In this case, each of the 1-bit memory cells is arranged in such a manner as to be divided into eight memory cell blocks. Fig. 19 is a view showing a configuration of a nonvolatile semiconductor memory device according to a thirteenth embodiment of the present invention, which is an example in which a memory cell block is formed by concentrating address units of η bits in the row direction. In the example shown in Fig. 19, the data input signal is composed of 8-bit elements of Dinl00~Dinl07 (IO-100~10-107), and the memory cell array is η bits in the row direction and m bits in the column direction. The unit is composed of memory cell blocks 1100-0 to 1100-7 divided into 8 parts. That is, the memory cells are like Μ111-0~~11η- 0.....Mill-7~Mlln-7, concentrated in the row direction by the address unit of η bits, and are formed into the memory cell block 1100 - 〇~ 11〇〇—7. The selected gate wirings SG101 to SG10 are connected in the row direction to -117- 201010062. The memory cells are connected to the gate selection gate SG100 of the first transistor. Further, the control gates CG100 of the gates of the second transistors, which are connected to the respective memory cells, are connected in common in the row direction by the control gate wirings CG101 to CG10m. Further, the source of each memory cell is connected in common by the source line S101. The column decoders 120-1 to 1200-m accept the address signals and output column selection signals for selecting the memory cells. The first level shifting circuit 1203 converts the column selection signal output from the column decoders 1200 - l to 1200 - m into a signal applied to the first voltage VP101 of the selection gate SG100. Further, the second bit shifting circuit 1205 converts the signal output from the column decoders 120-1 to 1200-m into a signal applied to the second voltage VP102 of the control gate CG1 00. The row decoders 1400 - 1 to 1 400 - n are n row decoders corresponding to the number of bits η in the row direction of the cells, and are output from the memory cell arrays 1100 - 1 to 1100. - 7 each selects a row selection signal of one billion cells. The third bit shifting circuit 1403 converts the row selection signal output from the row decoder into a signal of the third voltage VP103 and outputs it. Further, corresponding to each of the eight memory cell arrays 1 100 - 〇 1 1 〇〇 -7, a row selection transistor of η bit units is set (C10 1 - 0 to C 10 η ~ 〇... ..C1 01 — 7~Cl On — 7), the row selection transistor will use the row selection signal VP103 output from the third bit shift circuit 1 403 as a gate input for each memory cell array 1 100 — 0 ~1 100 - 7 selects a bit line of one memory cell, and selects a memory cell of a total of 8 bits. The memory cell selected by the transistor is selected by this row, and the transistor is selected via the row, and is connected to the data input lines Data1OO to Datal07. Further, when the data input conversion circuit 1500 accepts the write data input of the 1-byte unit-118-201010062 and inputs the signals Din100 to Dinl07 and writes the data, the output is applied to the memory cell through the data input and output lines Datal00 to Datal07. The signal of the fourth voltage VP 104 of the drain of the first transistor of the element. Further, the sense amplifier 1 600 - 0 to 1 600 - 7 amplifies the data of the memory cells read by the data input lines DatalOO to Datal07 and outputs them to the outside. According to this configuration, the nonvolatile semiconductor memory device of the present invention can be concentrated in the row direction by η bit address units and constitute a memory cell block. Further, in the example shown in Fig. 19, an example in which the memory cell array is divided into eight in the row direction will be described. However, the number of bits k(k) that can be input and outputted into the I/O data is not limited thereto. 21), and the memory cell array is divided into arbitrary k in the row direction. [Fourteenth embodiment] FIG. 20 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention, and shows an example of an EEPROM cell. The non-volatile semiconductor memory device 记忆 (memory cell) shown in FIGS. 20A to 20F and the non-volatile semiconductor memory device (memory cell) shown in FIGS. 1A to 1E are different in composition. The n-type diffusion layer 1017 and the contact 1018 connected to the gate CG119 are removed and controlled, and are separated from the n-type well 1002, and the n-type diffusion layer 1026, the metal wiring 1028, and the n-type diffusion layer 1026 and the metal are newly disposed. Wiring 1 02 8 contacts 10 27 . The n-type well 1 〇〇 2 is supplied with the desired voltage CG Well 10 by the n-type diffusion layer 1026 and the metal wiring 1028. The n-type diffusion layer 1026, the contact 1027, and the metal wiring 1028 can be disposed in the empty space of the memory cell, and the area of the memory cell is not increased, and the first image to the -119-201010062 1E is deleted. The area of the n-type diffusion layer 1017 and the contact 1018 has a large reduction effect. Fig. 20A is a plan view showing a memory cell (EEPROM cell) of the fourteenth embodiment. Figure 20B shows an equivalent circuit diagram, Figure 20C shows a cross-sectional view along A10-A10' of Figure 20A, Figure 20D shows a cross-sectional view along BIO-B10', and Figure 20E shows along CIO-C10' The cross-sectional view of Fig. 20F shows a cross-sectional view along E10-E10. The memory cell is composed of a transistor T101, a transistor T102, and a capacitor C101 as shown in the equivalent circuit of FIG. 20B, and has a drain ❹ D100, a source S100, a selection gate SG100, a control gate CG100, and Floating gate FG100. C101 is a capacitor between the control gate CG100 and the floating gate FG100. Structurally, in FIGS. 20A to 20F, 1001 is a p-type semiconductor substrate, 1002 is an n-well formed on 1, 1003 is a transistor constituting T101, and 1004 is a transistor T102. a floating gate type transistor, 1005 is an n-type drain diffusion layer which becomes a drain of the transistor T101, and 1006 is a source of the transistor Τ101, and also becomes an n-type diffusion layer of the anode of the transistor Τ102, 10 07 is an n-type diffusion layer which becomes a source of the transistor Τ 102, 1008 is a polysilicon layer which becomes a gate of the transistor Τ101, and 1009 is a polysilicon layer which becomes a floating gate of the transistor Τ102, and becomes a capacitor C 1 0 1 One end 1010 is a contact connecting the n-type diffusion layer 1005 and the metal wiring 1012, 1011 is a contact connecting the diffusion layer 1007 and the metal wiring 1013, and 1〇12 is for pulling out the drain D100 of the transistor Τ101. The metal wiring 1013 is a metal wiring for pulling out the floating gate type transistor Τ102, and 1014 is an electric-120-201010062 container C101, which is a P-type diffusion layer and becomes the other end of the capacitor C101. 1016 is a junction connecting the p-type diffusion layer 1015 and a control gate wiring (metal wiring) 1019 for supplying a voltage to the control gate, 1026 is an n-type diffusion layer formed on the n-type well 1002, and 1027 is a connection n-type diffusion. The contact of layer 1026 and metal wiring 102 8 . The surface of the memory cell is characterized in that a metal wiring 1012 which is a drain of a pixel of a bit line is disposed in the vertical direction, and a polysilicon layer 1008 which is a gate electrode and a gate wiring 1〇19 are disposed in the lateral direction. Further, the metal wiring 1〇28 for supplying the desired voltage to the n-type well 1002 is disposed in the longitudinal direction Ο. Therefore, the area of the memory cell is minimized. Fig. 21 is a view for explaining the operation of the memory cell shown in Figs. 20 to 20F. Hereinafter, the operation will be described with reference to Fig. 21 . There are two ways to write to memory cells. The first method is a write method by hot electron injection. As write 1 - 1, apply 8V to select gate SG100, apply 3~8V to control gate CG100, apply 5V to drain D100, apply 0V» to source S100, apply high voltage to drain and gate, 〇 In order to operate in a saturated region, a high voltage is applied to the depletion layer near the drain, and hot electrons are generated, which are injected into the floating gate. Because of the injection of electrons, the threshold of the transistor τ 1 02 on the surface becomes high. In the case of erasing, the selection gate SG100 is biased to 10V in advance, the control gate CG100 is biased to 0V, the drain D100 is biased to 8V, and the source S100 is biased to open or about 2V. . In this state, a high voltage is applied between the drain D100 and the floating gate FG100, and the tunneling current of Fowler - Nor dheirn flows, and electrons are discharged from the floating gate to the drain, and the surface appears to have a lower limit. -121- 201010062 For reading, apply 3V to the selection gate SG100, apply 0V to the control gate CG100, apply IV to the drain D100, and apply 0V to the source S100, if it is in the write state (the threshold is positive) The current does not flow, but is judged as "〇". If it is erased (the threshold is negative), the current flows and is judged as "1". Further, the second writing method is a method of writing using a tunneling current of Fauler-Nordheim, and applying 8V to the selection gate SG100, 15V to the control gate CG100, and 0V to the gate D100, the source is applied. When the pole S1 00 is turned on or about 2V is applied, electrons are injected into the floating gate to be in the write state. Further, as shown in the operation of Fig. 21, in the writing, erasing, and reading, the voltage CGWel11O supplied to the n-type well 1002 by the contact 1027 and the metal wiring 1028 is always turned to a high potential, so as not to become a control. The p-type diffusion layer 1015 of the gate becomes a positive bias. Further, the characteristics of the transistor T1 02 (VCG-Id characteristic) of the memory cell shown in FIG. 3A and the characteristics (VSG-Id characteristic) of the transistor T101 and the transistor T102 shown in FIG. 4A are in the The memory cells of the fourteenth embodiment shown in Figs. 20A to 20F are also the same. Further, in the nonvolatile semiconductor memory device of the fourteenth embodiment shown in Figs. 20 to 20F, the transistor T101 corresponds to the first transistor described above, and the transistor T1 02 corresponds to the second transistor described above. . Further, the n-type diffusion layer 1 005 corresponds to the first In-type diffusion layer which is the drain of the first transistor, and the n-type diffusion layer 1 0 0 6 corresponds to the above-described second n-type diffusion layer, and the n-type diffusion layer 1007 Corresponding to the above-described third n-type diffusion layer, the n-type diffusion layer 1026 corresponds to the above-described seventh n-type diffusion layer. Further, a region between the In-type diffusion layer 1005 and the second n-type diffusion layer 1006 of the MOS transistor 1003 - 122 - 201010062 corresponds to the above-described first gate region portion, and is in the floating gate type transistor 104 A region between the second n-type diffusion layer 1006 and the third n-type diffusion layer 1007 corresponds to the second gate region described above. Further, the metal wiring 1012 corresponds to the first metal wiring described above, and the polysilicon layer 1 8 corresponds to the above-described polysilicon layer, the metal wiring 1013 to the second metal wiring, and the metal wiring 1028 to the third metal wiring. Further, when the charge is stored in the floating gate (at the time of writing), the voltage "8" V of the selection gate SG100 shown in the table of Fig. 21 corresponds to the above-mentioned gate applied to the first transistor. The first high voltage, the voltage "5" V of the drain D1 00 corresponds to the voltage "3 ~ 8" V of the second voltage 'control gate CG 1 0 0 applied to the drain described above, and V is equivalent to the above Controls the third voltage of the gate. Further, when the charge to the floating gate is erased, the voltage "10" V of the gate SG1 00 is selected to correspond to the fourth voltage applied to the gate of the first transistor, and the voltage "8" of the drain D100. V corresponds to the voltage "2" V Ο of the fifth voltage 'source S100 applied to the drain of the first transistor, and corresponds to the sixth voltage applied to the source of the second transistor. On the other hand, in the first direction on the surface of the semiconductor substrate (in the up-and-down direction in Fig. 20A), the transistor forming portion 1030 in which the first transistor and the second transistor are formed is disposed. The transistor forming portion 1030 is disposed in order from the top, the first inversion layer 1005 which is the drain of the first transistor T101, and the first gate region in which the channel of the first transistor is formed (the first diffusion layer 1〇) a region between the 〇5 and the second diffusion layer 1006), a source of the first transistor T101, and a second anotype diffusion layer 1 006 which also serves as a drain of the second transistor, and a second transistor T1 02 The second gate region portion of the channel (the region between the second diffusion layer 1 005 and the -123-201010062 3 diffusion layer 1007) and the third n-type diffusion layer 1 007 serving as the source. On the left side of the transistor forming portion 1030, the first metal wiring 1012 is disposed in the vertical direction.
此金屬配線1012從半導體基板表面隔著既定之距離 配置成和電晶體形成部1030平行，又，金屬配線1012利 用接點1012和第1電晶體的汲極（第In型擴散層1 005 )連 接。又，在左右方向形成多晶矽層1008，使其和第1電晶 體T101的第1閘極區域部相對向。 在電晶體形成部1 03 0的左側，以既定之寬度和深度在 左右方向所形成η型井1002。方形的浮動閘極1009在左 右方向配置成和半導體基板表面相對向，同時配置成其左 端部側的區域和η型井10 02的表面相對向，且右端部側的 區域和第2電晶體的第2閘極區域部（第2ιι型擴散層1〇〇6 和第3η型擴散層1007之中間的通道形成區域）相對向。The metal wiring 1012 is disposed in parallel with the transistor forming portion 1030 from a surface of the semiconductor substrate at a predetermined distance, and the metal wiring 1012 is connected to the drain of the first transistor (the In-type diffusion layer 1 005) by the contact 1012. . Further, the polysilicon layer 1008 is formed in the left-right direction so as to face the first gate region portion of the first transistor T101. On the left side of the transistor forming portion 101 0, an n-type well 1002 is formed in the left-right direction with a predetermined width and depth. The square floating gate 1009 is disposed to face the surface of the semiconductor substrate in the left-right direction while being disposed such that the region on the left end side thereof faces the surface of the n-type well 102, and the region on the right end side and the second transistor The second gate region portion (the channel formation region between the second type of diffusion layer 1〇〇6 and the third n-type diffusion layer 1007) faces each other.
在η型井1002之左側的區域，在左右方向形成ρ型擴 散層1015，其和與此η型井10 02的浮動閘極1009相對向 之區域的左側相鄰，並具有既定之寬度和深度。此ρ型擴 散層1015和控制閘極配線1019利用接點1016連接。此控 制閘極配線1019從半導體基板表面隔著既定之距離在左 右方向配置成和浮動閘極1009相對向，又，利用接點1〇16 和Ρ型擴散層1015連接。第2金靥配線1013從半導體基 板表面隔著既定之距離在左右方向配置成和成爲第2電晶 體Τ1 02之源極的第3η型擴散層1007相對向，此第2金屬 配線1013利用接點1〇11和第3η型擴散層1007連接。 -124- 201010062 又，在P型擴散層1015的上側，且第1 η型擴散層1005 之左側的位置，以既定之寬度和深度形成η型擴散層 1026。而且，設置金屬配線1028，其配置成和電晶體形成 部1 03 0平行，而且從半導體基板表面隔著既定之距離，此 金屬配線1028和η型擴散層1 02 6利用接點} 027連接。用 此金靥配線1028和η型擴散層1026，對η型井1002供給 所要之電位。 因而，以標準邏輯元件的CMOS製程可實現非揮發性 記憶體，同時可緊密地配置面積變大的電容器（在浮動閘極 和半導體基板表面所形成之電容器），使面積變成最小限 度。 [第15實施形態] 第22圖係表示本發明之第15實施形態的非揮發性半 導體記憶裝置的構成圖。第22圖所示的例子是將第20A 圖〜第20F圖所示之記憶胞元裝入陣列（記憶胞元陣列）之 EEPROM的電路例。 在第22圖所示之記憶胞元陣列的構成，例如記憶胞元 陣列（記憶胞元方塊）採用10—100〜10— 107之8位元構 成，將記憶胞元 Ml 1 1 — 0~M1 1 1 - 7、~、Mlml — 0~Mlml 一 7集中，而構成記憶胞元陣列1 1 0 0 ~ 1。如此，以8位元 單位集中，而構成至記憶胞元陣列1100— η爲止。 從記憶胞元Μ111—0至Μ111-7各自共同連接選擇閘 極配線SG101、控制閘極配線CG111以及源極配線S101。 其他的記憶胞元亦一樣，記憶胞元Mlml — 0〜Mlml_7和 選擇閘極配線SGlOm、控制閘極配線CGlml以及源極配線 •125- 201010062 S101連接。記憶胞元Μ11η—0~Μ11η-7和選擇閘極配線 SG101、控制閘極配線CGlln以及源極配線SlOn連接，記 憶胞元Mlmn— 0~Mlmn— 7和選擇閘極配線SGlOm、控制 閘極配線CGlmn以及源極配線SlOn連接。又，各源極線 S101~S10n各自和電晶體1101-1~1101— η連接，根據電 晶體1101— 1〜1101— η的閘極輸入信號ΕΒ100，而選擇使 各源極線S101~S10n變成開路或變成接地電位（0V)。 另一方面，利用根據列位址而輸出記憶胞元之選擇信 號的列解碼器1 200- 1〜1200— m，被設定成選擇記憶胞元 的選擇閘極SG100和控制閘極CG100»列解碼器12 00—1 由以下之元件所構成，列解碼電路1 20 1，係接受列位址信 號並輸出列選擇信號；反相器1202,係接受此列解碼電路 1201的輸出並輸出反相信號；以及位準挪移電路1 203,係 將反相器1202的輸出變換成髙電壓VP 101。將位準挪移電 路1203的輸出（電壓VP101的信號）供給選擇閘極SG101， 同時供給選擇電路1300 — 11之電晶體1303的汲極。 選擇電路1 300 - 1 1由以下之元件所構成，傳輸閘極電 晶體1303,係接受來自後述之行解碼器的選擇信號，並向 記憶胞元（例如記憶胞元Mill- 0)的控制閘極配線CG1 11 傳輸位準挪移電路 120 3的輸出信號；及開關用電晶體 13 04，係在不選擇行解碼器時，將控制閘極CG 100設定成 GND。傳輸閘極電晶體1303輸入行解碼電路的輸出信號 COLlOla，而開關用電晶體1 3 04輸入行解碼器輸出的反相 信號 COLlOlaB。 另一方面，設置根據行位址而選擇之行解碼器1400- -126- 201010062 1~1400— η，行解碼器1400 — 1〜1400 - η由根據行位址而選 擇輸出的解碼電路1401、反相器14 02、將反相器1402的 輸出變換成高電壓VP 103的位準挪移電路1403、接受解碼 電路1401之輸出的N AND電路1404以及接受NAND電路 1 404的輸出並變換成高電壓VP102的位準挪移電路1405 所構成。位準挪移電路1 405的輸出是上述的信號 COLlOla， NAND 電路 1404的輸出是上述的信號 ^ COLlOlaB。又，第3位準挪移電路1 4 0 3的輸出爲信號 〇 COLlOlb » 此外，記憶胞元Ml 1 1 — 0~Mlml — 0的汲極和位元線 BIT101 — 0連接，記憶胞元Mill — 7~Mlml— 7的汲極和位 元線BIT101— 7連接。位元線BIT101-0~BIT101— 7各自 和根據行解碼電路的輸出信號COL 10 lb所選擇的行選擇電 晶體 C101 _ 0~ C101 — 7連接，行選擇電晶體 C101 — 0~ C101— 7的另一端各自和資料輸出入線Datal00~Datal07 連接。資料輸出入線Datal00~Datal07和資料輸入變換電 ^ 路1 500連接，其接受寫入資料輸入信號DinlOO〜Dinl07， 並輸出寫入、拭除所需的高電壓信號VP 104。 又，資料輸出入線DatalOO〜Datal07和將讀出資料放 大並向外部輸出的感測放大器1600-0〜1600— 7連接，並 輸出輸出資料Doutl00~ Doutl07。關於記億胞元陣列（記億 胞元方塊）1100— η，亦進行一樣的連接。 其次，說明此記憶體的動作。 例如，說明選擇Μ 1 1 1 - 0〜Μ 1 1 1 — 7之8位元的記憶胞 元之情況的寫入動作。根據列位址而選擇列解碼器1 2 00 - -127- 201010062 1。根據列位址而選擇列解碼電路1 2 0 1，輸出“ 1 ” 。反相 器1 202的输出變成“0” ，位準挪移電路1 203輸出電塵 VP101(例如8V)的信號。 又，根據行位址而選擇行解碼器1400 - 1，解碼電路 1 4 0 1輸出“ 1 ” ，而反相器1 4 0 2輸出“ 0 ” ，位準挪移電 路1403以COLlOlb信號輸出電壓VP103(例如lOV^NAND 電路14 04輸入寫入信號W100。 寫入時，因爲寫入信號W1 00爲“ 1” ，所以NAND電 路1404變成“0” ，而位準挪移電路1405輸出VP102(例 如5V)的信號。將NAND電路1 404的輸出信號COLlOlaB、 位準挪移電路1 405的輸出信號COLlOla供給選擇電路 1300 - 11〜1300 - lm。 在選擇電路1300 — 11，電晶體1303接受信號COLlOla 而變成導通，電晶體13 04接受信號COL 101 aB而變成不導 通。對選擇閘極配線SG111供給位準挪移電路1203的輸 出信號，即電壓 VP 10 1(8V)的信號，對控制閘極配線 CG111，經由第2傳輸閘極電晶體1303而供給選擇閘極 S G 1 0 1的信號。 此時，寫入輸入資料DinlOO〜Dinl07經由資料輸入變 換電路1 500，對資料輸出入線DatalOO〜Datal07供給寫入 電壓 VP104(例如5VP在此，若輸入「Dinl00= “ 0”（寫 入）、Din 10 0= “ 1”（禁止寫入），則變成「Data 10 0 = 5 V、 Datal07 = 0V」，因爲行選擇電晶體C101-0~ C101— 7變 成導通，所以對位元線BIT1 1 1 - 0施加5V，對BIT1 1 1 - 7 施加0V。因此，對記憶胞元Ml 1 1 _ 0寫入資料“ 〇” ，而 -128- 201010062 臨限値變高。又，M111-7變成資料“1”（禁止寫入），而 臨限値依然低。 另一方面，行解碼器1400-n變成非選擇，因爲輸出 信號COLlOna、COLlOnaB各自變成“〇” 、 “1” ，所以 選擇電路1300 — ln~1300 — mn變成非選擇’而記憶胞兀陣 列1100— η變成非選擇狀態。又，列解碼器1200-n亦變 成非選擇，因爲位準挪移電路 1 203的輸出變成 “ 0”（0V)，所以Mlml — 0〜Mlml—7變成非選擇。 在此，關於寫入，若在拭除時進行過度拭除，因爲記 憶胞元的電晶體T102在非飽和區域進行動作，所以初期具 有難寫入的問題。在此情況，寫入時，將控制閘極CG100 的電壓（VP102)設爲最初的4V，接著5V、6.0V、…，寫入 複數次，只要每次使電壓VP102逐步上昇，就對Τ102的 控制閘極施加「VP102— Vth(電晶體 1 3 03的臨限値電 壓）」，而可總是使在飽和區域進行動作，結果，可達成高 速寫入。In a region on the left side of the n-type well 1002, a p-type diffusion layer 1015 is formed in the left-right direction adjacent to the left side of the region opposite to the floating gate 1009 of the n-type well 102, and has a predetermined width and depth. . The p-type diffusion layer 1015 and the control gate wiring 1019 are connected by a contact 1016. The control gate wiring 1019 is disposed to face the floating gate 1009 in the left-right direction from the surface of the semiconductor substrate with a predetermined distance therebetween, and is connected to the 扩散-type diffusion layer 1015 by the contact 1〇16. The second metal wiring 1013 is disposed so as to face the third n-type diffusion layer 1007 which is the source of the second transistor Τ102 in the left-right direction from the surface of the semiconductor substrate with a predetermined distance therebetween, and the second metal wiring 1013 uses the contact. 1〇11 and the 3rd n-type diffusion layer 1007 are connected. Further, on the upper side of the P-type diffusion layer 1015 and on the left side of the first n-type diffusion layer 1005, the n-type diffusion layer 1026 is formed with a predetermined width and depth. Further, a metal wiring 1028 is disposed which is disposed in parallel with the transistor forming portion 100 0, and the metal wiring 1028 and the n-type diffusion layer 168 are connected by a contact} 027 from a surface of the semiconductor substrate with a predetermined distance therebetween. The gold-line wiring 1028 and the n-type diffusion layer 1026 are used to supply the desired potential to the n-type well 1002. Therefore, the non-volatile memory can be realized by the CMOS process of the standard logic element, and the capacitor having a large area (the capacitor formed on the floating gate and the surface of the semiconductor substrate) can be closely arranged to minimize the area. [Fifteenth Embodiment] Fig. 22 is a view showing the configuration of a nonvolatile semiconductor memory device according to a fifteenth embodiment of the present invention. The example shown in Fig. 22 is an example of a circuit in which the memory cells shown in Figs. 20A to 20F are loaded into the EEPROM of the array (memory cell array). In the structure of the memory cell array shown in FIG. 22, for example, the memory cell array (memory cell block) is composed of 8-bits 10-100 to 10-107, and the memory cell M1 1 1 - 0~M1 is used. 1 1 - 7, ~, Mlml — 0~Mlml A 7-concentration, and constitutes a memory cell array 1 1 0 0 ~ 1. Thus, it is concentrated in octet units and formed until the memory cell array 1100 - η. The gate wiring SG101, the control gate wiring CG111, and the source wiring S101 are connected in common from the memory cells Μ111-0 to Μ111-7. The other memory cells are also the same, the memory cell Mlml — 0 to Mlml_7 and the selection gate wiring SGlOm, the control gate wiring CGlml and the source wiring • 125- 201010062 S101 connection. The memory cell Μ11η_0~Μ11η-7 is connected to the selection gate wiring SG101, the control gate wiring CG11n, and the source wiring S1On, the memory cell Mlmn_0~Mlmn-7, and the selection gate wiring SG10m, and the control gate wiring. CGlmn and source wiring SlOn are connected. Further, each of the source lines S101 to S10n is connected to the transistors 1101-1 to 1101-n, and the source lines S101 to S10n are selected in accordance with the gate input signal ΕΒ100 of the transistors 1101 - 1 to 1101 - η. Open circuit or become ground potential (0V). On the other hand, the column decoders 1 200-1 to 1200-m for outputting the selection signals of the memory cells according to the column addresses are set to select the selection gates SG100 of the memory cells and the control gate CG100»column decoding The device 12 00-1 is composed of the following elements, the column decoding circuit 1 20 1 receives the column address signal and outputs a column selection signal; the inverter 1202 receives the output of the column decoding circuit 1201 and outputs an inverted signal. And the level shifting circuit 1 203 converts the output of the inverter 1202 into a 髙 voltage VP 101. The output of the level shifting circuit 1203 (the signal of the voltage VP101) is supplied to the selection gate SG101 while being supplied to the drain of the transistor 1303 of the selection circuit 1300-11. The selection circuit 1 300 - 1 1 is composed of the following elements, and the transmission gate transistor 1303 receives a selection signal from a row decoder described later and controls the gate of the memory cell (for example, the memory cell Mill-0). The polarity wiring CG1 11 transmits the output signal of the level shifting circuit 120 3; and the switching transistor 13 04 sets the control gate CG 100 to GND when the row decoder is not selected. The transmission gate transistor 1303 is input to the output signal COL1Ola of the row decoding circuit, and the switching transistor 1 3 04 is input to the inverted signal COL1OlaB of the row decoder output. On the other hand, the row decoders 1400--126-201010062 1~1400-n selected according to the row address are set, and the row decoders 1400-1 1400-n are selected by the decoding circuit 1401 which is output according to the row address. The inverter 14 02 converts the output of the inverter 1402 into a level shifting circuit 1403 of the high voltage VP 103, an N AND circuit 1404 that receives the output of the decoding circuit 1401, and receives the output of the NAND circuit 1 404 and converts it into a high voltage. The level shift circuit 1405 of the VP 102 is constructed. The output of the level shifting circuit 1 405 is the above-described signal COL101a, and the output of the NAND circuit 1404 is the above-mentioned signal ^COLlOlaB. Moreover, the output of the third level shifting circuit 1 4 0 3 is the signal 〇COLlOlb » In addition, the drain of the memory cell M1 1 1 - 0~Mlml — 0 is connected to the bit line BIT101 — 0, and the memory cell Mill — The drain of 7~Mlml-7 is connected to the bit line BIT101-7. The bit lines BIT101-0~BIT101-7 are respectively connected to the row selection transistors C101_0~C101-7 selected according to the output signal COL10 lb of the row decoding circuit, and the row selection transistors C101-0~ C101-7 The other end is connected to the data input and output lines Datal00~Datal07. The data input and output lines Datal00~Datal07 are connected to the data input conversion circuit 1500, and receive the data input signals DinlOO to Dinl07, and output the high voltage signal VP 104 required for writing and erasing. Further, the data input and output lines DatalOO to Datal07 are connected to the sense amplifiers 1600-0 to 1600-7 which amplify the read data and output to the outside, and output the output data Doutl00 to Doutl07. The same connection is also made for the 100 million cell array (100 million cell block) 1100 - η. Next, the action of this memory will be described. For example, a description will be given of a write operation in the case where a memory cell of 8 bits of Μ 1 1 1 - 0 to Μ 1 1 1 - 7 is selected. The column decoder 1 2 00 - -127- 201010062 1 is selected according to the column address. The column decoding circuit 1 2 0 1 is selected according to the column address, and "1" is output. The output of the inverter 1 202 becomes "0", and the level shifting circuit 1 203 outputs a signal of the electric dust VP101 (e.g., 8V). Further, the row decoder 1400-1 is selected according to the row address, the decoding circuit 1 4 0 1 outputs "1", and the inverter 1 4 0 2 outputs "0", and the level shifting circuit 1403 outputs the voltage VP103 with the COL1Olb signal. (For example, the lOV^NAND circuit 14 04 inputs the write signal W100. At the time of writing, since the write signal W1 00 is "1", the NAND circuit 1404 becomes "0", and the level shift circuit 1405 outputs VP102 (for example, 5V). The signal COL1OlaB of the NAND circuit 1404 and the output signal COL10la of the level shifting circuit 1405 are supplied to the selection circuits 1300 - 11 to 1300 - lm. At the selection circuit 1300 - 11, the transistor 1303 receives the signal COL1Ola and becomes conductive. The transistor 13 04 receives the signal COL 101 aB and becomes non-conductive. The output signal of the selection gate wiring SG111 supplied to the level shift circuit 1203, that is, the signal of the voltage VP 10 1 (8 V) is applied to the control gate wiring CG111. The second transmission gate transistor 1303 supplies a signal for selecting the gate SG 1 0 1. At this time, the write input data Din100 to Dinl07 are supplied to the data output lines Data100 to Datal07 via the data input conversion circuit 1500. Input voltage VP104 (for example, 5VP here, if "Dinl00 = "0" (write), Din 10 0 = "1" (write prohibited), "Data 10 0 = 5 V, Datal07 = 0V", Since the row selection transistors C101-0 to C101-7 become conductive, 5V is applied to the bit line BIT1 1 1 - 0, and 0 V is applied to the BIT1 1 1 - 7. Therefore, the memory cell M1 1 1 _ 0 is written. The data "〇", and the -128- 201010062 threshold becomes higher. In addition, M111-7 becomes the data "1" (write prohibited), while the threshold is still low. On the other hand, the row decoder 1400-n becomes Non-selection, because the output signals COLlOna, COLlOnaB each become "〇", "1", so the selection circuit 1300 - ln ~ 1300 - mn becomes non-selected 'and the memory cell array 1100 - η becomes non-selected state. Again, column decoding The 1200-n also becomes non-selected because the output of the level shifting circuit 1 203 becomes "0" (0V), so Mlml - 0~Mlml - 7 becomes non-selection. Here, regarding writing, if erasing Excessive erasing, because the transistor T102 of the memory cell operates in the unsaturated region, so A difficult period with written questions. In this case, at the time of writing, the voltage (VP102) of the control gate CG100 is set to the first 4V, followed by 5V, 6.0V, ..., and the writing is repeated a plurality of times, as long as the voltage VP102 is gradually increased each time, the Τ102 is The control gate applies "VP102 - Vth (the threshold voltage of the transistor 1 3 03)", and can always operate in the saturation region, and as a result, high-speed writing can be achieved.
此外，電壓VP101、VP102、VP103、VP104例如可利 用上述之第7圖所示的電源電壓控制電路1700產生。此電 源電壓控制電路1700具有電源昇壓電路1701，此電源昇 壓電路1701由振盪器（oscillator)、充電栗、電壓檢測電路 等（都未圖示）所構成。而且，將外部電源VCC100(例如3V) 作爲電源，進行內部昇壓，而輸出各種輸出電壓（例如 10V)。利用此電源電壓控制電路1 700，如第8A圖所示， 可將寫入時的電壓VP102進行步升並輸出。 在拭除時’因爲列解碼器1200 - 1之位準挪移電路 -129- 201010062 1203的輸出爲VPIOI(IOV)，對選擇閘極SG101施加10V， 因爲行解碼器1400 — 1變成W100= “0” ，所以位準挪移電 路1405的輸出信號COLlOla輸出0V，第3位準挪移電路 1403 的輸出信號 COLlOlb 輸出 VP103(10V)。 在資料輸出入線Data 100〜Data 107,經由資料輸入變換 電路1500而輸出VP 104(8 V)。又，拭除控制信號EB 100變 成"〇” ，電晶體1101— 1〜1101— η變成不導通。因此，在 記憶胞元Mill〜Mlln，汲極變成8V，控制閘極變成0V， 源極變成開路，而被拭除。 Θ 讀出時，從位準挪移電路1203輸出VP101(3V)，因爲 信號 W100變成“〇” ，所以位準挪移電路1405輸出 “ 0”（〇V)，NAND電路1404輸出“1” 。對資料輸出入線Further, the voltages VP101, VP102, VP103, and VP104 can be generated, for example, by the power supply voltage control circuit 1700 shown in Fig. 7 described above. The power supply voltage control circuit 1700 has a power supply boosting circuit 1701. The power supply voltage rising circuit 1701 is composed of an oscillator, a charging pump, a voltage detecting circuit, and the like (all not shown). Further, an external power supply VCC100 (for example, 3V) is used as a power source to perform internal boosting, and various output voltages (for example, 10 V) are output. With this power supply voltage control circuit 1700, as shown in Fig. 8A, the voltage VP102 at the time of writing can be stepped up and output. At the time of erasing, 'because the output of the column decoder 1200-1's level shifting circuit-129-201010062 1203 is VPIOI (IOV), 10V is applied to the selection gate SG101 because the row decoder 1400-1 becomes W100=“0 Therefore, the output signal COL10a1 of the level shifting circuit 1405 outputs 0V, and the output signal COL1O1b of the third level shifting circuit 1403 outputs VP103 (10V). The data input/output lines Data 100 to Data 107 are output via the data input conversion circuit 1500 to output VP 104 (8 V). Further, the erasing control signal EB 100 becomes "〇, and the transistors 1101 - 1101_1 - η become non-conducting. Therefore, in the memory cells Mill to Mlln, the drain becomes 8V, and the control gate becomes 0V, the source It becomes an open circuit and is erased. Θ When reading, VP101 (3V) is output from the level shifting circuit 1203. Since the signal W100 becomes "〇", the level shifting circuit 1405 outputs "0" (〇V), the NAND circuit. 1404 output "1". Data input and output line
DatalOO〜Datal07，自感測放大器1600 - 0~1600- 7施加位 元線預充電電壓IV，若記憶胞元Mill— 0是寫入狀態（不 導通），且若位元線BIT111-0是IV、記憶胞元Mill— 7 是拭除狀態（導通），則電流流動，，而位元線BIT1 1 1 - 7及 Datal07的位準下降，感測放大器1600 — 0~1600 ~ 7檢測 〇 此電壓差，而輸出 Doutl00= “0” 、Doutl07= “1” 。 此外，在第22圖所示之本發明之第15實施形態的非 揮發性半導體記憶裝置（EEPROM)，位準挪移電路1 203相 當於上述之第1位準挪移電路，位準挪移電路1 40 5相當於 上述之第2位準挪移電路，位準挪移電路1 403相當於上述 之第3位準挪移電路。 而’在第15實施形態所示之非揮發性半導體記憶裝 置’在其構成上，配置成由將記憶胞元對各列在行方向以 -130- 201010062 1位元組單位（例如，記憶胞元Mill- 0~M111- 7)被進行 行選擇之8位元單位的記億胞元方塊所構成。又，沿著列 方向利用位元線BIT 101— 0~ BIT 1 On— 7共同連接各記憶 胞元Ml 1 1 — 0〜Mlmn— 7之第1電晶體T101的汲極。 而，沿著行方向利用選擇閘極配線SG101~SG10m共同 連接記憶胞元之係屬第1電晶體T101的閘極的選擇閘極 SG1 00。又，對各記憶胞元方塊，沿著行方向利用控制閘 極配線CG111〜CGlmn共同連接記憶胞元之係屬第2電晶 〇 體T102的閘極的控制閘極CG100。 又，在行方向以1位元組單位所選擇之各行選擇範圍 內設置源極線S101〜S10n，該行選擇範圍內之所有的列之 各各記憶胞元之第 2電晶體的源極各自利用源極線 S 1 01〜S 1 On共同連接。 列解碼器1200 — 1〜1200- m接受位址信號，並輸出選 擇記憶胞元的列選擇信號》第1位準挪移電路1 203將從列 解碼器1200- 1~1200 — m所輸出之信號變換成施加於選擇 Q 閘極SG100之第1電壓VP101的信號。行解碼器1400 — 1〜1400 — n接受位址信號，並輸出以1位元組單位選擇記 憶胞元的行選擇信號。第2位準挪移電路1 40 5將從行解碼 器1400 — l-1 400-n所輸出之行選擇信號變換成第2電壓 VP 102的信號。第3位準挪移電路1403將從行解碼器所輸 出之行選擇信號變換成第3電壓VP 103的信號。 選擇電路1300 — 11〜1300 — mn具有傳輸閘極電晶體 1303，其將位準挪移電路1203的輸出信號VP101直接向 選擇閘極SG100傳輸，同時將從位準挪移電路1203所輸 -131- 201010062 出之列選擇信號VP101作爲汲極輸入，並將從位準挪移電 路1405所輸出之列選擇信號VP 102作爲閘極輸入。利用 此第 2傳輸閘極電晶體 1 3 03，向控制閘極配線 CGlll~CGlmn傳輸從位準挪移電路1203所輸出之行選擇 信號VP101，或位準挪移電路1 405的輸出信號VP102和傳 輸閘極電晶體1303之臨限値Vth的電壓之差的電壓信號 (VP 1 02 - Vth)。 行選擇電晶體，例如行選擇電晶體C101-0~C101—7 將從第3位準挪移電路1 403所輸出之行選擇信號VP 103 作爲閘極輸入，並選擇1位元組單位之記憶胞元的位元 線。在由此行選擇電晶體C101— 0〜C101-7所選擇之1位 元組的位元線BIT101 - 0〜BIT101 — 7，經由該行選擇電晶 體，而連接1位元組的資料輸出入線Data 100〜Data 107 ^ 又，資料輸入變換電路1 5 00在接受1位元組單位之寫 入資料Dinl00~Dinl07的輸入信號，並進行資料的寫入及 資料的拭除時，輸出透過該資料輸出入線Datal00~Datal07 及位元線而施加於第1電晶體之汲極的第 4電壓信號 VP1 〇4。又，在讀出資料時，利用感測放大器1600- 0〜1600 —7將資料輸出入線DatalOO〜Datal07所讀出之記憶胞元 的資料放大並向外部輸出。 如此，在第15實施形態所示之本發明的非揮發性半導 體記憶裝置，將從列解碼器所輸出之列選擇信號施加於選 擇閘極SG100的信號變換成第1電壓VP101，並將從行解 碼器所輸出之行選擇信號變換成第2電壓VP102。而，在 選擇電路1300 — 11〜1300-mn，將第1電壓VP101直接向 -132- 201010062 選擇閘極SG100傳送’並利用將第2電壓VPl〇2之行選擇 信號作爲閘極輸入的第2傳輸閘極電晶體1 3 03 ’向控制閘 極CG100傳輸由第2電壓VP102和第2傳輸閘極電晶體 1303的臨限値Vth所決定的電壓（例如VP102— Vth)。 因而，因爲使用第20A圖〜第20F圖所示之非揮發性 半導體記憶元件，可構成非揮發性半導體記憶裝置 (EEPROM)，所以可提供縮小記憶胞元配置上之面積的非揮 發性半導體記憶裝置。又’藉由控制第2電壓VP102的位 〇準，而在寫入資料時，可對控制閘極施加步升電壓。 以上，作爲本發明之第15實施形態，雖然說明使用第 20A圖~第2 0F圖所示之非揮發性半導體記憶元件，構成非 揮發性半導體記憶裝置（EEPROM)之情況的例子，但是未限 定如此，可實現其他的構成之非揮發性半導體記億裝置。 例如，和第6圖所示的第2實施形態、或和第9圖所 示的第3實施形態、或和第18圖所示的第12實施形態一 樣，可採用將記憶胞元陣列在行方向以I/O位元單位（例如 〇 8位元）集中之構成。又，和第19圖所示的第13實施形態 一樣，可採用將記憶胞元陣列在行方向以η位元的位址單 ί立集中之構成。 [第16實施形態] 第23圖係表示本發明之第16實施形態的非揮發性半 導體記憶裝置的構成圖，表示記憶胞元陣列的布置配置。 第23圖所示之記憶胞元陣列的布置是將第20Α圖〜第 2GF圖所示的記憶胞元單元配置成陣列狀，此記憶胞元單 元如上述所示，具有：用以和η型井1 002連接的第7η型 -133- 201010062 擴散層1026、對η型井供給既定之電壓CGWelllOO的第3 金屬配線1028、以及連接第7n型擴散層1026和第3金屬 配線1 028的接點1 027。此第7η型擴散層1 026、接點1027 以及第3金屬配線1 02 8可配置於記憶胞元的空空間，不會 使記憶胞元的面積變大，而刪除第1人圖~第1Ε圖所示之η 型擴散層1017、接點1018之面積縮小效果大。 在第23圖所示的記憶胞元陣列，使選擇閘極配線 SGI"、SG121、SG131、SG141.....控制閘極配線 CG111、 CG12卜CG13卜…在橫向通過，使位元線ΒΙΤ1(Μ、ΒΙΤ102、 BIT 103、…在縱向通過，又，使金屬配線1028在縱向通過。 而且，以第3金屬配線1028爲中心左右對稱地配置、並以 源極線S101爲中心上下對稱地配置第2 0A圖〜第2OF圖所 示的記憶胞元單元，又，使彼此共用η型井1002，以縮小 面積。 例如，在圖上排列於最上段的記憶胞元（Μ 1 1 1、 Μ112)，電晶體Τ101的選擇閘極SG100(多晶矽層1〇〇8)和 共用的選擇閘極配線SGI 1 1連接。又，各記憶胞元（mi 1 1、 Ml 12)之控制閘極CG1 09所連接的控制閘極配線ι〇19和共 用的控制閘極配線（金屬配線）CGI 1 1連接。一樣地，各記 憶胞元（M111、M112)之電晶體T102的源極所連接的第2 金屬配線1013和共用的源極線S101連接。 又，在共用之源極線S 1 0 1的下側所排列的各記憶胞元 (M121、M122)之電晶體T101的選擇閘極SG100(多晶矽層 1008)和共用的選擇閘極配線SG121連接，各記憶胞元之電 晶體T102之控制閘極CG1 09和共用的控制閘極配線（金屬 -134- 201010062 配線）CG121連接。 又，η型井1 002是2行之各記憶胞元（例如汲極和位元 線ΒΙΤ101及位元線ΒΙΤ102連接之2行的記憶胞元）所共有 的η型井，此η型井1002利用在η型井1〇〇2之複數個位 置所形成之η型擴散層1 026及接點1 027和金屬配線1028 連接。 而且，在第23圖所示的非揮發性半導體記億裝置，將 合計4個記憶胞元Mill、Μ112、Μ121、Μ122作爲配置的 〇 基本單位，其中2個記憶胞元（例如Ml 1 1、Ml 12)使彼此共 用η型井1〇 〇2並左右對稱地配置，而其他2個記憶胞元（例 如Ml 1 1和Ml 12)對該左右對稱地配置之2個記憶胞元，使 彼此共用第2金屬配線1013(共用的源極線S101)，並在下 方向對稱地配置。而且，將成爲基本單位之4個記憶胞元 在左右方向平行地排列配置，同時在上下方向亦平行地排 列配置。因而，可緊密地配置本發明的非揮發性半導體記 憶元件，並可使使非揮發性半導體記憶裝置的面積變成最 〇小限度。 此外，在第23圖所示的第16實施形態，在記憶胞元（根 據位元線BIT 102和選擇閘極配線SG11 1所選擇的記憶胞 元），雖然金屬配線1012配置於電晶體形成部1 03 0的左 側，但是配置於正上或配置於右側亦一樣。其中，在本例， 配置於右側時，因爲記憶胞元尺寸由金屬配線1012的間隔 所決定，所以有記憶胞元尺寸變成稍大的情況。 第24圖係用以說明第23圖所示之非揮發性半導體記 憶裝置的動作圖，表示動作表。 -135- 201010062 例如，考慮選擇第23圖之Mill的情況。此時，亦包 含變成非選擇之M113的動作。在寫入1一1的情況，選擇 位元線BIT 101，而變成5V，因爲BIT 103變成非選擇，而 成爲0V。因此，雖然對Mill進行寫入，但是對M113不 進行寫入。 關於拭除，亦因爲位元線BIT 101變成8V，而位元線 BIT103成爲0V，所以在和位元線BIT103連接之記憶胞元 不進行拭除。讀出亦相同。在寫入1_2的情況，因爲對位 元線BIT101施加0V、對CG101施加5V，所以對記憶胞元 Μ 1 1 1的汲極和控制閘極施加1 5 V的電場，即，對浮動閘極 和汲極之間，設α100 = 0.6，施加「（15Vx0.6 — 0V) = 9V」， 雖然從汲極向浮動閘極注入電子，但是因爲位元線BIT 103 在非選擇時變成5V，所以對浮動閘極和汲極之間，施加 (15Vx0.6- 5V) = 4V，因爲電場弱，所以不會發生寫入。 在如以上所說明之本發明的實施形態中之第2、第3、 第4、第5、第12以及第15實施形態，雖然全部以丨位元 組（8位元胞元）的單位說明記憶體構成，但是未限定如此， 因應於要求規格，而作成字元單位（16位元胞元）或雙字元 (32位元胞元）等的記憶胞元陣列構成，主旨亦完全相同。 如以上之說明所示，在本發明之非揮發性半導體記憶 元件及非揮發性半導體記憶裝置，以標準邏輯元件的 CMOS製程可實現非揮發性記憶體，並可簡單且便宜地實 現邏輯元件混載記憶體。 [第17實施形態] 第25A圖〜第25D圖係表示本發明之第17實施形態之 -136- 201010062 非揮發性半導體記憶元件的構成圖。此外，在以下的說明， 有時將「非揮發性半導體記憶元件」只稱爲「記憶胞元」。 第25A圖表示記憶胞元的平面圖，第25B圖表示等價 電路圖，第25C圖表示沿著第25A圖之A20— A20’的剖 面圖，第25D圖表示沿著B20— B20’的剖面圖。 此記憶胞元如第25B圖的等價電路所示，由電晶體 T201和電容器C201所構成，並具有汲極D200、源極S200、 控制閘極CG200以及浮動閘極FG200。C201是控制閘極 〇 CG200和浮動閘極FG200之間的電容器。 在構造上，在第25A圖〜第25D圖，符號2001是p型 半導體基板，2 002是形成於p型半導體基板200 1上的n 型井（以下n-we 11)，符號2003是電晶體形成部，符號2 00 4 是構成電晶體T2 0 1的浮動閘極型電晶體的通道形成部（閘 極區域部），符號2005是電晶體T2 01的η型汲極擴散層， 符號2006是成爲電晶體Τ2 01之源極的η型擴散層，符號 2009是成爲電晶體Τ2 01之浮動閘極的多晶矽層，並成爲 Q 電容器C 201的一端。符號2010是連接η型擴散層2005 和金屬配線2012的接點，符號2011是連接擴散層2006和 金屬配線2013的接點，符號2012是用以拉出電晶體Τ201 之汲極D200的金屬配線，符號2013是用以拉出電晶體 Τ201之源極S200的金屬配線，符號2014是電容器C201， 符號2015是ρ型擴散層，並成爲電容器C2 01的另一端。 符號2016是連接ρ型擴散層2015和控制閘極配線 1019的接點，符號2017是形成於η型井2002上的η型擴 散層，符號2018是連接η型擴散層2017和控制閘極配線 -137- 201010062 20 19的接點。符號2019是成爲控制閘極配線的金屬配線， 2020是分離用絕緣氧化膜。 此記憶胞元之特徵如圖所示，在縱向（在圖面上爲上下 方向）配置電晶體形成部2003，其包含有電晶體T201的η 型擴散層2005、及成爲電晶體Τ2 01之源極的η型擴散層 2006等。又，亦在縱向配置成爲位元線之記憶胞元之汲極 的金屬配線2012，在橫向（在圖面上爲左右方向）配置成爲 控制閘極配線2019的金屬配線，又緊密地配置面積變大的 電容器 C201(由 2002、2009、2014、2015 以及 2016 等所 構成），使面積變成最小限度。 第26A圖~第26C圖係用以說明第25A圖〜第25D圖所 示之記憶胞元的動作圖。以下，參照第26 A圖~第2 6C圖， 說明其動作。 作爲動作，分成用作OTP的情況，和可進行複數次之 寫入、拭除之用作MTP的情況，加以說明。 第26A圖表示使作爲OTP進行動作之情況的動作表。 以下，使用第26A圖說明使作爲OTP進行動作之情況。 在OTP動作之情況的寫入，藉由注入熱電子，而向浮 動閘極注入電子。 在此情況，對控制閘極CG200施加6V，對汲極D200 施加5V，對源極S200施加0V。對汲極及閘極施加高電壓， 爲了在飽和區域進行動作，而在汲極附近對空乏層施加高 電壓，產生熱電子，其被注入浮動閘極。因爲注入電子， 所以表面上浮動閘極型電晶體T201的臨限値變高》 此外，在此，關於寫入電壓，雖然將控制閘極CG200 -138- 201010062 設爲 6V，將汲極 D200 設爲 5 V(CG200 = 6V、D200 = 5 V)，但 是因爲產生熱電子，只要使其在飽和區域進行動作即可， 所以不受此電壓規定。例如亦可將控制閘極CG2 00設爲 5V，將汲極 D200 設爲 5V(CG200 = D200 = 5V)，即使汲極 D200 的電壓比控制閘極CG200的電壓高，在動作上亦無問題。 其次，關於讀出，對控制閘極CG200施加3V，對汲極 D200施加IV，對源極S200施加0V時，因爲起始的臨限 値是約IV，所以不寫入時電晶體T201變成導通（邏輯 〇 “1”），而寫入時，因爲被注入電子，而臨限値表面上變 成約5V，所以變成不導通（邏輯“ 0”），而記憶資料。 第26B圖表示使作爲MTP進行動作之情況的動作表。 以下，使用第26B圖說明使作爲MTP進行動作之情況。 在MTP動作之情況的寫入，係和OTP動作之情況一樣。 在拭除的情況，以拭除2— 1和拭除2— 2之2步驟進 行。 在拭除2 — 1的步驟，預先將控制閘極CG200偏壓至 Q 0V，將汲極D200偏壓至8V，使源極S2 00變成開路（open) 或偏壓至約2V。在此狀態，對汲極和浮動閘極間施加高電 壓，而Fowler— Nordheim的穿.險電流（以下簡稱爲FN電流） 流動，從浮動閘極向汲極放出電子，而表面上看起來臨限 値降低。 其次，作爲拭除2—2的步驟，將控制閘極CG200設 爲0或1V，將汲極D200設爲8V，將源極S200設爲0V。 若是記憶胞元被過度拭除，因爲浮動閘極帶正電’所 以若將源極設爲0V，則導通電流流動。在此，因爲使汲極 -139- 201010062 變成高電壓，所以產生弱的熱電子，而發生寫入。將其定 義爲弱寫入（drain stress)。 此外，第27A圖及第27B圖係表示第25A圖〜第25D 圖所示之記憶胞元之電晶體T201的特性圖，表示VCG- ID 特性。在第2 7A圖，在起始値之特性A— 2的狀態，進行 寫入時，成爲寫入特性B— 2。 其次，執行拭除2- 1的步驟時，成爲過度拭除的特性 C_2»然後，藉由執行拭除2 - 2的步驟，而可從過度拭除 的特性C - 2向起始値之特性A-2的狀態寫回。 在第28A圖，表示弱寫入的特性。第28B圖係表示第 28A圖之特性的電路構成圖。在第28A圖，在橫軸表示施 加弱寫入的時間，在縱軸取臨限値時，例如若使閘極電壓 CG200變成0V，藉由施加弱寫入（drain stress)，產生微小 卻利用汲極附近之高電場而得到高能量的熱電子，其一部 分被取入浮動閘極內，成爲弱寫入，最後自收歛成起始狀 態。在此，若使閘極電壓CG2 00變成IV，收歛之臨限値位 準收歛成平行挪移IV的値。若使用此特性，即使有以拭除 2_1進行過度拭除的胞元，亦能以拭除2- 2使自收歛至 某程度之任意的正臨限値，而可應付過度拭除。 第29A圖表示此胞元之耦合系統的等價電路。第29B 圖係表示第29 A圖的電路構成圖。若浮動閘極之狀態爲起 始狀態（中性狀態），因爲此系統的總電荷爲0，所以 若(VCG200 — VFG200)xC200(FC200)+ (Vsub200 — VFG200)xC200(FB200)+ (VD200 - V F G 2 0 0) x C 2 0 0 ( F D 2 0 0) + (VS200 - VFG200)xC200(FS200) = 0 、 C200(FC200) + -140- 201010062 C200(FB200) + C200(FD200) + C200(FS200) = CT200(總和），貝|J VFG200 = VCG200xC200(FC200)/CT200 + Vsub200xC200 (FB200) /CT200 + VD200xC200(FD200)/CT200 + VS200xC200(FS200) /CT200DatalOO~Datal07, self-sensing amplifier 1600 - 0~1600-7 applies bit line pre-charge voltage IV, if memory cell Mill_0 is write state (non-conducting), and if bit line BIT111-0 is IV When the memory cell Mill-7 is in the erase state (conduction), the current flows, and the levels of the bit lines BIT1 1 1 - 7 and Datal07 fall, and the sense amplifier 1600 - 0~1600 ~ 7 detects this voltage. Poor, and the output Doutl00 = "0", Doutl07 = "1". Further, in the nonvolatile semiconductor memory device (EEPROM) according to the fifteenth embodiment of the present invention shown in Fig. 22, the level shifting circuit 1 203 corresponds to the above-described first level shifting circuit, and the level shifting circuit 1 40 5 corresponds to the second level shifting circuit described above, and the level shifting circuit 1 403 corresponds to the third level shifting circuit described above. On the other hand, the non-volatile semiconductor memory device shown in the fifteenth embodiment is configured such that the memory cell pairs are arranged in the row direction at -130 to 201010062 in 1-bit units (for example, memory cells). Yuan Mill-0-M111-7) is composed of a octet cell of an 8-bit unit selected for row selection. Further, the drains of the first transistor T101 of the respective memory cells M1 1 1 - 0 to Mlmn-7 are connected in common in the column direction by the bit lines BIT 101 - 0 to BIT 1 On - 7. On the other hand, the selection gates SG101 to SG10m are used to connect the memory cell to the gate selection gate SG1 00 of the first transistor T101. Further, for each memory cell block, the control gate CG100 of the gate of the second transistor T102 is connected to the memory cell by the control gate wirings CG111 to CGlmn in the row direction. Further, source lines S101 to S10n are provided in each row selection range selected by one byte unit in the row direction, and the source of the second transistor of each of the memory cells in all the columns in the row selection range is selected. The source lines S 1 01 to S 1 On are connected in common. The column decoder 1200-1 1200-m receives the address signal and outputs a column selection signal for selecting the memory cell. The first bit shifting circuit 1 203 outputs the signal from the column decoders 1200-1 to 1200-m. It is converted into a signal applied to the first voltage VP101 that selects the Q gate SG100. The row decoders 1400 - 1 to 1400 - n accept the address signals and output a row selection signal for selecting the memory cells in 1-bit units. The second level shifting circuit 1 40 5 converts the line selection signal output from the line decoder 1400-1-1-n to the signal of the second voltage VP 102. The third bit shifting circuit 1403 converts the row select signal output from the row decoder into a signal of the third voltage VP 103. The selection circuit 1300 - 11 1300 - 1300 - mn has a transmission gate transistor 1303 which transmits the output signal VP101 of the level shifting circuit 1203 directly to the selection gate SG100, and will be transferred from the level shifting circuit 1203 - 131 - 201010062 The output column selection signal VP101 is used as a drain input, and the column selection signal VP 102 output from the level shift circuit 1405 is used as a gate input. By using the second transfer gate transistor 133, the row select signal VP101 output from the level shift circuit 1203, or the output signal VP102 of the level shift circuit 1405 and the transfer gate are transmitted to the control gate wirings CG11 to CGlmn. The voltage signal (VP 1 02 - Vth) of the difference between the voltages of the polar transistors 1303 and the voltage of Vth. The row selection transistor, for example, the row selection transistor C101-0~C101-7, selects the row selection signal VP 103 output from the third bit shift circuit 1 403 as a gate input, and selects a memory cell of 1 byte unit. The bit line of the yuan. In this row, the 1-bit tuple bit line BIT101 - 0 to BIT101 - 7 selected by the transistor C101 - 0 - C101 - 7 is selected, and the transistor is selected via the row, and the 1-bit data output line is connected. Data 100~Data 107 ^ In addition, the data input conversion circuit 1 500 receives the input signal of the data Dinl00~Dinl07 in the 1-bit unit, and writes the data and erases the data. The input voltage lines Datal00 to Datal07 and the bit lines are applied to the fourth voltage signal VP1 〇4 of the drain of the first transistor. Further, when reading data, the data of the memory cells read out by the data output lines Data1OO to Datal07 are amplified by the sense amplifiers 1600-1 to 1600-7 and output to the outside. As described above, in the nonvolatile semiconductor memory device of the present invention shown in the fifteenth embodiment, the signal applied from the column select signal output from the column decoder to the selection gate SG100 is converted into the first voltage VP101, and the line is switched. The row selection signal output by the decoder is converted into a second voltage VP102. On the other hand, in the selection circuits 1300-11 to 1300-mn, the first voltage VP101 is directly transmitted to the -132-201010062 gate SG100, and the second selection signal of the second voltage VP1〇2 is used as the gate input. The transfer gate transistor 133' transmits a voltage (e.g., VP102 - Vth) determined by the threshold 値Vth of the second voltage VP102 and the second transfer gate transistor 1303 to the control gate CG100. Therefore, since the non-volatile semiconductor memory device shown in FIGS. 20A to 20F can be used to form a non-volatile semiconductor memory device (EEPROM), it is possible to provide a non-volatile semiconductor memory that reduces the area of the memory cell configuration. Device. Further, by controlling the bit level of the second voltage VP102, a step-up voltage can be applied to the control gate when data is written. As described in the fifteenth embodiment of the present invention, a nonvolatile semiconductor memory device shown in FIGS. 20A to 20F is used to form a nonvolatile semiconductor memory device (EEPROM). However, the present invention is not limited. In this way, a non-volatile semiconductor device of other configurations can be realized. For example, in the second embodiment shown in Fig. 6, or in the third embodiment shown in Fig. 9, or in the twelfth embodiment shown in Fig. 18, the memory cell array can be used in the line. The direction is composed of I/O bit units (for example, 〇8 bits). Further, as in the thirteenth embodiment shown in Fig. 19, it is possible to adopt a configuration in which the memory cell array is arbitrarily concentrated in the row direction by n bits. [16th embodiment] FIG. 23 is a view showing a configuration of a nonvolatile semiconductor memory device according to a sixteenth embodiment of the present invention, showing an arrangement arrangement of memory cell arrays. The memory cell array shown in FIG. 23 is arranged such that the memory cell units shown in the 20th to 2nd GF are arranged in an array, and the memory cell unit has the following: The 7th n-type-133-201010062 connected to the well 1 002, the diffusion layer 1026, the third metal wiring 1028 that supplies the predetermined voltage CGWelllOO to the n-type well, and the junction that connects the seventh n-type diffusion layer 1026 and the third metal wiring 1 028 1 027. The 7th n-type diffusion layer 1 026, the contact 1027, and the third metal interconnection 1 08 8 can be disposed in the empty space of the memory cell, and the first pixel map is deleted without increasing the area of the memory cell. The n-type diffusion layer 1017 and the contact 1018 shown in the figure have a large area reduction effect. In the memory cell array shown in Fig. 23, the gate wirings SGI", SG121, SG131, SG141..... control gate wirings CG111, CG12, CG13, etc. are passed in the lateral direction so that the bit lines ΒΙΤ1 (Μ, ΒΙΤ 102, BIT 103, ... pass through in the longitudinal direction, and the metal wiring 1028 is passed in the longitudinal direction. Further, the third metal wiring 1028 is disposed symmetrically about the center, and is vertically symmetrically arranged around the source line S101. The memory cell unit shown in the 20th to the 2ndth image is further shared with the n-type well 1002 to reduce the area. For example, the memory cells arranged in the uppermost stage on the map (Μ 1 1 1 , Μ 112 The selection gate SG100 (polysilicon layer 1〇〇8) of the transistor 101 is connected to the common selection gate wiring SGI 1 1. Further, the control gate CG1 09 of each memory cell (mi 1 1 , M12) The connected control gate wiring 〇19 is connected to the common control gate wiring (metal wiring) CGI 1 1. Similarly, the second source of the transistor T102 of each memory cell (M111, M112) is connected. The metal wiring 1013 is connected to the common source line S101. Also, the source of sharing The selection gate SG100 (polysilicon layer 1008) of the transistor T101 of each memory cell (M121, M122) arranged on the lower side of the line S1 0 1 is connected to the common selection gate wiring SG121, and the memory of each memory cell The control gate CG1 09 of the crystal T102 is connected to the common control gate wiring (metal-134-201010062 wiring) CG121. Further, the n-type well 1 002 is a memory cell of two rows (for example, the drain and the bit line 101) The n-type well shared by the memory cells of the two rows connected by the bit line ΒΙΤ102, the n-type well 1002 is connected by the n-type diffusion layer 1 026 formed at a plurality of positions of the n-type well 1〇〇2 Point 1 027 is connected to the metal wiring 1028. Further, in the nonvolatile semiconductor device shown in Fig. 23, a total of four memory cells Mill, Μ112, Μ121, and Μ122 are used as the basic unit of the configuration, of which two The memory cells (for example, M11, M12) share the n-type well 1〇〇2 with each other and are symmetrically arranged left and right, and the other two memory cells (for example, M11 and M12) are symmetrically arranged to the left and right. The two memory cells share the second metal wiring 1013 with each other (the shared source line S 101) and arranged symmetrically in the lower direction. Further, the four memory cells which are the basic units are arranged in parallel in the left-right direction, and are arranged in parallel in the vertical direction. Therefore, the non-invention of the present invention can be closely arranged. The volatile semiconductor memory element allows the area of the non-volatile semiconductor memory device to be minimized. Further, in the sixteenth embodiment shown in Fig. 23, in the memory cell (the memory cell selected based on the bit line BIT 102 and the selection gate wiring SG11 1), the metal wiring 1012 is disposed in the transistor forming portion. The left side of 1 03 0, but the same as the configuration on the right side or the right side. However, in this example, when arranged on the right side, since the memory cell size is determined by the interval of the metal wiring 1012, the memory cell size becomes slightly larger. Fig. 24 is a view for explaining the operation of the nonvolatile semiconductor memory device shown in Fig. 23, showing an operation table. -135- 201010062 For example, consider the case of selecting Mill in Figure 23. At this time, it also includes an action of changing to M113 which is not selected. In the case of writing 1-1, the bit line BIT 101 is selected and becomes 5V because BIT 103 becomes non-selected and becomes 0V. Therefore, although Mill is written, M113 is not written. Regarding the erasing, since the bit line BIT 101 becomes 8V and the bit line BIT103 becomes 0V, the memory cell connected to the bit line BIT103 is not erased. The reading is also the same. In the case of writing 1_2, since 0 V is applied to the bit line BIT101 and 5 V is applied to the CG 101, an electric field of 15 V is applied to the drain of the memory cell Μ 1 1 1 and the control gate, that is, the floating gate Between the anode and the drain, let α100 = 0.6 and apply "(15Vx0.6 - 0V) = 9V". Although the electron is injected from the drain to the floating gate, since the bit line BIT 103 becomes 5V when it is not selected, Between the floating gate and the drain, (15Vx0.6-5V) = 4V, because the electric field is weak, so writing does not occur. The second, third, fourth, fifth, twelfth, and fifteenth embodiments in the embodiments of the present invention as described above are all described in units of units of octets (octets). The memory configuration is not limited thereto, and the memory cell array such as a character unit (16-bit cell) or a double character (32-bit cell) is formed in accordance with the required specifications, and the subject matter is also completely the same. As shown in the above description, in the non-volatile semiconductor memory device and the non-volatile semiconductor memory device of the present invention, non-volatile memory can be realized by a CMOS process of standard logic elements, and logic element mixing can be realized simply and inexpensively. Memory. [17th embodiment] FIG. 25A to FIG. 25D are diagrams showing a configuration of a nonvolatile semiconductor memory device of the 136th to 201010062 of the seventeenth embodiment of the present invention. In addition, in the following description, a "nonvolatile semiconductor memory element" may be simply referred to as a "memory cell." Fig. 25A shows a plan view of the memory cell, Fig. 25B shows an equivalent circuit diagram, Fig. 25C shows a cross-sectional view taken along line A20-A20' of Fig. 25A, and Fig. 25D shows a cross-sectional view along B20-B20'. This memory cell is composed of a transistor T201 and a capacitor C201 as shown in the equivalent circuit of Fig. 25B, and has a drain D200, a source S200, a control gate CG200, and a floating gate FG200. C201 is a capacitor between the control gate CG CG200 and the floating gate FG200. Structurally, in the 25A to 25D, the symbol 2001 is a p-type semiconductor substrate, 2 002 is an n-type well (hereinafter n-we 11) formed on the p-type semiconductor substrate 200 1 , and the symbol 2003 is a transistor. The forming portion, the symbol 2 00 4 is a channel forming portion (gate region portion) of the floating gate type transistor constituting the transistor T2 0 1 , and the symbol 2005 is an n-type drain diffusion layer of the transistor T2 01, the symbol 2006 is An n-type diffusion layer which becomes a source of the transistor Τ201, symbol 2009 is a polysilicon layer which becomes a floating gate of the transistor Τ201, and becomes one end of the Q capacitor C201. The symbol 2010 is a contact connecting the n-type diffusion layer 2005 and the metal wiring 2012, the symbol 2011 is a contact connecting the diffusion layer 2006 and the metal wiring 2013, and the symbol 2012 is a metal wiring for pulling out the drain D200 of the transistor Τ201, Reference numeral 2013 is a metal wiring for pulling out the source S200 of the transistor 201, the symbol 2014 is a capacitor C201, and the symbol 2015 is a p-type diffusion layer, and becomes the other end of the capacitor C2 01. Symbol 2016 is a joint connecting the p-type diffusion layer 2015 and the control gate wiring 1019, the symbol 2017 is an n-type diffusion layer formed on the n-type well 2002, and the symbol 2018 is an n-type diffusion layer 2017 and a control gate wiring - 137- 201010062 20 19 contacts. Reference numeral 2019 is a metal wiring that serves as a gate wiring, and 2020 is an insulating oxide film for separation. The characteristics of this memory cell are as shown in the figure, and a transistor forming portion 2003 including an n-type diffusion layer 2005 of a transistor T201 and a source of the transistor Τ201 is disposed in a longitudinal direction (up and down direction on the drawing). A very large n-type diffusion layer 2006 or the like. In addition, the metal wiring 2012 which is the drain of the memory cell which is the bit line is disposed in the vertical direction, and the metal wiring which serves as the control gate wiring 2019 is disposed in the lateral direction (the horizontal direction on the drawing), and the area is changed closely. The large capacitor C201 (consisting of 2002, 2009, 2014, 2015, and 2016) minimizes the area. Fig. 26A to Fig. 26C are diagrams for explaining the operation of the memory cell shown in Fig. 25A to Fig. 25D. Hereinafter, the operation will be described with reference to FIGS. 26A to 2 6C. The operation is divided into a case where it is used as an OTP, and a case where it can be used for MTP in which a plurality of times of writing and erasing can be performed. Fig. 26A is a diagram showing an operation of the case where the OTP is operated. Hereinafter, a case where the OTP is operated will be described using FIG. 26A. In the case of the OTP operation, electrons are injected into the floating gate by injecting hot electrons. In this case, 6 V is applied to the control gate CG200, 5V is applied to the drain D200, and 0V is applied to the source S200. A high voltage is applied to the drain and the gate, and in order to operate in the saturation region, a high voltage is applied to the depletion layer near the drain to generate hot electrons, which are injected into the floating gate. Since the electrons are injected, the threshold of the floating gate type transistor T201 becomes high on the surface. Further, here, regarding the write voltage, although the gate CG200 - 138 - 201010062 is set to 6V, the drain D200 is set. It is 5 V (CG200 = 6V, D200 = 5 V), but since it generates hot electrons, it is only required to operate in a saturated region, so it is not regulated by this voltage. For example, the control gate CG2 00 can be set to 5V, and the drain D200 can be set to 5V (CG200 = D200 = 5V). Even if the voltage of the drain D200 is higher than the voltage of the control gate CG200, there is no problem in operation. Next, regarding the reading, when 3V is applied to the control gate CG200, IV is applied to the drain D200, and 0V is applied to the source S200, since the initial threshold 値 is about IV, the transistor T201 becomes conductive when not written. (Logic 〇 "1"), while writing, because the electron is injected, and the threshold becomes about 5V on the surface, it becomes non-conductive (logic "0"), and the data is memorized. Fig. 26B is a diagram showing an operation table in the case of operating as an MTP. Hereinafter, a case where the operation is performed as the MTP will be described using FIG. 26B. The writing in the case of the MTP operation is the same as in the case of the OTP operation. In the case of erasing, the steps of wiping 2-1 and erasing 2-2 are performed. In the step of erasing 2-1, the control gate CG200 is biased to Q 0V in advance, the drain D200 is biased to 8V, and the source S2 00 is turned open or biased to about 2V. In this state, a high voltage is applied between the drain and the floating gate, and Fowler-Norway's dangerous current (hereinafter referred to as FN current) flows, and electrons are emitted from the floating gate to the drain, and the surface appears to be The limit is reduced. Next, as a step of erasing 2-2, the control gate CG200 is set to 0 or 1V, the drain D200 is set to 8V, and the source S200 is set to 0V. If the memory cell is excessively erased, since the floating gate is positively charged, the on current flows if the source is set to 0V. Here, since the drain-139-201010062 is made high voltage, weak hot electrons are generated and writing occurs. It is defined as a drain stress. Further, Fig. 27A and Fig. 27B are diagrams showing the characteristics of the transistor T201 of the memory cell shown in Figs. 25A to 25D, showing the VCG-ID characteristics. In the case of Fig. 2A, when the write is performed in the state of the characteristic A-2, the write characteristic B-2 is obtained. Next, when the step of erasing 2-1 is performed, the characteristic C_2» which becomes excessively erased is then subjected to the step of erasing 2-2, and the characteristic of the excessively erased characteristic C-2 is started. The status of A-2 is written back. In Fig. 28A, the characteristics of weak writing are shown. Fig. 28B is a circuit configuration diagram showing the characteristics of Fig. 28A. In Fig. 28A, the horizontal axis indicates the time during which the weak writing is applied, and when the vertical axis is the threshold, for example, if the gate voltage CG200 is changed to 0 V, the application of the weak stress causes a slight use. A high-energy hot electron near the bungee pole, a part of which is taken into the floating gate, becomes weakly written, and finally self-converges into an initial state. Here, if the gate voltage CG2 00 is changed to IV, the threshold of convergence converges to 値 which shifts IV in parallel. If this feature is used, even if there is a cell that is over-erased by erasing 2_1, it can be self-converged to a certain degree of positive threshold by wiping off 2- 2, and it can cope with excessive erasure. Figure 29A shows the equivalent circuit of the coupling system of this cell. Fig. 29B is a circuit diagram showing the structure of Fig. 29A. If the state of the floating gate is the initial state (neutral state), since the total charge of this system is 0, if (VCG200 - VFG200)xC200(FC200)+(Vsub200 - VFG200)xC200(FB200)+ (VD200 - VFG 2 0 0) x C 2 0 0 ( FD 2 0 0) + (VS200 - VFG200) xC200 (FS200) = 0, C200 (FC200) + -140- 201010062 C200 (FB200) + C200 (FD200) + C200 ( FS200) = CT200 (sum), shell|J VFG200 = VCG200xC200(FC200)/CT200 + Vsub200xC200 (FB200) /CT200 + VD200xC200(FD200)/CT200 + VS200xC200(FS200) /CT200
在此，若 C200(FD200)=C200(FS200)= 0 ' Vsub200= VS200 = 0，貝IJ VFG200 = YCG200xC200(FC200)/{C200(FC200) + C200( o FB00)} 在此，若 C200(FC200)/{C200(FC200) + C200(FBOO)} = a 200(耦合比），則 VFG200=a 200xVCG200。 一般，設定成a 200 4 0.6。 此外，n型擴散層2005相當於上述之成爲電晶體之汲 極的第In型擴散層，η型擴散層2006相當於上述之第2η 型擴散層。又，第In型擴散層2005和第2η型擴散層2006 〇 之間的區域相當於上述的閘極區域部，金屬配線2012相當 於上述的第1金屬配線，金屬配線20 13相當於上述的第2 金屬配線。Here, if C200(FD200)=C200(FS200)= 0 ' Vsub200= VS200 = 0, Bay IJ VFG200 = YCG200xC200(FC200)/{C200(FC200) + C200( o FB00)} Here, if C200 (FC200) ) / {C200 (FC200) + C200 (FBOO)} = a 200 (coupling ratio), then VFG200 = a 200xVCG200. Generally, it is set to a 200 4 0.6. Further, the n-type diffusion layer 2005 corresponds to the above-described first In-type diffusion layer which becomes the anode of the transistor, and the n-type diffusion layer 2006 corresponds to the above-described second n-type diffusion layer. Further, a region between the first In-type diffusion layer 2005 and the second n-type diffusion layer 2006 相当于 corresponds to the above-described gate region portion, the metal wiring 2012 corresponds to the above-described first metal wiring, and the metal wiring 20 13 corresponds to the above-described first 2 Metal wiring.
又，在對浮動閘極儲存電荷時（寫入時），第26 Α圖所 示之控制閘極CG200的電壓“ 6” V相當於上述之施加於 第1電晶體之閘極的第1高電壓，汲極D2 00的電壓“ 5” V 相當於上述之施加於汲極D200的第2電壓。又，第26B 圖所示之汲極D200的電壓“ 8” V相當於在上述之第1拭 除部施加於汲極D200的第3電壓，源極S200的電壓“2” V -141- 201010062 相當於在上述之施加於源極s 200的第4電壓。又，第26B 圖所示之控制閘極CG200的電壓“ 1” V相當於在上述之 第2拭除部施加於控制閘極CG2 00的第5電壓。 而，在半導體基板表面上的第1方向（在第25A圖上爲 上下方向），配置形成電晶體的電晶體形成部2003，此電晶 體形成部20 03由上依序配置：成爲電晶體T2 01之汲極的 第In型擴散層2 005、形成通道的閘極區域部2004(第1擴 散層2005和第2擴散層2006之中間的區域）、以及成爲電 晶體T201之源極的第2η型擴散層2006。 在此電晶體形成部2003的左側，在上下方向配置金屬 配線20 12。此金屬配線2012從半導體基板表面隔著既定 之距離配置成和電晶體形成部2003平行，又，金屬配線 2012利用接點2010和電晶體Τ201的汲極（第In型擴散層 2005)連接。 在此電晶體形成部2003的左側，以既定之寬度和深度 在左右方向所形成方形的η型井2002。方形的浮動閘極 20 0 9在左右方向配置成和半導體基板表面相對向，同時配 置成其左端部側的區域和η型井2002的表面相對向，而且 右端部側的區域和電晶體Τ201的閘極區域部2004(第In 型擴散層2005和第2n型擴散層2006之中間的通道形成區 域）相對向。 在η型井2002之左側，在左右方向形成p型擴散層 2015，其和與此η型井2002的浮動閘極2009相對向之區 域的左側相鄰，並具有既定之寬度和深度。此ρ型擴散層 20 1 5和控制閘極配線20 1 9利用接點20 1 6連接。此控制閘 -142- 201010062 極配線2019從半導體基板表面隔著既定之距離在左右方 向配置成和浮動閘極2009相對向，又，利用接點2016和 P型擴散層2015連接。第2金屬配線2013從半導體基板 表面隔著既定之距離在左右方向配置成和成爲電晶體 T201之源極的第2n型擴散層2006相對向，此第2金屬配 線2013利用接點2011和第2n型擴散層2006連接。 利用這種構成，以標準邏輯元件的CMOS製程可實現 非揮發性記憶體，同時可實現OTP或MTP。又，可緊密地 〇配置面積變大的電容器（在浮動閘極和半導體基板表面所 形成之電容器），使面積變成最小限度。 此外，在第25A圖〜第25D圖所示的第17實施形態， 雖然將金屬配線2012配置於電晶體形成部2003的左側， 但是亦可配置於正上或配置於右側。 [第18實施形態] 第30圖係表示本發明之第18實施形態的非揮發性半 導體記憶裝置的構成圖。第30圖所示的例子是將本發明的 〇 非揮發性半導體記憶元件（記憶胞元）裝入陣列（記憶胞元 陣列）的例子，是OTP的例子。 在第3 0圖所示的例子，作爲記憶陣列之構成，輸出入 I/O採用I/O — 0〜I/O — 7之8位元構成，記憶陣列由在行方 向爲η位元、在列方向爲m位元之單位的記憶胞元方塊 2100 — 0~2100 - 7所構成。即，記憶胞元如M211— 0〜M21n -0、M211— 7~ M21n— 7般，在行方向以n位元的位址單 位集中，而構成至記憶胞元方塊2100 — 0〜2 10 0— 7。此外， 記憶胞元的源極全部共同連接》 -143- 201010062 列解碼器2200- 1~2200— m各自由位址解碼器2201、 反相器2202以及位準挪移電路2203所構成。位準挪移電 路2203將從列解碼器2200- 1~2200 — m所輸出之列選擇 信號變換成第1信號電壓VP201。位準挪移電路2203的輸 出各自成爲字元線WL201~WL20m的輸出信號。 因爲OTP的情況不需要拭除，所以可在列方向共同連 接字元線WL201~WL2 0m。例如，字元線WL201和記憶胞 元 M211-0~ M21n— 0、M211 — 7~ M21n — 7 全部共同連 接。對於字元線WL20m亦一樣。 行解碼器2300- 1 ~2 300— η亦和列解碼器一樣，各自 由位址解碼器2301、反相器2302以及位準挪移電路2303 所構成。位準挪移電路2303將從行解碼器2300 — 1〜2300 -η所輸出之行選擇信號變換成第2信號電壓VP202。 此位準挪移電路2303的輸出各自成爲信號COL2 01~ COL20n «各自輸入行選擇電晶體 CG201 — 0〜CG201 — 7.....CG2 0n-0~ CG20n-7的閘極。例如，行解碼器2300 -1的輸出成爲行選擇電晶體CG2 01— 0~ CG2 01— 7的閘 極輸入信號。 記憶胞元的汲極所連接之位元線BIT201— 0~BIT201 一7經由行選擇電晶體CG201— 0〜CG201 — 7,各自和資料 輸入線 D200〜D207連接。一樣地，位元線 BIT20n~ 0~BIT20n — 7經由行選擇電晶體CG20n — 0~ CG20n~ 7，各 自和資料輸入線D200-D207連接。 在資料輸入線D200〜D207連接用以接受寫入輸入資料 Din200~Din207並輸出寫入資料（例如，寫入電壓5V)的資 -144- 201010062 料變換電路2400、及用以接受讀出時之記憶胞元的資料並 將信號放大輸出的感測放大電路2500 — 0~2500 — 7。 其次，說明動作。 在寫入時’例如若選擇列解碼器2200 — 1及行解碼器 2300 - 1’則選擇字元線WL201及信號COL201，各個被施 加6V(第1信號電壓VP201)及8V(第2信號電壓VP202)的 電壓。又，此時，對應於寫入資料Din200~Din207，自資 料變換電路2400向資料輸入線D200~D207輸出5 V(第3 ❹ 信號電壓VP203 )。 在此’作爲寫入資料，假設輸入「Din200 = Din202 = Din204=Din206= “0” （寫入資料）」、「Din201=Din203= Din205 = Din207=“l”（不寫入資料）」。 在此情況，在資料輸出入線D2 00〜D207，輸出 「D200 = D202 = D204 = D206 = 5 V」、「D 2 0 1 = D 2 0 3 =D 2 0 5 = D207 = 0V」，因爲信號COL2 01被選擇而變成8V，所以位 元線 BIT201-0、BIT201— 2、BIT201-4、BIT201-6 變 〇 成 5V，位元線 BIT201—卜 BIT201— 3、BIT201- 5、BIT201 _7 變成 0V，對記憶胞元 M211— 0、M211— 2、M211— 4、 M211— 6進行寫入，對記憶胞元M211 - 1、M211— 3、M211 -5、M2 11— 7不進行寫入。如此，可對任意的記憶胞元寫 入任意的資料。 讀出時，因爲若所選擇的記憶胞元是拭除狀態 (“ 1” ；導通），電流流向記憶胞元，若是寫入狀態（“ 0” ； 不導通），電流不流動，所以利用感測放大電路2500判定 之，並輸出資料Dout200~Dout207 » -145- 201010062 如此，在第18實施形態所示之非揮發性半導體記憶裝 置的構成，如第30圖所示，OTP構成記憶胞元，配置成由 將此記憶胞元在行方向進行8分割，並在行方向具有！！位 元之寬度的8個記憶胞元方塊所構成。 而且，沿著列方向利用位元線BIT201-〇~BIT20n— 7 共同連接各記憶胞元之電晶體的汲極，利用各列所設置的 字元線 WL201〜WL20m，各自沿著行方向共同連接各列之 記憶胞元之電晶體的控制閘極CG200。又，利用源極S201 共同連接構成記憶胞元陣列之各記憶胞元之電晶體的源 極，此源極S201和GND( “ 0” V)連接。 在各列所設置之列解碼器2200 — l~2200-m接受位址 信號，並產生選擇記憶胞元的列選擇信號，同時將該列選 擇信號變換成第1信號電壓 VP201，並施加於字元線 WL20 l~WL20m ° 行解碼器2300 — 1 ~2300 — η是對應於在記憶胞元方塊 之行方向的位元數η所設置之η個行解碼器，輸出從各記 憶胞元方塊選擇1個記憶胞元的行選擇信號。第2位準挪 移電路23 03將從行解碼器所輸出之行選擇信號變換成第2 信號電壓VP202的信號並輸出。 又，在各記憶胞元方塊，設置η位元單位的行選擇電 晶體（CG201- 0 〜CG20n - 0.....CG201— 7 〜CG20n - 7)， 此行選擇電晶體將從第2位準挪移電路所輸出之行選擇信 號VP202作爲閘極輸入，對各記憶胞元方塊選擇1個記憶 胞元的位元線，而選擇合計8位元單位的.記憶胞元。 由此行選擇電晶體所選擇的記憶胞元，經由該行選擇 -146- 201010062 電晶體而和資料輸出入線D200~D207連接。又，資料變換 電路2400在接受1位元組單位之寫入資料的輸入信號 Din2 00~Din207,並進行資料的寫入時，輸出透過資料輸出 入線D2 0 0〜D2 07而施加於記憶胞元之電晶體之汲極的第3 信號電壓VP203。又，感測放大器2500- 0-2500 — 7將資 料輸出入線D200-D207所讀出之記憶胞元的資料放大並向 外部輸出。 利用這種構成，使用本發明的非揮發性半導體記憶元 Ο件，可構成OTP。 [第19實施形態] 第31圖係表示本發明之第19實施形態的非揮發性半 導體記憶裝置的構成圖。第27A圖所示的例子是MTP的例 子。 第31圖所示之非揮發性半導體記憶裝置和第30圖所 示之非揮發性半導體記憶裝置在構成上的相異點是改良列 解碼器2200— l~2 200-m。又，爲了以字元單位進行拭除， 〇 在對各列共同連接記憶胞元的源極，利用共用源極 S2 0 1〜S 20m對各列共用源極上相異。其他的構成和第30 圖所示的非揮發性半導體記憶裝置一樣。因而，對相同的 構成部分附加相同的符號。 第 32A圖係表示第 31圖所示之列解碼器2200 — 1〜2 200— m的構成圖。第32B圖係用以說明第31圖所示之 列解碼器的圖。 在第32A圖所示的列解碼器2200，輸入用以控制此列 解碼器2200之動作模式的控'制信號E201及E202。 -147- 201010062 又，在此列解碼器2200，符號2221是接受位址並被 選擇的NAND電路，符號2222是將NAND電路2221的輸 出反相的反相器，符號2223是將控制信號E202反相的反 相器，符號2224、2225是傳輸開關，符號2226是反相器， 符號2227是位準挪移電路，符號2228是NOR電路。 第33圖係表示用以說明第32A圖所示之列解碼器之 動作的動作表。Further, when the charge is stored in the floating gate (at the time of writing), the voltage "6" V of the control gate CG200 shown in Fig. 26 corresponds to the first height applied to the gate of the first transistor. The voltage, the voltage "5" V of the drain D2 00 corresponds to the second voltage applied to the drain D200 described above. Further, the voltage "8" V of the drain D200 shown in Fig. 26B corresponds to the third voltage applied to the drain D200 in the first erasing portion, and the voltage "2" of the source S200 is V - 141 - 201010062. This corresponds to the fourth voltage applied to the source s 200 as described above. Further, the voltage "1" V of the control gate CG200 shown in Fig. 26B corresponds to the fifth voltage applied to the control gate CG2 00 by the second erasing portion. On the other hand, in the first direction on the surface of the semiconductor substrate (upward and downward direction in FIG. 25A), a transistor forming portion 2003 in which a transistor is formed is disposed, and the transistor forming portion 203 is sequentially arranged from above to become a transistor T2. The first In-type diffusion layer 2 005 of the drain of 01, the gate region portion 2004 where the channel is formed (the region between the first diffusion layer 2005 and the second diffusion layer 2006), and the second η which is the source of the transistor T201 Type diffusion layer 2006. On the left side of the transistor forming portion 2003, the metal wiring 20 12 is disposed in the vertical direction. The metal wiring 2012 is disposed in parallel with the transistor forming portion 2003 from a predetermined distance of the surface of the semiconductor substrate, and the metal wiring 2012 is connected to the drain (the first in-type diffusion layer 2005) of the transistor 201 by the contact 2010. On the left side of the transistor forming portion 2003, a square n-type well 2002 is formed in the left-right direction with a predetermined width and depth. The square floating gate 20 0 9 is disposed to face the surface of the semiconductor substrate in the left-right direction while being disposed such that the region on the left end side thereof faces the surface of the n-type well 2002, and the region on the right end side and the region of the transistor Τ 201 The gate region portion 2004 (the channel formation region between the first In-type diffusion layer 2005 and the second n-type diffusion layer 2006) faces each other. On the left side of the n-type well 2002, a p-type diffusion layer 2015 is formed in the left-right direction adjacent to the left side of the region opposite to the floating gate 2009 of the n-type well 2002, and has a predetermined width and depth. The p-type diffusion layer 20 15 and the control gate wiring 20 1 9 are connected by a contact 20 16 . The control gate - 142 - 201010062 is connected to the floating gate electrode 2009 in the left-right direction from the surface of the semiconductor substrate via a predetermined distance, and is connected to the P-type diffusion layer 2015 by the contact 2016. The second metal wiring 2013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 2006 serving as the source of the transistor T201. The second metal interconnection 2013 uses the contact point 2011 and the second. The type diffusion layer 2006 is connected. With this configuration, non-volatile memory can be realized in a CMOS process of standard logic elements, and OTP or MTP can be realized at the same time. Further, it is possible to closely arrange a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate) to minimize the area. Further, in the seventeenth embodiment shown in FIGS. 25A to 25D, the metal wiring 2012 is disposed on the left side of the transistor forming portion 2003, but may be disposed directly above or on the right side. [Embodiment 18] Fig. 30 is a view showing the configuration of a nonvolatile semiconductor memory device according to an eighteenth embodiment of the present invention. The example shown in Fig. 30 is an example in which the 〇 nonvolatile semiconductor memory device (memory cell) of the present invention is incorporated in an array (memory cell array), and is an example of an OTP. In the example shown in FIG. 30, as a configuration of the memory array, the input/output I/O is composed of octets of I/O — 0 to I/O — 7 , and the memory array is n bits in the row direction. The memory cell block 2100 - 0~2100 - 7 is arranged in units of m bits in the column direction. That is, the memory cells, like M211-0~M21n-0, M211-7~M21n-7, are concentrated in the row direction by n-bit address units, and are formed to the memory cell block 2100 - 0~2 10 0 — 7. In addition, the sources of the memory cells are all connected in common. The -143-201010062 column decoders 2200-1 to 2200-m are each composed of an address decoder 2201, an inverter 2202, and a level shift circuit 2203. The level shifting circuit 2203 converts the column selection signal output from the column decoders 2200-1 to 2200-m into the first signal voltage VP201. The outputs of the level shift circuit 2203 are output signals of the word lines WL201 to WL20m, respectively. Since the OTP case does not need to be erased, the word lines WL201 to WL2 0m can be commonly connected in the column direction. For example, the word line WL201 and the memory cells M211-0~M21n-0, M211-7~ M21n-7 are all connected in common. The same is true for the word line WL20m. The row decoders 2300-1 to 2300-n are also constituted by the address decoder 2301, the inverter 2302, and the level shift circuit 2303, similarly to the column decoder. The level shift circuit 2303 converts the row selection signal output from the row decoders 2300-1 to 2300-n into the second signal voltage VP202. The outputs of the level shifting circuit 2303 are each a signal COL2 01~ COL20n « respective input row selection transistors CG201 - 0 to CG201 - 7.. CG2 0n-0~ CG20n-7 gates. For example, the output of row decoder 2300-1 becomes the gate input signal of row select transistors CG2 01-0~ CG2 01-7. The bit lines BIT201_0~BIT201-7 connected to the drain of the memory cell are connected to the data input lines D200 to D207 via the row selection transistors CG201-0~CG201-7. Similarly, the bit lines BIT20n~0~BIT20n-7 are connected to the data input lines D200-D207 via the row selection transistors CG20n - 0~ CG20n~7. The data input line D200 to D207 are connected to receive the input data Din200 to Din207 and output the write data (for example, the write voltage of 5V) - the material conversion circuit 2400, and the read-out device The data of the memory cell is amplified and the signal is amplified and outputted by a sense amplifier circuit 2500 - 0~2500-7. Next, explain the action. At the time of writing, for example, if the column decoder 2200-1 and the row decoder 2300-1 are selected, the word line WL201 and the signal COL201 are selected, and 6V (first signal voltage VP201) and 8V (second signal voltage) are applied to each. VP202) voltage. Further, at this time, the self-material conversion circuit 2400 outputs 5 V (the third 信号 signal voltage VP203) to the data input lines D200 to D207 in accordance with the write data Din200 to Din207. Here, as the write data, assume that "Din200 = Din202 = Din204 = Din206 = "0" (write data)", "Din201 = Din203 = Din205 = Din207 = "l" (no data is written)". In this case, at the data input lines D2 00 to D207, the output "D200 = D202 = D204 = D206 = 5 V", "D 2 0 1 = D 2 0 3 = D 2 0 5 = D207 = 0V" because the signal COL2 01 is selected to become 8V, so bit lines BIT201-0, BIT201-2, BIT201-4, BIT201-6 become 5V, bit lines BIT201-b BIT201-3, BIT201-5, BIT201_7 become 0V The memory cells M211-0, M211-2, M211-4, and M211-6 are written, and the memory cells M211-1, M211-3, M211-5, and M2 11-7 are not written. In this way, any data can be written to any memory cell. When reading, because if the selected memory cell is in the erase state ("1"; conduction), the current flows to the memory cell. If the write state ("0"; no conduction), the current does not flow, so the sense of use The measurement and amplification circuit 2500 determines and outputs the data Dout200 to Dout207 » -145- 201010062. In the configuration of the nonvolatile semiconductor memory device shown in the eighteenth embodiment, as shown in FIG. 30, the OTP constitutes a memory cell. Configured to divide this memory cell by 8 in the row direction and in the row direction! ! The eight memory cell blocks of the width of the bit are formed. Further, the drains of the transistors of the memory cells are commonly connected in the column direction by the bit lines BIT201-〇~BIT20n-7, and the word lines WL201 to WL20m provided in the respective columns are commonly connected in the row direction. The control gate CG200 of the transistor of each column of memory cells. Further, the source S201 is commonly connected to the source of the transistor constituting each of the memory cells of the memory cell array, and the source S201 is connected to GND ("0" V). The column decoders 2200 - 1 to 2200-m arranged in the respective columns receive the address signals, and generate column selection signals for selecting the memory cells, and simultaneously convert the column selection signals into the first signal voltage VP201 and apply them to the words. WL20 l~WL20m ° line decoder 2300 — 1 ~ 2300 — η is η row decoders corresponding to the number of bits η in the row direction of the memory cell block, and the output is selected from each memory cell block A row selection signal for one memory cell. The second-order shift circuit 23 03 converts the row select signal output from the row decoder into a signal of the second signal voltage VP202 and outputs it. Further, in each memory cell block, a row selection transistor (CG201-0 to CG20n - 0.....CG201-7 to CG20n-7) of η bit units is provided, and the row selection transistor will be from the second The row selection signal VP202 outputted by the level shifting circuit is used as a gate input, and a bit line of one memory cell is selected for each memory cell block, and a memory cell of a total of 8 bit units is selected. The memory cell selected by the transistor is selected by this row, and the -146-201010062 transistor is selected via the row to be connected to the data input and output lines D200 to D207. Further, when the data conversion circuit 2400 receives the input signals Din2 00 to Din 207 of the data to be written in one byte unit and writes the data, the data is input to the memory cells by the output data input lines D2 0 0 to D2 07. The third signal voltage VP203 of the drain of the transistor. Further, the sense amplifiers 2500 - 0 - 2500 - 7 amplify the data of the memory cells read by the data input lines D200 - D207 and output them to the outside. With such a configuration, the OTP can be constructed by using the nonvolatile semiconductor memory element of the present invention. [19th embodiment] Fig. 31 is a view showing the configuration of a nonvolatile semiconductor memory device according to a 19th embodiment of the present invention. The example shown in Fig. 27A is an example of MTP. The difference between the nonvolatile semiconductor memory device shown in Fig. 31 and the nonvolatile semiconductor memory device shown in Fig. 30 is the improved column decoder 2200 - 1 to 2 200 - m. Further, in order to perform erasing in units of characters, 源 the source of the memory cell is connected to each column in common, and the common source S2 0 1 to S 20m is different for the common source of each column. The other construction is the same as the non-volatile semiconductor memory device shown in Fig. 30. Therefore, the same components are attached to the same components. Fig. 32A is a view showing the configuration of the column decoders 2200 - 1 to 2 200 - m shown in Fig. 31. Fig. 32B is a view for explaining the column decoder shown in Fig. 31. In the column decoder 2200 shown in Fig. 32A, control signals E201 and E202 for controlling the operation mode of the column decoder 2200 are input. Further, in this column decoder 2200, the symbol 2221 is a NAND circuit that accepts an address and is selected, the symbol 2222 is an inverter that inverts the output of the NAND circuit 2221, and the symbol 2223 is a reverse control signal E202. The phase inverters, symbols 2224, 2225 are transmission switches, symbol 2226 is an inverter, symbol 2227 is a level shifting circuit, and symbol 2228 is a NOR circuit. Fig. 33 is a flowchart showing the operation of the column decoder shown in Fig. 32A.
例如，說明選擇第31圖所示之行解碼器2300 - 1 (即選 擇COL201)，及選擇列解碼器2200 - 1的情況。在此情況， 選擇記憶胞元M211— 0~M2 11— 7。 首先，說明寫入（寫入模式）的情況。在此情況，在第 33圖所示的動作表，在寫入的情況，控制信號E2 01及E202 變成「E201=E202= " 0”」。在已選擇位址解碼器的情況， 因爲NAND電路2221的輸出爲“0” 、反相器2222的輸出 爲“ 1” 、E202爲“ 0” ，所以傳輸開關2224變成導通， 傳輸開關2225變成不導通，反相器2226的輸出爲“ 0” ，For example, a case will be described in which the row decoder 2300-1 shown in Fig. 31 is selected (i.e., COL201 is selected) and the column decoder 2200-1 is selected. In this case, the memory cells M211-0~M2 11-7 are selected. First, the case of writing (write mode) will be described. In this case, in the operation table shown in Fig. 33, in the case of writing, the control signals E2 01 and E202 become "E201 = E202 = " 0"". In the case where the address decoder has been selected, since the output of the NAND circuit 2221 is "0", the output of the inverter 2222 is "1", and E202 is "0", the transfer switch 2224 becomes conductive, and the transfer switch 2225 becomes Turned on, the output of the inverter 2226 is "0",
位準挪移電路2227的輸出，即字元線WL201的信號變成 第1信號電壓VP201(5V)。 另一方面，因爲控制信號E201爲“ 0” ，所以NOR電 路222 8的輸出信號SB201變成“1” ，記憶胞元的源極 S201 變成 0V ° 因爲對在此狀態所選擇之記憶胞元的汲極 D200(D200~D207)施加5V，所以記憶胞元發生寫入。和非 選擇解碼器2200- m連接的非選擇記憶胞元，因爲字元線 WL20m爲0V、源極S20m爲開路（open)，所以未發生寫入。 -148- 201010062 其次，說明拭除2_1的步驟（第1拭除模式） 在拭除2— 1的步驟，將控制信號E201及E2 02設爲 「E201=E2 02=“1”」。選擇位址解碼器時，因爲 N AND 電路222 1的輸出爲“ 0” 、控制信號E202爲“ 1” ，所以 傳輸開關2224變成不導通，傳輸開關2225變成導通，反 相器2226的輸出變成“1” ，位準挪移電路2 227的輸出， 即字元線WL201的輸出變成0V。又，因爲「E201=“l”」， 所以NOR電路2228的輸出一定變成“0”，而源極線S20m Ο 變成開路。因爲在此狀態汲極D200變成8V，所以將記憶 胞元進行拭除。 另一方面，關於和非選擇列連接的非選擇胞元，因爲 NAND電路2221的輸出爲“ 1” ，所以字元線WL20m變成 例如3V，源極線S20m之往開關用電晶體SB20m的信號爲 0V，而源極線S20m亦變成開路。雖然汲極D200是8V， 但是因爲施加於字元線WL20m的閘極電壓髙達3V，所以 緩和汲極一閘極之間的電場，而不會發生拭除。因而，僅 〇 拭除所選擇的列。 其次，說明拭除2— 2的步驟（第2拭除模式） 在拭除2-2之步驟的情況，將控制信號E201及E202 設爲「E201= “ 0” 、E202= “ 1”」。因爲控制信號E202 爲“1” ，所以位址解碼器的輸出被反相，而字元線WL201 變成0V。又，因爲控制信號E201爲“ 0” ，所以NOR電 路2228接受NAND電路222 1的輸出“0”，而源極線S201 之往開關用電晶體 SB201 的信號變成 “ 1”（SB20 1= “ 1”），即源極線S201變成0V，所選擇之 -149- 201010062 記憶胞元自收歛。 另一方面，非選擇解碼器2221的輸出被反相，而字元 線WL20m變成例如3V，源極SB20m變成0V，源極S20m 變成開路，不會發生自收歛。 在讀出的情況，因爲控制信號E201及E202變成 E201=E202= “0” ，所以對所選擇之字元線 WL201施加 3V，對汲極D2 00施加IV，根據記憶胞元的資料，而讀出 "1，’ 或 “ 0，， 。 如此，第19實施形態所示的非揮發性半導體記憶裝 置，如第31圖所示，以MTP構成記憶胞元，並配置成由 在行方向將此記憶胞元進行8分割，並在行方向具有8位 元寬度之8個記憶胞元方塊所構成。 又，沿著列方向利用位元線BIT201— 0~BIT20n-7共 同連接各記憶胞元之電晶體的汲極，利用在各列所設置之 字元線WL201〜WL20m，各自沿著行方向共同連接各列之 記憶胞元之電晶體的控制閘極CG200。 又，利用在各列所設置之源極線S2 01〜S 20m，沿著行 方向共同連接各列之記憶胞元之電晶體的源極。在此源極 線之各條，設置用以選擇使該源極線接地成GND( “ 0” V) 或變成開路的開關用電晶體SB201〜SB20m。 在各列所設置之列解碼器2200 — 1 -2200 - m接受位址 信號，並產生選擇記憶胞元的列選擇信號，因應於寫入及 拭除模式（拭除2—1和拭除2— 2)，選擇該列選擇信號的位 準，並施加於字元線 WL201〜WL20m，同時輸出用以控制 開關用電晶體SB201~SB20m開閉的控制信號。 -150- 201010062 行解碼器2300- 1~2300 - η是對應於在記憶胞元方塊 之行方向的位元數η所設置之η個行解碼器，輸出從各記 憶胞元方塊選擇1個記憶胞元的行選擇信號。第2位準挪 移電路2303將從行解碼器所輸出之行選擇信號變換成第2 信號電壓VP202的信號並輸出。 又，在各記憶胞元方塊’設置η位元單位的行選擇電 晶體（CG201— 0~ CG20n — 0、…、CG201— 7~ CG20n — 7)， 此行選擇電晶體將從第2位準挪移電路所輸出之行選擇信 © 號（第2信號電壓VP202)作爲閘極輸入，對各記憶胞元方 塊選擇1個記憶胞元的位元線，而選擇合計8位元單位的 記憶胞元。 由此行選擇電晶體所選擇的記憶胞元，經由該行選擇 電晶體而和資料輸出入線D20 0〜D207連接。又，資料變換 電路2400在接受1位元組單位之寫入資料的輸入信號 Din2 0 0~Din2 07,並進行資料的寫入或資料的拭除時，輸出 透過資料輸出入線D2 00-D2 07而施加於記憶胞元之電晶體 〇 之汲極的第3信號電壓VP203 »又，感測放大器2500 -0~2 500 — 7將資料輸出入線D2 00-D2 07所讀出之記憶胞元 的資料放大並向外部輸出。 利用這種構成’使用本發明的非揮發性半導體記憶元 件，可構成MTP。 [第20實施形態] 第34圖係表示本發明之第20實施形態的非揮發性半 導體記億裝置的構成圖，是MTP的例子。 在第34圖所示的第20實施形態，因爲以8位元單位 -151- 201010062 進行改寫，所以爲了使布置的配置變成更佳，而以將記憶 胞元陣列在行方向以8位元單位進行分割的記億胞元方塊 2101— 1~2101— η構成。例如，記憶胞元方塊2101-1由 在行方向8位元、在列方向m位元的記憶胞元M2 1 1 -0~M211-7.....M2ml - 0~M2ml - 7 所構成。 又，爲了以字元單位進行拭除，和第31圖所示的非揮 發性半導體記憶裝置一樣，對各列共同連接記憶胞元的源 極，至共用源極線S201- S2 0m爲止一樣地進行共用化，列 解碼器亦和第32A圖所示的列解碼器2200 —樣。 如此，在第20實施形態所示的非揮發性半導體記憶裝 置，如第34圖所示，以MTP構成記憶胞元，並配置成由 將記憶胞元對各列在行方向以8位元單位被進行行選擇之 8位元單位的記憶胞元方塊所構成。 又，沿著列方向利用位元線BIT201 — 0〜ΒΙΤ20Π — 7共 同連接各記憶胞元之電晶體的汲極，利用在各列所設置之 字元線 WL201〜WL20m，各自沿著行方向共同連接各列之 記憶胞元之電晶體的控制閘極CG200。 又，利用在各列所設置之源極線S201〜S20m，沿著行 方向共同連接各列之記憶胞元之電晶體的源極。在此源極 線之各條，設置用以選擇使該源極線接地成GND( “ 0” V) 或變成開路的開關用電晶體2209 — l~2209-m。 在各列所設置之列解碼器2200 — 1-2200 - m接受位址 信號，並產生選擇記憶胞元的列選擇信號，因應於寫入模 式及拭除模式，而選擇該列選擇信號的電壓位準，並施加 於字元線 WL201〜WL20m，同時輸出用以控制開關用電晶 -152- 201010062 體2209 — 1~2209 — m開閉的控制信號SB201〜SB20m。 行解碼器2300 - 1~2300 - η是在各記憶胞元方塊2101 -1〜2101— η所設置之行解碼器，在行方向以8位元單位 選擇1個記憶胞元方塊。第2位準挪移電路2303將從行解 碼器所輸出之行選擇信號變換成第2信號電壓VP2 02的信 號並輸出。 又，在各記憶胞元方塊，設置8位元單位的行選擇電 晶體（CG201- 0〜CG201- 7、CG2 0n - 0~ CG20n - 7)，此行 Ο 選擇電晶體將從第2位準挪移電路所輸出之行選擇信號 COL201〜COL20n(第2信號電壓VP202)作爲閘極輸入，選 擇1個記憶胞元方塊的位元線，而選擇8位元單位的記憶 胞元。 由此行選擇電晶體所選擇之記憶胞元方塊的位元線， 經由該行選擇電晶體而和資料輸出入線D200-D 207連接。 又，資料變換電路2400在接受1位元組單位之寫入資料的 輸入信號Din200〜Din207，並進行資料的寫入及資料的拭 〇 除時，輸出透過資料輸出入線D200〜D207而施加於記憶胞 元之電晶體之汲極的第3信號電壓VP203。又，感測放大 器2500 - 0-2500-7將資料輸出入線D200~D 207所讀出之 記憶胞元的資料放大並向外部輸出。 因而，使用本發明的非揮發性半導體記憶元件，可構 成MTP ’同時可將記憶胞元陣列在行方向以8位元單位進 行分割，並以8位元單位進行資料的寫入及讀出。 [第21實施形態] 第3 5圖係表示本發明之第2 1實施形態的非揮發性半 -153- 201010062 導體記憶裝置的構成圖。第35圖所示的例子，在第34圖 所示的非揮發性半導體記憶裝置，係作成每2列共用源極 線。依此方式，在布置上，無浪費的空區域。 在第36圖表示列解碼器的電路。此第36圖所示的列 解碼器2200A，相對於第32A圖所示的列解碼器2200，追 加控制信號E203B，又將第3 2A圖所示的反相器2226變更 成反相器2226A，並輸入控制信號E203B。 第37圖表示第36圖所示之列解碼器的動作表。第37 圖所示之動作表和第33圖所示之動作表的相異點是非選 擇胞元之拭除2— 2的步驟。以粗框包圍注目處。 在第32A圖所示之列解碼器的電路，在拭除2 - 2的步 驟時，非選擇的字元線WL202變成3V，源極S200變成開 路，而作成第3 5圖所示之記憶胞元陣列的構成時，源極線 S200(l、2)變成共用，因爲成爲在動作表的信號SB201、 SB202，所以信號SB202變成“0” ，電晶體2209— 2變成 不導通，但是因爲信號SB201爲“ 1” ，所以電晶體2209 一 1變成導通。 因此，施加於共用之源極線S200(l、2)的信號SB201、 SB202變成0V，字元線WL202是3V時，和字元線WL202 連的記憶胞元就變成導通。爲了避免之’而設置控制信號 E2 03B，若設定成在拭除2-2時變成“〇” ，則NAND電 路2206的輸出變成“ 1” ，即使2201之解碼器輸出是非選 擇，位準挪移電路2207之往字元線WL202的輸出信號變 成0V，而，非選擇之記億胞元的電流不流動° 在此，在此狀態，在拭除2- 2的步驟’即自收歛動作 -154- 201010062 時，在和所選擇之字元線WL2 0 1連接的記憶胞元、及和相 鄰之字元線WL202連接的非選擇記憶胞元，同時，自收歛 的電壓，即汲極變成5V，閘極變成0V，源極變成0V，在 被拭除的胞元發生自收歛。若和字元線WL2 02連接的記憶 胞元在之前之狀態曾發生自收歛時，在此，因爲發生第2 次的自收歛動作，所以變成2次自收歛。 可是，若看第28A圖所示之自收歛動作的特徵，因爲 自收歛的極限是收歛至起始値，所以即使過度地施加自收 Ο 歛動作亦無問題。 如此，在第21實施形態所示的非揮發性半導體記憶裝 置，如第3 5圖所示，以MTP構成記憶胞元，並配置成由 將記憶胞元對各列在行方向以1位元組單位被進行行選擇 .之8位元單位的記憶胞元方塊所構成。 又，沿著列方向利用位元線BIT201 - 0〜BIT20n- 7共 同連接各記憶胞元之電晶體的汲極，利用在各列所設置之 字元線WL201〜WL20m，各自沿著行方向共同連接各列之 ❹ 記憶胞元之電晶體的控制閘極CG200。 又，利用每2列所設置之源極線S200(l、2)~S200(m —1、m)，沿著行方向共同連接2列之記憶胞元之電晶體的 源極。在此源極線，共同連接：第1開關用電晶體（例如開 關用電晶體2209 — 1)，係接受來自其中一列的開閉信號（例 如信號SB201)，並選擇使源極線接地成GND( “0” V)或變 成開路；及第2開關用電晶體（例如開關用電晶體2209 -2)，係接受來自另一列的開閉信號（例如信號SB202)，並選 擇使源極線接地成GND( “0” V)或變成開路。 -155- 201010062 又，在各列所設置之列解碼器2200 - 1〜2200— m接受 位址信號，並產生選擇該記憶胞元的列選擇信號，因應於 寫入模式及拭除模式，而選擇該列選擇信號的電壓位準， 並施加於字元線 WL201~WL20m。又，列解碼器 2200 — 1〜2200 — m每2個構成對，從一方的列解碼器（例如2200 一 1)輸出使第1開關用電晶體（例如開關用電晶體2209 - 1 ) 開閉信號（例如信號SB201)。又，從另一方的列解碼器（例 如2200 — 2)輸出使第2開關用電晶體（例如開關用電晶體 2209 - 2)開閉信號（例如信號88202)。 行解碼器2300 — 1~2300 — n(參照第34圖）在各|己憶胞 元方塊2101— 1〜2101-n所設置之行解碼器，在行方向以 8位元單位選擇1個記憶胞元方塊。第2位準挪移電路23 0 3 將從行解碼器所輸出之行選擇信號變換成第2信號電壓 VP202的信號並輸出。 又，在各記憶胞元方塊，設置8位元單位的行選擇電 晶體（CG201-0〜CG201-7.....CG20n-0〜CG20n-7)， 此行選擇電晶體將從第2位準挪移電路所輸出之行選擇信 號（第2信號電壓VP 202)作爲閘極輸入，選擇1個記憶胞 元方塊之記憶胞元的位元線，而選擇8位元單位的記憶胞 元。 由此行選擇電晶體所選擇之記憶胞元方塊的位元線， 經由該行選擇電晶體而和資料輸出入線D200〜D207連接。 又，資料變換電路2400在接受1位元組單位之寫入資料的 輸入信號Din200~Din207，並進行資料的寫入及資料的拭 除時，輸出透過資料輸出入線D200-D207而施加於記憶胞 -156- 201010062 元之電晶體之汲極的第3信號電壓VP203。又，感測放大 器2500 — 0-2500 — 7將資料輸出入線D200~D207所讀出之 記憶胞元的資料放大並向外部輸出。 因而，使用本發明的非揮發性半導體記憶元件，可構 成MTP，同時每2列共用源極線，在布置上可消除浪費的 空區域。 此外，在第18、第19、第20以及第21實施形態，雖 然說明1位元組單位的寫入、拭除動作，但是未限定爲1 G位元組單位。 例如，將未圖示之行解碼器一起選擇信號輸入行解碼 器2300，若設定作同時選擇行解碼器2300 — 1〜2 300-n， 可同時寫入或拭除和一條字元線連接之例如 Mill-0〜Ml 1 1— 7 (nX8個）之記憶胞元的全部。因而，可進行所謂 的以頁單位之寫入、拭除。 又，記憶陣列（記憶胞元方塊）之構成，在第3 0圖、第 31圖所示的例子，以行位址單位（η位元）集中地配置，而 ❹ 在第34圖、第35圖所示的例子，採用以I/O位元數的單 位（在此爲1位元組單位）集中之構成。 亦考慮布置上配置的方便，而判斷採用哪一種方式。 此外，在第34圖、第35圖所示的例子，雖然作爲輸 出入I/O單位，採用1位元組單位（8位元），但是即使是以 字元單位（16位元）或雙字元單位（32位元）、或更大之I/O 位元數構成，主旨及效果亦一樣。 [第22實施形態] 第38圖係表示本發明之第22實施形態的非揮發性半 -157- 201010062 導體記憶裝置的構成圖。第38圖所示的例子是表示第30 圖所示之OTP之記憶胞元之布置配置的例子。即，是將第 25 A圖〜第2 5D圖所示的記憶胞元配置成陣列。 在第 3 8 圖，利用金屬配線使字元線（控制閘 極）WL201、WL202、WL203、…在圖面上的左右方向（橫向） 通過，使源極線S201、S202在左右方向通過，使位元線 BIT201、BIT202、BIT 2 0 3、…在圖面上的上下方向（縱向） 通過，在上下左右將25 A圖~第25D圖所示的非揮發性半 導體記憶體（記憶胞元）配置成對稱型，彼此共用η型井， 以縮小面積。依此方式，消除浪費的空空間，而作成效率 佳的配置。在特性上、面積上都成爲最佳的配置。此布置 亦可應用於第35圖所示之源極共用型的非揮發性半導體 記憶裝置。 如此，在第22實施形態所示的非揮發性半導體記憶裝 置，作爲記憶胞元，將25八圖~第25D圖所示的非揮發性 半導體記憶元件（記憶胞元）用作ΟΤΡ。 而，例如著眼於在第38圖以虛線所包圍之部分Α2000 的記憶胞元（由字元線WL201和位元線ΒΙΤ202所選擇的記 憶胞元），說明以此布置所配置的記憶胞元時，在圖上之上 下方向所配置的電晶體形成部2003，包含有：成爲電晶體 之汲極的第In型擴散層2005、形成電晶體之通道的閘極 區域部（第1擴散層2005和第2擴散層2006之中間的區 域）、以及成爲電晶體之源極的第2n型擴散層2006。 在此電晶體形成部200 3的左側，在上下方向配置第1 金屬配線2012。此金屬配線2012從半導體基板表面隔著 -158- 201010062 既定之距離配置成和電晶體形成部1 03 0平行，又，金屬配 線2012利用接點和電晶體的汲極（第In型擴散層2005)連 接。此第1金屬配線2012和位元線BIT202連接。 在電晶體形成部1 03 0的左側，以既定之寬度和深度在 左右方向所形成方形的η型井2002。方形的浮動閘極2009 在左右方向配置成和半導體基板表面相對向，同時配置成 其左端部側的區域和η型井2002的表面相對向，且右端部 側的區域和閘極區域部（第In型擴散層2005和第2η型擴 〇 散層2006之中間的通道形成區域）相對向。 在η型井2002的左側，在左右方向形成ρ型擴散層 2015，其和與此η型井2002的浮動閘極2009相對向之區 域的左側相鄰，並具有既定之寬度和深度。此Ρ型擴散層 2015和控制閘極配線2019利用接點連接。此控制閘極配 線2019從半導體基板表面隔著既定之距離在左右方向配 置成和浮動閘極2009相對向，又，利用接點和ρ型擴散層 2015連接。控制閘極配線2019和共用的字元線WL20 1連 〇接。 第2金屬配線2013從半導體基板表面隔著既定之距離 在左右方向配置成和成爲電晶體Τ2 01之源極的第2η型擴 散層2006相對向，此第2金靥配線2013利用接點和第2η 型擴散層2006連接。此第2金屬配線2013利用接點和第 2η型擴散層2006連接。此第2金屬配線2013和共用的源 極線S201連接。 而，在各記憶胞元的配置，將彼此共用η型井20 02並 左右對稱地配置之2個記憶胞元、及相對於該左右對稱地 -159- 201010062 配置之2個記憶胞元，彼此共用金屬配線2013(源極線 S2 01)並在下方向對稱地配置之2個記憶胞元之合計4個記 憶胞元作爲配置的基本單位，在左右方向平行地排列配 置，同時在上下方向亦平行地排列配置成爲此基本單位的 4個記憶胞元。 因而，可使用本發明的非揮發性半導體記憶元件，構 成OTP，同時在布置上，可消除浪費的空空間。 此外，在第38圖所示的第22實施形態，在記憶胞元（由 位元線BIT202和字元線WL201所選擇的記憶胞元），雖然 Q 金屬配線2012配置於電晶體形成部2003的左側，但是配 置於右側亦一樣，又，亦可配置於正上。其中，在本例， 配置於右側時，因爲記憶胞元尺寸由金屬配線2012的間隔 所決定，所以有記憶胞元尺寸變成稍大的情況。 [第23實施形態] 第3 9A圖及第39B圖係表示本發明之第23實施形態 之非揮發性半導體記憶元件的構成圖。是對第25A圖~第 25D圖所示之第17實施形態的記憶胞元，省略n型井，而 〇 更加發揮面積縮小效果。 第39Α圖表示平面圖，第39Β圖表示沿著Β20—Β20’ 的剖面圖。第39Α圖及第39Β圖所示的記憶胞元和對第25Α 圖〜第25D圖所示之記憶胞元在構成上的相異點，是省略 第25Α圖所示的η型井（n— Well)2，替代地設置第39Β圖 所不之空乏型（Depletion — type)通道注入2021，並將p型 擴散層2015變更成n型擴散層2015’ 。即，第25A圖〜第 25D圖所示之電晶體形成部20 30中之成爲電晶體Τ201之 -160- 201010062 汲極的第In型擴散層2005、形成電晶體之通道的閘 域部（第In型擴散層2 00 5和第2n型擴散層2006之中 區域）以及第2η型擴散層2006的配置是相同，又，關 屬配線2012、2013、控制閘極配線等亦一樣。又’第 圖所示之等價電路亦相同。因而，對相同的構成部分 相同的符號，並省略重複說明。 如此，在第23實施形態所示的記憶胞元，爲了省 型井，而作成在電容器 2014的閘極下進行空 (Depletion — type)通道注入2021，使可高效率地進 合。雖然對標準CMOS製程，需要D型式的通道注入 是因爲是追加注入步驟，對總步驟只是微增，不會成 程之繁雜性的負荷。 此外，在第23實施形態，η型擴散層2005相當 述之成爲電晶體之汲極的第In型擴散層，η型擴散層 相當於上述的第2η型擴散層，η型擴散層20 15’相當 述的第3η型擴散層。又，金屬配線2012相當於上述 Q 1金屬配線，金屬配線2013相當於上述的第2金屬配 而，在半導體基板表面上的第1方向（在圖上爲上 向），配置電晶體形成部2003，此電晶體形成部2003 依序配置：成爲電晶體Τ201之汲極的第In型擴 2005、形成電晶體T2 01之通道的閘極區域部（第1擴 2005和第2擴散層2006之中間的區域）、以及成爲電 T2 01之源極的第2η型擴散層2006。 在此電晶體形成部2003的左側，在上下方向配置 配線2012。此金屬配線2012從半導體基板表面隔 極區 間的 於金 25Β 附加 略η 乏型 行耦 ，但 爲製 於上 2006 於上 的第 線。 下方 由上 散層 散層 曰Η體 金屬 既定 -161- 201010062 之距離配置成和電晶體形成部2003平行，又，金屬配線 2012利用接點和電晶體的汲極（第111型擴散層2005)連接。 又’在電晶體形成部2003的左側，以既定之寬度和深 度在左右方向所形成方形的空乏型（Depletion — type)通道 注入2 021。方形的浮動閘極2009在左右方向配置成和半 導體基板表面相對向，同時配置成其左端部側的區域和通 道注入202 1的表面相對向，而且右端部側的區域和閘極區 域部（第In型擴散層2005和第2n型擴散層2006之中間的 通道形成區域）相對向。 在通道注入202 1的左側，以和此通道注入202 1相鄰 的方式在左右方向形成η型擴散層1015’ ，此η型擴散層 1 0 1 5 ’和控制閘極配線20 1 9利用接點連接。控制閘極配線 2019從半導體基板表面隔著既定之距離在左右方向配置成 和浮動閘極2009相對向，又，利用接點2016和η型擴散 層2015’連接。第2金屬配線2013從半導體基板表面隔 著既定之距離在左右方向配置成和成爲電晶體Τ201之源 極的第2η型擴散層2006相對向，此金屬配線2013利用接 點2011和第2η型擴散層2006連接。 根據這種構成，以標準邏輯元件的CMOS製程可實現 非揮發性記憶體，同時可實現OTP或MTP。又’可緊密地 配置面積變大的電容器（在浮動閘極和半導體基板表面所 形成之電容器）’使面積變成最小限度。此外’對第25 A圖 〜第25D圖所示之記憶胞元，省略η型井’而可更加發揮 面積縮小效果。 此外，在第39Α圖及第39Β圖所示之第23實施形態， -162- 201010062 雖然將金屬配線2012配置於電晶體形成部20030的左側， 但是亦可配置於右側，亦可配置於正上》 [第24實施形態] 第40圖係表示本發明之第24實施形態的非揮發性半 導體記憶裝置的構成圖。第40圖所示的非揮發性半導體記 憶裝置是將第39A圖及第39B圖所示的非揮發性半導體記 憶元件（記憶胞元）配置於陣列上。 和第38圖所示的非揮發性半導體記憶裝置一樣，上下 〇 左右對稱地配置記憶胞元，可將面積縮小省略η型井的份 量。 如此，在第24實施形態所示的非揮發性半導體記憶裝 置，例如著眼於在第40圖以虛線所包圍之部分Α2 000的記 憶胞元（由字元線WL201和位元線ΒΙΤ202所選擇的記憶胞 元），說明記憶胞元時，在圖上之上下方向所配置的電晶體 形成部2003，包含有：成爲電晶體之汲極的第In型擴散 層2005、形成電晶體之通道的閘極區域部（第1擴散層2005 〇 和第2擴散層2006之中間的區域）、以及成爲電晶體之源 極的第2η型擴散層2006。 在此電晶體形成部20 03的左側，將第1金屬配線2012 配置成和電晶體形成部2003平行而且從半導體基板表面 隔著既定之距離。此第1金屬配線2012和位元線ΒΙΤ202 連接。 又，在半導體基板上，在該電晶體形成部2003的左 側，以既定之寬度和深度在左右方向所形成未圖示之空乏 型（depletion— type)通道注入（參照第39Β圖的通道注入 -163- 201010062 2021) 〇 浮動閘極2009在左右方向配置成和半導體基板表面 相對向，同時配置成左端部側的區域和上述之通道注入的 表面相對向，且右端部側的區域和電晶體形成部2003的閘 極區域部（第In型擴散層2005和第2η型擴散層2006之中 間的通道形成區域）相對向。The output of the level shift circuit 2227, that is, the signal of the word line WL201 becomes the first signal voltage VP201 (5V). On the other hand, since the control signal E201 is "0", the output signal SB201 of the NOR circuit 222 8 becomes "1", and the source S201 of the memory cell becomes 0V ° because of the 记忆 of the memory cell selected in this state. The pole D200 (D200~D207) applies 5V, so the memory cell is written. The non-selected memory cells connected to the non-selective decoder 2200-m have no writes because the word line WL20m is 0V and the source S20m is open. -148- 201010062 Next, the procedure for erasing 2_1 (the first erasing mode) will be described. In the step of erasing 2-1, the control signals E201 and E2 02 are set to "E201=E2 02="1"". When the address decoder is selected, since the output of the N AND circuit 222 1 is "0" and the control signal E202 is "1", the transfer switch 2224 becomes non-conductive, the transfer switch 2225 becomes conductive, and the output of the inverter 2226 becomes " 1", the output of the level shifting circuit 2 227, that is, the output of the word line WL201 becomes 0V. Further, since "E201 = "1"", the output of the NOR circuit 2228 must become "0", and the source line S20m Ο becomes an open circuit. Since the bungee D200 becomes 8V in this state, the memory cell is erased. On the other hand, regarding the non-selected cells connected to the non-selected column, since the output of the NAND circuit 2221 is "1", the word line WL20m becomes, for example, 3V, and the signal of the switching transistor SB20m of the source line S20m is 0V, and the source line S20m also becomes an open circuit. Although the drain D200 is 8V, since the gate voltage applied to the word line WL20m reaches 3V, the electric field between the gate and the gate is moderated without erasing. Therefore, only 所 the selected column is erased. Next, the procedure for erasing 2-2 (2nd erasing mode) will be described. In the case of erasing 2-2, control signals E201 and E202 are set to "E201 = "0"" and E202 = "1". Since the control signal E202 is "1", the output of the address decoder is inverted, and the word line WL201 becomes 0V. Further, since the control signal E201 is "0", the NOR circuit 2228 receives the output "0" of the NAND circuit 222 1 and the signal of the source transistor S201 to the switching transistor SB201 becomes "1" (SB20 1 = "1" "), that is, the source line S201 becomes 0V, and the selected -149-201010062 memory cell self-converges. On the other hand, the output of the non-selective decoder 2221 is inverted, and the word line WL20m becomes, for example, 3V, the source SB20m becomes 0V, and the source S20m becomes an open circuit, and self-convergence does not occur. In the case of reading, since the control signals E201 and E202 become E201=E202=“0”, 3V is applied to the selected word line WL201, IV is applied to the drain D2 00, and reading is performed based on the data of the memory cell. Thus, the nonvolatile semiconductor memory device shown in the nineteenth embodiment has a memory cell formed by MTP as shown in FIG. 31, and is arranged to be in the row direction. The memory cell is divided into 8 segments and is composed of 8 memory cell blocks having an 8-bit width in the row direction. Further, the memory cells are connected in common along the column direction by bit lines BIT201-0~BIT20n-7. The drain of the transistor is connected to the control gate CG200 of the transistor of each column of memory cells in the row direction by the word lines WL201 to WL20m provided in the respective columns. The source lines S2 01 to S 20m are arranged to connect the sources of the transistors of the memory cells of the columns in the row direction. The strips of the source lines are arranged to select the source lines to be grounded. GND (“0” V) or open-circuit switch transistor SB201~SB20m The decoder 2200 - 1 - 2200 - m set in each column accepts the address signal and generates a column selection signal for selecting the memory cell, in response to the write and erase modes (erasing 2-1 and erasing 2) 2) Selecting the level of the column selection signal and applying it to the word lines WL201 to WL20m, and simultaneously outputting a control signal for controlling the opening and closing of the switching transistors SB201 to SB20m. -150- 201010062 Row Decoder 2300-1 ~2300 - η is n row decoders corresponding to the number of bits η in the row direction of the memory cell block, and outputs a row selection signal for selecting one memory cell from each memory cell block. The quasi-shift circuit 2303 converts the row selection signal output from the row decoder into a signal of the second signal voltage VP202 and outputs it. Further, a row selection transistor of η-bit units is provided in each memory cell block (CG201-0) ~ CG20n — 0,..., CG201— 7~ CG20n — 7), the row selection transistor will use the row selection signal © (second signal voltage VP202) output from the 2nd quasi-migration circuit as the gate input. Each memory cell block selects a bit of a memory cell Line, and select a memory cell of a total of 8 bit units. The memory cell selected by the transistor is selected by this row, and the transistor is selected via the row to be connected to the data output lines D20 0 to D207. Further, the data conversion circuit 2400 When accepting the input signal Din2 0 0~Din2 07 of the data input in 1-bit unit, and writing data or erasing data, the output is applied to the memory cell through the data input and output line D2 00-D2 07. The third signal voltage VP203 of the transistor of the transistor 又 又 又 感 感 感 感 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 . With such a configuration, the MTP can be constructed by using the nonvolatile semiconductor memory device of the present invention. [Twentyth embodiment] FIG. 34 is a view showing a configuration of a nonvolatile semiconductor device according to a twentieth embodiment of the present invention, and is an example of MTP. In the twentieth embodiment shown in Fig. 34, since the octet unit -151 - 201010062 is rewritten, in order to make the arrangement of the arrangement better, the memory cell array is in the octet unit in the row direction. The segmentation of the billion cell block 2101 - 1 ~ 2101 - η constitutes. For example, the memory cell block 2101-1 is composed of memory cells M2 1 1 -0~M211-7.....M2ml - 0~M2ml - 7 in the row direction of 8 bits in the column direction m bits. . Further, in order to erase in units of characters, as in the nonvolatile semiconductor memory device shown in FIG. 31, the sources of the memory cells are connected to the respective columns, and the source lines S201-S2 0m are the same as the common source lines S201-S2 0m. For the sharing, the column decoder is also the same as the column decoder 2200 shown in Fig. 32A. As described above, in the nonvolatile semiconductor memory device of the twentieth embodiment, as shown in FIG. 34, memory cells are formed by MTP, and are arranged in units of octaves in the row direction by memory cells. It is composed of memory cell blocks of 8-bit units selected for row selection. Further, the drains of the transistors of the memory cells are commonly connected in the column direction by the bit lines BIT201 - 0 to ΒΙΤ 20 Π - 7, and the word lines WL201 WL WL20m provided in the respective columns are used in the row direction. The control gate CG200 of the transistor connecting the memory cells of each column. Further, the source lines of the memory cells of the respective columns are connected in the row direction by the source lines S201 to S20m provided in the respective columns. In each of the source lines, a switching transistor 2209 - 1 to 2209-m for selecting the source line to be grounded to GND ("0" V) or to be open is provided. The column decoders 2200 - 1-2200 - m arranged in the respective columns receive the address signals, and generate column selection signals for selecting the memory cells, and select the voltages of the column selection signals in response to the write mode and the erase mode. The level is applied to the word lines WL201 to WL20m, and the control signals SB201 to SB20m for controlling the opening and closing of the switch crystals - 152 - 201010062 body 2209 - 1 - 2209 - m are simultaneously output. The row decoders 2300 - 1 to 2300 - η are line decoders provided in the memory cell blocks 2101 -1 to 2101 - η, and one memory cell block is selected in the row direction in 8-bit units. The second level shifting circuit 2303 converts the line selection signal output from the line decoder into a signal of the second signal voltage VP2 02 and outputs it. Further, in each memory cell block, an 8-bit unit row selection transistor (CG201- 0 to CG201-7, CG2 0n - 0 to CG20n - 7) is provided, and this row selects the transistor from the second level. The row selection signals COL201 to COL20n (second signal voltage VP202) outputted by the shift circuit are used as gate inputs, and bit cells of one memory cell block are selected, and memory cells of 8-bit units are selected. The bit line of the memory cell block selected by the transistor is selected by this row, and the transistor is selected via the row to be connected to the data output line D200-D 207. Further, when the data conversion circuit 2400 receives the input signals Din200 to Din207 of the write data in one byte unit and writes the data and erases the data, the data conversion circuit 2400 outputs the data through the data input lines D200 to D207 and applies them to the memory. The third signal voltage VP203 of the drain of the transistor of the cell. Further, the sense amplifier 2500 - 0-2500-7 amplifies the data of the memory cell read out from the data input lines D200 to D 207 and outputs it to the outside. Therefore, by using the nonvolatile semiconductor memory device of the present invention, MTP' can be constructed while the memory cell array can be divided in 8-bit units in the row direction, and data can be written and read in 8-bit units. [21st embodiment] Fig. 5 is a view showing the configuration of a nonvolatile half-153-201010062 conductor memory device according to a second embodiment of the present invention. In the example shown in Fig. 35, the nonvolatile semiconductor memory device shown in Fig. 34 is formed as a common source line for every two columns. In this way, there is no wasted empty area in the arrangement. The circuit of the column decoder is shown in Fig. 36. The column decoder 2200A shown in Fig. 36 adds a control signal E203B to the column decoder 2200 shown in Fig. 32A, and changes the inverter 2226 shown in Fig. 3A to the inverter 2226A. And input control signal E203B. Fig. 37 is a view showing the operation table of the column decoder shown in Fig. 36. The difference between the action table shown in Fig. 37 and the action table shown in Fig. 33 is the step of erasing 2-2 of the non-selected cells. Surround the attention area with a thick frame. In the circuit of the column decoder shown in Fig. 32A, when the step of erasing 2 - 2 is performed, the unselected word line WL202 becomes 3V, and the source S200 becomes an open circuit, and the memory cell shown in Fig. 5 is created. In the configuration of the element array, the source line S200 (1, 2) becomes common, and since the signals SB201 and SB202 in the operation table become the signal SB202 becomes "0", the transistor 2209-2 becomes non-conductive, but because the signal SB201 It is "1", so the transistor 2209-1 becomes conductive. Therefore, when the signals SB201 and SB202 applied to the common source line S200(1, 2) become 0V and the word line WL202 is 3V, the memory cell connected to the word line WL202 becomes conductive. In order to avoid 'setting the control signal E2 03B, if it is set to "〇" when erasing 2-2, the output of the NAND circuit 2206 becomes "1", even if the decoder output of 2201 is not selected, the level shifting circuit The output signal of the word line WL202 of 2207 becomes 0V, and the current of the non-selected cell is not flowing. Here, in this state, the step of erasing 2- 2 'self-convergence action-154- At 201010062, the memory cell connected to the selected word line WL2 0 1 and the non-selected memory cell connected to the adjacent word line WL202, at the same time, the self-converging voltage, that is, the drain becomes 5V. The gate becomes 0V, the source becomes 0V, and the self-convergence occurs in the erased cell. When the memory cell connected to the word line WL2 02 self-converges in the previous state, the second self-convergence occurs because the second self-convergence operation occurs. However, if we look at the characteristics of the self-convergence action shown in Fig. 28A, since the limit of self-convergence converges to the initial enthalpy, there is no problem even if the self-retracting action is excessively applied. As described above, in the nonvolatile semiconductor memory device of the twenty-first embodiment, as shown in FIG. 5, the memory cells are formed by MTP, and are arranged such that the memory cell pairs are in the row direction by one bit. The group unit is composed of rows of memory cells in an 8-bit unit. Further, the drains of the transistors of the memory cells are commonly connected by bit lines BIT201 - 0 to BIT20n - 7 along the column direction, and the word lines WL201 - WL20m provided in the respective columns are used in the row direction. Connect the control gate CG200 of the transistor of the memory cell of each column. Further, the source lines of the memory cells of the two columns of memory cells are connected in common in the row direction by the source lines S200 (1, 2) to S200 (m - 1, m) provided in each of the two columns. In this source line, commonly connected: the first switching transistor (for example, switching transistor 2209-1) accepts an open/close signal from one of the columns (for example, signal SB201), and selects to ground the source line to GND ( "0" V) or become an open circuit; and the second switching transistor (for example, switching transistor 2209-2) accepts an open/close signal from another column (for example, signal SB202) and selects the source line to be grounded to GND. (“0” V) or become an open circuit. -155- 201010062 Further, the decoders 2200-1 to 2200-m provided in the respective columns receive the address signals, and generate a column selection signal for selecting the memory cells, in response to the write mode and the erase mode. The voltage level of the column selection signal is selected and applied to the word lines WL201 to WL20m. Further, each of the column decoders 2200-1 to 2200-m is paired, and one of the column decoders (for example, 2200 to 1) is output to open and close the first switching transistor (for example, the switching transistor 2209-1). (eg signal SB201). Further, the second switching transistor (e.g., switching transistor 2209-2) is turned on and off (e.g., signal 88202) from the other column decoder (e.g., 2200-2). Row decoder 2300 - 1~2300 - n (refer to Fig. 34) The row decoder set in each of the memory cell blocks 2101 - 1 to 2101-n selects one memory in the row direction in 8-bit units. Cell box. The second level shift circuit 23 0 3 converts the line selection signal output from the row decoder into a signal of the second signal voltage VP202 and outputs it. Further, in each memory cell block, an 8-bit unit row selection transistor (CG201-0 to CG201-7.....CG20n-0 to CG20n-7) is provided, and the row selection transistor will be from the second The row selection signal (second signal voltage VP 202) outputted by the level shifting circuit is used as a gate input, and a bit line of a memory cell of one memory cell block is selected, and a memory cell of an 8-bit unit is selected. The bit line of the memory cell block selected by the transistor is selected in this row, and the transistor is selected via the row to be connected to the data output lines D200 to D207. Further, when the data conversion circuit 2400 receives the input signals Din200 to Din207 of the data to be written in one byte unit, and writes the data and erases the data, the data conversion circuit 2400 outputs the data to the memory cell by inputting the data input and output lines D200-D207. -156- 201010062 The third signal voltage VP203 of the drain of the transistor. Further, the sense amplifier 2500 - 0-2500 - 7 amplifies the data of the memory cell read out from the data input lines D200 to D207 and outputs it to the outside. Thus, with the non-volatile semiconductor memory device of the present invention, MTP can be constructed while sharing the source lines every two columns, eliminating wasted empty areas in arrangement. Further, in the eighteenth, nineteenth, twenty-th, and twenty-first embodiments, the writing and erasing operations of one-byte units are described, but the present invention is not limited to the 1 G-bit unit. For example, a row decoder (not shown) is selected together to input a signal to the row decoder 2300. If it is set to simultaneously select the row decoders 2300-1 to 2 300-n, it can be simultaneously written or erased and connected to a word line. For example, all of the memory cells of Mill-0~Ml 1 1-7 (nX8). Therefore, so-called writing and erasing in page units can be performed. Further, the configuration of the memory array (memory cell block) is collectively arranged in the row address unit (n-bit) in the examples shown in FIG. 30 and FIG. 31, and 第 in FIG. 34 and FIG. The example shown in the figure is constructed by concentrating in units of I/O bits (here, 1-bit units). Also consider the convenience of the layout configuration, and determine which way to use. Further, in the examples shown in Figs. 34 and 35, although 1-bit units (8-bit units) are used as the input/output I/O unit, even in the word unit (16-bit) or double The character unit (32 bits), or a larger number of I/O bits, consists of the same subject and effect. [Twenty-Fourth Embodiment] Fig. 38 is a view showing the configuration of a nonvolatile half-157-201010062 conductor memory device according to a twenty-second embodiment of the present invention. The example shown in Fig. 38 is an example of the arrangement configuration of the memory cells of the OTP shown in Fig. 30. That is, the memory cells shown in Figs. 25A to 25D are arranged in an array. In the third drawing, the word lines (control gates) WL201, WL202, WL203, ... are passed by the metal wiring in the horizontal direction (lateral direction) on the drawing, and the source lines S201 and S202 are passed in the left-right direction. The bit lines BIT201, BIT202, BIT 2 0 3, ... pass through the vertical direction (longitudinal direction) on the drawing surface, and the non-volatile semiconductor memory (memory cell) shown in Fig. 25A to Fig. 25D is placed up and down and left and right. Configured to be symmetrical, sharing the n-type well with each other to reduce the area. In this way, the wasted empty space is eliminated and an efficient configuration is made. It is the best configuration in terms of characteristics and area. This arrangement can also be applied to the source-shared type non-volatile semiconductor memory device shown in Fig. 35. As described above, in the nonvolatile semiconductor memory device of the twenty-second embodiment, the nonvolatile semiconductor memory device (memory cell) shown in Figs. 25 to 25D is used as the memory cell. For example, attention is paid to a memory cell (a memory cell selected by the word line WL201 and the bit line 202) surrounded by a broken line in Fig. 38, and the memory cell configured by this arrangement is explained. The transistor forming portion 2003 disposed in the upper and lower directions of the drawing includes an in-type diffusion layer 2005 which is a drain of the transistor, and a gate region portion (a first diffusion layer 2005 and a channel which forms a channel of the transistor). A region in the middle of the second diffusion layer 2006) and a second n-type diffusion layer 2006 serving as a source of the transistor. On the left side of the transistor forming portion 200 3, the first metal wiring 2012 is placed in the vertical direction. The metal wiring 2012 is disposed in parallel with the transistor forming portion 100 0 from a predetermined distance of the surface of the semiconductor substrate via -158-201010062, and the metal wiring 2012 utilizes a contact and a drain of the transistor (the In-type diffusion layer 2005). )connection. This first metal wiring 2012 is connected to the bit line BIT202. On the left side of the transistor forming portion 101 0, a square n-type well 2002 is formed in the left-right direction with a predetermined width and depth. The square floating gate 2009 is disposed to face the surface of the semiconductor substrate in the left-right direction while being disposed such that the region on the left end side thereof faces the surface of the n-type well 2002, and the region on the right end side and the gate region portion (the The channel formation region in the middle of the In-type diffusion layer 2005 and the second n-type diffusion layer 2006 is opposed to each other. On the left side of the n-type well 2002, a p-type diffusion layer 2015 is formed in the left-right direction adjacent to the left side of the region opposite to the floating gate 2009 of the n-type well 2002, and has a predetermined width and depth. The germanium diffusion layer 2015 and the control gate wiring 2019 are connected by contacts. The control gate wiring 2019 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the floating gate 2009 at a predetermined distance, and is connected to the p-type diffusion layer 2015 by a contact. The control gate wiring 2019 is connected to the common word line WL20 1 . The second metal wiring 2013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 2006 which is the source of the transistor Τ210, and the second metal wiring 2013 uses the contact and the second The 2n type diffusion layer 2006 is connected. This second metal wiring 2013 is connected to the second n-type diffusion layer 2006 by a contact. This second metal wiring 2013 is connected to the common source line S201. Further, in the arrangement of the memory cells, two memory cells which are mutually symmetrically arranged with the n-type well 20 02 and two memory cells which are arranged symmetrically with respect to the left-right symmetrically -159-201010062 are mutually In the common metal wiring 2013 (source line S2 01), the total of four memory cells, which are symmetrically arranged in the lower direction, are the basic units of the arrangement, and are arranged in parallel in the left-right direction, and are also parallel in the vertical direction. The four memory cells that are arranged to be the basic unit are arranged. Thus, the non-volatile semiconductor memory device of the present invention can be used to construct an OTP while eliminating wasteful empty space in arrangement. Further, in the twenty-second embodiment shown in Fig. 38, in the memory cell (the memory cell selected by the bit line BIT202 and the word line WL201), the Q metal wiring 2012 is disposed in the transistor forming portion 2003. The left side, but the same on the right side, can also be placed on the right side. However, in this example, when it is placed on the right side, since the memory cell size is determined by the interval of the metal wiring 2012, the memory cell size becomes slightly larger. [Thirty-third embodiment] FIG. 3A and FIG. 39B are views showing a configuration of a nonvolatile semiconductor memory device according to a twenty-third embodiment of the present invention. In the memory cell of the seventeenth embodiment shown in Figs. 25A to 25D, the n-type well is omitted, and the area reduction effect is further exhibited. Fig. 39 is a plan view, and Fig. 39 is a sectional view taken along Β20-Β20'. The memory cell shown in Fig. 39 and Fig. 39 and the difference in the composition of the memory cell shown in Fig. 25 to Fig. 25D are omitted from the n-type well shown in Fig. 25 (n- Well) 2, instead of setting the depletion-type channel injection 2021 of the 39th map, and changing the p-type diffusion layer 2015 to the n-type diffusion layer 2015'. That is, in the transistor forming portion 20 30 shown in FIGS. 25A to 25D, the first In-type diffusion layer 2005 which becomes the -160-201010062 of the transistor 201, and the gate region which forms the channel of the transistor (the The arrangement of the in-type diffusion layer 2 00 5 and the second n-type diffusion layer 2006 and the arrangement of the second n-type diffusion layer 2006 are the same, and the same applies to the related wirings 2012 and 2013, the control gate wiring, and the like. The equivalent circuit shown in the figure is the same. Therefore, the same components are denoted by the same reference numerals and the description thereof will not be repeated. As described above, in the memory cell shown in the twenty-third embodiment, in order to save the well, a depletion-type channel injection 2021 is formed under the gate of the capacitor 2014, so that the memory cell can be efficiently integrated. Although for the standard CMOS process, the D-type channel injection is required because of the additional injection step, the total step is only slightly increased, and the complicated load of the process is not performed. Further, in the twenty-third embodiment, the n-type diffusion layer 2005 corresponds to the first In-type diffusion layer which is the drain of the transistor, the n-type diffusion layer corresponds to the above-described second n-type diffusion layer, and the n-type diffusion layer 20 15' The third n-type diffusion layer is described. Further, the metal wiring 2012 corresponds to the Q 1 metal wiring, and the metal wiring 2013 corresponds to the second metal described above, and the transistor forming portion 2003 is disposed in the first direction (upward in the drawing) on the surface of the semiconductor substrate. The transistor forming portion 2003 is disposed in the order of the first In-type extension 2005 which becomes the drain of the transistor 201, and the gate region which forms the channel of the transistor T2 01 (between the first extension 2005 and the second diffusion layer 2006). The region) and the second n-type diffusion layer 2006 that becomes the source of the electric T2 01. On the left side of the transistor forming portion 2003, wirings 2012 are arranged in the vertical direction. This metal wiring 2012 is attached to the gold Β Β Β Β Β Β Β 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The distance from the upper scattered layer of the bulk metal is set to -161 - 201010062 to be parallel to the transistor forming portion 2003, and the metal wiring 2012 utilizes the contact and the drain of the transistor (the 111th type diffusion layer 2005). connection. Further, on the left side of the transistor forming portion 2003, a depletion-type channel formed by a square having a predetermined width and depth in the left-right direction is injected 2 021. The square floating gate 2009 is disposed to face the surface of the semiconductor substrate in the left-right direction while being disposed such that the region on the left end side thereof faces the surface of the channel injection 202 1 and the region on the right end side and the gate region portion The channel formation region in the middle of the In-type diffusion layer 2005 and the second n-type diffusion layer 2006 is opposed to each other. On the left side of the channel injection 202 1 , an n-type diffusion layer 1015 ′ is formed in the left-right direction adjacent to the channel injection 202 1 , and the n-type diffusion layer 1 0 1 5 ′ and the control gate wiring 20 1 9 are connected. Point connection. The control gate wiring 2019 is disposed so as to face the floating gate 2009 in the left-right direction with a predetermined distance from the surface of the semiconductor substrate, and is connected to the n-type diffusion layer 2015' by the contact 2016. The second metal wiring 2013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 2006 serving as the source of the transistor 201, and the metal wiring 2013 is formed by the contact 2011 and the second n-type diffusion. Layer 2006 is connected. According to this configuration, a non-volatile memory can be realized by a CMOS process of standard logic elements, and OTP or MTP can be realized at the same time. Further, a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate) can be closely arranged to minimize the area. Further, the memory cells shown in Figs. 25A to 25D are omitted, and the area reduction effect can be further exerted. Further, in the twenty-third embodiment shown in the 39th and 39th drawings, -162-201010062, the metal wiring 2012 is disposed on the left side of the transistor forming portion 20030, but may be disposed on the right side or may be disposed on the right side. [Fourth Embodiment] Fig. 40 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty fourth embodiment of the present invention. The nonvolatile semiconductor memory device shown in Fig. 40 is such that the nonvolatile semiconductor memory elements (memory cells) shown in Figs. 39A and 39B are arranged on the array. As in the nonvolatile semiconductor memory device shown in Fig. 38, the memory cells are arranged symmetrically in the upper and lower sides, and the area can be reduced to omit the weight of the n-type well. As described above, in the nonvolatile semiconductor memory device described in the twenty-fourth embodiment, for example, attention is paid to a portion of the memory cell surrounded by a broken line in FIG. 40 (selected by the word line WL201 and the bit line 202). In the memory cell, when the memory cell is described, the transistor forming portion 2003 disposed in the upper and lower directions of the drawing includes the first In-type diffusion layer 2005 which becomes the drain of the transistor, and the gate which forms the channel of the transistor. The polar region portion (the region between the first diffusion layer 2005 and the second diffusion layer 2006) and the second n-type diffusion layer 2006 serving as the source of the transistor. On the left side of the transistor forming portion 203, the first metal wiring 2012 is disposed in parallel with the transistor forming portion 2003 and is spaced apart from the surface of the semiconductor substrate by a predetermined distance. This first metal wiring 2012 is connected to the bit line 202. Further, on the semiconductor substrate, on the left side of the transistor forming portion 2003, a depletion-type channel (not shown) is formed in the left-right direction with a predetermined width and depth (refer to channel injection in Fig. 39). 163- 201010062 2021) The floating gate 2009 is disposed in the left-right direction so as to face the surface of the semiconductor substrate while being disposed such that the region on the left end side faces the surface on which the above-described channel is implanted, and the region on the right end side and the transistor are formed. The gate region portion of the portion 2003 (the channel formation region between the first In-type diffusion layer 2005 and the second n-type diffusion layer 2006) faces each other.
在通道注入的左側，將η型擴散層2015’設置成和此 通道注入相鄰。又，控制閘極配線2019從半導體基板表面 隔著既定之距離在左右方向配置成和浮動閘極2009相對 向。此控制閘極配線2019和字元線WL2 01連接。又，第2 金屬配線2013從半導體基板表面隔著既定之距離在左右 方向配置成和第2η型擴散層2 0 06相對向，此第2金屬配 線2013利用接點和第2η型擴散層2006連接。此第2金屬 配線2013和源極線S201連接。 而，在記億胞元陣列的配置，將2個記憶胞元左右對 稱地配置成共用η型擴散層2015’ （在圖上爲左側的記憶On the left side of the channel injection, the n-type diffusion layer 2015' is placed adjacent to this channel implantation. Further, the control gate wiring 2019 is disposed to face the floating gate 2009 in the left-right direction from the surface of the semiconductor substrate with a predetermined distance therebetween. This control gate wiring 2019 is connected to the word line WL2 01. In addition, the second metal interconnections 2013 are arranged to face the second n-type diffusion layer 205 in the left-right direction with a predetermined distance from the surface of the semiconductor substrate, and the second metal interconnections 2013 are connected by the contacts and the second n-type diffusion layer 2006. . This second metal wiring 2013 is connected to the source line S201. However, in the arrangement of the cell array, two memory cells are symmetrically arranged to share the n-type diffusion layer 2015' (the memory on the left side in the figure)
胞元），又對該左右對稱地配置的2個記憶胞元，在上下方 向將2個記憶胞元對稱地配置（在圖上爲下側的2個記憶胞 兀）成共用源極線S201’將這4個記憶胞兀作爲基本單位， 在左右方向作爲記憶胞元陣列排列。而，亦在上下方向平 行地排列配置在左右方向所排列的記憶胞元陣列。 利用這種構成’在2列記憶胞元共用源極線之情況的 布置，高效地配置記憶胞元，可減少記憶胞元陣列的配置 面積。 此外，在第40圖所示的第24實施形態，在記憶胞元（由 -164- 201010062 位元線BIT202和字元線WL201所選擇的記憶胞元），雖然 金屬配線2012配置於電晶體形成部20 03的左側，但是配 置於右側亦一樣，又，亦可配置於正上。其中，在本例， 配置於右側時，因爲記憶胞元尺寸由金屬配線2012的間隔 所決定，所以有記憶胞元尺寸變成稍大的情況。 [第25實施形態] 第41圖係表示本發明之第25實施形態的非揮發性半 導體記憶裝置的構成圖。是對第41圖之浮動閘極的形狀， 〇 使電容器部分之寬度比電晶體通道部分的寬度寬，而減少 浪費的空間，以更縮小面積。 即，例如著眼於在第41圖以虛線所包圍之部分A2 0 00 的記憶胞元（由字元線WL201和位元線BIT202所選擇的記 憶胞元），說明以此布置所配置的記憶胞元時，在圖上之上 下方向所配置的電晶體形成部200 3，包含有：成爲電晶體 之汲極的第In型擴散層2005、形成電晶體之通道的閘極 區域部（第1擴散層20 05和第2擴散層2006之中間的區 ©域）、以及成爲電晶體之源極的第2n型擴散層2006。 在此電晶體形成部2003的左側，第1金屬配線2012 配置成和電晶體形成部203 0平行而且從半導體基板表面 隔著既定之距離。此第1金屬配線2012和位元線BIT2 02 連接》 又，在半導體基板上，在該電晶體形成部2030的左 側，以既定之寬度和深度在左右方向所形成未圖示之空乏 型（depletion — type)通道注入（參照第 39B圖的通道注入 2021) ° -165- 201010062 浮動閘極2009在左右方向配置成和半導體基板表面 相對向，同時配置成左端部側的區域和上述之通道注入的 表面相對向，且右端部側的區域和電晶體形成部2003的閘 極區域部（第In型擴散層2005和第2n型擴散層20 06之中 間的區域）相對向。又，在此浮動閘極2009，在左端部的區 域具備有方形的面積擴張部20 09A，以利用此面積擴張部 200 9A使電容器的容量變大之方式構成。In the two memory cells arranged symmetrically to the left and right, two memory cells are symmetrically arranged in the vertical direction (two memory cells on the lower side in the figure) to form a common source line S201. 'The four memory cells are used as the basic unit and arranged in the left and right direction as a memory cell array. Further, the memory cell arrays arranged in the left-right direction are also arranged in parallel in the vertical direction. With the arrangement of the case where the two columns of memory cells share the source line, the memory cells are efficiently arranged, and the arrangement area of the memory cell array can be reduced. Further, in the twenty-fourth embodiment shown in Fig. 40, in the memory cell (memory cell selected by -164 - 201010062 bit line BIT202 and word line WL201), the metal wiring 2012 is disposed in the transistor. The left side of the portion 20 03 is the same as that disposed on the right side, and may be disposed directly above. However, in this example, when it is placed on the right side, since the memory cell size is determined by the interval of the metal wiring 2012, the memory cell size becomes slightly larger. [25th embodiment] Fig. 41 is a view showing the configuration of a nonvolatile semiconductor memory device according to a 25th embodiment of the present invention. It is the shape of the floating gate of Fig. 41. 〇 The width of the capacitor portion is wider than the width of the transistor channel portion, and the wasted space is reduced to further reduce the area. That is, for example, focusing on the memory cell (the memory cell selected by the word line WL201 and the bit line BIT202) of the portion A2 0 00 surrounded by the broken line in Fig. 41, the memory cell configured by this arrangement is explained. In the case of the element, the transistor forming portion 200 3 disposed in the upper and lower directions of the drawing includes the first In-type diffusion layer 2005 which becomes the drain of the transistor, and the gate region which forms the channel of the transistor (the first diffusion) A region © in the middle of the layer 20 05 and the second diffusion layer 2006, and a second n-type diffusion layer 2006 serving as a source of the transistor. On the left side of the transistor forming portion 2003, the first metal wiring 2012 is disposed in parallel with the transistor forming portion 203 0 and spaced apart from the surface of the semiconductor substrate by a predetermined distance. The first metal wiring 2012 and the bit line BIT2 02 are connected to each other. On the semiconductor substrate, a depletion (not shown) is formed on the left side of the transistor forming portion 2030 with a predetermined width and depth in the left-right direction. — type) channel injection (refer to channel injection 2021 of Fig. 39B) ° -165- 201010062 Floating gate 2009 is arranged in the left-right direction to face the surface of the semiconductor substrate, and is disposed at the left end side and the above-mentioned channel injection The surface faces each other, and the region on the right end side faces the gate region portion of the transistor forming portion 2003 (the region between the first In-type diffusion layer 2005 and the second n-type diffusion layer 2020). Further, in the floating gate 2009, a square area expanding portion 209A is provided in the region at the left end portion, and the capacity of the capacitor is increased by the area expanding portion 209A.
在通道注入的左側，將η型擴散層2015’設置成和此 通道注入相鄰。又，控制閘極配線2019從半導體基板表面 隔著既定之距離在左右方向配置成和浮動閘極2009相對 向。此控制閘極配線2019和字元線WL201連接。又，第2 金屬配線2013從半導體基板表面隔著既定之距離在左右 方向配置成和第2ιι型擴散層2006相對向，此第2金靥配 線2013利用接點和第2η型擴散層2006連接。此第2金屬 配線2013和源極線S201連接。On the left side of the channel injection, the n-type diffusion layer 2015' is placed adjacent to this channel implantation. Further, the control gate wiring 2019 is disposed to face the floating gate 2009 in the left-right direction from the surface of the semiconductor substrate with a predetermined distance therebetween. This control gate wiring 2019 is connected to the word line WL201. In addition, the second metal wiring 2013 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second iv type diffusion layer 2006, and the second metal ray distribution line 2013 is connected to the second n-type diffusion layer 2006 by the contact. This second metal wiring 2013 is connected to the source line S201.
而，在記憶胞元陣列的配置，將2個記憶胞元左右對 稱地配置成共用η型擴散層2015’ （在圖上爲左側的記憶 胞元），又對該左右對稱地配置的2個記憶胞元，在上下方 向將2個記憶胞元對稱地配置（在圖上爲下側的2個記憶胞 元）成共用源極線S201，將這4個記憶胞元在構成上作爲 基本單位，在左右方向作爲記憶胞元陣列排列。而，亦在 上下方向平行地排列配置在左右方向所排列的記憶胞元陣 列。 利用這種構成，在2列記憶胞元共用源極線之情況的 布置，高效地配置記憶胞元，可減少記憶胞元陣列的配置 -166- 201010062 面積。 此外，在第41圖所示的第25實施形態，在記憶胞元（由 位元線BIT202和字元線WL201所選擇的記憶胞元），雖然 金屬配線2012配置於電晶體形成部2003的左側，但是配 置於右側亦一樣，又，亦可配置於正上。其中，在本例， 配置於右側時，因爲記憶胞元尺寸由金屬配線2012的間隔 所決定，所以有記憶胞元尺寸變成稍大的情況。 [第26實施形態] 〇 第42圖係表示本發明之第26實施形態的非揮發性半 導體記憶裝置的構成圖。是對應於第31圖所示之非揮發性 半導體記憶裝置的電路構成、及第34圖所示之非揮發性半 導體記憶裝置的電路構成的布置配置例，例如，對應於字 元線WL201而配置源極線S201，對應於字元線WL20 2、 WL202、WL204 而配置源極線 S202、S203、S204。即，是 源極線對各字元線獨立之情況的布置。 例如著眼於在第42圖以虛線所包圍之部分A2000的 0 記憶胞元（由字元線WL203和位元線BIT202所選擇的記憶 胞元），說明以此布置所配置的記憶胞元時，在圖上之上下 方向所配置的電晶體形成部20 03，配置：成爲電晶體之汲 極的第In型擴散層2005、形成電晶體之通道的閘極區域 部（第1擴散層2 00 5和第2擴散層2 006之中間的區域）、 以及成爲電晶體之源極的第2n型擴散層2006» 在此電晶體形成部2003的左側，第1金屬配線2012 配置成和電晶體形成部2030平行而且從半導體基板表面 隔著既定之距離。此第1金屬配線2012和位元線BIT2 02 -167- 201010062 連接。 又，在半導體基板上，在該電晶體形成部2030的左 側，以既定之寬度和深度在左右方向所形成未圖示之空乏 型（depletion — type)通道注入（參照第39B圖的通道注入 2021) »On the other hand, in the arrangement of the memory cell array, two memory cells are symmetrically arranged in a bilaterally shared n-type diffusion layer 2015' (the memory cell on the left side in the figure), and two of the left and right symmetrically arranged. In the memory cell, two memory cells are symmetrically arranged in the vertical direction (the two memory cells on the lower side in the figure) to form a common source line S201, and the four memory cells are configured as a basic unit. , arranged in the left and right direction as a memory cell array. Further, the memory cell array arranged in the left-right direction is also arranged in parallel in the vertical direction. With this configuration, in the case where the two columns of memory cells share the source line, the memory cells are efficiently arranged, and the area of the memory cell array can be reduced -166 - 201010062. Further, in the twenty-fifth embodiment shown in Fig. 41, in the memory cell (memory cell selected by the bit line BIT202 and the word line WL201), the metal wiring 2012 is disposed on the left side of the transistor forming portion 2003. However, the configuration is the same on the right side, and it can also be placed on the right side. However, in this example, when it is placed on the right side, since the memory cell size is determined by the interval of the metal wiring 2012, the memory cell size becomes slightly larger. [Embodiment 26] Fig. 42 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty sixth embodiment of the present invention. It is an arrangement example of the circuit configuration of the nonvolatile semiconductor memory device shown in FIG. 31 and the circuit configuration of the nonvolatile semiconductor memory device shown in FIG. 34, and is configured corresponding to, for example, the word line WL201. The source line S201 is provided with source lines S202, S203, and S204 corresponding to the word lines WL20 2, WL202, and WL204. That is, it is an arrangement in which the source lines are independent of the respective word lines. For example, focusing on the 0 memory cells of the portion A2000 (memory cells selected by the word line WL203 and the bit line BIT202) surrounded by a broken line in Fig. 42, when the memory cells configured by this arrangement are explained, The transistor forming portion 203 disposed in the upper and lower directions of the drawing is provided with an In-type diffusion layer 2005 which becomes a drain of the transistor, and a gate region portion which forms a channel of the transistor (first diffusion layer 2 00 5 a region between the second diffusion layer 2 006 and a second n-type diffusion layer 2006» which is a source of the transistor. On the left side of the transistor formation portion 2003, the first metal interconnection 2012 is disposed and the transistor formation portion. 2030 is parallel and spaced from the surface of the semiconductor substrate by a predetermined distance. This first metal wiring 2012 is connected to the bit line BIT2 02 -167- 201010062. Further, on the semiconductor substrate, on the left side of the transistor forming portion 2030, a depletion-type channel (not shown) is formed in the left-right direction with a predetermined width and depth (see the channel injection 2021 of FIG. 39B). ) »
浮動閘極2009在左右方向配置成和半導體基板表面 相對向，同時配置成左端部側的區域和上述之通道注入的 表面相對向，且右端部側的區域和電晶體形成部2003的閘 極區域部（第In型擴散層2005和第2η型擴散層2006之中 間的區域）相對向。又，在此浮動閘極2009，在左端部的區 域具備有方形的面積擴張部2009Α，以利用此面積擴張部 200 9Α使電容器的容量變大之方式構成。The floating gate 2009 is disposed in the left-right direction so as to face the surface of the semiconductor substrate while being disposed such that the region on the left end side faces the surface on which the above-described channel is implanted, and the region on the right end side and the gate region of the transistor forming portion 2003 The portion (the region between the first In-type diffusion layer 2005 and the second n-type diffusion layer 2006) faces each other. Further, in the floating gate 2009, a square area expansion portion 2009 is provided in the region at the left end portion, and the capacity of the capacitor is increased by the area expansion portion 200 9 .
在通道注入的左側，將η型擴散層2015’設置成和此 通道注入相鄰。又，控制閘極配線2019從半導體基板表面 隔著既定之距離在左右方向配置成和浮動閘極2009相對 向。此控制閘極配線2019和字元線WL203連接。又，第2 金屬配線2013從半導體基板表面隔著既定之距離在左右 方向配置成和第2η型擴散層2006相對向，此第2金屬配 線2013利用接點和第2η型擴散層2006連接。 而，在記憶胞元陣列的配置，將2個記憶胞元左右對 稱地配置成共用η型擴散層2015’ （在圖上爲左側的記憶 胞元），又對該左右對稱地配置的2個記憶胞元，在上下方 向對稱地配置2個記億胞元（在圖上爲上側的記憶胞元）， 將這4個記憶胞元作爲單位，在左右方向作爲記憶胞元陣 列排列。而，在上下方向平行地排列配置在左右方向所排 -168- 201010062 列的記憶胞元陣列。 利用這種構成，在源極線對各字元線獨立之情況的布 置’高效地配置記憶胞元，可減少記憶胞元陣列的配置面 積。 此外’在第42圖所示的第26實施形態，在記憶胞元（由 位元線BIT202和字元線WL203所選擇的記億胞元），雖然 金屬配線20 12配置於電晶體形成部20 03的左側，但是配 置於右側亦一樣，又，亦可配置於正上。其中，在本例， © 配置於右側時，因爲記憶胞元尺寸由金屬配線2012的間隔 所決定，所以有記憶胞元尺寸變成稍大的情況。 [第27實施形態] 第43圖係表示本發明之第27實施形態的非揮發性半 導體記憶裝置的構成圖。所圖示的非揮發性半導體記憶裝 置是將第30圖所示之第18實施形態的非揮發性半導體記 憶裝置進行變形的例子。 第43圖所示的非揮發性半導體記憶裝置和第30圖所 Q 示之非揮發性半導體記憶裝置在構成上的相異點，是記憶 胞元方塊之構成相異。即，在第30圖所示的例子，將記憶 陣列在行方向因應於I/O位元數（在圖例爲8位元）進行8 分割，而構成在行方向爲η位元單位（位址單位）的記憶胞 元方塊2100 — 0〜2100— 7。另一方面，在第43圖所示的第 27實施形態，將記憶胞元陣列以1/0位元數的單位（在圖例 爲8位元）在行方向進行分割。即’因爲對陣以8位元單位 進行改寫’所以爲了使布置的配置變成更佳’而由在行方 向以8位元單位（I/O單位）所分割的記億胞元方塊2101一 -169- 201010062 1 ~2 1 0 1 - η構成記憶胞元陣列。例如，記憶胞元方塊2 1 0 1 -1由在行方向爲8位元、在列方向爲m位元的記憶胞元 Μ2 1 1 — Ο~Μ21 1 — 7、…、M2ml — 0~M2ml _ 7 所構成。 如此，在第27實施形態的非揮發性半導體記憶裝置， 以MTP構成記億胞元，並配置成由將記憶胞元對各列在行 方向以1位元組單位（I/O位元數的單位）被進行行選擇之記 憶胞元方塊所構成。 而，沿著行方向利用位元線BIT201— 0~BIT20n-7共 同連接各記憶胞元之電晶體的汲極，並利用對各列所設置 之字元線WL201~WL20m，各自沿著行方向共同連接各列 之記憶胞元之電晶體的控制閘極CG200。 又，利用源極線S201，共同連接各列之記憶胞元之電 晶體的源極。將此源極線S201接地成GND( “ Ο” V)。 在各列所設置之列解碼器2200 — 1〜2200 - m接受位址 信號，並產生選擇記憶胞元的列選擇信號，因應於寫入模 式及拭除模式，而選擇該列選擇信號的電壓位準，並施加 於字元線WL201~WL20m。 行解碼器2300 - l~2 300-n是在各記憶胞元方塊2101 -l~2101-n所設置之行解碼器，在行方向以8位元單位 選擇1個記憶胞元方塊。第2位準挪移電路2 3 03將從行解 碼器所輸出之行選擇信號變換成第2信號電壓VP202的信 號並輸出。 又，在各記憶胞元方塊，設置8位元單位的行選擇電 晶體 i(CG201— 0~CG201— 7、…、CG20n — 0〜CG20n — 7)， 此行選擇電晶體將從第2位準挪移電路所輸出之行選擇信 -170- 201010062 號（第2信號電壓VP202)作爲閘極輸入，選擇1個記憶胞 元方塊的位元線，而選擇8位元單位的記憶胞元。 由此行選擇電晶體所選擇之記憶胞元方塊的位元線， 經由該行選擇電晶體而和資料輸出入線D2 0 0~D207連接。 又，資料變換電路2400在接受1位元組單位之寫入資料的 輸入信號Din200~Din207，並進行資料的寫入或資料的拭 除時，輸出透過資料輸出入線D200〜D207而施加於記憶胞 元之電晶體之汲極的第3信號電壓VP203。又，感測放大 〇 器2500-0〜2 500— 7將資料輸出入線D 2 00〜D207所讀出之 記憶胞元的資料放大並向外部輸出。 因而，使用本發明的非揮發性半導體記憶元件，可構 成MTP，同時可將記憶胞元陣列在行方向以8位元單位進 行分割，並以8位元單位進行資料的寫入和讀出。 此外，在第43圖所示的例子，雖然說明將記憶胞元陣 列在行方向以8位元單位分割成8個的例子，但是未限定 如此’亦可因應於I/O位元數的要求規格，而作成以字元 Q 單位（16位元胞元）或雙字元（32位元胞元）等之任意的位元 數單位進行分割。 [第28實施形態] 第44圖係表示本發明之第28實施形態的非揮發性半 導體記憶裝置的構成圖。所圖示的非揮發性半導體記憶裝 置是將第35圖所示之第21實施形態的非揮發性半導體記 憶裝置進行變形的例子。 第44圖所示的非揮發性半導體記憶裝置和第3 5圖所 示之非揮發性半導體記憶裝置在構成上的相異點，是記憶 -171 - 201010062 胞元方塊之構成相異。即，在第35圖所示的例子’將記憶 陣列在行方向因應於I/O位元數（8位元）進行分割’而構成 記憶胞元方塊。另一方面，在第44圖所示的例子，將記憶 胞元陣列在行方向以I/O位元數的單位（在圖例爲8位元） 進行分割，而構成在行方向爲η位元及在列方向爲m位元 的單位的記憶胞元方塊2100 — 0~2 100 - 7。即’記憶胞元 如 M211-0~M21n-0.....M211-7~M21n-7 般，在行方 向以η位元的位址單位集中，而構成至記憶胞元方塊2100 —0〜2100 — 7爲止。 行解碼器2300— 1~2 300_η是設置成和各記憶胞元方 塊2100-0〜2100— 7的位址寬度η位元相對向之η個行解 碼器。此行解碼器2300 — 1~2300-η各自由位址解碼器 2301、 反相器2302以及位準挪移電路2303所構成。位 準挪移電路2303將從行解碼器2300 - 1-2300— η所輸出之 行選擇信號變換成第2信號電壓VP2 02。 行選擇電晶體 CG20 1 - 0~CG20n — 0.....CG201- 0 7〜CG2 On- 7是對記憶胞元方塊的各個所設置之η位元單 位的行選擇電晶體，將從第2位準挪移電路所輸出之第2 信號電壓VP202(信號COL201〜COL20n)作爲閘極輸入，從 各記億胞元方塊選擇1個記憶胞元方塊的位元線，而選擇 合計8位元（I/O位元數）之記憶胞元的位元線。 列解碼器2200 — l~2200-m之構成是和第35圖所示 之列解碼器一樣之構成。又，在記憶胞元方塊之位元線 BIT201- 0~BIT20n - 7 的連接方法、字元線 WL201 〜WL20m 的連接方法、源極線S200(l、2)〜S200(m— 1、m)的連接方 -172- 201010062 法、開關用電晶體 2209 - 1、2209 — 2~2209 — (m — 1)、2209 _m的連接方法亦和第35圖所示的電路一樣。 即，沿著列方向利用位元線BIT201-0~BIT20n-7共 同連接各記憶胞元之電晶體的汲極，利用各列所設置的字 元線WL201〜WL20m，各自沿著行方向共同連接各列之記 憶胞元之電晶體的控制閘極CG200。 利用每2列所設置之源極線S200(l、2)〜S200(m-1、 m)沿著行方向共同連接成對之2列之記憶胞元之電晶體的 Ο 源極。在此源極線共同連接：第1開關用電晶體（例如開關 用電晶體2209 — 1 )，係接受來自其中一列的開閉信號（例如 信號SB201)，並選擇使源極線接地成GND( “0” V)或變成 開路；及第2開關用電晶體（例如開關用電晶體22 09 - 2)， 係接受來自另一列的開閉信號（例如信號SB202)，並選擇 使源極線接地成GND( “ 0” V)或變成開路 又，在各列所設置之列解碼器2200 — 1〜2200 - m接受 位址信號，並產生選擇記憶胞元的列選擇信號，並因應於 〇 寫入模式及拭除模式，而選擇該列選擇信號的電壓位準， 並施加於字元線 WL201〜WL20m。又，列解碼器 2200 -1~2200 — m每2個構成對，從一方的列解碼器（例如2200 一1)輸出使第1開關用電晶體（例如開關用電晶體220 9-1) 開閉信號（例如信號SB201)。 又，從另一方的列解碼器（例如2200 - 2)輸出使第2開 關用電晶體（例如開關用電晶體2209 - 2)開閉信號（例如信 號 SB202)° 又，由行選擇電晶體CG201- 0〜CG20n - 0.....CG201 173· 201010062 —07〜CG20n — 7所選擇之記憶胞元方塊之共8條的位元 線，經由該行選擇電晶體，而和資料輸出入線D200〜D207 連接。又，資料變換電路2400在接受1位元組單位之寫入 資料的輸入信號Din200〜DU207，並進行資料的寫入及資 料的拭除時，輸出透過資料輸出入線D2 00〜D2 07而施加於 記憶胞元之電晶體之汲極的第3信號電壓VP203。又，感 測放大器2500- 0~2 500- 7將資料輸出入線D2 00-D207所 讀出之記憶胞元的資料放大並向外部輸出。 如此，第28實施形態所示之非揮發性半導體記憶裝 置，以MTP構成記憶胞元，在行方向以η位元的位址單位 集中，而構成記憶胞元方塊，又每2列共用源極線，而在 布置上以消除浪費之空區域的方式構成。 [第29實施形態] 第45 Α圖〜第45Ε圖係表示本發明之第29實施形態的 非揮發性半導體記憶裝置（記憶胞元）的構成圖。第45A圖〜 第45E圖所示之記憶胞元和第25A圖~第25D圖所示之記 憶胞元的相異點，是刪除第25 A圖~第25D圖所示之和控 制閘極CG200(20 1 9)連接的η型擴散層2017及接點2018, 而和η型井2002分離，並新設置和η型井2002連接的η 型擴散層2023、對η型井2002供給所要之電壓CGWell200 的金屬配線2 025、以及連接η型擴散層2023和金屬配線 2025的接點2024。此η型擴散層2 023、接點2024以及金 屬配線2025可配置於記憶胞元的空空間，而不會使記憶胞 元的面積變大，刪除第25 Α圖~第25D圖所示之η型擴散 層2017、 接點2018之面積縮小效果大。 -174- 201010062 第45 A圖表示第29實施形態之記憶胞元的平面圖。第 45B圖表示等價電路圖，第45C圖表示沿著第45A圖之 A20— A20’的剖面圖，第45D圖表示沿著B20— B20，的 剖面圖，第45E圖表示沿著E20— E20’的剖面圖。 此記憶胞元如第45B圖的等價電路所示，由電晶體 T2 01和電容器C201所構成，並具有汲極D200、源極S200、 控制閘極CG200以及浮動閘極FG2 00。電容器.C201是控 制閘極CG200和浮動閘極FG200之間的電容器》 〇 在構造上，在第45A圖〜第45E圖，符號2001是P型 半導體基板，符號2002是形成於p型半導體基板2001上 的η型井（n-well)，符號2003是電晶體形成部，符號2004 是構成電晶體T201的浮動閘極型電晶體的通道形成部（閘 極區域部），符號2005是成爲電晶體T201之汲極的η型汲 極擴散層，符號2006是成爲電晶體Τ201之源極的η型擴 散層，符號2009是成爲電晶體Τ201之浮動閘極的多晶矽 層，並成爲電容器C2 01的一端。符號2010是連接η型擴 Q 散層2005和金屬配線2012的接點，符號2012是用以拉出 電晶體Τ2 01之汲極D200的金屬配線，符號2013是用以 拉出電晶體Τ201之源極的金屬配線，符號2014是電容器 C201，符號2015是ρ型擴散層，並成爲電容器C1的另一 t-r'f _。 符號20 16是連接ρ型擴散層20 15和控制閘極配線 2019的接點，符號2 02 3是形成於n型井2002上的η型擴 散層，符號2024是連接η型擴散層2023和對η型井2002 供給電壓之金屬配線2025的接點。符號2019是成爲控制 -175- 201010062 閘極配線的金屬配線，符號2020是分離用絕緣氧化膜。 第46A圖及第46B圖係用以說明第45A圖〜第45E圖 所示之記憶胞元之動作的圖。以下，參照第46A圖及第46B 圖，說明其動作。 第46A圖是OTP的情況，第46B圖是MTP的情況。 ❹ 第46A圖所示的動作表是和第46A圖所示的動作表一 樣，只是追加透過金屬配線2025施加於η型井2002的電 壓 CGWell200。因而，省略重複說明，而僅說明電壓 CGWell200。 如第46A圖及第46B圖所示，對施加於η型并2002 的電壓CGWell200，預先設定成總是高電壓，以免由η型 井2002和η型擴散層2023所形成之二極體被順向偏壓。 例如，在電壓CGWell200比控制閘極CG219(電容器2014 的P型擴散層側）之電壓高的情況，因爲對電容器2014的 反相層施加反向偏壓，所以臨限値變成更負値，雖然效率 變成稍差，但是微小，不會成爲大問題。On the left side of the channel injection, the n-type diffusion layer 2015' is placed adjacent to this channel implantation. Further, the control gate wiring 2019 is disposed to face the floating gate 2009 in the left-right direction from the surface of the semiconductor substrate with a predetermined distance therebetween. This control gate wiring 2019 is connected to the word line WL203. In addition, the second metal interconnections 2013 are arranged to face the second n-type diffusion layer 2006 in the left-right direction with a predetermined distance from the surface of the semiconductor substrate. The second metal interconnections 2013 are connected to the second n-type diffusion layer 2006 by the contacts. On the other hand, in the arrangement of the memory cell array, two memory cells are symmetrically arranged in a bilaterally shared n-type diffusion layer 2015' (the memory cell on the left side in the figure), and two of the left and right symmetrically arranged. In the memory cell, two cells (the upper memory cell in the figure) are symmetrically arranged in the vertical direction, and the four memory cells are arranged as a unit in the left-right direction as a memory cell array. On the other hand, the memory cell arrays arranged in the left-right direction in the -168-201010062 column are arranged in parallel in the vertical direction. With such a configuration, the memory cells are efficiently arranged in the arrangement of the source lines for the respective word lines, and the arrangement area of the memory cell array can be reduced. Further, in the twenty-sixth embodiment shown in Fig. 42, in the memory cell (the cell of the cell selected by the bit line BIT202 and the word line WL203), the metal wiring 20 12 is disposed in the transistor forming portion 20 The left side of 03, but the same on the right side, can also be placed on the right side. However, in this example, when the signal is disposed on the right side, since the memory cell size is determined by the interval of the metal wiring 2012, the memory cell size becomes slightly larger. [27th embodiment] Fig. 43 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty-seventh embodiment of the present invention. The nonvolatile semiconductor memory device shown in the figure is an example in which the nonvolatile semiconductor memory device of the eighteenth embodiment shown in Fig. 30 is modified. The difference between the nonvolatile semiconductor memory device shown in Fig. 43 and the nonvolatile semiconductor memory device shown in Fig. 30 is that the memory cell block is different in composition. That is, in the example shown in Fig. 30, the memory array is divided into 8 segments in the row direction in accordance with the number of I/O bits (8 bits in the legend), and is formed in the row direction as an n-bit unit (address). Unit) memory cell block 2100 - 0~2100-7. On the other hand, in the twenty-seventh embodiment shown in Fig. 43, the memory cell array is divided in the row direction by a unit of 1/0 bit number (8 bits in the legend). That is, 'because the pair is rewritten in 8-bit units, so in order to make the arrangement of the arrangement better, the cells are divided into octave units (I/O units) in the row direction. - 201010062 1 ~ 2 1 0 1 - η constitutes a memory cell array. For example, the memory cell block 2 1 0 1 -1 is a memory cell of 8 bits in the row direction and m bits in the column direction Μ 2 1 1 - Ο~Μ21 1 - 7, ..., M2ml - 0~M2ml _ 7 constitutes. As described above, in the nonvolatile semiconductor memory device of the twenty-seventh embodiment, the MTP is used to constitute the cells, and the memory cells are arranged in the row direction by one byte unit (I/O bit number). The unit is composed of memory cell blocks that are selected for row selection. And, in the row direction, the drains of the transistors of the memory cells are commonly connected by the bit lines BIT201-0~BIT20n-7, and the word lines WL201~WL20m set for the respective columns are used along the row direction. The control gate CG200 of the transistor of the memory cells of each column is connected in common. Further, the source of the transistor of the memory cells of each column is commonly connected by the source line S201. Ground this source line S201 to GND ("Ο" V). The column decoders 2200-1 to 2200-m arranged in the respective columns receive the address signals, and generate column selection signals for selecting the memory cells, and select the voltages of the column selection signals in response to the write mode and the erase mode. The level is applied to the word lines WL201 to WL20m. The row decoder 2300 - l~2 300-n is a row decoder set in each of the memory cell blocks 2101 -1 to 2101-n, and selects one memory cell block in the row direction in 8-bit units. The second level shifting circuit 2 3 03 converts the line selection signal output from the line decoder into a signal of the second signal voltage VP202 and outputs it. Further, in each memory cell block, an 8-bit unit row selection transistor i (CG201-0~CG201-7, ..., CG20n-0~CG20n-7) is set, and the row selects the transistor from the second bit. The row selection signal -170-201010062 (the second signal voltage VP202) outputted by the quasi-migration circuit is used as the gate input, and the bit line of one memory cell block is selected, and the memory cell of the 8-bit unit is selected. The bit line of the memory cell block selected by the transistor is selected by this row, and the transistor is selected via the row to be connected to the data output lines D2 0 0 to D207. Further, when the data conversion circuit 2400 receives the input signals Din200 to Din207 of the data to be written in one byte unit and writes the data or erases the data, the data conversion circuit 2400 outputs the data to the memory cells through the data output lines D200 to D207. The third signal voltage VP203 of the drain of the transistor of the element. Further, the sense amplifiers 2500-0 to 2 500-7 amplify the data of the memory cells read out from the data input lines D 2 00 to D207 and output them to the outside. Thus, by using the nonvolatile semiconductor memory device of the present invention, MTP can be constructed, and the memory cell array can be divided in 8-bit units in the row direction, and data can be written and read in 8-bit units. Further, in the example shown in Fig. 43, although an example in which the memory cell array is divided into eight in the order of 8 bits in the row direction has been described, the limitation is not limited to the requirement of the number of I/O bits. The specification is divided into arbitrary bit number units such as a character Q unit (16-bit cell) or a double character (32-bit cell). [Embodiment 28] Fig. 44 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty-eighthth embodiment of the present invention. The nonvolatile semiconductor memory device shown in the figure is an example in which the nonvolatile semiconductor memory device of the twenty first embodiment shown in Fig. 35 is modified. The difference in the configuration between the non-volatile semiconductor memory device shown in Fig. 44 and the non-volatile semiconductor memory device shown in Fig. 5 is that the memory cell structure of the -171 - 201010062 is different. That is, in the example shown in Fig. 35, the memory array is divided in accordance with the number of I/O bits (8 bits) in the row direction to constitute a memory cell block. On the other hand, in the example shown in Fig. 44, the memory cell array is divided in units of I/O bits in the row direction (8 bits in the legend), and is formed in the row direction as n bits. And memory cell block 2100 - 0~2 100 - 7 in units of m bits in the column direction. That is, the 'memory cell, like M211-0~M21n-0.....M211-7~M21n-7, is concentrated in the row direction by the address unit of η bits, and is formed to the memory cell block 2100-0. ~2100-7. The row decoders 2300-1 to 2300_n are set to be η row decoders opposite to the address width η bits of the memory cell blocks 2100-0 to 2100-7. The row decoders 2300 - 1 to 2300 - η are each constituted by an address decoder 2301, an inverter 2302, and a level shifting circuit 2303. The bit shift circuit 2303 converts the row select signal output from the row decoder 2300 - 1-2300 - n into the second signal voltage VP2 02. Row selection transistor CG20 1 - 0~CG20n — 0.....CG201- 0 7~CG2 On- 7 is a row selection transistor for each of the η-bit units set in the memory cell block. The second signal voltage VP202 (signals COL201 to COL20n) output by the 2-bit quasi-migration circuit is used as a gate input, and a bit line of one memory cell block is selected from each cell of the cell, and a total of 8 bits is selected ( The bit line of the memory cell of the I/O bit number). The column decoder 2200 - l 2200-m is constructed in the same manner as the column decoder shown in Fig. 35. Further, a connection method of the bit line BIT201-0 to BIT20n-7 of the memory cell block, a connection method of the word line WL201 to WL20m, and a source line S200 (1, 2) to S200 (m-1, m) The connection method of the circuit-172- 201010062 method, the switching transistor 2209 - 1, 2209 - 2~2209 - (m - 1), 2209 _m is also the same as the circuit shown in Figure 35. That is, the drains of the transistors of the memory cells are commonly connected by the bit lines BIT201-0 to BIT20n-7 along the column direction, and the word lines WL201 to WL20m provided in the respective columns are commonly connected in the row direction. The control gate CG200 of the transistor of each column of memory cells. The source lines of the transistors of the pair of memory cells are connected in common in the row direction by the source lines S200 (1, 2) to S200 (m-1, m) provided in each of the two columns. The source lines are connected in common: the first switching transistor (for example, the switching transistor 2209-1) accepts an opening and closing signal (for example, signal SB201) from one of the columns, and selects to ground the source line to GND (" 0" V) or become an open circuit; and the second switching transistor (such as the switching transistor 22 09 - 2) accepts an open/close signal from another column (for example, signal SB202) and selects to ground the source line to GND. ("0" V) or become an open circuit. The decoders 2200-1 to 2200-m set in each column accept the address signals and generate column selection signals for selecting memory cells, and respond to the write mode. And the erase mode, the voltage level of the column selection signal is selected and applied to the word lines WL201 WL WL20m. Further, each of the column decoders 2200-1 to 2200-m is paired, and is output from one of the column decoders (for example, 2200 to 1) to open and close the first switching transistor (for example, the switching transistor 220 9-1). Signal (eg signal SB201). Further, the second switching transistor (for example, the switching transistor 2209-2) is turned on and off (for example, the signal SB202) from the other column decoder (for example, 2200-2), and the transistor CG201- is selected by the row. 0~CG20n - 0.....CG201 173· 201010062 —07~CG20n — A total of 8 bit lines of the selected memory cell block, through which the transistor is selected, and the data output line D200~ D207 is connected. Further, when the data conversion circuit 2400 receives the input signals Din200 to DU207 of the data to be written in one byte unit, and writes the data and erases the data, the data conversion circuit 2400 is applied to the transmission data input lines D2 00 to D2 07 and applied to The third signal voltage VP203 of the drain of the transistor of the memory cell. Further, the sense amplifier 2500- 0~2 500- 7 amplifies the data of the memory cell read out from the data input line D2 00-D207 and outputs it to the outside. As described above, in the nonvolatile semiconductor memory device of the twenty-eighth embodiment, the memory cells are formed by MTP, and are concentrated in the address direction of n bits in the row direction to form a memory cell block, and the source is shared every two columns. The line is constructed in such a way as to eliminate the wasted area. [Twenty-ninth embodiment] FIG. 45 is a view showing a configuration of a nonvolatile semiconductor memory device (memory cell) according to a twenty-ninth embodiment of the present invention. The difference between the memory cell shown in Fig. 45A to Fig. 45E and the memory cell shown in Fig. 25A to Fig. 25D is to delete the control gate CG200 shown in Fig. 25A to Fig. 25D. (20 1 9) The connected n-type diffusion layer 2017 and the contact 2018 are separated from the n-type well 2002, and the n-type diffusion layer 2023 connected to the n-type well 2002 is newly provided, and the required voltage is supplied to the n-type well 2002. The metal wiring 2 025 of the CGWell 200 and the contact 2024 connecting the n-type diffusion layer 2023 and the metal wiring 2025. The n-type diffusion layer 2 023, the contact 2024, and the metal wiring 2025 can be disposed in the empty space of the memory cell without increasing the area of the memory cell, and deleting the η shown in the 25th to 25th The area of the diffusion layer 2017 and the contact 2018 has a large reduction effect. -174- 201010062 Fig. 45A is a plan view showing the memory cell of the twenty-ninth embodiment. Figure 45B shows an equivalent circuit diagram, Figure 45C shows a cross-sectional view along A20-A20' of Figure 45A, Figure 45D shows a cross-sectional view along B20-B20, and Figure 45E shows along E20-E20' Sectional view. This memory cell is composed of a transistor T2 01 and a capacitor C201 as shown in the equivalent circuit of Fig. 45B, and has a drain D200, a source S200, a control gate CG200, and a floating gate FG2 00. The capacitor C201 is a capacitor between the control gate CG200 and the floating gate FG200. 构造 In construction, in the 45A to 45E, the symbol 2001 is a P-type semiconductor substrate, and the symbol 2002 is formed on the p-type semiconductor substrate 2001. In the n-well, the symbol 2003 is a transistor forming portion, the symbol 2004 is a channel forming portion (gate region portion) of the floating gate type transistor constituting the transistor T201, and the symbol 2005 is a transistor. The n-type drain diffusion layer of the drain of T201, the symbol 2006 is an n-type diffusion layer which becomes the source of the transistor 201, and the symbol 2009 is a polysilicon layer which becomes the floating gate of the transistor 201, and becomes one end of the capacitor C2 01. . The symbol 2010 is a joint connecting the n-type Q-stacked layer 2005 and the metal wiring 2012, the symbol 2012 is a metal wiring for pulling out the drain D200 of the transistor Τ201, and the symbol 2013 is a source for pulling out the transistor Τ201. The pole metal wiring, symbol 2014 is capacitor C201, symbol 2015 is a p-type diffusion layer, and becomes another t-r'f_ of capacitor C1. Reference numeral 20 16 is a junction connecting the p-type diffusion layer 20 15 and the control gate wiring 2019, the symbol 206 2 is an n-type diffusion layer formed on the n-type well 2002, and the symbol 2024 is an n-type diffusion layer 2023 and a pair The n-well 2002 is the junction of the metal wiring 2025 to which the voltage is supplied. Reference numeral 2019 is a metal wiring for controlling the gate wiring of -175 to 201010062, and symbol 2020 is an insulating oxide film for separation. Fig. 46A and Fig. 46B are diagrams for explaining the operation of the memory cell shown in Figs. 45A to 45E. Hereinafter, the operation will be described with reference to Figs. 46A and 46B. Fig. 46A is the case of the OTP, and Fig. 46B is the case of the MTP.动作 The operation table shown in Fig. 46A is the same as the operation table shown in Fig. 46A, except that the voltage CGWell 200 applied to the n-well 2002 through the metal wiring 2025 is additionally added. Therefore, the overlapping description will be omitted, and only the voltage CGWell 200 will be described. As shown in FIGS. 46A and 46B, the voltage CGWell 200 applied to the n-type and 2002 is preset to always be a high voltage so that the diode formed by the n-type well 2002 and the n-type diffusion layer 2023 is prevented from being cis. Bias bias. For example, in the case where the voltage CGWell 200 is higher than the voltage of the control gate CG219 (the P-type diffusion layer side of the capacitor 2014), since the reverse bias is applied to the inversion layer of the capacitor 2014, the threshold 値 becomes more negative, although Efficiency becomes a bit worse, but it is not a big problem.
此外，在第45A圖〜第45E圖所示的第29實施形態， 雖然將金屬配線2012電晶體形成部2003的左側，但是亦 可配置於右側。 此外，在第45人圖~第45E圖所示之第29實施形態的 非揮發性半導體記憶元件，η型擴散層2005相當於上述之 成爲電晶體之汲極的第In型擴散層，η型擴散層2006相 當於上述之第2η型擴散層，η型擴散層2 02 3相當於上述 之第4η型擴散層。又，第In型擴散層2 00 5和第2η型擴 散層2006之間的區域相當於上述的閘極區域部，金屬配線 -176- 201010062 20 12相當於上述的第1金屬配線，金屬配線2 025相當於 上述的第3金屬配線。 又，在對浮動閘極儲存電荷時（寫入時），第46A圖所 示之控制閘極CG200的電壓“ 6” V相當於上述之施加於 第1電晶體之閘極的第1高電壓，汲極D200的電壓“ 5” V 相當於上述之施加於汲極D200的第2電壓。又，第46B 圖所示之汲極D200的電壓“ 8” V相當於在上述之第1拭 除部施加於汲極D200的第3電壓，源極S200的電壓“2” V Ο 相當於在上述之施加於源極S200的第4電壓。又，第46B 圖所示之控制閘極CG200的電壓“ 1” V相當於在上述之 第2拭除部施加於控制閘極CG200的第5電壓。 而，在半導體基板表面上的第1方向（在第45 A圖上爲 上下方向），配置形成電晶體的電晶體形成部2 003，此電晶 體形成部2 003由上依序配置：成爲電晶體T2 01之汲極的 第In型擴散層2 005、形成通道的閘極區域部2004(第1擴 散層2005和第2擴散層2006之中間的區域）、以及成爲電 〇 晶體T201之源極的第2n型擴散層2006。 在此電晶體形成部200 3的左側，在上下方向配置金屬 配線2012。此金屬配線2012從半導體基板表面隔著既定 之距離配置成和電晶體形成部2 003平行，又，金屬配線 2012利用接點2010和電晶體T2 01的汲極（第In型擴散層 2005)連接。 在電晶體形成部2003的左側，以既定之寬度和深度在 左右方向所形成η型井2 002。方形的浮動閘極2009在左 右方向配置成和半導體基板表面相對向，同時配置成其左 -177- 201010062 端部側的區域和η型井2002的表面相對向，而且右端部側 的區域和電晶體Τ201的閘極區域部2004(第In型擴散層 2005和第2n型擴散層2006之中間的通道形成區域）相對 向。Further, in the twenty-ninth embodiment shown in Figs. 45A to 45E, the left side of the metal wiring 2012 transistor forming portion 2003 may be disposed on the right side. Further, in the nonvolatile semiconductor memory device of the twenty-ninth embodiment shown in the 45th to 45thth, the n-type diffusion layer 2005 corresponds to the first In-type diffusion layer which becomes the drain of the transistor, and the n-type The diffusion layer 2006 corresponds to the above-described second n-type diffusion layer, and the n-type diffusion layer 203 3 corresponds to the above-described fourth n-type diffusion layer. Further, a region between the first In-type diffusion layer 2 00 5 and the second n-type diffusion layer 2006 corresponds to the above-described gate region portion, and the metal wiring -176 - 201010062 20 12 corresponds to the first metal wiring described above, and the metal wiring 2 025 corresponds to the third metal wiring described above. Further, when the charge is stored in the floating gate (at the time of writing), the voltage "6" V of the control gate CG200 shown in Fig. 46A corresponds to the first high voltage applied to the gate of the first transistor. The voltage "5" V of the drain D200 corresponds to the second voltage applied to the drain D200 described above. Further, the voltage "8" V of the drain D200 shown in Fig. 46B corresponds to the third voltage applied to the drain D200 in the first erasing portion, and the voltage "2" V 源 of the source S200 corresponds to The fourth voltage applied to the source S200 is as described above. Further, the voltage "1" V of the control gate CG200 shown in Fig. 46B corresponds to the fifth voltage applied to the control gate CG200 in the second erasing portion. On the other hand, in the first direction on the surface of the semiconductor substrate (in the upper and lower directions in FIG. 45A), a transistor forming portion 2003 in which a transistor is formed is disposed, and the transistor forming portion 2003 is sequentially arranged from above: The first In-type diffusion layer 2 005 of the drain of the crystal T2 01, the gate region portion 2004 forming the channel (the region between the first diffusion layer 2005 and the second diffusion layer 2006), and the source of the electric crystal T201 The 2n-type diffusion layer 2006. On the left side of the transistor forming portion 200 3, the metal wiring 2012 is disposed in the vertical direction. The metal wiring 2012 is disposed in parallel with the transistor forming portion 2 003 from the surface of the semiconductor substrate at a predetermined distance, and the metal wiring 2012 is connected by the contact 2010 and the drain of the transistor T2 01 (the In-type diffusion layer 2005). . On the left side of the transistor forming portion 2003, an n-type well 2 002 is formed in the left-right direction with a predetermined width and depth. The square floating gate 2009 is disposed in the left-right direction so as to face the surface of the semiconductor substrate while being disposed such that the region on the end side of the left-177-201010062 is opposite to the surface of the n-type well 2002, and the region on the right end side is electrically The gate region portion 2004 of the crystal germanium 201 (the channel formation region between the first in-type diffusion layer 2005 and the second n-type diffusion layer 2006) faces each other.
在η型井2002之左側，在左右方向形成p型擴散層 2015，其和與此η型井2002的浮動閘極2009相對向之區 域的左側相鄰，並具有既定之寬度和深度。此ρ型擴散層 2015和控制閘極配線2019利用接點2016連接。此控制閘 極配線2019從半導體基板表面隔著既定之距離在左右方 向配置成和浮動閘極2009相對向，又，利用接點2016和 Ρ型擴散層2015連接。第2金靥配線2013從半導體基板 表面隔著既定之距離在左右方向配置成和成爲電晶體 Τ201之源極的第2型擴散層2006相對向，此第2金屬配 線2013利用接點2011和第2η型擴散層2006連接。On the left side of the n-type well 2002, a p-type diffusion layer 2015 is formed in the left-right direction adjacent to the left side of the region opposite to the floating gate 2009 of the n-type well 2002, and has a predetermined width and depth. This p-type diffusion layer 2015 and the control gate wiring 2019 are connected by a contact 2016. The control gate wiring 2019 is disposed to face the floating gate 2009 in the left-right direction with a predetermined distance from the surface of the semiconductor substrate, and is connected to the 扩散-type diffusion layer 2015 by the contact 2016. The second metal wiring 2013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the second type diffusion layer 2006 serving as the source of the transistor 201, and the second metal wiring 2013 uses the contact point 2011 and the first The 2n-type diffusion layer 2006 is connected.
又，在Ρ型擴散層2015的上側且第In型擴散層之左 側的位置’以既定之寬度和深度形成第4n型擴散層2 02 3。 而且’設置第3金屬配線2025，其從半導體基板表面隔著 既定之距離配置成和電晶體形成部2003平行，此金屬配線 2025和第4n型擴散層2023利用接點2024連接。利用此 金屬配線2025和n型擴散層2023，對n型井2002供給所 要之電位。 利用這種構成’以標準邏輯元件的CMOS製程可實現 非揮發性記億體，同時可實現OTP或MTP。又，可緊密地 配置面積變大的電容器（在浮動閘極和半導體基板表面所 形成之電容器），使面積變成最小限度。此外，可將對η型 -178- 201010062 井供給既定之電壓CGWell 100的η型擴散層和金屬配線配 置於空的空間，而可更縮小記億胞元的面積。 [第30實施形態] 第47圖係表示本發明之第30實施形態的非揮發性半 導體記憶裝置的構成圖。第47圖所示的例子是將本發明的 非揮發性半導體記憶元件（記憶胞元）裝入陣列（記憶胞元 陣列）的例子，是ΟΤΡ之情況的例子。 在第47圖所示的例子，作爲記億陣列之構成，輸出入 〇 I/O採用10 — 0~1〇— 7之8位元構成，記憶陣列由在行方 向爲η位元、在列方向爲m位元之單位的記憶胞元方塊 2100-0~2100 — 7 所構成。 即，^憶胞元如 M211— 0〜M21n - 0、M211- 7〜M21n -7般，在行方向以η位元的位址單位集中，而構成至記 憶胞元方塊2100 — 0-2100 — 7。因此，成爲m列χη行χ8位 元的記憶容量。 列解碼器2200- 1〜2200 - m各自由位址解碼器2201、 Q 反相器2202以及位準挪移電路2203所構成。又，位準挪 移電路2203的輸出各自成爲字元線WL2 01~WL2 0m的輸出 信號。 因爲OTP無拭除，所以可在列方向共同連接字元線。 例如，字元線WL201和記憶胞元M211-0~M21n — 0、M211 —7〜M21n-7全部共同連接。對於字元線WL2 0m亦一樣。 行解碼器2300-l~2300-n亦和列解碼器一樣，各自 由位址解碼器2301、反相器2302以及位準挪移電路2303 所構成。位準挪移電路2303將從行解碼器2300— 1 -2 300 -179- 201010062 — η所輸出之行選擇信號變換成第2信號電壓VP202。 此位準挪移電路23 03的輸出各自成爲信號COL201~ COL20n’各自輸入行選擇電晶體 CG201 — 〇~ CG201 _ 7.....CG20n - 0〜CG20n - 7的閘極。例如，行解碼器2300 —1的輸出成爲行選擇電晶體CG2 01— 0〜CG201-7的閘 極輸入信號。 記憶胞元的汲極所連接之位元線BIT201- 0-BIT201 一7經由行選擇電晶體CG201— 0~ CG201 - 7,各自和資料 線 D200-D207 連接。 一樣地，位元線BIT20n— 0〜BIT20n— 7經由行選擇電 晶體CG20n_0~ CG20n-7，各自和資料線D200~D207連 接。 在資料線D200-D207，連接用以接受寫入輸入資料 Din200~Din207並輸出寫入資料（寫入電壓5V)的資料變換 電路24 0 0、及用以接受讀出時之記憶胞元的資料並將信號 放大輸出之成爲讀出輸出電路的感測放大電路25 00 — 0~2500 - 7。 其次，說明動作。 在寫入時，例如若選擇列解碼器2200 - 1及行解碼器 2300 — 1’則選擇字元線WL2 0 1及信號COL2 01，各個被施 加6V(第1信號電壓乂1>201)及8V(第2信號電壓¥1>2〇2)的 電壓。又’此時，對應於寫入資料Din2 00〜Din207，自資 料變換電路24〇〇向資料輸入線D200〜D207輸出寫入電壓5 V(第3信號電壓VP203)。 假設輸入 在此’作爲寫入資料 ， -180- 201010062 「Din200 = Din202 = Din204 = Din206= “ 0” 資料（寫入資 料）」、「Din201=Din203 = Din205 = Din207= “ 1"資料（不寫 入資料）」。 在此情況，在資料線 D200〜D207 ，輸出 「 D200 = D202 = D204 = D206 = 5 V 」 、 「 D201=D2O3=D205=D207=0V」，因爲信號 COL201 被選 擇而變成 8V，所以位元線的信號電壓變成「81了20 1-0 = BIT201 - 2 = BIT201 - 4 = BIT20 1 — 6 = 5V」、「BIT201-O 1=BIT201- 3=BIT201- 5=BIT201- 7= 0V」，對記憶胞元 M21 1 — 0、M2U — 2、M21 1 - 4、M21 1 — 6 進行寫入，對記 憶胞元 M211-1、M211— 3、M211— 5、M211— 7 不進行寫 入。如此，可對任意的記憶胞元寫入任意的資料。 讀出時，因爲若所選擇的記憶胞元是拭除狀態 ("1” ；導通），電流流向記憶胞元，若是寫入狀態（“ 〇” ； 不導通），電流不流動，所以利用感測放大電路2 5 0 0進行 放大、判定，並輸出資料Dout200〜Dout207。此外，此電 〇 路是OTP，雖然一般不進行記憶胞元之資料的拭除，但是 在發生需要拭除記憶胞元的情況，將所選擇之控制閘極 WL200設爲0V，並經由所選擇的列解碼器對汲極施加8V 即可。 此外，第49A圖表示在上述之寫入動作的動作表。如 圖所示，將施加於金屬配線2025之電壓CGWell200設定 成總是和控制閘極CG200(字元線）的電壓相等或更大。 此外’在第47圖所示之第31實施形態的非揮發性半 導體記憶元件，位準挪移電路2203相當於上述之第1位準 -181- 201010062 挪移電路，位準挪移電路2303相當於上述之第2位準挪移 電路。 而，在第31實施形態的非揮發性半導體記憶裝置，作 爲其構成，配置複數個記憶胞元方塊2100-0~2100-7’ 其根據行位址η位元（η 2 1)、及io位元（i〇 2 1)的輸出入I/O 位元數，例如8位元，而將記憶胞元陣列在行方向以行位 址η位元單位，分割成該I/O位元數而構成。Further, the fourth n-type diffusion layer 203 is formed at a predetermined width and depth at a position on the upper side of the 扩散-type diffusion layer 2015 and on the left side of the NMOS diffusion layer. Further, the third metal wiring 2025 is disposed so as to be parallel to the transistor forming portion 2003 from the surface of the semiconductor substrate with a predetermined distance therebetween. The metal wiring 2025 and the fourth n-type diffusion layer 2023 are connected by a contact 2024. The n-well 2002 is supplied with a desired potential by the metal wiring 2025 and the n-type diffusion layer 2023. With this configuration, a non-volatile memory can be realized by a CMOS process using standard logic elements, and OTP or MTP can be realized. Further, a capacitor having a large area (a capacitor formed on the floating gate and the surface of the semiconductor substrate) can be closely arranged to minimize the area. In addition, the n-type diffusion layer and the metal wiring for supplying the n-type -178-201010062 well to the predetermined voltage CGWell 100 can be placed in an empty space, and the area of the billion cells can be further reduced. [30th embodiment] Fig. 47 is a view showing the configuration of a nonvolatile semiconductor memory device according to a 30th embodiment of the present invention. The example shown in Fig. 47 is an example in which the nonvolatile semiconductor memory device (memory cell) of the present invention is incorporated in an array (memory cell array), which is an example of the case. In the example shown in Fig. 47, as a configuration of the mega array, the input/output I/O is composed of 8-bits of 10 - 0 to 1 〇 -7, and the memory array is η bits in the row direction, in the column The memory cell block 2100-0~2100-7 is composed of m-bit units. That is, the memory cells such as M211-0~M21n-0, M211-7~M21n-7 are concentrated in the row direction by the address unit of η bits, and are formed to the memory cell block 2100 — 0-2100 — 7. Therefore, the memory capacity of the m-column χ χ χ 8 bits is obtained. The column decoders 2200-1 to 2200-m are each constituted by an address decoder 2201, a Q inverter 2202, and a level shift circuit 2203. Further, the outputs of the level shift circuit 2203 are output signals of the word lines WL2 01 to WL2 0m, respectively. Since the OTP is not erased, the word lines can be connected in the column direction. For example, the word line WL201 and the memory cells M211-0~M21n-0, M211-7~M21n-7 are all connected in common. The same is true for the word line WL2 0m. The row decoders 2300-1 to 2300-n are also constituted by the address decoder 2301, the inverter 2302, and the level shift circuit 2303, similarly to the column decoder. The level shift circuit 2303 converts the row selection signal output from the row decoders 2300-1 - 2 300 - 179 - 201010062 - η into the second signal voltage VP 202. The outputs of the level shifting circuit 23 03 are respectively gates of the input row selection transistors CG201 - 〇 CG201 _ 7..... CG20n - 0 to CG20n - 7 of the signals COL201 to COL20n'. For example, the output of the row decoder 2300-1 becomes the gate input signal of the row selection transistors CG2 01-0 CG201-7. The bit line BIT201- 0-BIT201-7 connected to the drain of the memory cell is connected to the data line D200-D207 via the row selection transistors CG201-0~ CG201-7. Similarly, the bit lines BIT20n-0 to BIT20n-7 are connected to the data lines D200 to D207 via the row selection transistors CG20n_0 to CG20n-7. In the data line D200-D207, a data conversion circuit 240 for accepting the write input data Din200 to Din207 and outputting the write data (write voltage 5V), and data for accepting the memory cell at the time of reading are connected. The signal is amplified and outputted into a sense amplifier circuit 25 00 — 0~2500 - 7 of the read output circuit. Next, explain the action. At the time of writing, for example, if the column decoder 2200-1 and the row decoder 2300-1' are selected, the word line WL2 0 1 and the signal COL2 01 are selected, and 6 V (first signal voltage 乂 1 > 201) is applied. The voltage of 8V (second signal voltage ¥1>2〇2). Further, at this time, the self-input conversion circuit 24 outputs a write voltage of 5 V (third signal voltage VP203) to the data input lines D200 to D207 in response to the write data Din2 00 to Din207. Suppose the input is here as 'written data, -180- 201010062 "Din200 = Din202 = Din204 = Din206= "0" data (write data)", "Din201=Din203 = Din205 = Din207= "1" data (do not write Enter the information)". In this case, on the data lines D200 to D207, "D200 = D202 = D204 = D206 = 5 V" and "D201 = D2O3 = D205 = D207 = 0V" are output, because the signal COL201 is selected to become 8V, so the bit line The signal voltage becomes "81. 20 1-0 = BIT201 - 2 = BIT201 - 4 = BIT20 1 - 6 = 5V", "BIT201-O 1 = BIT201 - 3 = BIT201 - 5 = BIT201 - 7 = 0V", right The memory cells M21 1 - 0, M2U - 2, M21 1 - 4, and M21 1 - 6 are written, and the memory cells M211-1, M211-3, M211-5, and M211-7 are not written. In this way, any data can be written to any memory cell. When reading, because if the selected memory cell is in the erase state ("1"; conduction), the current flows to the memory cell, and if it is in the write state ("〇"; non-conducting), the current does not flow, so the use The sense amplifier circuit 2500 performs amplification and determination, and outputs data Dout200~Dout207. In addition, the power path is OTP, although the data of the memory cell is generally not erased, but the memory cell needs to be erased. In the case of the element, the selected control gate WL200 is set to 0 V, and 8 V is applied to the drain via the selected column decoder. Further, Fig. 49A shows an operation table of the above-described write operation. As shown, the voltage CGWell 200 applied to the metal wiring 2025 is set to be equal to or greater than the voltage of the control gate CG200 (character line). Further, the non-volatile portion of the 31st embodiment shown in Fig. 47 is shown. The semiconductor memory device, the level shifting circuit 2203 corresponds to the first level -181 - 201010062 shifting circuit described above, and the level shifting circuit 2303 corresponds to the second level shifting circuit described above. The non-volatile portion of the 31st embodiment As a semiconductor memory device, a plurality of memory cell blocks 2100-0 to 2100-7' are arranged, which are input and output according to a row address η bit (η 2 1) and an io bit (i 〇 2 1). The number of I/O bits, for example, 8 bits, is formed by dividing the memory cell array in the row direction by the row address η bit unit into the number of I/O bits.
而且，構成爲具有：複數條位元線ΒΙΤ201-0〜BIT20bn - 7,係沿著列方向共同連接各記憶胞元之電晶體的汲極； 字元線WL201~WL20m，係在各列所設置之字元線，並沿 著行方向共同連接各記憶胞元之電晶體的控制閘極；源極 線S200，係共同連接各記憶胞元之電晶體的源極；列解碼 器2200 — 1〜2 200 _ m，係在各列所設置之列解碼器，接受 位址信號並產生該記憶胞元的列選擇信號；第1位準挪移 電路2203，係將從各列解碼器所輸出之列選擇信號變換成 施加於該字元線之第1信號電壓VP201的信號；η個行解 碼器2300- 1〜2300— η，係對應於在記憶胞元方塊之行方 向的位元數η所設置的行解碼器，並輸出從各該記憶胞元 方塊選擇1個記憶胞元的行選擇信號；第2位準挪移電路 23 03,係將從各行解碼器所輸出之行選擇信號變換成第2 信號電壓VP2 02的信號；行選擇電晶體CG201—0〜CG20n 係對各個記憶胞元方塊所設置之η位元單位的行選擇 電晶體，將從第2位準挪移電路2303所輸出之第2信號電 壓VP2 02作爲閘極輸入，並從各記憶胞元方塊選擇1個記 憶胞元的位元線，以選擇該I/O位元數的記憶胞元；該I/O -182- 201010062 位元數的資料輸出入線D200~D207，係經由該行選擇電晶 體而連接由行選擇電晶體所選擇之該I/O位元數的位元 線；資料變換電路2400，係在接受I/O位元數之寫入資料 的輸入信號，並進行資料的寫入及資料的拭除時，輸出透 過該資料輸出入線而施加於電晶體之汲極的第3電壓信號 VP203 ；以及感測放大電路 2500，係將資料輸出入線 D2 00〜D20 7所讀出之記憶胞元的資料放大並向外部輸出。 因而，使用第45 A圖〜第45E圖所示的非揮發性半導 Ο 體記憶元件，可實現OTP。又，可緊密地配置面積變大的 電容器（在浮動閘極和半導體基板表面所形成之電容器）， 並使面積變成最小限度。此外，可將對η型井2002供給所 要之電壓CGWell200的η型擴散層2023和金屬配線2 02 5 配置於空的空間，而可更加縮小記億胞元的面積。 以上，作爲本發明之第30實施形態，雖然說明使用第 45 Α圖〜第45Ε圖所示的非揮發性半導體記憶元件，構成 OTP的情況，但是未限定如此，可構成其他之構成的OTP 〇 或 MTP。 例如，和第3 1圖所示的第1 9實施形態、或第44圖所 示的第2 8實施形態一樣，可構成將記憶胞元陣列在行方向 以η位元的位址單位集中的MTP。又，和第34圖所示的第 20實施形態一樣，可構成將記憶胞元陣列在行方向以I/O 位元單位（例如8位元）集中的ΜΤΡ。此外，和第43圖所示 的第27實施形態一樣，可構成將記憶胞元陣列在行方向以 I/O位元單位（例如8位元）集中的ΟΤΡ。 第49Β圖表示利用第45Α圖~第45Ε圖所示的非揮發 -183- 201010062 性半導體記憶元件構成OTP及MTP之情況的動作表。 [第31實施形態] 第48圖係表示本發明之第31實施形態的非揮發性半 導體記憶裝置的構成圖，表示記憶胞元陣列的布置配置。 第48圖所示之記憶胞元陣列的布置是將第45Α圖〜第 45Ε圖所示的非揮發性半導體記憶元件（記憶胞元）配置成 陣列狀，此記憶胞元如上述所示，具有：用以和η型井20〇2 連接的η型擴散層2023、對η型井供給既定之電壓 CGWell200的金屬配線2025、以及連接η型擴散層2023 和金屬配線2025的接點2024。 而，在第 48圖所示的記憶胞元陣列，使字元線 WL201、字元線WL202、字元線WL203.....以及源極線 S201(S201、 202)、 S201(S203、 204)、…在橫向通過，使 位元線BIT201、BIT202、BIT203、…在縱向通過，又，使 金屬配線2025在縱向通過。而且，以金屬配線2025爲中 心左右對稱地配置、並以源極線S201爲中心上下對稱地配 置第45A圖〜第45E圖所示的記憶胞元單元單元，又，使 彼此共用η型井1002，以縮小面積。此η型井2002是由2 行的記憶胞元（例如汲極和位元線ΒΙΤ201及位元線ΒΙΤ202 連接之2行的記憶胞元）所共用的η型井，此η型井20 0 2 利用形成於η型井2002之複數個位置的η型擴散層2023 和接點2024和金屬配線2025連接。 而，例如著眼於在第48圖以虛線所包圍之部分Α200 0 的記憶胞元（由字元線WL201和位元線ΒΙΤ202所選擇的記 憶胞元），說明以此布置所配置的記憶胞元時，在圖上之上 -184- 201010062 下方向所配置的電晶體形成部2003，包含有：成爲電晶體 之汲極的第In型擴散層2005、形成電晶體之通道的閘極 區域部（第1擴散層2 00 5和第2擴散層20 06之中間的區 域）、以及成爲電晶體之源極的第2n型擴散層2006。 在此電晶體形成部2003的左側，在上下方向配置第1 金屬配線2012。此金屬配線2012從半導體基板表面隔著 既定之距離配置成和電晶體形成部2003平行，又，金屬配 線2012利用接點2010和電晶體的汲極（第In型擴散層 〇 2005)連接。此第1金屬配線2012和位元線BIT202連接。 方形的浮動閘極2009在左右方向配置成和半導體基 板表面相對向，同時配置成其左端部側的區域和η型井 2 0 02的表面相對向，且右端部側的區域和閘極區域部（第 In型擴散層2005和第2η型擴散層20 06之中間的通道形 成區域）相對向。 在η型井2002的左側，在左右方向形成ρ型擴散層 2015，其和與此η型井2002的浮動閘極2009相對向之區 Q 域的左側相鄰，並具有既定之寬度和深度。此ρ型擴散層 20 1 5和控制閘極配線20 1 9利用接點20 1 6連接。此控制閘 極配線2019從半導體基板表面隔著既定之距離在左右方 向配置成和浮動閘極2009相對向，又，利用接點2016和 Ρ型擴散層2015連接。控制閘極配線2019和共用的字元 線WL201連接。 第2金屬配線2013從半導體基板表面隔著既定之距離 在左右方向配置成和成爲電晶體Τ201之源極的第2η型擴 散層2006相對向，此第2金屬配線2013利用接點2011和 -185- 201010062 第2n型擴散層2 00 6連接。此第2金屬配線2013和共用的 源極線S20 1連接。 又，在P型擴散層2015的上側且第2η型擴散層2006 之左側的位置，以既定之寬度和深度形成第4η型擴散層 2023,將第3金屬配線2025從半導體基板表面隔著既定之 距離在左右方向配置成第1金屬配線2012平行。此第3金 屬配線2025利用接點2024和第4η型擴散層2023連接。 而，在第48圖所示的非揮發性半導體記憶裝置，將合 計4個記憶胞元作爲配置的基本單位，其中2個記憶胞元 (由ΒΙΤ201、WL201及ΒΙΤ2 02、WL201所選擇的2個記憶 胞元）彼此共用η型井2002，並以金屬配線2025爲中心左 右對稱地配置，其他2個記憶胞元相對於該左右對稱地配 置之2個記憶胞元，彼此共用共同的源極線S201並在下方 向對稱地配置。 而且，在左右方向平行地排列配置，同時在上下方向 亦平行地排列配置成爲此配置之基本單位的4個記憶胞 元。 因而，可緊密地配置第45Α圖〜第45Ε圖所示的非揮 發性半導體記憶元件，並可使非揮發性半導體記憶裝置之 面積變成最小限度。 如以上之說明所示，在本發明之非揮發性半導體記憶 元件及非揮發性半導體記憶裝置，以標準邏輯元件的 CMOS製程可實現非揮發性記憶體，並可簡單且便宜地實 現邏輯元件混載記億體。 首先，本發明之第32~第36之各實施形態的特徵爲將 -186- 201010062 複數個浮動閘極型電晶體設置於1個非揮發性半導體記憶 胞元。在其說明之前，在此首先，參照第50A圖〜第50圖， 使用將一個浮動閘極型電晶體設置於1個胞元的構.造，說 明在本發明之第32~第36之各實施形態所使用之非揮發性 半導體記憶胞元的基本構造、動作。第50A圖表示非揮發 性半導體記憶體（EEPROM胞元）的平面圖。第50B圖表示 等價電路圖，第50C圖表示沿著第50A圖之A30— A30’ 的剖面圖，第50D圖表示沿著B30— B30’的剖面圖，第 〇 50E圖表示沿著C30— C30’的剖面圖。此EEPROM胞元如 第50B圖的等價電路所示，由串接之電晶體T301、電晶體 T3 02以及電容器C301所構成。在此，電晶體T3 01是用以 選擇記億胞元的開關（選擇電晶體），電晶體T3 02是浮動閘 極型電晶體。在此記憶胞元，電晶體T3 01的汲極成爲記憶 胞元的汲極D300，電晶體T302的源極成爲記憶胞元的源 極S300，電晶體T301的閘極成爲用以選擇該記憶胞元的 選擇閘極SG300，一端和電晶體T3 02的浮動閘極FG300 ©連接之電容器C301的另一端成爲用以控制該記憶胞元之 記憶內容的控制閘極CG3 00。此電容器C301是控制閘極 CG300和浮動閘極FG300之間的電容器。 在第50八圖~第50E圖，符號3001是p型半導體基板， 符號3002是形成於p型半導體基板3001上的η型井（以下 亦記爲n-well)，符號3 003是構成電晶體Τ301的電晶體（ρ 型半導體基板3 00 1的部分和氧化膜），符號3 004是構成電 晶體T3 02的浮動閘極型電晶體（ρ型半導體基板3001的部 分和氧化膜），符號3005是電晶體T301的η型汲極擴散 -187- 201010062Further, the method has a plurality of bit lines ΒΙΤ201-0 to BIT20bn-7, which are connected to the drains of the transistors of the memory cells in the column direction; the word lines WL201 to WL20m are set in the respective columns. The word line, and the control gates of the transistors of the memory cells are connected in the row direction; the source line S200 is a source connecting the transistors of the memory cells; the column decoder 2200-1~ 2 200 _ m, which is a column decoder set in each column, receives an address signal and generates a column selection signal of the memory cell; the first level shifting circuit 2203 is a column output from each column decoder The selection signal is converted into a signal applied to the first signal voltage VP201 of the word line; n row decoders 2300-1 to 2300-n are set corresponding to the number of bits η in the row direction of the memory cell block. a row decoder, and outputting a row selection signal for selecting one memory cell from each of the memory cell blocks; the second bit shifting circuit 23 03 converts the row selection signal outputted from each row of decoders into a second Signal voltage VP2 02 signal; row selection transistor CG201-0~CG 20n is a row selection transistor of η bit units set for each memory cell block, and the second signal voltage VP2 02 outputted from the second level shifting circuit 2303 is used as a gate input, and is derived from each memory cell. The block selects a bit line of one memory cell to select the memory cell of the I/O bit number; the data of the I/O-182-201010062 bit number is input to the line D200~D207, and the row is selected through the row. The transistor is connected to the bit line of the number of I/O bits selected by the row selection transistor; the data conversion circuit 2400 is an input signal for writing data of the I/O bit number, and performing data When the writing and data are erased, the third voltage signal VP203 applied to the drain of the transistor through the data input and output line is output; and the sense amplifier circuit 2500 reads the data output line D2 00 to D20 7 The data of the memory cell is amplified and output to the outside. Therefore, the OTP can be realized by using the nonvolatile semiconductive memory element shown in Figs. 45A to 45E. Further, a capacitor having a large area (a capacitor formed on the floating gate and the surface of the semiconductor substrate) can be closely arranged, and the area can be minimized. Further, the n-type diffusion layer 2023 and the metal wiring 205 5 which supply the required voltage CGWell 200 to the n-type well 2002 can be disposed in an empty space, and the area of the cells can be further reduced. As described in the thirtieth embodiment of the present invention, the non-volatile semiconductor memory device shown in Figs. 45 to 45 is used to constitute the OTP. However, the present invention is not limited thereto, and other configurations of the OTP can be configured. Or MTP. For example, similarly to the ninth embodiment shown in FIG. 31 or the twenty-eighth embodiment shown in FIG. 44, it is possible to configure the memory cell array to be concentrated in the row direction by η bits. MTP. Further, similarly to the twentieth embodiment shown in Fig. 34, it is possible to configure the memory cell array to be concentrated in I/O bit units (e.g., 8-bit units) in the row direction. Further, similarly to the twenty-seventh embodiment shown in Fig. 43, it is possible to configure the memory cell array to be concentrated in I/O bit units (e.g., 8-bit units) in the row direction. Fig. 49 is a diagram showing the operation of the case where the non-volatile -183-201010062 semiconductor memory device shown in Fig. 45 to Fig. 45 is used to form OTP and MTP. [31st embodiment] Fig. 48 is a view showing the configuration of a nonvolatile semiconductor memory device according to a 31st embodiment of the present invention, showing an arrangement arrangement of memory cell arrays. The memory cell array shown in FIG. 48 is arranged such that the non-volatile semiconductor memory elements (memory cells) shown in FIGS. 45 to 45 are arranged in an array, and the memory cell has the above-described : an n-type diffusion layer 2023 connected to the n-type well 20〇2, a metal wiring 2025 for supplying a predetermined voltage CGWell200 to the n-type well, and a contact 2024 connecting the n-type diffusion layer 2023 and the metal wiring 2025. On the other hand, in the memory cell array shown in FIG. 48, the word line WL201, the word line WL202, the word line WL203....., and the source line S201 (S201, 202), S201 (S203, 204) are caused. In the lateral direction, the bit lines BIT201, BIT202, BIT203, ... are passed in the longitudinal direction, and the metal wiring 2025 is passed in the longitudinal direction. In addition, the memory cell unit units shown in FIGS. 45A to 45E are arranged symmetrically about the metal line 2025 and centered on the source line S201, and the n-type well 1002 is shared with each other. To reduce the area. The n-type well 2002 is an n-type well shared by two rows of memory cells (for example, two rows of memory cells connected by a drain and a bit line 201 and a bit line 202), and the n-type well 20 0 2 The n-type diffusion layer 2023 and the contact 2024 formed at a plurality of positions formed in the n-type well 2002 are connected to the metal wiring 2025. For example, focusing on a memory cell (the memory cell selected by the word line WL201 and the bit line 202) surrounded by a dotted line in FIG. 48, the memory cell configured by this arrangement is explained. In the case where the transistor forming portion 2003 disposed in the lower direction of -184 to 201010062 in the upper surface of the drawing includes the first In-type diffusion layer 2005 which becomes the drain of the transistor, and the gate region which forms the channel of the transistor ( A region between the first diffusion layer 2 00 5 and the second diffusion layer 208 and a second n-type diffusion layer 2006 serving as a source of the transistor. On the left side of the transistor forming portion 2003, the first metal wiring 2012 is placed in the vertical direction. The metal wiring 2012 is disposed in parallel with the transistor forming portion 2003 from the surface of the semiconductor substrate at a predetermined distance, and the metal wiring 2012 is connected to the drain of the transistor (the first in-type diffusion layer 〇 2005) by the contact 2010. This first metal wiring 2012 is connected to the bit line BIT202. The square floating gate 2009 is disposed in the left-right direction so as to face the surface of the semiconductor substrate while being disposed such that the region on the left end side thereof faces the surface of the n-type well 206, and the region on the right end side and the gate region portion (The channel formation region between the first In-type diffusion layer 2005 and the second n-type diffusion layer 2020) faces each other. On the left side of the n-type well 2002, a p-type diffusion layer 2015 is formed in the left-right direction adjacent to the left side of the region Q region opposite to the floating gate 2009 of the n-type well 2002, and has a predetermined width and depth. The p-type diffusion layer 20 15 and the control gate wiring 20 1 9 are connected by a contact 20 16 . The control gate wiring 2019 is disposed to face the floating gate 2009 in the left-right direction with a predetermined distance from the surface of the semiconductor substrate, and is connected to the 扩散-type diffusion layer 2015 by the contact 2016. The control gate wiring 2019 is connected to the common word line WL201. The second metal wiring 2013 is disposed in the left-right direction from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 2006 serving as the source of the transistor 201, and the second metal wiring 2013 uses the contacts 2011 and -185. - 201010062 2n type diffusion layer 2 00 6 connection. This second metal interconnection 2013 is connected to the common source line S20 1 . Further, on the upper side of the P-type diffusion layer 2015 and on the left side of the second n-type diffusion layer 2006, the fourth n-type diffusion layer 2023 is formed with a predetermined width and depth, and the third metal interconnection 2025 is separated from the surface of the semiconductor substrate. The distance is arranged in the left-right direction so that the first metal wires 2012 are parallel. The third metal wiring 2025 is connected to the fourth n-type diffusion layer 2023 by a contact 2024. On the other hand, in the non-volatile semiconductor memory device shown in Fig. 48, a total of four memory cells are used as the basic unit of configuration, and two memory cells (two selected by ΒΙΤ201, WL201, ΒΙΤ02, WL201) The memory cells share the n-type well 2002, and are arranged symmetrically about the metal wiring 2025. The other two memory cells share a common source line with respect to the two memory cells symmetrically arranged. S201 is symmetrically arranged in the lower direction. Further, the memory cells are arranged in parallel in the left-right direction, and four memory cells which are the basic units of the arrangement are arranged in parallel in the vertical direction. Therefore, the non-volatile semiconductor memory elements shown in Figs. 45 to 45 can be closely arranged, and the area of the nonvolatile semiconductor memory device can be minimized. As shown in the above description, in the non-volatile semiconductor memory device and the non-volatile semiconductor memory device of the present invention, non-volatile memory can be realized by a CMOS process of standard logic elements, and logic element mixing can be realized simply and inexpensively. Remember the billion body. First, each of the 32th to 36th embodiments of the present invention is characterized in that a plurality of floating gate type transistors of -186 to 201010062 are provided in one nonvolatile semiconductor memory cell. Before the description, first, referring to FIG. 50A to FIG. 50, a configuration in which one floating gate type transistor is provided in one cell is used, and each of the 32nd to 36thth aspects of the present invention is explained. The basic structure and operation of the non-volatile semiconductor memory cells used in the embodiments. Fig. 50A is a plan view showing a nonvolatile semiconductor memory (EEPROM cell). Figure 50B shows an equivalent circuit diagram, Figure 50C shows a cross-sectional view along A30-A30' of Figure 50A, Figure 50D shows a cross-sectional view along B30-B30', and Figure 50E shows along C30-C30 'The section view. This EEPROM cell is composed of a series connected transistor T301, a transistor T3 02, and a capacitor C301 as shown in the equivalent circuit of Fig. 50B. Here, the transistor T3 01 is a switch for selecting a cell (selecting a transistor), and the transistor T3 02 is a floating gate type transistor. In this memory cell, the drain of the transistor T3 01 becomes the drain D300 of the memory cell, the source of the transistor T302 becomes the source S300 of the memory cell, and the gate of the transistor T301 is used to select the memory cell. The gate selection gate SG300, one end and the floating gate FG300 of the transistor T3 02. The other end of the connected capacitor C301 becomes the control gate CG3 00 for controlling the memory content of the memory cell. This capacitor C301 is a capacitor between the control gate CG300 and the floating gate FG300. In the 50th to 50thth drawings, the symbol 3001 is a p-type semiconductor substrate, the symbol 3002 is an n-type well (hereinafter also referred to as n-well) formed on the p-type semiconductor substrate 3001, and the symbol 3 003 is a transistor. a transistor of the crucible 301 (a portion of the p-type semiconductor substrate 3 00 1 and an oxide film), and a symbol 3 004 is a floating gate type transistor (a portion of the p-type semiconductor substrate 3001 and an oxide film) constituting the transistor T3 02, symbol 3005 Is the n-type bungee diffusion of transistor T301-187- 201010062
層，符號3006是電晶體T301的源極，亦成爲電晶體T302 之汲極的η型擴散層，符號3007是成爲電晶體T302之源 極的η型擴散層，符號3008是成爲電晶體Τ301之閘極的 多晶矽層，符號3009是成爲電晶體Τ302之浮動閘極的多 晶矽層，並成爲電容器C301的一端。符號3010是連接擴 散層3005和金屬配線3012的接點，符號3011是連接擴散 層3007和金屬配線3013的接點，符號3012是用以拉出電 晶體Τ301之汲極D300的金屬配線，符號3013是用以拉 出浮動閘極型電晶體Τ302之源極S300的金屬配線，符號 3014是電容器C301 (η型井3002的一部分和氧化膜），符號 3015是ρ型擴散層，並成爲電容器C301的另一端。符號 3016是連接ρ型擴散層3015和金靥配線3019的接點，符 號3017是形成於η型井3 002上的η型擴散層，符號3018 是連接η型擴散層3017和金屬配線3019的接點，符號3019 是成爲控制閘極配線的金屬配線，符號3020是分離用絕緣 氧化膜。The layer 300 is the source of the transistor T301 and also serves as the n-type diffusion layer of the drain of the transistor T302. The symbol 3007 is the n-type diffusion layer which becomes the source of the transistor T302, and the symbol 3008 is the transistor 301. The polysilicon layer of the gate, symbol 3009, is a polysilicon layer which becomes a floating gate of the transistor 302 and becomes one end of the capacitor C301. Reference numeral 3010 is a contact connecting the diffusion layer 3005 and the metal wiring 3012, reference numeral 3011 is a contact connecting the diffusion layer 3007 and the metal wiring 3013, and reference numeral 3012 is a metal wiring for pulling out the drain D300 of the transistor 301, symbol 3013 It is a metal wiring for pulling out the source S300 of the floating gate type transistor 302, the symbol 3014 is a capacitor C301 (a part of the n-type well 3002 and an oxide film), and the symbol 3015 is a p-type diffusion layer, and becomes the capacitor C301. another side. Reference numeral 3016 is a joint connecting the p-type diffusion layer 3015 and the gold-line wiring 3019, reference numeral 3017 is an n-type diffusion layer formed on the n-type well 3 002, and reference numeral 3018 is a connection connecting the n-type diffusion layer 3017 and the metal wiring 3019. Point, symbol 3019 is a metal wiring that serves as a gate wiring, and reference numeral 3020 is an insulating oxide film for separation.
此記憶胞元的特徵爲：在圖面上的縱向配置成爲位元 線並成爲記憶胞元之汲極D300的金屬配線3012，在圖面 上的橫向配置成爲選擇閘極SG300的多晶矽層3008及成 爲控制閘極CG300之配線的金屬配線3019,又緊密地配置 面積變大的電容器C301，並使面積變成最小限度。 在此’電容器C301由η型井3002、電容器3014、ρ 型擴散層3015、接點”“^型擴散層3〇17以及接點3018 所構成。 參照第51圖，說明第50 a圖〜第5 0Ε圖所示之記憶胞 -188 - 201010062 元的動作。關於寫入，有2種方式。第1種方法是藉熱電 子注入的寫入方式（只記爲「寫入」）。作爲「寫入」，對 SG300施力口 8V，對CG300施力口 3〜8V，對D300施力口 5V， 對S3 00施加0V。對電晶體T3 01的汲極及閘極施加高電 壓，爲了在後述的飽和區域進行動作，而在汲極附近對空 乏層施加高電壓，產生熱電子，其被注入浮動閘極FG3 00。 因爲注入電子，所以表面上電晶體T3 02的臨限値變高。 在拭除的情況，預先對SG300偏壓至10V，對CG300 〇 偏壓至0V，對D300偏壓至8V，對S300偏壓至開路（open) 或約2V。在此狀態，對汲極和浮動閘極FG3 00之間施加高 電壓，而Fowler— Nordheim的穿隧電流（以下簡稱爲FN電 流）流動，從浮動閘極FG3 00向汲極放出電子，而表面上看 起來臨限値降低。 關於讀出，對SG300施加3~5V，對CG3 00施加0V， 對D300施加IV，對S300施加0V時，若是寫入狀態（臨限 値爲正），電流不會流動，而判斷爲“ 〇” 。若是拭除狀態（臨 Q 限値爲負），電流流動，而判斷爲“ 1 ” 。 又，第2寫入方法是元件的耐壓比較高的情況，亦以 FN電流進行寫入的情況，作爲「寫入3 _ 2」。在此情況， 若對SG300施加5V，對CG300施加15V，對D300施加0V， 對S3 00施加開路或0V，對通道和浮動閘極間間施加髙電 壓，而進行注入電子。The memory cell is characterized in that the metal wiring 3012 which is a bit line in the vertical direction on the drawing and becomes the drain D300 of the memory cell is disposed in the lateral direction on the drawing surface as the polysilicon layer 3008 of the gate SG300 and As the metal wiring 3019 that controls the wiring of the gate CG300, the capacitor C301 having a large area is closely arranged, and the area is minimized. Here, the capacitor C301 is composed of an n-type well 3002, a capacitor 3014, a p-type diffusion layer 3015, a contact, a "type diffusion layer 3"17, and a contact 3018. Referring to Fig. 51, the operation of the memory cell -188 - 201010062 shown in Fig. 50a to Fig. 5 is illustrated. There are two ways to write. The first method is the method of writing by hot electron injection (only "write"). As "write", apply 8V to the SG300, apply 3 to 8V to the CG300, apply 5V to the D300, and apply 0V to the S3 00. A high voltage is applied to the drain and the gate of the transistor T3 01. In order to operate in a saturation region to be described later, a high voltage is applied to the depletion layer near the drain to generate hot electrons, which are injected into the floating gate FG3 00. Because of the injection of electrons, the threshold of the transistor T3 02 on the surface becomes high. In the case of erasing, SG300 is pre-biased to 10V, CG300 偏压 is biased to 0V, D300 is biased to 8V, and S300 is biased to open or approximately 2V. In this state, a high voltage is applied between the drain and the floating gate FG3 00, and the tunneling current of Fowler-Norweyheim (hereinafter referred to as FN current) flows, and electrons are discharged from the floating gate FG3 00 to the drain, and the surface It seems that the threshold is reduced. For reading, 3 to 5 V is applied to SG300, 0 V is applied to CG3 00, IV is applied to D300, and 0 V is applied to S300. If the state is written (the threshold is positive), the current does not flow, and it is judged as "〇" ". If the erased state (proximity Q is negative), the current flows and is judged as "1". Further, the second writing method is a case where the withstand voltage of the device is relatively high, and the writing is performed with the FN current as "write 3 _ 2". In this case, if 5 V is applied to SG300, 15 V is applied to CG300, 0 V is applied to D300, and an open circuit or 0 V is applied to S3 00, and a zeta voltage is applied between the channel and the floating gate to perform electron injection.
在第52A圖，作爲僅電晶體T302的特性，表示VCG -Id特性。第52B圖係表示第50A圖〜第50E圖所示之基 本構造之非揮發性半導體記億胞元的電路圖。在第52 A -189 - 201010062In Fig. 52A, as a characteristic of only the transistor T302, the VCG-Id characteristic is shown. Fig. 52B is a circuit diagram showing the nonvolatile semiconductor cells of the basic structure shown in Figs. 50A to 50E. At 52 A - 189 - 201010062
圖，VCG3 00表示在將源極S300設爲0V之情況的控制閘 極CG300的電壓，Id表示電晶體Τ302的汲極電流。起始 的臨限値是約IV。進行寫入時，因爲電子被注入浮動閘極 FG3 00內，所以如圖所示，顯示表面上臨限値升高至3V的 特性。又，拭除時，顯示表面上臨限値下降至一3V的特性。 在此，將該寫入電壓設爲3 ~8V，是因爲電晶體T3 02被過 度拭除時，如後述所示，浮動閘極FG3 00帶正電，所以在 寫入時，若將控制閘極CG3 00設爲太高的電壓，就進入非 飽和區域，難產生熱電子，而具有寫入特性變差的課題。 過度拭除狀態時，可採用步升寫入方式，其將控制閘極 CG 3 00的電壓設定成稍低，若要寫入，和寫入量合倂，而 使控制閘極CG3 00的電壓逐漸升高。In the figure, VCG3 00 indicates the voltage of the control gate CG300 when the source S300 is set to 0V, and Id represents the gate current of the transistor Τ302. The initial threshold is about IV. When writing is performed, since electrons are injected into the floating gate FG3 00, as shown in the figure, the characteristic of the surface is raised to 3V. Also, when erasing, the display surface exhibits a characteristic that the threshold 値 drops to a level of 3V. Here, the write voltage is set to 3 to 8 V. When the transistor T3 02 is excessively erased, as will be described later, the floating gate FG3 00 is positively charged, so if the gate is to be gated during writing, When the pole CG3 00 is set to a voltage that is too high, it enters an unsaturated region, and it is difficult to generate hot electrons, and the writing characteristics are deteriorated. In the over-wiping state, a step-up writing mode can be employed, which sets the voltage of the control gate CG 3 00 to be slightly lower, and if it is to be written, and the amount of writing is combined, the voltage of the control gate CG3 00 is made. Gradually rise.
第53A圖表示電晶體T301和T302被串接的特性。第 5 3B圖係表示第50 A圖~第5 0E圖所示之基本構造之非揮發 性半導體記憶胞元的電路圖。在第53A圖，讀出時，因爲 控制閘極CG300的電壓是CG30 0 = 0V，所以若電晶體T302 之臨限値的起始値爲約IV，VSG— Id特性（記憶胞元的特 性）是電流幾乎不流動之狀態。在此，VSG3 00是選擇閘極 SG300的電壓，Id是記憶胞元之汲極D300的電流。進行 寫入時，電流完全不流動。在拭除時，因爲電晶體T3 02 總是導通狀態，所以作爲記憶胞元特性，和控制閘極CG3 00 的電壓成正比的電流流動。 第54A圖表示第50八圖~第50E圖之記憶胞元之耦合 系統的等價電路。第54B圖係表示第50八圖~第5 0E圖所 示之基本構造之非揮發性半導體記憶胞元的電路圖。 -190- 201010062 又，第55圖表示耦合的計算式。在此，VCG300是控 制閘極CG300的電壓，VFG300是浮動閘極FG300的電壓， VD300是汲極D的電壓，VS300是源極S300的電壓， VSub300是p型半導體基板3001的電壓。又，C300(FC300) 是控制閘極CG300和浮動閘極FG300間的電容器（=電容器 C301)，C300(FB300)是浮動閘極FG3 00和p型半導體基板 3001間的電容器，C300(FS300)是浮動閘極FG300和源極 S300間的電容器，C300(FD300)是浮動閘極FG300和汲極 〇 D3 00間的電容器。 若浮動閘極FG3 00之狀態爲起始狀態爲起始狀態（中 性狀態），因爲此系統之總電荷爲零，所以在第55圖的第 (1)式，Q300 = 0，M (VCG3 00 - YF G 3 0 0) x C 3 0 0 (F C 3 0 0) + (VD3 00 - VFG300)xC3 00(FD300) + (VS300 - VFG300)xC300 (FS300) + (VSub300 - VFG300)xC300(FB300) = 0。 在此，若 C300(FC300) + C300(FB300) + C300(FS300) = CT300(總和），貝!J VFG300 = VCG300xC300(FC3 00)/CT300 + Q Vsub300xC300(FB300)/CT300 + VD300xC300(FD300)/CT300 + VS300xC300(FS 300)/CT3 00 » 在此，若 C300(FD300)=C300(FS300)= 0 ' Vsub300= VS 3 00-0 > 貝IJ VFG300 = VCG300xC300(FC300)/{C300 (FC300) + C300(FB300)}(第（4)式）。 在此，若 C300(FC300)/{C300(FC300) + C300(FB300)} = α 300(耦合比），則 VFG300=a 300xVCG300。一般，設定 成 α 300 = 0.6。 其次，說明將複數個浮動閘極型電晶體設置於一個非 -191- 201010062 揮發性半導體記憶胞元之作爲本發明之第32~第36實施形 態的非揮發性半導體記憶胞元。 [第32實施形態] 參照第56A圖〜第57C圖，說明作爲本發明之第32實 施形態的非揮發性半導體記憶胞元。第56A圖表示非揮發 性半導體記憶胞元的平面圖，第56B圖表示等價電路，第 56C圖表示沿著第56A圖之A30 — A 3 0 的剖面圖’第57A 圖表示沿著B30— B30’的剖面圖’第57B圖表示沿著 C30— C30，的剖面圖，第57C圖表示沿著D30 — D30’的 剖面圖。此外，在以下的各圖，對和第50A圖~第50E圖 所示者相同（或對應）的構成使用相同的符號。又，在各圖’ 在設置複數個和第50 A圖~第5 0E圖所示之構成相同（或對 應）的構成的情況，使用對在第5 0入圖~第5 0E圖所使用之 符號（數字）追加1個英文字母（a、b等）的符號（例如對η型 擴散層3 006，使用η型擴散層3 006a、3 006b等）。 此EEPROM胞元如第56B圖的等價電路所示，由電晶 體T301、電晶體T302、電晶體T303、電容器C301以及電 容器C302所構成。在電晶體T301，串接由電晶體T302及 電晶體T3 03所並列地連接者。電晶體T301是用以選擇記 憶胞元的開關，電晶體T3 02及電晶體T3 03是浮動閘極型 電晶體。在此記憶胞元，電晶體T301的汲極成爲記億胞元 的汲極D300,電晶體T302及電晶體T303的源極成爲記憶 胞元的源極 S3 00，電晶體 T3 01的閘極成爲選擇閘極 SG300»又，一端各自和電晶體T302、T303的浮動閘極 FG301、FG302連接之電容器C301、C3 02的另一端成爲共 -192- 201010062 用的控制閘極CG3 00。電晶體T3 02、T3 03之浮動閘極 FG301、FG302的各一端如圖上的虛線所示，在外部連接。 此電容器C301是控制閘極CG3 00和浮動閘極FG301之間 的電容器，電容器C 3 02是控制閘極CG3 00和浮動閘極 FG3 02之間的電容器。在第56B圖，電晶體T302和電晶體 T303是對應於第50B圖之電晶體T302的構成。 在第56A圖、第56C圖以及第5 7AH~第57C圖，符 號3001是p型半導體基板，符號3 002是形成於p型半導 Ο 體基板3001上的η型井，符號3 003是構成電晶體T3 01 的電晶體，符號30 04 a及符號3004b是構成電晶體Τ302及 T3 03的浮動閘極型電晶體，符號3005是電晶體T301的η 型汲極擴散層，符號3006a及符號3006b是電晶體Τ301的 源極，亦成爲電晶體T3 02及T3 03之汲極的η型擴散層， 符號3007是成爲電晶體Τ3 02及Τ303之源極的η型擴散 層，符號3008是成爲電晶體Τ301之閘極的多晶矽層，符 號3009a、符號300 9b是成爲電晶體Τ3 02、Τ303之浮動閘 ©極的多晶矽層，並成爲電容器C301及C302的一端。符號 3010是連接擴散層3005和金屬配線3012的接點，符號 3011是連接擴散層3007和金屬配線3013的接點，符號 3012是用以拉出電晶體T301之汲極（汲極D300)的金屬配 線，符號3013是用以拉出浮動閘極型電晶體T3 02及T3 03 之源極（源極S3 00)的金屬配線，符號3014a、符號3014b 各自是電容器C301、C302，符號3015a及符號3015b是p 型擴散層，各自成爲電容器C301、C3 02的另一端。符號 3016a、符號3016b是連接p型擴散層3015a、3015b和金 -193- 201010062 屬配線3019a、符號3019b的接點，符號3017a、符號3017b 是形成於η型井3002上的η型擴散層，符號3〇18a、符號 3018b是連接η型擴散層3017a、符號3017b和金屬配線 3019a、3019b的接點，符號3019a、符號3〇191?各自是成 爲T302及T3 03之控制閘極配線的金屬配線，符號3 020 是分離用絕緣氧化膜。符號21a、符號'21b是將金屬配線 層3 022和η型擴散層3006a、3〇06b連接的接點，符號3 022 是金屬配線層。 本實施形態的記憶胞元作成利用共用的η型井3002形 成電晶體Τ302及Τ303的控制閘極CG300。即，其特徵爲： 在控制閘極CG3 00和複數個浮動閘極型電晶體Τ3 02、Τ3 03 的各浮動閘極FG301、FG302之間所形成的複數個電容器 C301、C302是使用同一 η型井30 02形成。藉由依此方式， 而不需要分離井（Well)的邊界，而胞元面積可變小。又， 在圖面上的縱向配置成爲位元線並成爲記憶胞元之汲極 D300的金屬配線3012,在圖面上的橫向配置成爲選擇閘極 SG300的多晶矽層3008及成爲控制閘極CG300之配線的 金靥配線3019a、3019b，又緊密地配置面積變大的電容器 C301、C3 02，又，以金屬配線層3 022連接成爲記憶元件 之電晶體T302、T303的汲極3006a、3006b’使面積變成 最小限度。又，本實施形態的記憶胞元的特徵之一是在P 型半導體基板3001上將複數個浮動閘極型電晶體T302、 T3 0 3和成爲選擇電晶體的電晶體T301排列成直線形’是 以直線形的金屬配線層3022連接複數個浮動閘極型電晶 體T302、T303的各汲極。在此，電容器c301由n型井3002、 -194- 201010062 電容器C301(3014a)、p型擴散層3015a、接點3〇16a、n型 擴散層3017a以及接點3018a所構成。又，電容器C302由 η型井3 002、電容器C3 02(30 1 4b)、p型擴散層3〇15b、接 點3016b、η型擴散層3017b以及接點3018b所構成。 此外，在第56A圖，雖然p型擴散層3〇15a、3〇15b 分離，但是因爲是同電位，所以亦可一體化成p型擴散層 3015。這在面積變小的情況有效。但是，在本例，因爲電 晶體T3 02和電晶體T3 03的控制閘極互相連接，所以如第 Ο 5 6B圖的等價電路所示，電晶體T3 02和電晶體T3 03的控 制閘極共用地成爲控制閘極CG 300。 將電晶體T3 02和電晶體T3 03的控制閘極共用地作爲 控制閘極CG 300之情況的動作，是和參照第51圖所說明 的一樣。 [第33實施形態] 第58圖表示將第56A圖〜第56C圖之記憶胞元配置成 陣列的例子。記憶胞元在列方向（橫向）配置4個M3 11〜 〇 M314，在行方向（縱向）如M3 11-M331般配置3個，而配 置4x3 = 12個胞元。藉由對比地配置共用部分，而更有效地 配置第56 A圖~第56C圖的記憶胞元，而可縮小面積。 在此情況，如記億胞元M3 11和記憶胞元M3 12般在橫 向排列之一對記憶胞元，使用共用的η型井3 002，同時亦 共用接點3018a及3018b。又，在縱向所排列的記憶胞元 M311〜M331和共用的金屬配線3012連接，這成爲位元線 BIT301。一樣地，記憶胞元M312~ M332和共用的金屬配 線3012連接，這成爲位元線BIT302。又，記憶胞元M313~ -195- 201010062 M333、記憶胞元M314〜M334各自和共用的金屬配線3012 連接，這些成爲位元線BIT3 03、BIT3 04。又，在橫向所排 列之記憶胞元M311~M314的各接點3016a、3018a和共用 的金屬配線3019a連接，各3016b、3018b和共用的金屬配 線3019b連接，這些金屬配線3019a和金屬配線3019b各 自成爲控制閘極配線CG301。這一對控制閘極配線CG301 在未圖示之記憶胞元陣列的外部電路連接。又，在橫向所 排列之記憶胞元M3 11~ M3 14的各接點3011和共用的金屬 配線3013連接，此金屬配線3013成爲源極配線S301。一 樣地，在橫向所排列之記憶胞元M321〜M3 24的各接點 3016a、3018a和共用的金屬配線3019a連接，各3016b、 301 8b和共用的金屬配線301 9b連接，這些金屬配線3019a 和金屬配線3019b各自成爲控制閜極配線CG3 02。這一對 控制閘極配線CG3 02在未圖示之記憶胞元陣列的外部電路 連接。又，在橫向所排列之記憶胞元M321〜M3 24的各接 點3011和共用的金屬配線3013連接，此金屬配線3013成 爲源極配線S 3 0 2。又，在橫向所排列之記億胞元M331-M3 3 4的各接點3016a、3018a和共用的金屬配線3019a連 接，各3016b、3018b和共用的金屬配線3019b連接，這些 金屬配線3019a和金屬配線3019b各自成爲控制閘極配線 CG3 03 〇這一對控制閘極配線CG303在未圖示之記憶胞元 陣列的外部電路連接。又，在橫向所排列之記憶胞元M331〜 M334的各接點3011和共用的金屬配線3013連接，此金屬 配線3013成爲源極配線S303。又，3條多晶矽層3008各 自由在橫向所排列之記憶胞元所共用，由上依序成爲選擇 -196- 201010062 閘極配線SG301、SG302以及SG303 ° [第34實施形態] 在第5 9A圖〜第59C圖，表示另外的實施形態。第5 9A 圖係本實施形態之記憶胞元的平面圖，第59B圖係等價電 路圖，第59C圖係沿著第59A圖之A30— A30’的剖面圖。 此外，在第59八圖~第59C圖，對和第56八圖~第57C圖所 示者相同（或對應）的構成使用相同的符號。爲了更提高記 憶胞元的可靠性，如第59B圖的等價電路所示，將和電晶 〇 體T301串列地連接之彼此並列地連接的3個浮動閘極型電 晶體T3 02、T3 03以及T3 04設置爲非揮發性半導體記憶元 件。在本例，3個電晶體T3 02、T3 03以及T3 04之控制閘 極CG3 00共用，以發揮面積縮小效果。 本實施形態和第56A圖〜第56C圖所示之第33實施形 態的記憶胞元相比，在省略控制閘極用的η型井3 002，脰 時省略η型擴散層3017a、3017b和接點3018a、3018b， 還將構成電晶體T302〜T304之電容器C301〜C303的另一 〇 端的擴散層變更成η型擴散層3055，並共用上相異。又， 在將電晶體Τ302〜Τ304之電容器C301〜C303的另一端共 同連接的控制閘極CG300,經由接點3016而連接金屬配線 3019。即，本實施形態之特徵爲：使用同一η型擴散層3055 形成在控制閘極CG300和複數個浮動閘極型電晶體丁302~ Τ304的各浮動閘極之間所形成的複數個電容器c301~ C3 03。 此外，在第59A圖〜第59C圖’符號3004〇是構成電 晶體T304的浮動閘極型電晶體，符號3006a是電晶體T301 -197- 201010062 的源極’亦成爲電晶體T3 〇2之汲極的η型擴散層，符號 3 006b是經由金屬配線層3022和電晶體Τ301的源極連 接’亦成爲電晶體T3 03、T3 04之汲極的η型擴散層，符號 3007a是成爲電晶體Τ302、Τ303之源極的η型擴散層，符 號3007b是成爲電晶體Τ304之源極的η型擴散層，符號 3〇〇9c是成爲電晶體Τ3〇4之浮動閘極的多晶矽層，並成爲 電容器C3 03的一端。符號3011a是連接擴散層3007a和金 屬配線3013a的接點，符號3011b是連接擴散層3007b和 金屬配線3013b的接點，符號3〇1 3a是用以拉出電晶體 T3 02及T3 03之源極的金屬配線，符號3013b是用以拉出 電晶體T304之源極的金屬配線，符號3019是成爲 T3 02〜T 3 04之控制閘極配線的金屬配線。 又，雖未圖示，對形成電容器C301~C303的閘極部注 入（1111?1&111&^〇11)磷（1) + )等的雜質，若進行〇(46?1以丨〇11)型式 化，作爲效率高的電容器進行動作。 [第35實施形態] 第60圖表示將第59A圖〜第59C圖所示之記憶胞元進 行陣列配置的實施形態。第60圖所示的記憶胞元，在列方 向（橫向）配置記憶胞元M3 11~M3 14之4個，在行方向（縱 向）配置如M311〜Μ331之3個，而配置4x3 = 12個胞元。藉 由對照地配置共用部分，而更有效地配置第5 9Β圖的記憶 胞元，可縮小面積。在此情況，連接電晶體Τ301之η型汲 極擴散層3005和金屬配線3012的接點3010、及連接成爲 電晶體Τ304之源極的η型擴散層3007b和金屬配線3013b 的接點1 1 b，在上下的記憶胞元（例如記憶胞元Μ 3 2 1和記 -198- 201010062 憶胞元Μ 3 3 1)共用，又，左右之記憶胞元（例如記憶胞元 M311和記憶胞元M312)的複數個電容器C301〜C3 03形成 於同一 η型擴散層3055內，而布置可更縮小。 在此情況，在橫向所排列之記憶胞元Μ311〜Μ314的各 接點3016和共用的金屬配線（第5 9Α圖〜第5 9C圖的金屬 配線3019)連接，該金屬配線成爲控制閘極配線CG301。 又，在橫向所排列之記憶胞元Μ311~Μ314的各接點3011a 或3011b各自和共用的金屬配線3013a或3013b連接，此 Ο 金屬配線3013a成爲源極配線S311，此金屬配線3013b成 爲源極配線S312。此源極配線S311和源極配線S312是對 應於第5 9A圖〜第59C圖之記憶胞元的源極S300，在未圖 示之記憶胞元陣列的外部電路連接源極配線S311和源極 配線S312 。 —樣地，在橫向所排列之記憶胞元M3 21 ~M3 24的各接 點3016和共用的金屬配線連接，此金屬配線成爲控制閘極 配線CG3 02。又，在橫向所排列之記憶胞元M321〜M324 Ο 的各接點3011a或3011b各自和共用的金屬配線3013a或 3013b連接，此金屬配線3013a成爲源極配線S321，此金 屬配線3013b成爲源極配線S322。此源極配線S321和源 極配線S3 22是對應於第5 9A圖〜第59C圖之記憶胞元的源 極S300,在未圖示之記憶胞元陣列的外部電路連接源極配 線S321和源極配線S322。關於在橫向所排列之記憶胞元 M33 1 〜M334 亦一樣。 [第36實施形態] 第61圖表示使用本發明之第3 2〜第36之各實施形態 -199- 201010062 之非揮發性半導體記憶裝置的電路構成。作爲在第61圖的 記憶胞元M3 1 l~M3mn，可使用參照例如第56A圖〜第56C 圖、第59A圖〜第59C圖等所說明的非揮發性半導體記憶 胞元。又，該情況之各記憶胞元的配置可使用參照第58 圖、第60圖所說明的陣列配置。 在第61圖，符號（M311)〜（M3mn)是mxn個記憶胞元， 符號3100是將這些記憶胞元M311〜M3mn進行陣列配置的 記億胞元陣列，符號3200— 1〜3200 - m是m個列解碼器， 符號33 00是行選擇閘電路，符號3400—1〜3 40〇-11是11個 © 行解碼器，符號3500是寫入、拭除控制電路，符號3600， 是在讀出時進行動作的感測放大器，符號3 700是內部電源 用電路。此外，在第61圖所示的電路構成，雖然各記憶胞 元M311~M3mn使用由參照第56八圖~第56C圖所說明之3 個電晶體T3 01 ~T3 03所構成的記憶胞元，但是浮動閘極型 電晶體Τ3 02、Τ3 03等的並列地連接個數未限定爲2個，亦 可是第59 Α圖~第5 9C圖所示的3個，亦可是3個以上。 列解碼器3200 — 1由輸入列位址的解碼部3 2 0 1、向選 〇 擇閘極SG301輸出的反相器3202與位準挪移器兼緩衝器 3203、以及向控制閘極CG301輸出的N AND電路3204與 位準挪移器兼緩衝器（輸出部）3 205所構成。選擇閘極輸出 SG301和記憶胞元陣列3100所包含之在列方向（圖面上的 橫向）所配置的η個記憶胞元M3 1 1〜M3 In共同連接，控制 閘極輸出CG3 01 —樣和記憶胞元M311〜M31n共同連接。 選擇鬧極輸出SG301和各記憶胞元M311~M31n的選擇閘 極 SG3 00連接，控制閘極輸出 CG301和各記憶胞元 -200- 201010062 M311〜M31n的控制閘極 CG300連接。此外，列解碼器 3200— 1之NAND電路3204所輸入之寫入信號W300是用 以選擇記憶胞元M3 11~M31n之控制閘極CG300的信號， 寫入信號W300爲“ 1”時，NAND電路3204變成活化。又， 在拭除時及讀出時，藉由設定寫入信號W300=“0” ，而 NAND電路3204變成不活化，而控制閘極CG300被控制成 0V。列解碼器3200— 1藉以上之構成，而向既定之控制閘 極CG3 00(記憶胞元M3 11~M3 1n的控制閘極CG300)輸出根 〇據將指定記憶胞元之列位址（位址信號）解碼的信號及記憶 胞元的寫入信號W3 00所產生之控制閘極CG301。 列解碼器 3 200— m亦是一樣之構成。列解碼器 3200— m之選擇閘極輸出SG30m和記憶胞元陣列3100所 包含之在列方向所配置的η個記億胞元M3ml~M3mn共同 連接，控制閘極輸出CG30m —樣和記憶胞元M3ml〜M3mn 共同連接。選擇閘極輸出 SG30m 和各記憶胞元 M3ml〜M3mn的選擇閘極SG300連接，控制閘極輸出CG30m 〇 和各記憶胞元M3ml~M3mn的控制閘極CG300連接。 又，對列解碼器3200— l~3 200-m中的位準挪移器兼 緩衝器3203及位準挪移器兼緩衝器3205，供給從內部電 源用電路3700所輸出之電源VP301及VP3 02,而可控制施 加於各記憶胞元M3 1 1〜M3 In.....M3 m 1 ~M 3 mn的選擇閘 極SG3 00和控制閘極CG300的電壓。 行選擇閘電路 3 300由 η個行選擇閘極電晶體 COLG301~COLG30n所構成，各自在閘極輸入來自行解碼 器3400— 1~3400— η的輸出C0301~C030n。選擇閘極電晶 -201- 201010062 體COLG301〜COLG3〇n的各汲極和資料線Data300共同連 接，同時各源極各自和位元線BIT301— 0〜BIT 30η連接。此 外，行解碼器3400 — 1由輸入行位址的解碼部3401、反相 器3 402、以及輸出行線選擇信號CO301的位準挪移器兼緩 衝器3403所構成。其他的行解碼器3400 — 2〜3 4 00 -η亦一 樣地構成。 又，對行解碼器3400 — 1〜3400— η中的位準挪移器兼 緩衝器3403，供給從內部電源用電路37 00所輸出之電源 VP303，可控制施加於行選擇閘極電晶體 COLG301~COLG30n的各閘極的電壓。 寫入、拭除控制電路3500是接受寫入信號W300或拭 除信號E並向資料線Data3 0 0上輸出寫入電壓或拭除電壓 的控制電路。寫入、拭除控制電路3 5 00又在寫入時，根據 Din3 00信號而控制寫“0”或寫“1”（實質上“1”是禁止 寫入）。對此寫入、拭除控制電路3500,供給從內部電源用 電路3700所輸出之電源VP304，而可控制施加於各記憶胞 元 M311~M31n、…、M3ml~M3mn 的汲極 D300 的電壓。 此外，感測放大器3 6 00是在讀出時將記憶胞元的資料 放大輸出的感測放大器，而內部電源用電路3 7 00是在寫 入、拭除以及讀出時產生所需之電壓的電源電路。又，電 晶體3 800之汲極和各記憶胞元M3U~M3mn的源極S300 連接，對其源極施加既定的電壓，同時根據信號EB 3 00而 控制開閉。藉由控制此電晶體3 800，而可使各記憶胞元 M311~M3mn的源極S300變成開路，或施加既定的電位。 又，在本實施形態，雖然在內部電源用電路3 70 0產生寫入 -202- 201010062 及拭除所需的電壓（VP301〜VP304)，但是從外部直接供給 這些電壓VP301〜VP3 04，而省略內部電源用電路3700， 動作亦相同。 第62圖表示第61圖所示之非揮發性半導體記憶裝置 的動作表。第62圖表示在各動作模式，施加於各記憶胞元 M311~M3mn之選擇閘極SG300、控制閘極 CG300、汲極 D300以及源極S 300的電壓和寫入信號W300的邏輯位準。 在此，寫入信號W3 00是在寫入時變成“1” ，在非寫入時 ❹ (即讀出或拭除時）變成“ 〇”的信號，是在第61圖的寫入 時輸入列解碼器3200— 1~3 200— m及寫入、拭除控制電路 3500的信號。如上述所示，輸入列解碼器3200— 1〜3200— m 之N AND電路3204的寫入信號W3 00是用以選擇各記憶胞 元M311~M3mn之控制閘極CG300的信號，在寫入時，爲 了使NAND電路3204變成活化，而設爲W300=“l” ，而 在拭除時及讀出時，爲了使控制閘極CG3 00總是變成0V， 而設爲W300= “ 0” 。 〇 如第62圖所示，在寫入時（藉熱電子注入的寫入方 式），將W300設爲“1” ，並對SG300施加8V，對CG300 施加3~8V，對D300施加5V，對S300施加0V。對電晶體 T302及T303的汲極及閘極施加高電壓，爲了在上述的飽 和區域進行動作，而在汲極附近對空乏層施加高電壓，產 生熱電子，其被注入浮動閘極FG3 00。因爲注入電子，所 以表面上電晶體T3 02及T3 03的臨限値變高。 在驗證寫入時（在確認是否已完成寫入下的寫入時）， 將W3 00設爲“1” ，並對SG300施加3V，對CG300施加 -203 - 201010062 2V，對D300施加1V，對S300施加0V。如參照第62A圖 的說明所示，若已寫入，則臨限値變高。因此，在CG3 00 爲2V，若已寫入，則汲極電流不會流動。若未檢測到此電 流（或若是既定値以下），根據臨限値爲2V以上，而結束寫 而入。若臨限値爲2V以下，尙未充分地寫入，而再進行寫 入，並持續至臨限値變成2V以上爲止。Fig. 53A shows the characteristics in which the transistors T301 and T302 are connected in series. Fig. 5B is a circuit diagram showing the non-volatile semiconductor memory cells of the basic structure shown in Figs. 50A to 50E. In Fig. 53A, when reading, since the voltage of the control gate CG300 is CG30 0 = 0V, if the threshold 电 of the threshold T of the transistor T302 is about IV, the VSG_Id characteristic (characteristic of the memory cell) It is a state in which the current hardly flows. Here, VSG3 00 is the voltage of the gate SG300, and Id is the current of the drain D300 of the memory cell. When writing, the current does not flow at all. At the time of erasing, since the transistor T3 02 is always in an on state, as a memory cell characteristic, a current proportional to the voltage of the control gate CG3 00 flows. Fig. 54A shows an equivalent circuit of the coupling system of the memory cells of Figs. 50 to 50E. Fig. 54B is a circuit diagram showing the basic structure of the non-volatile semiconductor memory cells shown in Figs. 50 to 105E. -190- 201010062 Also, Fig. 55 shows the calculation formula of the coupling. Here, the VCG 300 is a voltage for controlling the gate CG300, VFG300 is the voltage of the floating gate FG300, VD300 is the voltage of the drain D, VS300 is the voltage of the source S300, and VSub300 is the voltage of the p-type semiconductor substrate 3001. Further, C300 (FC300) is a capacitor between control gate CG300 and floating gate FG300 (=capacitor C301), C300 (FB300) is a capacitor between floating gate FG3 00 and p-type semiconductor substrate 3001, and C300 (FS300) is A capacitor between the floating gate FG300 and the source S300, and C300 (FD300) is a capacitor between the floating gate FG300 and the drain 〇D3 00. If the state of the floating gate FG3 00 is the initial state (neutral state), since the total charge of this system is zero, in the equation (1) of Fig. 55, Q300 = 0, M (VCG3) 00 - YF G 3 0 0) x C 3 0 0 (FC 3 0 0) + (VD3 00 - VFG300) xC3 00 (FD300) + (VS300 - VFG300) xC300 (FS300) + (VSub300 - VFG300) xC300 (FB300 ) = 0. Here, if C300 (FC300) + C300 (FB300) + C300 (FS300) = CT300 (sum), Bay! J VFG300 = VCG300xC300 (FC3 00) / CT300 + Q Vsub300xC300 (FB300) / CT300 + VD300xC300 (FD300) / CT300 + VS300xC300(FS 300)/CT3 00 » Here, if C300(FD300)=C300(FS300)= 0 ' Vsub300= VS 3 00-0 > Bay IJ VFG300 = VCG300xC300(FC300)/{C300 (FC300) + C300(FB300)} (Formula (4)). Here, if C300 (FC300) / {C300 (FC300) + C300 (FB300)} = α 300 (coupling ratio), VFG300 = a 300xVCG300. In general, set to α 300 = 0.6. Next, a description will be given of a non-volatile semiconductor memory cell in which a plurality of floating gate type transistors are disposed in a non-191-201010062 volatile semiconductor memory cell as the 32nd to 36th embodiments of the present invention. [32th embodiment] Non-volatile semiconductor memory cells which are the 32nd embodiment of the present invention will be described with reference to Figs. 56A to 57C. Figure 56A shows a plan view of a non-volatile semiconductor memory cell, Figure 56B shows an equivalent circuit, and Figure 56C shows a cross-sectional view along A30-A 3 0 of Figure 56A. Figure 57A shows along B30-B30. The 'section view' section 57B shows a cross-sectional view along C30-C30, and the 57Cth line shows a cross-sectional view along D30-D30'. Further, in the following drawings, the same symbols are used for the same (or corresponding) configurations as those shown in Figs. 50A to 50E. In addition, in the case where the configuration of the plurality of pictures and the configurations shown in the 50A to 50E are the same (or corresponding), the use of the maps from the 50th to the 50th is used. The symbol (number) is a symbol of one English letter (a, b, etc.) (for example, the n-type diffusion layer 3 006, the n-type diffusion layer 3 006a, 3 006b or the like is used). This EEPROM cell is composed of an electric crystal T301, a transistor T302, a transistor T303, a capacitor C301, and a capacitor C302 as shown in the equivalent circuit of Fig. 56B. In the transistor T301, a series connection is made by the transistor T302 and the transistor T3 03 in parallel. The transistor T301 is a switch for selecting a memory cell, and the transistor T3 02 and the transistor T3 03 are floating gate type transistors. In this memory cell, the drain of the transistor T301 becomes the drain D300 of the billion cell, the source of the transistor T302 and the transistor T303 becomes the source S3 00 of the memory cell, and the gate of the transistor T3 01 becomes Selecting the gate SG300», the other ends of the capacitors C301, C3 02, which are connected to the floating gates FG301 and FG302 of the transistors T302 and T303, respectively, become the control gate CG3 00 for the common -192-201010062. The floating gates FG301 and FG302 of the transistors T3 02 and T3 03 are connected to the outside as shown by broken lines in the figure. This capacitor C301 is a capacitor between the control gate CG3 00 and the floating gate FG301, and the capacitor C 322 is a capacitor between the control gate CG3 00 and the floating gate FG302. In Fig. 56B, the transistor T302 and the transistor T303 are constructed corresponding to the transistor T302 of Fig. 50B. In the 56A, 56C, and 5th 7AH to 57C, the symbol 3001 is a p-type semiconductor substrate, the symbol 3 002 is an n-type well formed on the p-type semiconductor substrate 3001, and the symbol 3 003 is a composition. The transistor of transistor T3 01, symbol 30 04 a and symbol 3004b are floating gate type transistors constituting transistors Τ 302 and T3 03, and symbol 3005 is an n-type drain diffusion layer of transistor T301, symbol 3006a and symbol 3006b. It is the source of the transistor 301, and also serves as the n-type diffusion layer of the drains of the transistors T3 02 and T3 03. The symbol 3007 is the n-type diffusion layer which becomes the source of the transistors Τ302 and 303, and the symbol 3008 becomes the electricity. The polysilicon layer of the gate of the crystal germanium 301, symbol 3009a, symbol 300 9b is a polysilicon layer which becomes a floating gate of the transistor Τ302 and 303, and becomes one end of the capacitors C301 and C302. Reference numeral 3010 is a contact connecting the diffusion layer 3005 and the metal wiring 3012, reference numeral 3011 is a contact connecting the diffusion layer 3007 and the metal wiring 3013, and reference numeral 3012 is a metal for pulling out the drain (dip D300) of the transistor T301. Wiring, symbol 3013 is a metal wiring for pulling out the source (source S3 00) of the floating gate type transistors T3 02 and T3 03, and the symbols 3014a and 3014b are capacitors C301 and C302, respectively, symbol 3015a and symbol 3015b. It is a p-type diffusion layer, and each becomes the other end of the capacitors C301 and C302. Symbol 3016a, symbol 3016b is a junction connecting p-type diffusion layers 3015a, 3015b and gold-193-201010062-type wiring 3019a, symbol 3019b, and symbol 3017a, symbol 3017b is an n-type diffusion layer formed on n-type well 3002, symbol 3〇18a, symbol 3018b is a contact connecting the n-type diffusion layer 3017a, the symbol 3017b, and the metal wirings 3019a and 3019b, and the symbol 3019a and the symbol 3〇191 are each a metal wiring which becomes the control gate wiring of T302 and T3 03. Symbol 3 020 is an insulating oxide film for separation. The symbol 21a and the symbol '21b are contacts for connecting the metal wiring layer 3 022 and the n-type diffusion layers 3006a and 3〇06b, and the symbol 3 022 is a metal wiring layer. The memory cell of the present embodiment is formed by forming the transistor gate CG300 of the transistor 302 and the gate 303 by the common n-type well 3002. That is, it is characterized in that a plurality of capacitors C301 and C302 formed between the control gate CG3 00 and the floating gates FG301 and FG302 of the plurality of floating gate transistors Τ03 and Τ3 03 use the same n-type. Well 30 02 is formed. In this way, the boundary of the well is not required to be separated, and the cell area can be made small. Further, the metal wiring 3012 which is a bit line in the vertical direction and becomes the drain D300 of the memory cell in the vertical direction on the drawing surface is disposed in the lateral direction on the drawing surface as the polysilicon layer 3008 for selecting the gate electrode SG300 and as the control gate CG300. The wirings 3019a and 3019b of the wiring are closely arranged with the capacitors C301 and C03 which have a large area, and the drains 3006a and 3006b' of the transistors T302 and T303 which become the memory elements are connected by the metal wiring layer 3 022. It becomes minimal. Further, one of the characteristics of the memory cell of the present embodiment is that a plurality of floating gate type transistors T302 and T3 0 3 and a transistor T301 which becomes a selective transistor are arranged in a straight line on the P type semiconductor substrate 3001. The respective drains of the plurality of floating gate type transistors T302 and T303 are connected by a linear metal wiring layer 3022. Here, the capacitor c301 is composed of an n-type well 3002, -194-201010062 capacitor C301 (3014a), a p-type diffusion layer 3015a, a contact 3?16a, an n-type diffusion layer 3017a, and a contact 3018a. Further, the capacitor C302 is composed of an n-type well 3 002, a capacitor C3 02 (30 1 4b), a p-type diffusion layer 3〇15b, a contact 3016b, an n-type diffusion layer 3017b, and a contact 3018b. Further, in Fig. 56A, although the p-type diffusion layers 3a, 15a, and 3b are separated, they may be integrated into the p-type diffusion layer 3015 because they have the same potential. This is effective when the area is small. However, in this example, since the control gates of the transistor T3 02 and the transistor T3 03 are connected to each other, the control gates of the transistor T3 02 and the transistor T3 03 are shown as equivalent circuits of the FIG. The common ground becomes the control gate CG 300. The operation of the case where the control gates of the transistor T3 02 and the transistor T3 03 are commonly used as the control gate CG 300 is the same as that explained with reference to Fig. 51. [Thirty-third embodiment] Fig. 58 shows an example in which memory cells of Figs. 56A to 56C are arranged in an array. The memory cell is configured with four M3 11~ 〇 M314 in the column direction (lateral direction), three in the row direction (longitudinal direction) as M3 11-M331, and four x3 = 12 cells. By arranging the shared portion in a comparative manner, the memory cells of Fig. 56A to Fig. 56C are more effectively arranged, and the area can be reduced. In this case, if one of the memory cells is arranged in the horizontal direction like the memory cell M3 11 and the memory cell M3 12, the shared n-type well 3 002 is used, and the contacts 3018a and 3018b are also shared. Further, the memory cells M311 to M331 arranged in the vertical direction are connected to the common metal wiring 3012, which becomes the bit line BIT301. Similarly, the memory cells M312 to M332 are connected to the common metal wiring 3012, which becomes the bit line BIT302. Further, the memory cells M313 to -195-201010062 M333 and the memory cells M314 to M334 are connected to the common metal wiring 3012, and these become bit lines BIT3 03 and BIT3 04. Further, the contacts 3016a and 3018a of the memory cells M311 to M314 arranged in the lateral direction are connected to the common metal wiring 3019a, and the respective 3016b and 3018b are connected to the common metal wiring 3019b, and the metal wiring 3019a and the metal wiring 3019b are respectively The gate wiring CG301 is controlled. The pair of control gate wirings CG301 are connected to an external circuit of a memory cell array (not shown). Further, the respective contacts 3011 of the memory cells M3 11 to M3 14 arranged in the lateral direction are connected to the common metal wiring 3013, and the metal wiring 3013 serves as the source wiring S301. Similarly, the contacts 3016a, 3018a of the memory cells M321 to M3 24 arranged in the lateral direction are connected to the common metal wiring 3019a, and the respective 3016b, 301 8b and the common metal wiring 301 9b are connected, and these metal wirings 3019a and metal are connected. Each of the wirings 3019b serves as a control gate wiring CG302. The pair of control gate wirings CG3 02 are connected to an external circuit of a memory cell array (not shown). Further, the respective contacts 3011 of the memory cells M321 to M3 24 arranged in the lateral direction are connected to the common metal wiring 3013, and the metal wiring 3013 is formed as the source wiring S 3 0 2 . Further, the respective contacts 3016a and 3018a of the cells M331-M3 3 4 arranged in the lateral direction are connected to the common metal wiring 3019a, and the respective 3016b and 3018b are connected to the common metal wiring 3019b. These metal wirings 3019a and metal wiring are connected. Each of the pair of control gate wirings CG3 to 3019b is connected to an external circuit of a memory cell array (not shown). Further, the contacts 3011 of the memory cells M331 to M334 arranged in the lateral direction are connected to the common metal wiring 3013, and the metal wiring 3013 serves as the source wiring S303. Further, each of the three polysilicon layers 3008 is shared by the memory cells arranged in the lateral direction, and is selected from the above-196-201010062 gate wirings SG301, SG302, and SG303 ° [34th embodiment] at 5th 5A - Figure 59C shows another embodiment. Fig. 5A is a plan view of the memory cell of the embodiment, Fig. 59B is an equivalent circuit diagram, and Fig. 59C is a cross-sectional view taken along line A30-A30' of Fig. 59A. Further, in the descriptions of Figs. 59 to 59C, the same symbols are used for the same (or corresponding) configurations as those shown in Figs. 56 to 57C. In order to further improve the reliability of the memory cell, as shown by the equivalent circuit of FIG. 59B, three floating gate type transistors T3 02, T3 which are connected in series with the transistor body T301 in parallel are connected in parallel. 03 and T3 04 are set as non-volatile semiconductor memory components. In this example, the three control transistors T3 02, T3 03, and T3 04 control gate CG3 00 are shared to achieve an area reduction effect. In the present embodiment, as compared with the memory cells of the thirty-third embodiment shown in the 56th to 56thth embodiments, the n-type wells 3317 and 3017b are omitted when the n-type well 3 002 for controlling the gate is omitted. The dots 3018a and 3018b also change the diffusion layer of the other end of the capacitors C301 to C303 constituting the transistors T302 to T304 to the n-type diffusion layer 3055, and share the difference. Further, the control gate CG300 which is connected in common to the other ends of the capacitors C301 to C303 of the transistors Τ302 to Τ304 is connected to the metal wiring 3019 via the contact 3016. That is, the present embodiment is characterized in that a plurality of capacitors c301 formed between the control gate CG300 and the floating gates of the plurality of floating gate transistors 302 to 304 are formed using the same n-type diffusion layer 3055. C3 03. Further, in the 59Ath to 59thth drawings, the symbol 3004〇 is a floating gate type transistor constituting the transistor T304, and the symbol 3006a is the source of the transistor T301-197-201010062 which also becomes the transistor T3 〇2. The n-type diffusion layer of the pole, the symbol 3 006b is an n-type diffusion layer which is connected to the source of the transistor T3 03, T3 04 via the metal wiring layer 3022 and the source of the transistor 301, and the symbol 3007a is the transistor 302. The n-type diffusion layer of the source of Τ303, the symbol 3007b is an n-type diffusion layer which becomes the source of the transistor Τ304, and the symbol 3〇〇9c is a polysilicon layer which becomes a floating gate of the transistor Τ3〇4, and becomes a capacitor. One end of C3 03. Reference numeral 3011a is a contact connecting the diffusion layer 3007a and the metal wiring 3013a, reference numeral 3011b is a contact connecting the diffusion layer 3007b and the metal wiring 3013b, and symbol 3〇1 3a is a source for pulling out the transistors T3 02 and T3 03. The metal wiring, symbol 3013b is a metal wiring for pulling out the source of the transistor T304, and reference numeral 3019 is a metal wiring for controlling the gate wiring of T3 02 to T 3 04. Further, although not shown, impurities such as phosphorus (1) + ) are injected into the gate portions forming the capacitors C301 to C303, and 〇 is performed (46?1 to 丨〇11). It is typed and operates as a highly efficient capacitor. [35th Embodiment] Fig. 60 shows an embodiment in which memory cells shown in Figs. 59A to 59C are arrayed. In the memory cell shown in Fig. 60, four memory cells M3 11 to M3 14 are arranged in the column direction (lateral direction), and three of M311 to 331 are arranged in the row direction (longitudinal direction), and 4x3 = 12 are arranged. Cell. The area can be reduced by configuring the shared portion in contrast and more efficiently configuring the memory cells of the Fig. 95. In this case, the contact 3010 connecting the n-type drain diffusion layer 3005 of the transistor 301 and the metal wiring 3012, and the junction 1 1 b of the n-type diffusion layer 3007b and the metal wiring 3013b connected to the source of the transistor Τ304 are connected. , in the upper and lower memory cells (such as memory cells Μ 3 2 1 and remember -198- 201010062 memory cells Μ 3 3 1) shared, and, left and right memory cells (such as memory cells M311 and memory cells M312 The plurality of capacitors C301 to C3 03 are formed in the same n-type diffusion layer 3055, and the arrangement can be further reduced. In this case, the respective contacts 3016 of the memory cells 311 to 314 arranged in the lateral direction are connected to the common metal wiring (the metal wiring 3019 of the ninth to fifth ninth), and the metal wiring becomes the control gate wiring. CG301. Further, each of the contacts 3011a or 3011b of the memory cells 311 to 314 arranged in the lateral direction is connected to the common metal wiring 3013a or 3013b, and the metal wiring 3013a serves as the source wiring S311, and the metal wiring 3013b serves as the source wiring. S312. The source wiring S311 and the source wiring S312 are the source S300 corresponding to the memory cells of the fifth to fifth pictures, and the source wiring S311 and the source are connected to the external circuit of the memory cell array (not shown). Wiring S312. Similarly, the respective contacts 3016 of the memory cells M3 21 to M3 24 arranged in the lateral direction are connected to the common metal wiring, and this metal wiring becomes the control gate wiring CG3 02. Further, each of the contacts 3011a or 3011b of the memory cells M321 to M324 排列 arranged in the lateral direction is connected to the common metal wiring 3013a or 3013b, and the metal wiring 3013a serves as the source wiring S321, and the metal wiring 3013b serves as the source wiring. S322. The source wiring S321 and the source wiring S3 22 are source S300 corresponding to the memory cells of the ninth to ninety-fifthth, and the source wiring S321 and the source are connected to an external circuit of the memory cell array (not shown). The pole wiring S322. The same applies to the memory cells M33 1 to M334 arranged in the lateral direction. [36th embodiment] FIG. 61 is a view showing a circuit configuration of a nonvolatile semiconductor memory device using the embodiment -199-201010062 of the third to third embodiments of the present invention. As the memory cells M3 1 1 to M3mn in Fig. 61, nonvolatile semiconductor memory cells described with reference to, for example, Fig. 56A to Fig. 56C, Fig. 59A to Fig. 59C, and the like can be used. Further, the arrangement of the memory cells in this case can be performed by using the array configuration described with reference to Figs. 58 and 60. In Fig. 61, symbols (M311) to (M3mn) are mxn memory cells, and symbol 3100 is a cell array in which arrays of these memory cells M311 to M3mn are arrayed, and symbols 3200-1 to 3200-m are m column decoders, symbol 33 00 is the row selection gate circuit, symbols 3400-1 to 3 40〇-11 are 11 © row decoders, symbol 3500 is the write and erase control circuit, symbol 3600, is reading A sense amplifier that operates at the time, symbol 3 700 is an internal power supply circuit. Further, in the circuit configuration shown in Fig. 61, each memory cell M311 to M3mn uses a memory cell composed of three transistors T3 01 to T3 03 described with reference to Figs. 56 to 56C. However, the number of the parallel connection types of the floating gate type transistor Τ300, Τ3 03, etc. is not limited to two, and may be three or three or more as shown in the 59th to 5th 9th. The column decoder 3200-1 is outputted from the decoding unit 3 2 0 1 of the input column address, the inverter 3202 outputted to the selection gate SG301, the level shifter and buffer 3203, and the output to the control gate CG301. The N AND circuit 3204 is constituted by a level shifter and a buffer (output unit) 3 205. The gate output SG301 and the memory cell array 3100 are connected in common in the column direction (the horizontal direction on the drawing), and the gate output CG3 01 is controlled. The memory cells M311 to M31n are connected in common. The selection gate SG301 is connected to the selection gate SG3 00 of each of the memory cells M311 to M31n, and the control gate output CG301 is connected to the control gate CG300 of each memory cell -200-201010062 M311 to M31n. In addition, the write signal W300 input by the NAND circuit 3204 of the column decoder 3200-1 is a signal for selecting the control gate CG300 of the memory cells M3 11 to M31n, and when the write signal W300 is "1", the NAND circuit 3204 becomes activated. Further, at the time of erasing and reading, by setting the write signal W300 = "0", the NAND circuit 3204 becomes inactive, and the control gate CG300 is controlled to 0V. The column decoder 3200-1 is configured by the above, and outputs the root address of the memory cell to the predetermined control gate CG3 00 (the control gate CG300 of the memory cells M3 11 to M3 1n). The signal decoded by the address signal and the control gate CG301 generated by the write signal W3 00 of the memory cell. The column decoder 3 200-m is also constructed in the same way. The selected gate output SG30m of the column decoder 3200-m and the n-cell cells M3ml~M3mn arranged in the column direction included in the memory cell array 3100 are connected in common, and the gate output CG30m and the memory cell are controlled. M3ml~M3mn are connected together. The gate output SG30m is connected to the selection gate SG300 of each memory cell M3ml~M3mn, and the control gate output CG30m 连接 is connected to the control gate CG300 of each memory cell M3ml~M3mn. Further, the level shifter and buffer 3203 and the level shifter and buffer 3205 in the column decoders 3200-1 to 3200-m supply the power sources VP301 and VP3 02 output from the internal power supply circuit 3700, The voltages of the selection gate SG3 00 and the control gate CG300 applied to the respective memory cells M3 1 1 to M3 In.....M3 m 1 to M 3 mn can be controlled. The row selection gate circuit 3 300 is composed of η row selection gate transistors COLG301 to COLG30n, and outputs C0301 to C030n from the row decoders 3400-1 to 3400-η at the gates. Select gate electro-crystal -201- 201010062 The respective drains of the COLG301~COLG3〇n are connected in common with the data line Data300, and the respective sources are connected to the bit lines BIT301-0~BIT 30n. Further, the row decoder 3400-1 is composed of a decoding unit 3401 that inputs a line address, an inverter 3402, and a level shifter/buffer 3403 that outputs a line selection signal CO301. The other row decoders 3400 - 2 to 3 4 00 - η are also constructed in the same manner. Further, the level shifter and buffer 3403 in the row decoders 3400-1 to 3400-n are supplied with the power supply VP303 output from the internal power supply circuit 37 00, and can be controlled to be applied to the row selection gate transistor COLG301. The voltage of each gate of the COLG30n. The write/erase control circuit 3500 is a control circuit that accepts the write signal W300 or the erase signal E and outputs a write voltage or a erase voltage to the data line Data300. The write and erase control circuit 3 5 00, in writing, controls the write "0" or write "1" according to the Din3 00 signal (substantially "1" prohibits writing). The write/erase control circuit 3500 is supplied to the power supply VP304 output from the internal power supply circuit 3700, and the voltage applied to the drain D300 of each of the memory cells M311 to M31n, ..., M3ml to M3mn can be controlled. In addition, the sense amplifier 3 6 00 is a sense amplifier that amplifies and outputs the data of the memory cell at the time of reading, and the internal power supply circuit 3 00 generates a voltage required for writing, erasing, and reading. Power circuit. Further, the drain of the transistor 3 800 is connected to the source S300 of each of the memory cells M3U to M3mn, and a predetermined voltage is applied to the source thereof, and the opening and closing is controlled in accordance with the signal EB 3 00 . By controlling the transistor 3 800, the source S300 of each of the memory cells M311 to M3mn can be made to be open or a predetermined potential can be applied. Further, in the present embodiment, the internal power supply circuit 3 70 0 generates the write-202-201010062 and the voltages required for erasing (VP301 to VP304), but the voltages VP301 to VP3 04 are directly supplied from the outside, and are omitted. The internal power supply circuit 3700 operates in the same manner. Fig. 62 is a view showing the operation of the nonvolatile semiconductor memory device shown in Fig. 61. Fig. 62 shows the logic levels applied to the selection gate SG300, the control gate CG300, the drain D300, and the source S 300 of each of the memory cells M311 to M3mn and the write signal W300 in each operation mode. Here, the write signal W3 00 is "1" when writing, and becomes "〇" when 非 (that is, when reading or erasing) when non-writing, is input at the time of writing in Fig. 61. The column decoders 3200-1 to 3200-m and the signals of the write/erase control circuit 3500. As described above, the write signal W3 00 of the N AND circuit 3204 of the input column decoders 3200-1 to 3200-m is a signal for selecting the control gate CG300 of each of the memory cells M311 to M3mn, at the time of writing. In order to activate the NAND circuit 3204, W300 = "1" is set, and at the time of erasing and reading, in order to make the control gate CG3 00 always become 0V, W300 = "0" is set. As shown in Fig. 62, at the time of writing (writing by hot electron injection), W300 is set to "1", 8V is applied to SG300, 3~8V is applied to CG300, and 5V is applied to D300. S300 applies 0V. A high voltage is applied to the drains and gates of the transistors T302 and T303. In order to operate in the above-described saturated region, a high voltage is applied to the depletion layer near the drain to generate hot electrons, which are injected into the floating gate FG3 00. Because of the injection of electrons, the threshold of the transistors T3 02 and T3 03 on the surface becomes high. When verifying the write (when confirming whether or not writing has been completed), set W3 00 to "1", apply 3V to SG300, apply -203 - 201010062 2V to CG300, and apply 1V to D300. S300 applies 0V. As shown in the description of Fig. 62A, if it has been written, the threshold 値 becomes high. Therefore, the CG3 00 is 2V, and if written, the drain current does not flow. If this current is not detected (or if it is below 既), it will be 2V or more according to the threshold, and the write will end. If the threshold is 2V or less, 尙 is not sufficiently written, and then written again, and continues until the threshold becomes 2V or more.
在拭除的情況，預先將W3 00設爲“ 〇” ，並對SG300 偏壓至10V，對CG300偏壓至0V，對D300偏壓至8V，對 S3 00偏壓至開路（open)或約2V。在此狀態，對汲極和浮動 閘極FG300(FG301及FG302)之間施加高電壓，而FN電流 流動，從浮動閘極FG3 00向汲極放出電子，而表面上看起 來臨限値降低。 在驗證拭除的情況，將W300設爲"0” ，並對SG300In the case of erasing, set W3 00 to "〇" in advance, bias SG300 to 10V, bias CG300 to 0V, bias D300 to 8V, and bias S3 00 to open or about 2V. In this state, a high voltage is applied between the drain and the floating gate FG300 (FG301 and FG302), and the FN current flows, and electrons are discharged from the floating gate FG3 00 to the drain, and the surface appears to be reduced. In the case of verifying the erase, set W300 to "0" and SG300
施加3V，對CG300施加0V，對D300施加1.5V，對S300 施加0.5V以上的電壓。在此狀態，若表示拭除之規定的電 流流動，判斷爲拭除結束。在記憶胞元電流未達到規定値 的情況，再追加拭除，並再驗證拭除。 讀出時，將W300設爲“0” ，並對SG300施加3V(或 3〜5V)，對CG300施力口 0V ·對D300施力口 IV，對S300施 加0V時，若係寫入狀態（臨限値爲正），電流不流動，而判 斷爲“ 〇 ” ，若係拭除狀態（臨限値爲負），電流流動，而判 斷爲“ 1” 。 又，在寫入亦以FN電流進行的寫入3-2，將W300 設爲“ 1” ，並若對SG300施加8V(或5V)，對CG3 00施加 15V，對D300施加0V，對S300施加開路或0V，則對通道 -204- 201010062 和浮動閘極間施加高電壓，而被進行電子注入。 在以上之構成，列解碼器3200— 1〜3200_m因應於寫 入信號W300,至少在資料拭除時和讀出時各位準挪移器兼 緩衝器3205的輸出電壓變成0V» 以上，若依據本發明之第3 2 ~第36的各實施形態，因 爲在1層多晶矽製程，可在抑制布置面積的增大下，使用 複數個並列地連接的浮動閘極型電晶體構成記憶胞元，所 以以標準邏輯元件的CMOS製程可實現確保高可靠性的非 〇揮發性半導體記憶體，並可簡單且便宜地實現邏輯元件混 載記憶體。 此外，本發明之第32〜第36的實施形態未限定爲上述 者，例如可進行將在各記憶胞元之浮動閘極型電晶體的並 列地連接個數設爲3個以上之複數個的變更等。 [第37實施形態] 第63A圖表示構成在第37實施形態之記憶元件4001 之1個電晶體的平面圖，第63B圖表示剖面圖，第63 C圖 ❹ 表示等價電路。第63A圖〜第63C圖所示的記憶元件400 1 包含有使用1層多晶矽的胞元構造而形成於半導體基板 SUB400(電位Vsub4f0)上的浮動閘極FG400、汲極D400以 及源極S400而構成。此浮動閘極FG400是成爲電荷保持 區域，未設置電極，利用多晶矽形成於在半導體基板 SUB400所形成之閘極絕緣層上。汲極D400及源極S400 各自是形成於半導體基板SUB 400上的擴散區域，各自經 由接點而設置電極。 第64圖係表示記憶元件400 1之耦合系統之等價電路 -205- 201010062 的示意圖。若有位於浮動閘極FG4 00的電荷Q400,因爲此 系統的總電荷爲Q400，所以如以下的第（5)式表示電荷 Q400。 (VSub400— VFG400)氺 C400(FB400) + (VD400— VFG400)氺 C400(FD400) + (VS400- VFG400) * C400(FS400) + (Vch400-VFG400) * C400(FC400) = Q400 (5) 此外，VFG400、VD400、VS400 以及 Vch400 各自是 浮動閘極FG400的電位、汲極D400的電位、源極S400的 電位以及通道CH400的電位。又，C400(FB400)是浮動閘 極 FG400和半導體基板 SUB400之間的靜電電容， C400(FD400)是浮動閘極FG400和汲極D400之間的靜電電 容，C400(FS400)是浮動閘極FG400和源極S400之間的靜 電電容，C400(FC400)是浮動閘極FG400和通道CH400之 間的靜電電容。在此，若總靜電電容爲CT4 00，如以下的 第（6)式所示表達。 C400(FB400)+C400(FD400)+C400(FS400)+C400(FC400)=CT400 (6) 此外，如以下的第（7)所示表達VFG400。 VFG400 = VSub400 氺 C 4 0 0 (F D 4 0 0) / C T 4 0 0 + (V D 4 0 0 * C400(FD400)/CT400 + VS400 * C 4 0 0 ( F S 4 0 0) / C T 4 0 0 + V c h 4 0 〇 * C400(FC400)/CT400 — Q400/CT400 (7) 在此，Q400/CT400[V]表示對浮動閘極FG400注入電 荷時的電位。在此，若Vsub400 = 0[V]，則 VFG400= { VD400 氺 C 4 0 0 (F D 4 0 0) + V S 4 0 0 * C400(FS400) +Vch400 * C400(FC400)} /CT400 一 Q400/CT400 (8) -206- 201010062 在此，雖然各靜電電容的比因製程而稍微相異’但胃 大致上，C400(FD400): C400(FS400): C400(FC400) =約 〇· 1 ： 0.1: 0.8。在此，若將浮動閘極 FG4 00中的電荷設爲 Q400· CT400=_ZiVFG400，並設 CT400 = 1 ，貝 IJ 如以下的 第（9)式所示表達VFG400。When 3V is applied, 0V is applied to CG300, 1.5V is applied to D300, and a voltage of 0.5V or more is applied to S300. In this state, if the predetermined current flow of the erasing is indicated, it is determined that the erasing is completed. In the case where the memory cell current does not reach the specified threshold, the erase is added and the erase is verified. When reading, set W300 to “0”, apply 3V (or 3 to 5V) to SG300, apply 0V to CG300, apply force IV to D300, and apply 0V to S300. The threshold is positive), the current does not flow, and it is judged as “〇”. If the state is erased (the threshold is negative), the current flows and is judged as “1”. Further, writing 3-2 with FN current is written, W300 is set to "1", and if 8V (or 5V) is applied to SG300, 15V is applied to CG3 00, 0V is applied to D300, and S300 is applied to S300. Open circuit or 0V, a high voltage is applied between the channel -204-201010062 and the floating gate, and electron injection is performed. In the above configuration, the column decoders 3200-1 to 3200_m correspond to the write signal W300, and at least during data erasing and reading, the output voltage of the quasi-shifter and buffer 3205 becomes 0V» or more, according to the present invention. In the respective embodiments of the third to the thirty-sixth embodiments, in the one-layer polysilicon process, a plurality of floating gate-type transistors connected in parallel can be used to form the memory cell under the increase of the suppression arrangement area, so that the standard is The logic component CMOS process enables non-volatile volatile semiconductor memory that ensures high reliability, and the logic component mixed memory can be implemented simply and inexpensively. In addition, the 32nd to 36th embodiments of the present invention are not limited to the above, and for example, a plurality of floating gate type transistors in each memory cell may be connected in parallel to a plurality of three or more. Change, etc. [37th embodiment] Fig. 63A is a plan view showing one transistor constituting the memory element 4001 of the 37th embodiment, Fig. 63B is a cross-sectional view, and Fig. 63C is an equivalent circuit. The memory element 400 1 shown in FIGS. 63A to 63C includes a floating gate FG400, a drain D400, and a source S400 which are formed on the semiconductor substrate SUB400 (potential Vsub4f0) using a cell structure of one layer of polysilicon. . The floating gate FG400 is a charge holding region, and an electrode is not provided, and polysilicon is formed on the gate insulating layer formed on the semiconductor substrate SUB400. Each of the drain D400 and the source S400 is a diffusion region formed on the semiconductor substrate SUB 400, and electrodes are provided via the contacts. Fig. 64 is a view showing an equivalent circuit -205 - 201010062 of the coupling system of the memory element 400 1 . If there is a charge Q400 at the floating gate FG4 00, since the total charge of this system is Q400, the charge Q400 is represented by the following formula (5). (VSub400—VFG400)氺C400(FB400) + (VD400—VFG400)氺C400(FD400) + (VS400- VFG400) * C400(FS400) + (Vch400-VFG400) * C400(FC400) = Q400 (5) In addition, VFG400, VD400, VS400, and Vch400 are each the potential of the floating gate FG400, the potential of the drain D400, the potential of the source S400, and the potential of the channel CH400. Moreover, C400 (FB400) is the electrostatic capacitance between the floating gate FG400 and the semiconductor substrate SUB400, C400 (FD400) is the electrostatic capacitance between the floating gate FG400 and the drain D400, and C400 (FS400) is the floating gate FG400 and The electrostatic capacitance between the source S400, C400 (FC400) is the electrostatic capacitance between the floating gate FG400 and the channel CH400. Here, if the total electrostatic capacitance is CT4 00, it is expressed as shown in the following formula (6). C400 (FB400) + C400 (FD400) + C400 (FS400) + C400 (FC400) = CT400 (6) Further, VFG400 was expressed as shown in the following (7). VFG400 = VSub400 氺C 4 0 0 (FD 4 0 0) / CT 4 0 0 + (VD 4 0 0 * C400(FD400)/CT400 + VS400 * C 4 0 0 ( FS 4 0 0) / CT 4 0 0 + V ch 4 0 〇* C400(FC400)/CT400 — Q400/CT400 (7) Here, Q400/CT400[V] indicates the potential when the charge is applied to the floating gate FG400. Here, if Vsub400 = 0[V ], then VFG400= { VD400 氺C 4 0 0 (FD 4 0 0) + VS 4 0 0 * C400(FS400) +Vch400 * C400(FC400)} /CT400 A Q400/CT400 (8) -206- 201010062 Therefore, although the ratio of each electrostatic capacitance is slightly different due to the process, the stomach is roughly C400 (FD400): C400 (FS400): C400 (FC400) = about 〇·1 : 0.1: 0.8. Here, if it will float The electric charge in the gate FG4 00 is set to Q400 · CT400 = _ZiVFG400, and CT400 = 1 is set, and the shell IJ expresses the VFG 400 as shown in the following formula (9).
VFG400 = 0.1 xVD400 + 0.1xVS400 + 0.1 xVch400 + A VFG400 (9) 在此，說明在第63 A圖〜第6 3C圖所示之記憶元件4001 Ο 的拭除。設構成記憶元件400 1之電晶體的通道CH400的 臨限値爲 〇.5[V]。對記憶元件 400 1的拭除是施加 VD400 = 8V > VS400=開路（open)的電位而進行。因爲源極 S400爲開路，所以在此電晶體之通道CH4 00部分，空乏層 擴大，因爲浮動閘極FG400和半導體基板SUB400之間的 靜電電容變成很小，所以可忽略。設△ VFG400 = 0，則如下 式所示表達拭除時之浮動閘極 FG400 的電位 VFG400(Erase)。 ◎ VFG400(Erase) = 0.1x8(V) = 0.8(V) (10) 第65圖係以VFG400的電位爲參數，在模式上表示構 成記憶元件400 1之電晶體之汲極電壓和汲極電流之關係 的圖形。橫軸方向是施加於汲極D400的汲極電壓VD400， 縱軸方向是向汲極流動的汲極電流ID。 對汲極D400施加電壓時，首先，在汲極附近發生空乏 層的電場集中，如第65圖所示，由所謂的高能量所引起的 Band to Band (B to B;頻帶.頻帶間）的電流流動，而產生 一對電洞和電子。是具有高能量之電洞之熱電洞的一部分 -207- 201010062 被浮動閘極FG400取入，而更提高施加於汲極D400的電 壓時，在氧化膜比較厚的情況，如所圖示的圖形所示，在 Fowler-Nordheim的穿隧電流（以下簡稱爲FN電流）流動 前發生接面崩潰，而大電流從汲極D40 0急速地流向半導體 基板SUB400。將發生此接面崩潰的崩潰電壓稱爲VDB400。 此外，關於頻帶·頻帶間之電流的細節，參照「文獻： 『快閃記憶體技術手冊』，編者：舛岡富士雄，發行公司： Science Forum股份有限公司，1993年8月15日發行第1 版第1刷。第5章第2節在非揮發性記憶胞元之帶間隧道 現象的分析，P206〜2 15」》在此，因爲BtoB電流及崩潰 電流是在某固定電場產生，所以和浮動閘極FG400的電位 相依。如第66圖所示，VBD400和施加於閘極之閘極電壓 VG400 相依，VFG400 低時，VBD400 亦變低，而 VFG400 高時，VBD400亦變高。 接著，考察拭除動作。若設發生頻帶·頻帶間電流的 極限電位爲5V，則在VD400 = 8V時，拭除至浮動閘極FG400 的電位VFG4〇0變成3V爲止。換言之，熱電洞被拄入浮動 閘極。 拭除時，因爲使源極S400變成開路，VS400變成幾乎 0V，因爲通道亦變成不導通，若通道CH400亦變成幾乎 0V，在起始狀態，因爲△ VFG400 = 0V，所以可從第（9)式導 出第（10)式。因爲起始的VFG4 00爲0.8V，所以拭除後變 成3V時，拭除時的變化量△VFG400(Erase)變成+2.2V。 另一方面，對記憶元件4001的寫入，施加VD400 = 5V、 VS400 = 0V而進行。此時，寫入前的起始狀態一般是拭除狀 -208 - 201010062 態，若是電洞被儲存於浮動閘極FG400之狀態，因爲此電 晶體的通道爲導通狀態，所以通道在飽和區域進行動作。 因此，若假設通道CH400和浮動閘極FG4 00的實際耦合面 積變成一般的約一半，自第（9)式，導出寫入時之浮動閘極 FG400 的電位 VFG400(Program)，作爲第（11)式。 VFG400(Program) = 0.1x5(V) + 0.8x5(V)x0.5 = 2.5(V) (11) 浮動閘極FG400的電位VFG400變成2.5V，通道變成 〇導通，同時產生係屬具有高能量之電子的熱電子，而通道 電流流動。此時，一部分的熱電子被取入浮動閘極FG400， 而進行寫入。在此，因爲電晶體的臨限値爲0.5V，所以浮 動閘極FG400的電位VFG4 00變成0.5V時，通道電流變成 不流動，而結束寫入。此時，因爲浮動閘極FG400的電位 VFG400從 2.5V變成 〇. 5 V，所以寫入時的變化量 △ VFG400(Program)變成—2.0V。 第65圖係在模式上表示記憶元件400 1之拭除及寫入 〇 狀態的電晶體特性的圖。橫軸方向是浮動閘極FG400的電 位VFG400，縱軸方向是流向汲極D400的汲極電流Id，是 在模式上表示在拭除狀態、中性狀態以及寫入狀態的3種 狀態，改變浮動閘極FG400的電位VFG400所取入之電荷 的情況的汲極電流的圖。 其次，說明記憶元件4001的讀出。讀出時，施加 VD400=1V、VS400 = 0V的電壓而進行。此時，若浮動閘極 FG400取入△ VFG400的電荷，則導出浮動閘極FG400的 電位VFG40 0(read)，作爲下式第（12)式。 -209- 201010062 VFG4 00(Read) = 0.1xl(V) + AVFG400 ( 1 2) 記憶元件4 0 0 1記憶「0」時之讀出的情況，在寫入時’ 浮動閘極FG4 00儲存浮動閘極FG4 00的電位比起始狀態變 化一△VFG400(Program)= — 2.0V之量的電子。因而，從第 (12)式導出浮動閘極FG400的電位VFG400( “ 0”），如以 下的第 （13-1)式所示。另一方面，記憶元件4001記憶「1」 時之讀出，在拭除時，浮動閘極FG400儲存浮動閘極FG400 的電位比起始狀態變化△ VFG400(EraSe) = + 2.2V之量的電 洞。因而，從第（12)式導出浮動閘極 FG400的電位 VFG400( “ 1”），如以下的第（13 — 2)式所示。 VFG400(“0”）= 0_1(V)— 2.0(V)=- 1.9(V) (13-1) VFG400( “1” ) = 0.1 (V) + 2.2(V) = 2.3(V) (13-2) 第67圖係整理記憶元件400 1之動作的圖。此外，即 使在施加於汲極D400及源極S400之電位相反的情況，記 憶元件4001亦可進行動作。 其次，使用第68A圖〜第68C圖，說明非揮發性半導 體記憶胞元4002的構成。第68A圖係非揮發性半導體記憶 胞元4002的平面圖，第68B圖係沿著第68A圖之A4 0-A40’的剖面圖，第68C圖係表示由第68A圖及第68B圖 所構成之非揮發性半導體記憶胞元4002的等價電路圖。 首先，如第68C圖所示，非揮發性半導體記憶胞元4002 具有汲極端子 D400、源極端子 S400、選擇閘極端子 SG400、是MOS電晶體的選擇電晶體Tr421以及是浮動閘 極型之1層多晶矽電晶體的記憶元件TM22。此外，記憶 元件Tr422具有和第63 A圖〜第63C圖所示之記億元件400 1 -210- 201010062 相同的特性，並進行動作。 選擇電晶體Tr421的汲極和汲極端子D400連接，選擇 電晶體Tr421的源極和記憶元件Tr422的汲極連接，記憶 元件Tr422的源極和源極端子S400連接。選擇閘極端子 SG4 00輸入選擇信號，並和選擇電晶體Tr421的閘極連接。 其次，使用第68A圖及第68B圖，說明非揮發性半導 體記憶胞元4002的構造。4200是p型半導體基板，在p 型半導體基板上的電晶體形成部4020，形成按照η型擴散 Ο 層4201、閘極區域部42 04、η型擴散層42 02、閘極區域部 4205以及η型擴散層4203的順序串列地連接的區域。 η型擴散層4201(第In型擴散層）形成選擇電晶體 TM21的汲極，η型擴散層4202(第2η型擴散層）形成選擇 電晶體Tr421的源極及記憶元件Tr422的汲極。η型擴散 層4203 (第3η型擴散層）形成記憶元件Tr422的源極。 閘極區域部4204是η型擴散層4201、4202之間的區 域，並是形成選擇電晶體Tr421之通道的區域。閘極區域 〇 部4205是n型擴散層42 02、42 03之間的區域，並是形成 選擇電晶體Tr422之通道的區域。 多晶矽配線4206(第1多晶矽）形成選擇電晶體TM21 的閘極。多晶矽配線4207形成選擇電晶體Tr4 22的閘極。 金屬配線4208(第1金靥配‘線）連接η型擴散層4201和 汲極端子D 40 0。金屬配線4209(第2金屬配線）連接η型擴 散層4203和源極端子S400。接點4210連接η型擴散層4201 和金屬配線4208。 接點4211連接η型擴散層4203和金屬配線4209。 -211 - 201010062 其次’使用第69圖，說明非揮發性半導體記億胞元 4002的動作。 (拭除動作） 在非揮發性半導體記憶胞元4002，藉由對記憶元件 Tr422的浮動閘極注入熱電洞，而使放出浮動閘極所儲存 之電子的拭除動作，如以下所示進行。VFG400 = 0.1 x VD400 + 0.1xVS400 + 0.1 x Vch400 + A VFG400 (9) Here, the erasing of the memory element 4001 所示 shown in Figs. 63A to 6C is illustrated. The threshold 値 of the channel CH400 constituting the transistor of the memory element 400 1 is 〇.5 [V]. The erasing of the memory element 400 1 is performed by applying a potential of VD400 = 8V > VS400 = open. Since the source S400 is an open circuit, the depletion layer is enlarged in the channel CH4 00 portion of the transistor, because the electrostatic capacitance between the floating gate FG400 and the semiconductor substrate SUB400 becomes small, so it can be ignored. When ΔVFG400 = 0, the potential VFG400 (Erase) of the floating gate FG400 at the time of erasing is expressed as shown in the following equation. ◎ VFG400(Erase) = 0.1x8(V) = 0.8(V) (10) Fig. 65 shows the gate voltage and the drain current of the transistor constituting the memory element 400 1 in terms of the potential of the VFG400. The graph of the relationship. The horizontal axis direction is the gate voltage VD400 applied to the drain D400, and the vertical axis direction is the drain current ID flowing to the drain. When applying a voltage to the drain D400, first, the electric field concentration of the depletion layer occurs near the drain, as shown in Fig. 65, Band to Band (B to B; band. band) caused by the so-called high energy. Current flows, creating a pair of holes and electrons. It is part of the thermoelectric hole with high energy hole -207- 201010062 is taken in by the floating gate FG400, and when the voltage applied to the drain D400 is increased, the oxide film is thicker, as shown in the figure As shown, the junction collapse occurs before the tunneling current of Fowler-Nordheim (hereinafter referred to as FN current) flows, and a large current flows rapidly from the drain D40 0 to the semiconductor substrate SUB400. The crash voltage at which this junction collapses is called VDB400. For details of the current between the frequency band and the frequency band, refer to "Documentation: "Flash Memory Technology Manual", editor: Sakaoka Fujio, Distribution Company: Science Forum Co., Ltd., August 15, 1993, Issue 1 1 brush. Chapter 5, Section 2 Analysis of the phenomenon of inter-band tunneling in non-volatile memory cells, P206~2 15" Here, because the BtoB current and the breakdown current are generated at a fixed electric field, and the floating gate The potential of the pole FG400 is dependent. As shown in Figure 66, the VBD400 is dependent on the gate voltage VG400 applied to the gate. When the VFG400 is low, the VBD400 is also low, and when the VFG400 is high, the VBD400 is also high. Next, the erase operation is examined. When the limit potential of the band-to-band current is 5 V, when VD400 = 8 V, the potential VFG4 〇 0 of the floating gate FG400 is erased to 3 V. In other words, the thermoelectric hole is broken into the floating gate. At the time of erasing, since the source S400 is made open, VS400 becomes almost 0V, because the channel also becomes non-conductive, and if the channel CH400 becomes almost 0V, in the initial state, since ΔVFG400 = 0V, it can be from the (9) Equation (10) is derived. Since the initial VFG4 00 is 0.8V, the amount of change ΔVFG400 (Erase) at the time of erasing becomes +2.2V when it is changed to 3V after erasing. On the other hand, writing to the memory element 4001 is performed by applying VD400 = 5V and VS400 = 0V. At this time, the initial state before writing is generally the erased state -208 - 201010062 state. If the hole is stored in the state of the floating gate FG400, since the channel of the transistor is in a conducting state, the channel is performed in the saturated region. action. Therefore, if it is assumed that the actual coupling area of the channel CH400 and the floating gate FG4 00 becomes about half of the general value, the potential VFG400 (Program) of the floating gate FG400 at the time of writing is derived from the equation (9). formula. VFG400(Program) = 0.1x5(V) + 0.8x5(V)x0.5 = 2.5(V) (11) The potential of the floating gate FG400 VFG400 becomes 2.5V, the channel becomes 〇 conduction, and the system generates high energy. The electrons of the electrons flow while the channel current flows. At this time, a part of the hot electrons are taken into the floating gate FG400 to be written. Here, since the threshold 値 of the transistor is 0.5 V, when the potential VFG4 00 of the floating gate FG400 becomes 0.5 V, the channel current becomes non-flowing, and writing is ended. At this time, since the potential VFG400 of the floating gate FG400 is changed from 2.5V to 〇. 5 V, the amount of change in writing ΔVFG400 (Program) becomes -2.0V. Fig. 65 is a view schematically showing the characteristics of the transistor in the erased and written state of the memory element 400 1 in the mode. The horizontal axis direction is the potential VFG400 of the floating gate FG400, and the vertical axis direction is the drain current Id flowing to the drain D400, which is a mode indicating three states of the erase state, the neutral state, and the write state, and the floating state is changed. A diagram of the drain current in the case where the potential of the gate FG400 is taken in by the electric charge VFG400. Next, the reading of the memory element 4001 will be described. At the time of reading, voltages of VD400 = 1 V and VS400 = 0 V were applied. At this time, when the floating gate FG400 takes in the electric charge of ΔVFG400, the potential VFG40 0(read) of the floating gate FG400 is derived as the following equation (12). -209- 201010062 VFG4 00(Read) = 0.1xl(V) + AVFG400 ( 1 2) Memory component 4 0 0 1 When reading “0”, when floating, the floating gate FG4 00 is floating. The potential of the gate FG4 00 is changed by an amount of ΔVFG400 (Program) = - 2.0V. Therefore, the potential VFG400 ("0") of the floating gate FG400 is derived from the equation (12) as shown in the following equation (13-1). On the other hand, when the memory element 4001 memorizes "1", when floating, the floating gate FG400 stores the potential of the floating gate FG400 which is changed by the initial state ΔVFG400(EraSe) = + 2.2V. hole. Therefore, the potential VFG400 ("1") of the floating gate FG400 is derived from the equation (12) as shown in the following equation (13-2). VFG400("0") = 0_1(V) - 2.0(V)=- 1.9(V) (13-1) VFG400("1") = 0.1 (V) + 2.2(V) = 2.3(V) (13 -2) Fig. 67 is a diagram showing the operation of the memory element 4001. Further, even when the potential applied to the drain D400 and the source S400 is reversed, the memory element 4001 can be operated. Next, the configuration of the nonvolatile semiconductor memory cell 4002 will be described using Figs. 68A to 68C. Figure 68A is a plan view of a non-volatile semiconductor memory cell 4002, Figure 68B is a cross-sectional view taken along line A40-A40' of Figure 68A, and Figure 68C is a view of Figure 68A and Figure 68B. An equivalent circuit diagram of a non-volatile semiconductor memory cell 4002. First, as shown in FIG. 68C, the non-volatile semiconductor memory cell 4002 has a 汲 terminal D400, a source terminal S400, a selection gate terminal SG400, a selection transistor Tr421 which is a MOS transistor, and a floating gate type. A memory element TM22 of a 1-layer polycrystalline germanium transistor. Further, the memory element Tr422 has the same characteristics as those of the cells 1001 to 210-201010062 shown in Figs. 63A to 63C, and operates. The drain of the transistor Tr421 is selected to be connected to the drain terminal D400, the source of the transistor Tr421 is selected to be connected to the drain of the memory element Tr422, and the source of the memory element Tr422 is connected to the source terminal S400. The selection gate terminal SG4 00 inputs a selection signal and is connected to the gate of the selection transistor 22121. Next, the configuration of the nonvolatile semiconductor memory cell 4002 will be described using Figs. 68A and 68B. 4200 is a p-type semiconductor substrate, and a transistor forming portion 4020 on the p-type semiconductor substrate is formed in accordance with an n-type diffusion germanium layer 4201, a gate region portion 42 04, an n-type diffusion layer 42 02, a gate region portion 4205, and η. The region in which the diffusion layers 4203 are sequentially connected in series. The n-type diffusion layer 4201 (the first in-type diffusion layer) forms the drain of the selective transistor TM21, and the n-type diffusion layer 4202 (the second n-type diffusion layer) forms the source of the selective transistor Tr421 and the drain of the memory element Tr422. The n-type diffusion layer 4203 (third n-type diffusion layer) forms the source of the memory element Tr422. The gate region portion 4204 is a region between the n-type diffusion layers 4201 and 4202, and is a region where a channel for selecting the transistor Tr421 is formed. The gate region 205 portion 4205 is a region between the n-type diffusion layers 42 02 and 42 03 and is a region where a channel for selecting the transistor Tr422 is formed. The polysilicon wiring 4206 (first polysilicon) forms the gate of the selection transistor TM21. The polysilicon wiring 4207 forms a gate of the selection transistor Tr4 22. The metal wiring 4208 (the first metal 靥 [wire] is connected to the n-type diffusion layer 4201 and the 汲 terminal D 40 0. The metal wiring 4209 (second metal wiring) is connected to the n-type diffusion layer 4203 and the source terminal S400. The contact 4210 connects the n-type diffusion layer 4201 and the metal wiring 4208. The contact 4211 connects the n-type diffusion layer 4203 and the metal wiring 4209. -211 - 201010062 Next, the operation of the non-volatile semiconductor memory cell 4002 will be described using Fig. 69. (Erasing operation) In the nonvolatile semiconductor memory cell 4002, a cleaning operation for discharging electrons stored in the floating gate by injecting a thermoelectric hole into the floating gate of the memory element Tr422 is performed as follows.
對選擇閘極端子SG400施加10V的電壓，並對汲極端 子D400施加8V的電壓，使源極端子S400變成開路（開路 狀態）。此時，選擇電晶體Tr421變成導通狀態，記憶元件 Tr422的汲極經由選擇電晶體Tr4 21，被施加8V的電壓。 因而，在記憶元件Tr 422的汲極附近發生空乏層的電 場集中，B to B的電流流動，而產生一對電洞和電子。所 產生之是具有高能量之電洞之熱電洞的一部分被浮動閘極 取入，而從浮動閘極放出電子。因爲電洞被儲存於浮動閘 極，所以記憶元件Tr422的臨限値降低。A voltage of 10 V was applied to the selection gate terminal SG400, and a voltage of 8 V was applied to the gate terminal D400 to make the source terminal S400 open (open state). At this time, the selection transistor Tr421 is turned on, and the drain of the memory element Tr422 is applied with a voltage of 8 V via the selection transistor Tr421. Thus, the electric field concentration of the depletion layer occurs in the vicinity of the drain of the memory element Tr 422, and the current of B to B flows to generate a pair of holes and electrons. A portion of the thermoelectric hole that is created with a high energy hole is taken in by the floating gate and emits electrons from the floating gate. Since the hole is stored in the floating gate, the threshold of the memory element Tr422 is lowered.
此外，施加於汲極端子D400的電壓經由選擇電晶體 Tr421而施加於記憶元件Tr422的汲極，施加於選擇閘極 端子的電壓比施加於汲極端子D400的電壓高時，比較容易 控制記憶元件Tr422的汲極電壓。 (寫入動作） 藉由對記憶元件Tr422的浮動閘極注入熱電子，而對 浮動閘極注入電子的寫入動作，如以下所示進行。對選擇 閘極端子SG400施加7V的電壓，並對汲極端子D400施加 5V的電壓，對源極端子S400施加0V的電壓。因爲進行寫 入時一般是拭除狀態，所以浮動閘極內儲存電洞，而記憶 -212- 201010062 元件Tr422位於導通狀態。 因而，和記憶元件Tr422之汲極和源極的通道電流同 時產生熱電子，部分的熱電子被注入浮動閘極。 因爲浮動閘極儲存電子，所以記憶元件Tr422的臨限 値變高。 (讀出動作） 對選擇閘極端子SG400施加3V的電壓，並對汲極端 子D400施加IV的電壓，對源極端子S400施加0V的電壓 Ο而進行讀出。 此外，相對於在讀出時施加於閘極的電壓（3 V)，將記 憶元件Tr422的臨限値電壓高之狀態（寫入狀態）的情況當 作記憶資料“ 〇” ，而將記憶元件Tr422的臨限値電壓低之 狀態（拭除狀態）的情況當作記憶資料“ 1 ” 。 (非選擇動作） 對記憶元件Tr 4 22不進行動作時，對選擇閘極端子 SG400施力卩0V的電壓。因而，選擇電晶體Tr 421變成不導 〇 通狀態，而成爲非選擇之狀態。 如上述所示，對非揮發性半導體記憶胞元4002進行寫 入、拭除、讀出以及非選擇。此外，在各個動作之浮動閘 極FG400的電位及電位的變化量和第67圖所示的電位及 電位的變化量是相同》 藉由在非揮發性半導體記憶胞元4002所具備之記憶 元件Tr4 2 2使用具有藉1層多晶矽之浮動閘極FG4 00的構 成，而可使用標準CMOS製程，即在形成邏輯電路之CMOS 電晶體所使用的製程，製造非揮發性半導體記憶胞元4002。 -213- 201010062 [第38實施形態] 第70A圖〜第70C圖係表示第38實施形態之非揮發性 半導體記憶胞元3之構成的示意圖。第70A圖係非揮發性 半導體記憶胞元4003的平面圖，第70B圖係沿著第70A 圖之B40— B40’的剖面圖，第70C圖係表示由第70A圖 及第70B圖所構成之非揮發性半導體記憶胞元4003的等價 電路圖。 首先，如第70C圖所示，非揮發性半導體記憶胞元4003 具有汲極端子 D400、源極端子 S400、選擇閘極端子 SG400、是MOS電晶體的選擇電晶體Tr4 31以及是浮動閘 極型之1層多晶矽電晶體的記憶元件Tr432、Tr433。此外， 記憶元件Tr432、Tr433具有和第63 A圖~第63C圖所示之 記憶元件400 1相同的特性，並進行動作》 選擇電晶體Tr431的汲極和汲極端子D400連接，而源 極和記憶元件Tr432、Tr43 3的汲極連接，記憶元件Tr4 3 2、 Tr43 3的源極和源極端子S400連接。即，並列地連接的記 憶元件Tr43 2、Tr43 3和選擇電晶體Tr43 1串列地連接。選 擇閘極端子SG4 00輸入選擇信號，並和選擇電晶體Tr4 31 的閘極連接。 其次，使用第70A圖及第70B圖，說明非揮發性半導 體記憶胞元4003的構造。在p型半導體基板4300上的電 晶體形成部4030,按照η型擴散層4301(第In型擴散層）、 閘極區域部4305、η型擴散層4302(第2n型擴散層）、閘極 區域部4306、η型擴散層4303 (第3n型擴散層）、閘極區域 部4307以及η型擴散層4304(第4n型擴散層）的順序串列 -214- 201010062 地配置，並在串列方向形成長條狀的區域。 在非揮發性半導體記憶胞元4003，η型擴散層430 1形 成選擇電晶體Tr431的汲極。η型擴散層43 02形成選擇電 晶體Tr431的源極及記憶元件Tr43 2的汲極，η型擴散層 43 03形成記憶元件Tr43 2的源極及記憶元件Tr43 3的源 極。η型擴散層43 04形成記憶元件Tr43 3的汲極。 閘極區域部（第1閘極區域部）4305是η型擴散層 4301、43 02之間的區域，並是形成選擇電晶體Tr431之通 〇 道的區域。閘極區域部4306(第2閘極區域部）是η型擴散 層4302、4303之間的區域，並是形成記憶元件Tr432之通 道的區域。閘極區域部4307(第3閘極區域部）是η型擴散 層4303、43 04之間的區域，並是形成記憶元件Tr43 3之通 道的區域。 多晶矽4308(第1多晶矽）形成選擇電晶體Tr421的閘 極。多晶矽4309(第2多晶矽）形成記憶元件Tr 4 32之浮動 閘極FG402的電極。多晶矽4310(第3多晶矽）形成記憶元 〇 件TM33之浮動閘極FG4 03的電極。 金屬配線4311(第1金屬配線）經由接點4314而連接形 成選擇電晶體Tr4 31之汲極的η型擴散層4301和汲極端子 D400,並在與串列方向垂直的方向配置。金靥配線4312(第 2金屬配線）經由接點4315、4316而連接η型擴散層4302 和η型擴散層4304,並在串列方向配置。金屣配線4313(第 3金屬配線）經由接點4317而連接η型擴散層4303和源極 端子S400，並在與串列方向垂直的方向配置。 此外，金屬配線4313配置成與半導體基板表面保持固 -215- 201010062 定之距離。又，金屬配線43 11、4312配置成保持比金屬配 線4313更遠離半導體基板表面之距離。 其次，第71圖係表示非揮發性半導體記憶胞元4003 的動作圖。說明非揮發性半導體記憶胞元4003的動作。 (寫入動作） 在非揮發性半導體記億胞元4003，藉由對記憶元件 Tr43 2、Tr43 3的浮動閘極FG402、FG403注入熱電子，而 將電子儲存於該浮動閘極的寫入動作，如以下所示進行。 對選擇閘極端子SG400施加7V的電壓，並對汲極端子D400 施加5V的電壓，對源極端子S400施加0V的電壓。因爲 進行寫入動作時一般是拭除狀態，所以浮動閘極FG402、 FG4 03內儲存電洞，而臨限値挪移，記憶元件Tr43 2、Tr4 3 3 是導通狀態。因而，和在記憶元件Tr43 2、Tr433各自的汲 極和源極之間流動的通道電流同時產生熱電子，部分的熱 電子被注入浮動閘極FG402、FG4 03。電子被儲存於浮動閘 極FG402、FG403。結果，記憶元件Tr432、Tr433的臨限 値變高，而成爲進行寫入之狀態。 藉由將熱電洞注入記憶元件Tr43 2、Tr43 3各自的浮動 閘極FG402、FG403，而放出浮動閘極FG402、FG403所儲 存之電子的拭除動作，有以下所示之拭除4- 1及拭除4-2之2種方法。 (拭除4 — 1的動作） 首先，一方之拭除4— 1的動作，對選擇閘極端子SG40 0 施加10V的電壓，並對汲極端子D400施加8V的電壓，使 源極端子S400變成開路（開路狀態）而進行。進行拭除動作 -216- 201010062 時，因爲一般浮動閘極FG402、FG403位於寫入狀態，所 以電子被儲存於浮動閘極FG402、FG403內，而臨限値挪 移，非揮發性記憶元件Tr432、Tr43 3是不導通狀態。此時， 在記憶元件Tr43 2、Tr43 3各自的汲極附近發生空乏層的電 場集中，B to B的電流流動，同時產生一對電洞和電子》 所產生之電洞中具有高能量之熱電洞的一部分被浮動閘極 FG402、FG4 03取入，而從浮動閘極FG402、FG403放出電 子。結果，由於浮動閘極FG402、FG403放出電子（取入電 Ο 洞），而記憶元件Tr43 2、Tr43 3的臨限値降低，成爲拭除 狀態。 (拭除4 — 2的動作） 其次，關於拭除4— 2的動作，對選擇閘極端子SG40 0 施加0V的電壓，並使汲極端子D400變成開路，對源極端 子S400施加8V的電壓而進行。進行拭除動作時，因爲一 般浮動閘極FG402、FG403位於寫入狀態，所以記憶元件 Tr43 2、Tr433是不導通狀態。又，選擇電晶體Tr431是不 〇 導通狀態。藉由對各自的端子施加電壓，而在記憶元件 Tr4 32、Tr4 33的源極附近發生空乏層的電場集中，B to B 的電流流動，同時產生具有高能量之電洞和電子的對。所 產生之電洞的一部分被浮動閘極FG4 02、FG4 03取入，而 從浮動閘極FG402、FG403放出電子。結果，由於浮動閘 極FG402、FG403放出電子（取入電洞），而記憶元件Tr432、 Tr43 3的臨限値降低，成爲拭除狀態。 (讀出動作） 接著，說明讀出動作。讀出動作是對選擇閘極端子 -217- 201010062 SG400施力□ 3V的電壓，並對汲極端子D400施加1 V的電 壓，對源極端子S4 00施加OV的電壓而進行。 此外，相對於在讀出時施加於閘極的電壓（3 V)，將記 憶元件Tr43 2、Tr43 3的臨限値電壓高之狀態（寫入狀態）的 情況當作記憶資料“ 0” ，而將記憶元件Tr43 2、Tr43 3的 臨限値電壓低之狀態（拭除狀態）的情況當作記憶資料 “ 1，， 〇 如上述所示，對非揮發性半導體記憶胞元4003進行使 記憶寫入與拭除之資料的動作、及讀出資料的動作。 非揮發性半導體記憶胞元4003使用上述之寫入、拭除 的動作，使在記憶元件Tr432、Tr43 3所具有之多晶矽所形 成之浮動閘極FG402、FG403儲存電荷，而記憶資料。又’ 非揮發性半導體記憶胞元4003和採用使用2層或3層多晶 矽之記憶元件的構成相比，所使用的製程不會變得複雜’ 而可使用標準CMOS製程來製造。因而’和以往之使用2 層或3層多晶矽的情況相比，可減少製造步驟，而可降低 製造費用。又，非揮發性半導體記憶胞元4003採用具備有 並列地連接之2個記憶元件Tr432、Tr43 3之構成。因而’ 藉由每1位元使用2個元件，而可提高可靠性。 (非揮發性半導體記憶裝置43 50之構成） 其次，第72圖係表示使用非揮發性半導體記憶胞元 4003之非揮發性半導體記憶裝置4350之構成的示意圖。 非揮發性半導體記憶裝置43 5 0具備有控制部43 5 1、感測 放大電路43 52、以及將第70A圖〜第70C圖所示之非揮發 性半導體記憶胞元4003配置成°1列n行（m、n》2)之陣列 -218- 201010062 狀的複數個非揮發性半導體記憶胞元M4 11~M4mn。 又，非揮發性半導體記憶裝置43 5 0具備有汲極線 D401~D40n 、源極線 S401〜S40m 、 選擇閘極線 SG401〜SG40m、資料輸出入線 Data400、行選擇閘 SW401〜SW40n以及行選擇信號線C401~C40n。 汲極線D401~D40n各自設置成對應陣列狀地配置之非 揮發性半導體記憶胞元4003的各行，並和構成各行之非揮 發性半導體記憶胞元4003的汲極端子D400共同連接。 Ο 選擇閘極線SG401~SG40m各自設置成對應陣列狀地 配置之非揮發性半導體記憶胞元4003的各列，並和構成各 列之非揮發性半導體記憶胞元4003的選擇閘極端子SG400 共同連接。 源極線S401~S40n各自設置成對應陣列狀地配置之非 揮發性半導體記憶胞元4003的各列，並和構成各列之非揮 發性半導體記憶胞元4003的源極端子S400共同連接。 行選擇閘 SW401~SW40n的一端和對應之汲極線 Q D401~D40n連接，另一端和資料輸出入線D at a4 00連接， 並切換汲極線D401~D40n和資料輸出入線Data400的連接 與切斷。 在非揮發性半導體記憶裝置43 50，控制部43 5 1具有 控制電路43 53、行解碼器、驅動器4354以及列解碼器、 驅動器4355 — 1〜4355 — m。在記憶胞元M411〜M4mn的各 列具備有列解碼器、驅動器4355 - 1〜4355-m。 控制電路4353根據從外部所輸入之表示動作的命令 信號，而向各個行解碼器、驅動器43 54及列解碼器、驅動 -219- 201010062 器4355 — 1~4355 — m輸出指示和動作對應之電壓之施加的 控制信號。在此，命令信號是表示寫入、拭除4- 1、拭除 4一 2以及讀出之任一種動作的信號。又’控制電路4353 根據所輸入命令信號’而進行對資料輸出入線Data4〇0施 加電壓、或使和資料輸出入線Data40 0的連接變成開路的 控制。 又，行解碼器、驅動器43 5 4根據從外部所輸入之選擇 記憶區域的位址信號和從控制電路43 5 3所輸入之控制信 號，而對行選擇信號線C401~C40n施加電壓，進行行選擇 閘 SW4 01~SW4 0n之導通及不導通的切換。將行選擇閘 SW401~SW40n 選擇導通時，使各個行選擇閘 SW401~SW40n所連接的汲極線D4Ο 1〜D40η和資料輸出入 線Data400變成通電狀態。又，將行選擇閘SW401〜SW40H 選擇不導通時，使各個行選擇閘SW401〜SW4〇n所連接的 汲極線D401〜D40n和資料輸出入線Data400變成不通電狀 態。在此，控制信號是表示對應於寫入、拭除4 - 1、拭除 4 一 2以及讀出之各個動作，而施加於行選擇信號線 C401~C40n、選擇閘極線 SG401~SG40m以及源極線 S401〜S40n之電壓的信號。 又，列解碼器、驅動器4355- 1〜4 355-m將從外部所 輸入之選擇記憶區域的位址信號進行解碼，並決定是否對 各自所連接之選擇閘極線及源極線施加電壓。此時，列解 碼器、驅動器4355 - 1 -4 355— m施加於各自所連接之選擇 閘極線及源極線的電壓是根據從控制電路43 53所輸入之 控制信號而決定。在此，列解碼器、驅動器4355-1 ~4 355 -220- 201010062 -m施加於源極線S401〜S40n的電壓是對應於所輸入之控 制信號所表示的動作之因應於第71圖所示的寫入、拭除以 及讀出動作的電壓，而施加於選擇閘極線SG401~SG40n的 電壓是因應於第71圖所示的寫入、拭除以及讀出動作的電 壓。 感測放大電路4352在讀出動作時，檢測資料輸出入線 Data400所讀出之記憶胞元M41 l~M4mn的資料，將所檢測 之資料放大並向外部輸出。 Ο 其次，說明非揮發性半導體記億裝置43 5 0的動作。在 此，舉例說明對非揮發性半導體記憶胞元M4 1 2的寫入、 拭除以及讀出。 (非揮發性半導體記憶胞元M4 1 2的寫入動作） 首先，控制電路4353從外部輸入表示寫入的命令信 號。行解碼器、驅動器43 54及列解碼器、驅動器43 5 5 — l~4 355-m從外部輸入位址信號。 又，控制電路43 53根據所輸入之命令信號，而對資料 〇 輸出入線Data400施加5V的電壓，並向行解碼器、驅動器 4354及列解碼器、驅動器4355 — 1~4355 — m輸出對應於寫 入的控制信號。又，行解碼器、驅動器43 54根據所輸入之 位址信號及控制信號，而對行選擇信號線C4 02施加7V的 電壓。又，列解碼器、驅動器43 5 5 - 1根據所輸入之位址 信號及控制信號，而對選擇閘極線SG401施加7V的電壓， 並對源極線S401施加〇v的電壓。此時，其他的列解碼器、 驅動器4355— 2〜4 355 — m將各自所連接的選擇閘極線及源 極線設爲開路狀態。 -221- 201010062 因而，資料輸出入線Data400經由行選擇閘SW402， 而和汲極線D402所連接之非揮發性半導體記憶胞元 M412〜M4m2的汲極端子D400連接。對各個非揮發性半導 體記憶胞元M412~M4m2的汲極端子D400施加5V的電 壓。又，藉由對選擇閘極線SG401施加7V的電壓，而非 揮發性半導體記憶胞元M411〜M41n所具有的選擇電晶體 Tr43 1變成導通狀態。而，非揮發性半導體記憶胞元M412 所具有的記憶元件Tr432、Tr433對汲極施加5V的電壓， 對源極施加OV的電壓。結果，非揮發性半導體記憶胞元 M4 12所具有的記憶元件Tr432、Tr433對各自的浮動閘極 FG402、FG403注入熱電子，並儲存電荷，而成爲寫入狀態。 (非揮發性半導體記憶胞元M4 1 2的拭除4 - 1動作） 首先，控制電路43 53從外部的裝置輸入表示拭除4 -1的命令信號。行解碼器、驅動器43 54及列解碼器、驅動 器4355- 1〜4 355— m從外部的裝置輸入位址信號》 又，控制電路43 53根據所輸入之命令信號，而對資料 輸出入線Data400施加8V的電壓，並向行解碼器、驅動器 4354及列解碼器、驅動器4355 — 1〜4355— m輸出對應於拭 除4一1的控制信號。又，行解碼器、驅動器4354根據所 輸入之位址信號及控制信號，而對行選擇信號線C 4 02施加 10V的電壓。又，列解碼器、驅動器43 5 5 - 1根據所輸入 之位址信號及控制信號，而對選擇閘極線SG401施加10V 的電壓，並將源極線S401設爲開路狀態。此時，其他的列 解碼器、驅動器4355 - 2〜4 355— m將各自所連接的選擇閘 極線SG402〜SG40m及源極線S402〜S40m設爲開路狀態。 -222- 201010062 因而，資料輸出入線Data400經由行選擇閘SW402， 而和汲極線D402所連接之非揮發性半導體記憶胞元 M4 12〜M4m2的汲極端子D400連接。而，對各個非揮發性 半導體記憶胞元M412~M4m2的汲極端子D400施加8V的 電壓。又，藉由對選擇閘極線SG4 01施加10V的電壓’而， 非揮發性半導體記憶胞元M4 11〜M41n所具有的選擇電晶 體Tr4 3 1變成導通狀態。而，非揮發性半導體記憶胞元M4 12 所具有的記憶元件Tr432、Tr43 3對汲極施加8V的電壓， 〇又，源極變成開路狀態。結果，非揮發性半導體記憶胞元 M412所具有的記憶元件Tr432、Tr433之各自的浮動閘極 FG4 02、FG4 03被注入熱電子，並儲存電荷，而成爲拭除狀 態。 (非揮發性半導體記憶胞元M412的拭除4— 2動作） 首先，控制電路4353從外部輸入表示拭除4- 2的命 令信號。行解碼器、驅動器43 5 4及列解碼器、驅動器43 5 5 -1〜4 355 - m從外部輸入位址信號。又，控制電路4353根 〇 據所輸入之命令信號，而將資料輸出入線Data400設爲開 路狀態，並向行解碼器、驅動器43 54及列解碼器、驅動器 4355- 1〜4355 — m輸出對應於拭除4-2的控制信號。 行解碼器、驅動器43 54根據所輸入之位址信號及控制 信號，而對行選擇信號線C4 02施加0V的電壓。列解碼器、 驅動器4355 — 1根據所輸入之位址信號及控制信號，而對 選擇閘極線SG401施加0V的電壓，並對源極線S401施加 8V的電壓。此時，其他的列解碼器、驅動器4355 - 2〜4355 —m對各自所連接的選擇閘極線SG402〜SG40m及源極線 -223- 201010062 S4 02〜S 4 0m不施加電壓，而將該選擇閘極線及該源極線設 爲開路狀態。Further, the voltage applied to the 汲 terminal D400 is applied to the drain of the memory element Tr422 via the selection transistor Tr421, and the voltage applied to the selection gate terminal is easier to control the memory element than when the voltage applied to the 汲 terminal D400 is higher. The drain voltage of Tr422. (Write Operation) The writing operation of injecting electrons into the floating gate by injecting hot electrons to the floating gate of the memory element Tr422 is performed as follows. A voltage of 7 V was applied to the selection gate terminal SG400, and a voltage of 5 V was applied to the gate terminal D400, and a voltage of 0 V was applied to the source terminal S400. Since the erase state is generally performed when writing, the hole is stored in the floating gate, and the memory -212-201010062 component Tr422 is in the on state. Therefore, hot electrons are generated simultaneously with the channel currents of the drain and source of the memory element Tr422, and part of the hot electrons are injected into the floating gate. Since the floating gate stores electrons, the threshold of the memory element Tr422 becomes high. (Reading operation) A voltage of 3 V was applied to the selection gate terminal SG400, and a voltage of IV was applied to the gate terminal D400, and a voltage of 0 V was applied to the source terminal S400 to perform reading. Further, with respect to the voltage (3 V) applied to the gate at the time of reading, the state in which the threshold voltage of the memory element Tr422 is high (write state) is regarded as the memory material "〇", and the memory element is used. The condition of the Tr422's threshold voltage (erased state) is regarded as the memory data "1". (Non-selection operation) When the memory element Tr 4 22 is not operated, a voltage of 卩0 V is applied to the selection gate terminal SG400. Therefore, the selection transistor Tr 421 becomes a non-conductive state and becomes a non-selected state. As described above, the non-volatile semiconductor memory cell 4002 is written, erased, read, and non-selected. Further, the amount of change in potential and potential of the floating gate FG400 of each operation is the same as the amount of change in potential and potential shown in Fig. 67" by the memory element Tr4 provided in the nonvolatile semiconductor memory cell 4002. 2 2 A configuration having a floating gate FG4 00 having a 1-layer polysilicon is used, and a non-volatile semiconductor memory cell 4002 can be fabricated using a standard CMOS process, that is, a process used in a CMOS transistor forming a logic circuit. - 213 - 201010062 [Embodiment 38] Fig. 70A to Fig. 70C are views showing the configuration of the nonvolatile semiconductor memory cell 3 of the 38th embodiment. Fig. 70A is a plan view of a nonvolatile semiconductor memory cell 4003, Fig. 70B is a cross-sectional view taken along line B40-B40' of Fig. 70A, and Fig. 70C is a view showing a non-form of Fig. 70A and Fig. 70B. An equivalent circuit diagram of a volatile semiconductor memory cell 4003. First, as shown in FIG. 70C, the non-volatile semiconductor memory cell 4003 has a 汲 terminal D400, a source terminal S400, a selection gate terminal SG400, a selection transistor Tr4 31 which is a MOS transistor, and a floating gate type. The memory elements Tr432 and Tr433 of the one-layer polycrystalline germanium transistor. Further, the memory elements Tr432 and Tr433 have the same characteristics as the memory element 4001 shown in FIGS. 63A to 63C, and operate to select the drain of the transistor Tr431 and the drain terminal D400, and the source and The drains of the memory elements Tr432 and Tr43 3 are connected, and the sources of the memory elements Tr4 3 2 and Tr43 3 are connected to the source terminal S400. Namely, the memory elements Tr43 2, Tr43 3 and the selection transistor Tr43 1 which are connected in parallel are connected in series. The gate terminal SG4 00 is selected to input a selection signal and is connected to the gate of the selected transistor Tr4 31. Next, the structure of the nonvolatile semiconductor memory cell 4003 will be described using Figs. 70A and 70B. The transistor forming portion 4030 on the p-type semiconductor substrate 4300 is an n-type diffusion layer 4301 (inner type diffusion layer), a gate region portion 4305, an n-type diffusion layer 4302 (second n-type diffusion layer), and a gate region. The portion 4306, the n-type diffusion layer 4303 (third n-type diffusion layer), the gate region portion 4307, and the n-type diffusion layer 4304 (fourth-type diffusion layer) are arranged in series -214 - 201010062, and are arranged in the serial direction. Form a long strip of area. In the non-volatile semiconductor memory cell 4003, the n-type diffusion layer 430 1 forms the drain of the selection transistor Tr431. The n-type diffusion layer 431 forms the source of the selection transistor Tr431 and the drain of the memory element Tr43 2, and the n-type diffusion layer 43 03 forms the source of the memory element Tr43 2 and the source of the memory element Tr43 3 . The n-type diffusion layer 43 04 forms the drain of the memory element Tr43 3 . The gate region portion (first gate region portion) 4305 is a region between the n-type diffusion layers 4301 and 430, and is a region where the via of the selection transistor Tr431 is formed. The gate region portion 4306 (second gate region portion) is a region between the n-type diffusion layers 4302 and 4303, and is a region where the channel of the memory element Tr432 is formed. The gate region portion 4307 (third gate region portion) is a region between the n-type diffusion layers 4303 and 430, and is a region where the channel of the memory element Tr43 3 is formed. The polysilicon 4308 (first polysilicon) forms the gate of the selection transistor Tr421. The polysilicon 4309 (the second polysilicon) forms the electrode of the floating gate FG402 of the memory element Tr 4 32. The polysilicon 4310 (third polysilicon) forms the electrode of the floating gate FG4 03 of the memory element TM33. The metal wiring 4311 (first metal wiring) is connected to the n-type diffusion layer 4301 and the drain terminal D400 which form the drain of the selection transistor Tr4 31 via the contact 4314, and is disposed in a direction perpendicular to the serial direction. The gold wiring 4312 (second metal wiring) connects the n-type diffusion layer 4302 and the n-type diffusion layer 4304 via the contacts 4315 and 4316, and is disposed in the series direction. The gold-line wiring 4313 (third metal wiring) is connected to the n-type diffusion layer 4303 and the source terminal S400 via the contact 4317, and is disposed in a direction perpendicular to the serial direction. Further, the metal wiring 4313 is disposed to maintain a fixed distance from the surface of the semiconductor substrate -215 to 201010062. Further, the metal wirings 43 11 and 4312 are arranged to maintain a distance further from the surface of the semiconductor substrate than the metal wiring 4313. Next, Fig. 71 shows an action diagram of the nonvolatile semiconductor memory cell 4003. The action of the non-volatile semiconductor memory cell 4003 will be described. (Write Operation) In the nonvolatile semiconductor cell 4003, by writing hot electrons to the floating gates FG402 and FG403 of the memory elements Tr43 2 and Tr43 3, writing of electrons to the floating gate is performed. , as shown below. A voltage of 7 V was applied to the selection gate terminal SG400, and a voltage of 5 V was applied to the gate terminal D400, and a voltage of 0 V was applied to the source terminal S400. Since the erasing state is generally performed during the writing operation, the floating gates FG402 and FG4 03 store the holes, and the thresholds are moved, and the memory elements Tr43 2 and Tr4 3 3 are turned on. Thus, the channel current flowing between the respective drain and source of the memory elements Tr43 2, Tr433 simultaneously generates hot electrons, and part of the hot electrons are injected into the floating gates FG402, FG4 03. The electrons are stored in floating gates FG402, FG403. As a result, the thresholds of the memory elements Tr432 and Tr433 become high, and the writing is performed. By injecting the thermoelectric holes into the floating gates FG402 and FG403 of the memory elements Tr43 2 and Tr43 3, the erase operation of the electrons stored in the floating gates FG402 and FG403 is released, and the eraser 4-1 and the following are shown. Wipe off 2-2 methods. (Operation of erasing 4 - 1) First, one of the operations of erasing 4-1 applies a voltage of 10 V to the selection gate terminal SG40 0 and a voltage of 8 V to the gate terminal D400, so that the source terminal S400 becomes Open circuit (open circuit state). When the erase operation -216- 201010062 is performed, since the floating gates FG402 and FG403 are in the write state, the electrons are stored in the floating gates FG402 and FG403, and the threshold is moved, and the non-volatile memory components Tr432 and Tr43 are stored. 3 is not conductive. At this time, electric field concentration of the depletion layer occurs in the vicinity of the respective drain electrodes of the memory elements Tr43 2 and Tr43 3, and current of B to B flows, and a pair of holes and electrons are generated to generate high-energy thermoelectricity in the hole generated by the electrons. A part of the hole is taken in by the floating gates FG402 and FG4 03, and electrons are discharged from the floating gates FG402 and FG403. As a result, since the floating gates FG402 and FG403 emit electrons (take in the hole), the thresholds of the memory elements Tr43 2 and Tr43 3 are lowered to become the erased state. (Operation of Wiping 4-2) Next, regarding the operation of erasing 4-2, a voltage of 0 V is applied to the selection gate terminal SG40 0, and the crucible terminal D400 is opened, and a voltage of 8 V is applied to the source terminal S400. And proceed. When the erase operation is performed, since the general floating gates FG402 and FG403 are in the write state, the memory elements Tr43 2 and Tr433 are in a non-conduction state. Further, the transistor Tr431 is selected to be in a non-conductive state. By applying a voltage to the respective terminals, the electric field concentration of the depletion layer occurs in the vicinity of the sources of the memory elements Tr4 32 and Tr4 33, and the current of B to B flows, and at the same time, a pair of holes and electrons having high energy is generated. A part of the generated hole is taken in by the floating gates FG4 02 and FG4 03, and electrons are discharged from the floating gates FG402 and FG403. As a result, since the floating gates FG402 and FG403 emit electrons (take in holes), the thresholds of the memory elements Tr432 and Tr43 3 are lowered, and the erased state is obtained. (Reading Operation) Next, the reading operation will be described. The read operation is performed by applying a voltage of 3 V to the gate terminal -217 - 201010062 SG400 and applying a voltage of 1 V to the gate terminal D400, and applying a voltage of OV to the source terminal S4 00. Further, the state in which the threshold voltage of the memory elements Tr43 2, Tr43 3 is high (write state) is regarded as the memory data "0" with respect to the voltage (3 V) applied to the gate at the time of reading, The memory element Tr43 2, Tr43 3 has a low threshold voltage (erased state) as the memory data "1, and as described above, the non-volatile semiconductor memory cell 4003 is made to be remembered. The operation of writing and erasing the data and the operation of reading the data. The non-volatile semiconductor memory cell 4003 forms the polysilicon which is present in the memory elements Tr432 and Tr43 3 by the above-described operation of writing and erasing. The floating gates FG402 and FG403 store charge and memorize data. Moreover, the process used by the non-volatile semiconductor memory cell 4003 and the memory element using two or three layers of polysilicon does not become complicated. 'It can be manufactured using a standard CMOS process. Therefore, it can reduce the manufacturing steps and reduce the manufacturing cost compared with the case of using two or three layers of polysilicon. In addition, non-volatile semiconductor memory cells The 4003 has a configuration in which two memory elements Tr432 and Tr43 3 are connected in parallel. Therefore, reliability can be improved by using two elements per one bit. (Configuration of the nonvolatile semiconductor memory device 43 50) Next, Fig. 72 is a view showing the configuration of a nonvolatile semiconductor memory device 4350 using a nonvolatile semiconductor memory cell 4003. The nonvolatile semiconductor memory device 43 50 is provided with a control portion 43 1 1 and a sense amplifier circuit. 43 52, and the non-volatile semiconductor memory cells 4003 shown in FIGS. 70A to 70C are arranged in an array of 1 column n rows (m, n 2)) - 218 - 201010062, a plurality of non-volatile The semiconductor memory cells M4 11 to M4mn. The non-volatile semiconductor memory device 43 50 includes the drain lines D401 to D40n, the source lines S401 to S40m, the selection gate lines SG401 to SG40m, and the data input and output lines Data400. The gates SW401 to SW40n and the row selection signal lines C401 to C40n are selected. The drain lines D401 to D40n are each arranged in a row corresponding to the rows of the non-volatile semiconductor memory cells 4003 arranged in an array, and the non-volatile portions constituting each row The 汲 terminal D400 of the conductor memory cell 4003 is commonly connected. Ο The gate lines SG401 to SG40m are respectively arranged in columns corresponding to the array of nonvolatile semiconductor memory cells 4003, and the non-volatile columns constituting each column The selection gate terminals SG400 of the semiconductor memory cell 4003 are connected in common. The source lines S401 to S40n are each arranged in a column corresponding to the array of the non-volatile semiconductor memory cells 4003, and the non-volatile columns constituting each column. The source terminals S400 of the semiconductor memory cells 4003 are connected in common. One end of the row selection gate SW401~SW40n is connected with the corresponding dipole line Q D401~D40n, and the other end is connected with the data input and output line D at a4 00, and the connection and disconnection of the dipole line D401~D40n and the data input and output line Data400 are switched. . In the non-volatile semiconductor memory device 435, the control unit 435 has a control circuit 43,53, a row decoder, a driver 4354, and a column decoder, drivers 4355-1 to 4355-m. Each of the memory cells M411 to M4mn is provided with a column decoder and drivers 4355-1 to 4355-m. The control circuit 4353 outputs a voltage corresponding to the instruction and the operation to each of the row decoder, the driver 43 54 and the column decoder, and the drive -219-201010062 4355 - 1 to 4355 - m based on the command signal indicating the operation input from the outside. The applied control signal. Here, the command signal is a signal indicating any one of the operations of writing, erasing 4-1, erasing 4-2, and reading. Further, the control circuit 4353 performs control for applying a voltage to the data input/output line Data4〇0 or opening the connection with the data output/output line Data400 in accordance with the input command signal '. Further, the row decoder and driver 435 apply voltage to the row selection signal lines C401 to C40n based on the address signal of the selected memory area input from the outside and the control signal input from the control circuit 435, and the line is performed. Select the switching between the conduction and non-conduction of the gate SW4 01~SW4 0n. When the row selection gate SW401~SW40n is selected to be turned on, the drain lines D4Ο1 to D40n and the data output/output line Data400 connected to the respective row selection gates SW401 to SW40n are turned on. When the row selection gates SW401 to SW40H are selected to be non-conductive, the drain lines D401 to D40n and the data input/output line Data400 to which the row selection gates SW401 to SW4〇n are connected are rendered non-energized. Here, the control signal is applied to the row selection signal lines C401 to C40n, the selection gate lines SG401 to SG40m, and the source corresponding to the operations of writing, erasing 4-1, erasing 4-2, and reading. The signal of the voltage of the polar lines S401 to S40n. Further, the column decoder and drivers 4355-1 to 355-m decode the address signals of the selected memory area input from the outside, and determine whether or not to apply voltages to the respective selected gate lines and source lines. At this time, the voltages applied to the respective selected gate lines and source lines by the column decoders and drivers 4355 - 1 - 4 355 - m are determined based on the control signals input from the control circuit 43 53. Here, the voltages applied to the source lines S401 to S40n by the column decoders and drivers 4355-1 to 4355-220-201010062-m are corresponding to the actions indicated by the input control signals, as shown in FIG. The voltages for writing, erasing, and reading operations, and the voltages applied to the selection gate lines SG401 to SG40n are voltages corresponding to the writing, erasing, and reading operations shown in FIG. The sense amplifier circuit 4352 detects the data of the memory cells M41 to M4mn read by the data input/output line Data400 during the read operation, and amplifies the detected data and outputs it to the outside. Ο Next, the operation of the non-volatile semiconductor device 430 will be described. Here, the writing, erasing, and reading of the nonvolatile semiconductor memory cell M4 12 are exemplified. (Write Operation of Nonvolatile Semiconductor Memory Cell M4 1 2) First, the control circuit 4353 inputs a command signal indicating writing from the outside. The row decoder, the driver 43 54 and the column decoder, and the driver 43 5 5 - l~4 355-m input the address signal from the outside. Moreover, the control circuit 43 53 applies a voltage of 5 V to the data input/output line Data 400 according to the input command signal, and outputs to the row decoder, the driver 4354, the column decoder, and the drivers 4355-1 to 4355-m corresponding to the write. Incoming control signal. Further, the row decoder and driver 43 54 applies a voltage of 7 V to the row selection signal line C4 02 in accordance with the input address signal and control signal. Further, the column decoder and driver 43 5 5 -1 applies a voltage of 7 V to the selection gate line SG401 based on the input address signal and the control signal, and applies a voltage of 〇v to the source line S401. At this time, the other column decoders and drivers 4355-2 to 355-m set the respective selected gate lines and source lines to an open state. -221- 201010062 Thus, the data input/output line Data400 is connected to the drain terminal D400 of the nonvolatile semiconductor memory cells M412 to M4m2 to which the drain line D402 is connected via the row selection gate SW402. A voltage of 5 V was applied to the enthalpy terminal D400 of each of the nonvolatile semiconductor memory cells M412 to M4m2. Further, by applying a voltage of 7 V to the selection gate line SG401, the selection transistor Tr43 1 of the nonvolatile semiconductor memory cells M411 to M41n becomes in an on state. On the other hand, the memory elements Tr432 and Tr433 included in the nonvolatile semiconductor memory cell M412 apply a voltage of 5 V to the drain and a voltage of OV to the source. As a result, the memory elements Tr432 and Tr433 of the nonvolatile semiconductor memory cell M4 12 inject thermal electrons into the respective floating gates FG402 and FG403, and store charges to be in a write state. (Abrasion 4 - 1 Operation of Nonvolatile Semiconductor Memory Cell M4 1 2) First, the control circuit 43 53 inputs a command signal indicating the erasure of 4-1 from an external device. The row decoder, the driver 43 54 and the column decoder, and the drivers 4355-1 to 355-m input the address signal from the external device. Further, the control circuit 43 53 applies the data input/output line Data400 according to the input command signal. The voltage of 8V is output to the row decoder, the driver 4354, and the column decoder, and the drivers 4355-1 to 4355-m, which output control signals corresponding to the erase 4-11. Further, the row decoder and driver 4354 applies a voltage of 10 V to the row selection signal line C 4 02 based on the input address signal and the control signal. Further, the column decoder and driver 43 5 5 -1 applies a voltage of 10 V to the selection gate line SG401 based on the input address signal and the control signal, and sets the source line S401 to an open state. At this time, the other column decoders and drivers 4355 - 2 to 4 355 - m set the respective selected gate lines SG402 to SG40m and the source lines S402 to S40m to an open state. -222- 201010062 Thus, the data input/output line Data400 is connected to the 汲 terminal D400 of the non-volatile semiconductor memory cells M4 12 to M4m2 to which the drain line D402 is connected via the row selection gate SW402. On the other hand, a voltage of 8 V was applied to the terminal terminal D400 of each of the nonvolatile semiconductor memory cells M412 to M4m2. Further, by applying a voltage of 10 V to the selection gate line SG04, the selective transistor Tr4 31 of the nonvolatile semiconductor memory cells M4 11 to M41n is turned on. On the other hand, the memory elements Tr432 and Tr43 3 of the nonvolatile semiconductor memory cell M4 12 apply a voltage of 8 V to the drain, and the source becomes an open state. As a result, the floating gates FG4 02 and FG4 03 of the memory elements Tr432 and Tr433 of the nonvolatile semiconductor memory cell M412 are injected with hot electrons, and the charges are stored to be erased. (Erasing 4-2 Operation of Nonvolatile Semiconductor Memory Cell M412) First, the control circuit 4353 inputs a command signal indicating the erasing of 2-4 from the outside. The row decoder, the driver 43 5 4 and the column decoder, and the driver 43 5 5 -1 to 4 355 - m input the address signals from the outside. Further, the control circuit 4353 sets the data input/output line Data400 to an open state according to the input command signal, and outputs the data to the row decoder, the driver 43 54 and the column decoder, and the drivers 4355-1 to 4355-m corresponding to Wipe out the 4-2 control signal. The row decoder and driver 43 54 applies a voltage of 0 V to the row selection signal line C4 02 in accordance with the input address signal and the control signal. The column decoder and driver 4355-1 applies a voltage of 0 V to the selection gate line SG401 and a voltage of 8 V to the source line S401 in accordance with the input address signal and control signal. At this time, the other column decoders and drivers 4355-2 to 4355-m do not apply voltage to the selected gate lines SG402 to SG40m and the source lines -223-201010062 S4 02 to S 4 0m. The gate line is selected and the source line is set to an open state.
因而，全部的汲極線D4 0 1〜D40n成爲開路狀態。又， 因爲對選擇閘極線SG401施加0V的電壓，所以非揮發性 半導體記憶胞元M41 1〜M41n所具有的選擇電晶體Tr431變 成不導通狀態。結果，非揮發性半導體記憶胞記憶胞元 M411~M41n所具有的記憶元件Tr432、Tr43 3之汲極爲開 路狀態，而源極被施加8V的電壓。結果，非揮發性半導體 記憶胞記憶胞元 M411〜M41n各自的浮動閘極FG402、 FG403被注入熱電子，並儲存電荷，而成爲拭除狀態。即， 進行非揮發性半導體記憶胞元M411~M4mn之各列的一起 拭除。 (非揮發性半導體記憶胞元M4 1 2的讀出動作）Therefore, all of the drain lines D4 0 1 to D40n are in an open state. Further, since a voltage of 0 V is applied to the selection gate line SG401, the selection transistor Tr431 included in the nonvolatile semiconductor memory cells M41 1 to M41n becomes non-conductive. As a result, the memory elements Tr432 and Tr43 3 of the nonvolatile semiconductor memory cell M411 to M41n are extremely open, and the source is applied with a voltage of 8V. As a result, the floating gates FG402 and FG403 of the non-volatile semiconductor memory cells M411 to M41n are injected with hot electrons, and the charges are stored to be erased. That is, the respective columns of the nonvolatile semiconductor memory cells M411 to M4mn are erased together. (Reading operation of non-volatile semiconductor memory cell M4 1 2)
首先，控制電路43 5 3從外部輸入表示讀出的命令信 號。行解碼器、驅動器43 54及列解碼器、驅動器43 5 5 -l~4355-m從外部輸入位址信號。又，控制電路4353根據 所輸入之命令信號，而將資料輸出入線Data400設爲開路 狀態，並向行解碼器、驅動器43 5 4及列解碼器、驅動器 4355- 1〜4 355 - m輸出對應於讀出的控制信號。 行解碼器、驅動器43 54根據所輸入之位址信號及控制 信號，而對行選擇信號線C402施加3V的電壓。列解碼器、 驅動器4355— 1根據所輸入之位址信號及控制信號，而對 選擇閘極線SG401施加3V的電壓，並對源極線S401施加 0V的電壓。此時，其他的列解碼器、驅動器4355 - 2〜4355 —m對各自所連接的選擇閘極線SG402~SG40m及源極線 -224- 201010062 S402~S40m不施加電壓，而將該選擇閘極線及該源極線設 爲開路狀態。 因而，資料輸出入線Data400經由行選擇閘SW402， 而和汲極線D402連接。又，非揮發性半導體記憶胞元M4 12 的選擇電晶體Tr431變成導通狀態，非揮發性半導體記憶 胞元M412的記憶元件Tr432、Tr43 3的汲極和資料輸出入 線Data400連接。 此時，該記憶元件Tr432、Tr43 3爲寫入狀態，即若因 Ο 各自的浮動閘極所儲存的電荷而記憶元件Tr432、Tr433是 不導通狀態時，電流不流動。又，該記憶元件Tr432、Tr433 爲拭除狀態，即若因各自的浮動閘極所儲存的電荷而記憶 元件Tr43 2、Tr4 3 3是導通狀態時，電流流動。 感測放大電路4352將資料輸出入線Data400的電流放 大並檢測，再向外部的裝置輸出資料。 如此，配置複數個非揮發性半導體記憶胞元4003，藉 由如上述所示連接各自的選擇閘極端子SG400、汲極端子 〇 D400以及源極端子S400，而記憶多位元，可構成可隨機 保存的非揮發性半導體記憶裝置43 50。又，藉由和記憶胞 元M41 l~M4mn —樣地以標準CMOS製程設計感測放大電 路4352、控制電路4353、行解碼器、驅動器4354以及列 解碼器、驅動器4355-1 -4 355— m，而可減少製程數，可 降低製造費用。又，可構成每一位元使用複數個記憶元件 之可靠性高的非揮發性半導體記憶裝置43 50。 (第3 8實施形態之記憶胞元陣列的布置） 其次，第73圖係表示非揮發性半導體記憶裝置43 5 0 -225- 201010062 之記憶胞元陣列部分的示意圖，表示將非揮發性半導體記 憶胞元4 0 0 3平行地配置成陣列狀之非揮發性半導體記憶 胞元Μ 4 1 1 ~ Μ 4 m η的布置。 如第73圖所示，在記憶胞元陣列部分，表示第70Α 圖所示之非揮發性半導體記憶胞元4003的布置配置。 非揮發性半導體記憶胞元Μ411在ρ型半導體基板表 面上的電晶體形成部4030a，雖未圖示，但是如第70Α圖 所示，交互依序配置η型擴散層和閘極區域部，各自串列 地形成方形。 在非揮發性半導體記憶胞元Μ411，多晶矽4308a是選 擇閘極線SG4 01，並是選擇電晶體Tr4 31的閘極。多晶矽 43 09a是記憶元件Tr432的浮動閘極。多晶矽4310a是非揮 發性半導體記憶元件Tr43 3的浮動閘極。 金屬配線4311a是經由接點 4314a和η型擴散層 4301 (第70Β圖）所連接的汲極端子D4 00。金屬配線4312a 經由接點4315a、4316a而連接η型擴散層4302(第70B圖） 和η型擴散層43 04(第7 0B圖）。金屬配線4313a是經由接 點4317a而和記憶元件Tr432、Tr4 33之形成源極的η型擴 散層連接的源極端子S400。 其次，非揮發性半導體記億胞元Μ421在ρ型半導體 基板表面上的電晶體形成部403 0b，雖未圖示，在縱向交 互依序配置第70A圖所示之η型擴散層和閘極區域部，並 形成方形。 在非揮發性半導體記憶胞元Μ42卜多晶矽4308b是選 擇閘極線SG402，並是選擇電晶體Tr43 1的閘極。多晶矽 -226- 201010062 430 9b是記憶元件Tr432的浮動閘極。多晶矽4310b是非 揮發性半導體記憶元件Tr433的浮動閘極。 金屬配線4311b是經由接點4314b和η型擴散層 4301 (第70Β圖）所連接的汲極端子D400。金屬配線4312b 經由接點4315b、4316b而連接η型擴散層4302(第7 0B圖） 和η型擴散層4304(第70B圖）。金屬配線4313b是經由接 點43 17b而和記憶元件Tr43 2、Tr43 3之形成源極的η型擴 散層連接的源極端子S400。 Ο 在所圖示的配置，共用非揮發性半導體記憶胞元Μ4 11 之是汲極端子D400的金屬配線43 11a和非揮發性半導體記 憶胞元M421之是汲極端子D400的金屬配線4311b。又， 共用非揮發性半導體記憶胞元M411、M421各自的接點 43 14a、43 14b，此外，非揮發性半導體記憶胞元M41 1、 M421各自之選擇電晶體TM31之形成汲極的η型擴散層亦 共用》 如此，在上下方向相鄰之2個非揮發性半導體記憶胞 〇 元4 00 3共用成爲選擇電晶體ΤΜ31之汲極的η型擴散層 43 0 1、成爲汲極端子D400的金屬配線4311以及接點 4314,並對金屬配線43 11上下對稱地配置。將如此所配置 之2個非揮發性半導體記憶胞元4 0 03作爲配置的基本單 位。 非揮發性半導體記憶裝置43 5 0之非揮發性半導體記 憶胞元Μ411〜M4mn在上下方向及左右方向排列配置的基 本單位而配置成陣列狀。 在此，非揮發性半導體記憶胞元M4 11〜M4mn使在各 -227- 201010062First, the control circuit 433 receives an external command signal indicating the readout. The row decoder, the driver 43 54 and the column decoder, and the driver 43 5 5 -1 to 4355-m input the address signals from the outside. Further, the control circuit 4353 sets the data output/output line Data400 to an open state based on the input command signal, and outputs the data to the row decoder, the driver 435, the column decoder, and the drivers 4355-1 to 355-m. The readout control signal. The row decoder and driver 43 54 applies a voltage of 3 V to the row selection signal line C402 in accordance with the input address signal and control signal. The column decoder and driver 4355-1 applies a voltage of 3 V to the selected gate line SG401 and a voltage of 0 V to the source line S401 in accordance with the input address signal and control signal. At this time, the other column decoders and drivers 4355 - 2 to 4355 - m do not apply voltage to the selected gate lines SG402 to SG40m and the source lines - 224 - 201010062 S402 - S40m, respectively, and the selection gate is applied. The line and the source line are set to an open state. Therefore, the data input/output line Data400 is connected to the drain line D402 via the row selection gate SW402. Further, the selection transistor Tr431 of the nonvolatile semiconductor memory cell M4 12 is turned on, and the drains of the memory elements Tr432 and Tr43 3 of the nonvolatile semiconductor memory cell M412 are connected to the data output line Data400. At this time, the memory elements Tr432 and Tr43 are in the write state, that is, when the memory elements Tr432 and Tr433 are in a non-conducting state due to the electric charge stored in the respective floating gates, the current does not flow. Further, the memory elements Tr432 and Tr433 are in a erased state, that is, when the memory elements Tr43 2 and Tr4 3 3 are in an on state due to charges stored in the respective floating gates, current flows. The sense amplifying circuit 4352 amplifies and detects the current of the data output to the line Data 400, and outputs the data to the external device. In this manner, a plurality of non-volatile semiconductor memory cells 4003 are arranged, and by connecting the respective selection gate terminals SG400, 汲 terminal 400D400, and source terminal S400 as described above, the multi-bits are memorized, and the random number can be configured to be random. The stored non-volatile semiconductor memory device 43 50. Moreover, the sensing amplifying circuit 4352, the control circuit 4353, the row decoder, the driver 4354, and the column decoder and the driver 4355-1 - 355-m are designed in a standard CMOS process in the same manner as the memory cells M41 l~M4mn. , can reduce the number of processes, can reduce manufacturing costs. Further, it is possible to constitute a highly reliable nonvolatile semiconductor memory device 430 having a plurality of memory elements per bit. (Arrangement of Memory Cell Array of the 38th Embodiment) Next, Fig. 73 is a view showing a memory cell array portion of the nonvolatile semiconductor memory device 43 5 - 225 - 201010062, showing the nonvolatile semiconductor memory The cell 4 0 0 3 is arranged in parallel in an array of non-volatile semiconductor memory cells Μ 4 1 1 ~ Μ 4 m η. As shown in Fig. 73, in the memory cell array portion, the arrangement configuration of the nonvolatile semiconductor memory cell 4003 shown in Fig. 70 is shown. The non-volatile semiconductor memory cell 411 is not shown in the transistor forming portion 4030a on the surface of the p-type semiconductor substrate, but as shown in FIG. 70, the n-type diffusion layer and the gate region are alternately arranged, respectively. Squares are formed in series. In the non-volatile semiconductor memory cell 411, polysilicon 4308a is the gate line SG4 01 selected and the gate of the transistor Tr4 31 is selected. The polysilicon 43 09a is the floating gate of the memory element Tr432. The polysilicon 4310a is a floating gate of the non-volatile semiconductor memory element Tr43 3 . The metal wiring 4311a is a 汲 terminal D4 00 connected via a contact 4314a and an n-type diffusion layer 4301 (Fig. 70). The metal wiring 4312a connects the n-type diffusion layer 4302 (FIG. 70B) and the n-type diffusion layer 43 04 (FIG. 70B) via the contacts 4315a and 4316a. The metal wiring 4313a is a source terminal S400 connected to the n-type diffusion layer forming the source of the memory elements Tr432 and Tr4 via the contact 4317a. Next, the non-volatile semiconductor cell 421 is formed on the surface of the p-type semiconductor substrate by a transistor forming portion 4030b, and is not shown, and the n-type diffusion layer and the gate shown in FIG. 70A are alternately arranged in the longitudinal direction. The regional department and form a square. In the non-volatile semiconductor memory cell 42, the polysilicon 4308b is a gate line SG402, and is a gate of the transistor Tr43. Polycrystalline germanium -226- 201010062 430 9b is the floating gate of the memory element Tr432. The polysilicon 4310b is a floating gate of the nonvolatile semiconductor memory element Tr433. The metal wiring 4311b is a gate terminal D400 connected via a contact 4314b and an n-type diffusion layer 4301 (Fig. 70). The metal wiring 4312b connects the n-type diffusion layer 4302 (FIG. 70B) and the n-type diffusion layer 4304 (FIG. 70B) via the contacts 4315b and 4316b. The metal wiring 4313b is a source terminal S400 connected to the n-type diffusion layer forming the source of the memory elements Tr43 2, Tr43 3 via the contact 43 17b. Ο In the illustrated configuration, the shared non-volatile semiconductor memory cell Μ4 11 is the metal wiring 43 11a of the 汲 terminal D400 and the non-volatile semiconductor memory cell M421 is the metal wiring 4311b of the 汲 terminal D400. Further, the contacts 43 14a and 43 14b of the non-volatile semiconductor memory cells M411 and M421 are shared, and the n-type diffusion of the drain of the selective transistor TM31 of the nonvolatile semiconductor memory cells M41 1 and M421 is formed. In this way, the two non-volatile semiconductor memory cells 4 00 3 adjacent in the vertical direction share the n-type diffusion layer 43 0 1 which is the drain of the selected transistor ΤΜ 31, and the metal which becomes the 汲 terminal D400. The wiring 4311 and the contact 4314 are arranged symmetrically with respect to the metal wiring 43 11 . The two non-volatile semiconductor memory cells 4 0 03 thus configured are used as basic units of configuration. The nonvolatile semiconductor memory devices 411 to M4mn of the nonvolatile semiconductor memory device 430 are arranged in an array in a vertical arrangement in the vertical direction and the horizontal direction. Here, the non-volatile semiconductor memory cells M4 11~M4mn are made at each -227- 201010062
列共同連接用以連接各自之源極端子s 4 00之金屬配線 4311a的源極線S401、S402、S403、S404、…在左右方向 直線狀地通過。又，非揮發性半導體記憶胞元M4 1 l~M4mn 使在各列共同連接各自之多晶矽43 0 8，即選擇電晶體 Tr431 之閘極的選擇閘極線 SG401、SG402、SG403、 SG404、…在左右方向直線狀地通過。又，非揮發性半導 體記憶胞元M411~M4mn使在各行共同連接各自之汲極端 子D400的汲極配線D401、D402、D403、D404、…在上下 方向直線狀地通過。 如上述所示，非揮發性半導體記憶裝置43 50的記憶胞 元陣列彼此共用非揮發性半導體記憶胞元4003所具有之 選擇電晶體Tr431之形成汲極的η型擴散層4301、接點 4314以及金屬配線43Η，並將上下對稱的配置作爲基本單 位，共用一部分地配置。The source lines S401, S402, S403, S404, ... which are connected in common to connect the metal wirings 4311a of the respective source terminals s 4 00 are linearly passed in the left-right direction. Further, the non-volatile semiconductor memory cells M4 1 l to M4mn are connected to the respective polysilicon 430 0 8 in each column, that is, the selection gate lines SG401, SG402, SG403, SG404, ... of the gate of the selected transistor Tr431 are The left and right directions pass straight through. Further, the non-volatile semiconductor memory cells M411 to M4mn linearly pass the drain wirings D401, D402, D403, D404, ... which are connected to the respective terminal terminals D400 in the respective rows in the vertical direction. As described above, the memory cell array of the non-volatile semiconductor memory device 43 50 shares the n-type diffusion layer 4301, the contact 4314 of the formation transistor Tr431 of the non-volatile semiconductor memory cell 4003, and the like. The metal wiring 43 is arranged in a common unit as a basic unit, and is partially shared.
因而，在配置非揮發性半導體記憶胞元M411~M4mn 時，可減少以往是必需之上下間的空間，同時藉由η型擴 散層4301、接點4314以及金屬配線4311的共用，而可使 非揮發性半導體記憶胞元所需的面積變小。又，記憶胞元 陣列的面積減少，而非揮發性半導體記憶裝置43 50的面積 變小，而可增加從1片半導體晶圓可製造之非揮發性半導 體記憶裝置4350的個數。又，亦可減少製造費用。 (第39實施形態） 第74圖係表示第39實施形態之非揮發性半導體記憶 裝置4360之構成的示意圖。非揮發性半導體記憶裝置4360 和第38實施形態的非揮發性半導體記億裝置43 50相比， -228 - 201010062 共同連接非揮發性半導體記憶胞元M411~M4mn之源極端 子S400所連接的源極線S401〜S40m。而共用化成1條源極 線。 在非揮發性半導體記憶裝置4360，對於和非揮發性半 導體記憶裝置43 50相異之控制部43 6 1、控制電路43 6 3、 列解碼器、驅動器4365 — 1~4365— m以及源極驅動器4366 以外之構成，附加相同的符號’並省略說明’以下說明構 成相異之控制電路43 63、列解碼器、驅動器4 3 6 5 -控制用 ◎ 電腦〜43 65 - m以及源極驅動器43 66。 控制部436 1具有控制電路43 63、行解碼器、驅動器 4354、列解碼器、驅動器4365- 1 -4 365— m以及源極驅動 器43 66。非揮發性半導體記憶胞元M41 1〜M4mn之各列具 備有列解碼器、驅動器4365- 1 -4 365— m，並和各列的選 擇閘極線SG401~SG40m連接。 控制電路43 63根據從外部所輸入之命令信號，而向各 個行解碼器、驅動器435 4、列解碼器、驅動器4365- 1〜4 365 Q 一 m以及源極驅動器4366輸出用以指示對應於動作之電壓 之施加的控制信號。在此，命令信號是表示寫入、拭除4 一 1、拭除4一 2以及讀出之任一種動作的信號。又，控制 電路4363根據所輸入之命令信號而進行對資料輸出入線 Data400施加電壓，或使和資料輸出入線Data400之連接變 成開路的控制。 又，行解碼器、驅動器4354根據從外部所輸入之選擇 記憶區域的位址信號和從控制電路4 3 6 3所輸入之控制信 號，而對行選擇信號線C401~C40n施加電壓，進行行選擇 -229- 201010062 閘 SW401〜SW40n之導通及不導通的切換。將行選擇閘 SW401~SW40n 選擇導通時，使各個行選擇閘 SW401~SW40n所連接的汲極線D401〜D40n和資料輸出入 線Data4 0 0變成通電狀態。又，將行選擇閘SW4 01〜SW4 0H 選擇不導通時，使各個行選擇閘SW401~SW40n所連接的 汲極線D401~D40n和資料輸出入線Data400變成不通電狀 態。在此，控制信號是表示對應於寫入、拭除4一 1、拭除 4 一 2以及讀出之各個動作，而施加於行選擇信號線 C401〜C40n、選擇閘極線 SG401~SG40m以及源極線 S401〜S40m之電壓的信號。 又，列解碼器、驅動器43 65 — 1〜4 365— m將從外部所 輸入之選擇記憶區域的位址信號進行解碼，並決定是否對 各自所連接之選擇閘極線施加電壓。此時，列解碼器、驅 動器4365 - l~4 365-m施加於各自所連接之選擇閘極線的 電壓是根據從控制電路43 63所輸入之控制信號而決定。源 極驅動器4366根據從控制電路43 6 3所輸入之控制信號， 而對部之非揮發性半導體記憶胞元M411〜M4mn的源極端 子所共同連接的源極線施加電壓。在此，源極驅動器4366 施加於源極線的電壓是第71圖所示之因應於寫入、拭除及 讀出之動作的電壓。又，列解碼器、驅動器4365 — 1〜4365 —m施加於選擇閘極線SG401〜SG40n的電壓是第71圖所 示之因應於寫入、拭除及讀出之動作的電壓。 其次，說明非揮發性半導體記憶裝置43 60的動作。在 此’舉例說明對非揮發性半導體記憶胞元M412的寫入、 拭除以及讀出。 -230- 201010062 (非揮發性半導體記憶胞元M4 1 2的寫 首先，控制電路4363從外部輸入表 號。行解碼器、驅動器43 54及列解碼器 1〜4 365 - m從外部輸入位址信號。 又，控制電路43 63根據所輸入之命令 輸出入線Data400施加5V的電壓，並向行 4354、列解碼器、驅動器4365- 1〜4365 — 器43 66輸出對應於寫入的控制信號。又， Ο 器43 54根據所輸入之位址信號及控制信部 號線C402施加7V的電壓。又，列解碼ί -1根據所輸入之位址信號及控制信號， SG401施加7V的電壓。此時，其他的列 43 65 — 2~4365 — m 將各自所連接白 SG402~SG40m設爲開路狀態。 因而，資料輸出入線Data400經由行 而和汲極線 D402所連接之非揮發性与 〇 M412~M4m2的汲極端子D400連接，而 D400施加5V的電壓。又，因爲對選擇閘 7V的電壓，所以非揮發性半導體記憶胞另 具有的選擇電晶體Tr4 31變成導通狀態。 半導體記憶胞元M4 12所具有的記憶元件 汲極施加5V的電壓，又，對源極施加0V 自的浮動閘極FG402、FG403注入熱電子 而成爲寫入狀態。 (非揮發性半導體記憶胞元M412的拭 入動作） 市寫入的命令信 、驅動器43 6 5 — 信號，而對資料 :解碼器、驅動器 m以及源極驅動 行解碼器、驅動 E，而對行選擇信 器、驅動器43 65 而對選擇閘極線 解碼器、驅動器 勺選擇閘極線 選擇閘SW402， S導體記憶胞元 對各個汲極端子 極線SG401施加 i M41 1 〜Μ41ιι 所 結果，非揮發性 Tr432 、 Tr433 對 的電壓，而對各 ，並儲存電荷， 除4 _ 1動作） -231 - 201010062 首先，控制電路4363從外部輸入表示拭除4-1的命 令信號。行解碼器、驅動器4354及列解碼器、驅動器4365 一卜43 65-m從外部輸入位址信號。 又，控制電路4363根據所輸入之命令信號，而對資料 輸出入線Data400施加8V的電壓，並向行解碼器、驅動器 4354及列解碼器、驅動器4365- 1~4365 — m輸出對應於拭 除4— 1的控制信號。又，行解碼器、驅動器43 54根據所 輸入之位址信號及控制信號，而對行選擇信號線C4 02施加 10V的電壓。又，列解碼器、驅動器43 65 — 1根據所輸入 之位址信號及控制信號，而對選擇閘極線SG401施加10V 的電壓。又，源極驅動器43 66根據所輸入之控制信號，而 將源極線設爲開路狀態。此時，其他的列解碼器、驅動器 43 65 - 2~4365 - m 將各自所連接的選擇閘極線 SG402~SG40m設爲開路狀態。 因而，資料輸出入線Data400經由行選擇閘SW402, 而和汲極線 D402所連接之非揮發性半導體記憶胞元 M412〜M4m2的汲極端子D400連接，而對各自的汲極端子 D400施加8V的電壓。又，因爲對選擇閘極線SG401施加 10V的電壓，所以非揮發性半導體記憶胞元M41 1〜M41I1所 具有的選擇電晶體Tr43 1變成導通狀態。結果，非揮發性 半導體記憶胞元M412所具有的記憶元件Tr432、Tr4 3 3對 汲極施加8V的電壓，又，源極變成開路狀態’而各自的浮 動閘極FG402、FG403被注入熱電子，並儲存電荷，而成 爲拭除狀態。 (非揮發性半導體記億胞元M4 12的拭除4— 2動作） -232- 201010062 首先，控制電路4363從外部輸入表示拭除4一 2的命 令信號。行解碼器、驅動器43 54及列解碼器、驅動器4365 -1〜4 365 — m從外部輸入位址信號。 又，控制電路4363根據所輸入之命令信號，而將資料 輸出入線Data400設爲開路狀態，並向行解碼器、驅動器 4354及列解碼器、驅動器4365 — 1〜4365-m、源極驅動器 輸出對應於拭除4- 2的控制信號。又，行解碼器、驅動器 43 54根據所輸入之位址信號及控制信號，而對行選擇信號 Ο 線C402施加0V的電壓。又，列解碼器、驅動器43 65 — 1 根據所輸入之位址信號及控制信號，而對選擇閘極線 SG401施加0V的電壓。又，源極驅動器4366根據所輸入 之控制信號，而對源極線施加8V的電壓。此時，其他的列 解碼器、驅動器4365— 2 ~4 365— m將各自所連接的選擇閘 極線SG402〜SG40m及源極線S402〜S40m設爲開路狀態。 因而，全部的汲極線D401~D40n成爲開路狀態。又’ 因爲對選擇閘極線SG401施加0V的電壓’所以非揮發性 〇 半導體記憶胞元M411~M4lIl所具有的選擇電晶體TΓ43 1變 成不導通狀態。結果，非揮發性半導體記憶胞記憶胞元 M411〜M41n所具有的記憶元件Tr432、Tr433之汲極爲開 路狀態，而源極被施加8V的電壓。結果，非揮發性半導體 記憶胞記憶胞元M411~M4mn各自的浮動閘極FG402、 FG4 0 3被注入熱電子，並儲存電荷，而成爲拭除狀態。即， 對全部之非揮發性半導體記憶胞元M411~M4mn進行一起 拭除》 (非揮發性半導體記億胞元M4 12的讀出動作） -233- 201010062 首先，控制電路4363從外部輸入表示讀出的命令信 號。行解碼器、驅動器4354及列解碼器、驅動器4365 -1〜4 365— m從外部輸入位址信號。 又，控制電路4363根據所輸入之命令信號，而將資料 輸出入線Data4 00設爲開路狀態，並向行解碼器、驅動器 4354及列解碼器、驅動器4365— 1〜4 365~m以及源極驅動 器4366輸出對應於讀出的控制信號。行解碼器、驅動器 4354根據所輸入之位址信號及控制信號，而對行選擇信號 線C402施加3V的電壓。又，列解碼器、驅動器4365-1 根據所輸入之位址信號及控制信號，而對選擇閘極線 SG401施加3V的電壓。又，源極驅動器4366根據所輸入 之控制信號，而對源極線S401施加0V的電壓。此時，其 他的列解碼器、驅動器4365 — 2-4 365— m將各自所連接的 選擇閘極線SG402~SG40m及源極線S402〜S40m設爲開路 狀態。 因而，資料輸出入線Data400經由行選擇閘SW402 , 而和汲極線D402連接。又，非揮發性半導體記憶胞元M4 12 的選擇電晶體Tr43 1變成導通狀態，非揮發性半導體記憶 胞元Μ412的記憶元件Tr432、Tr43 3的汲極和資料輸出入 線Data400連接》 此時，該記憶元件Tr432、TM33爲寫入狀態，即，若 因各自的浮動閘極所儲存的電荷而記憶元件Tr432、Tr433 是不導通狀態時，電流不流動。又，該記憶元件Tr432、 Tr4 3 3爲拭除狀態，即，若因各自的浮動閘極所儲存的電 荷而記億元件Tr432、Tr43 3是導通狀態時，電流流動。 -234- 201010062 感測放大電路43 52將資料輸出入線Data400的電流放 大並檢測，再向外部的裝置輸出資料。 如此，配置複數個非揮發性半導體記憶胞元 M4 11〜M4mn，藉由如上述所示連接各自的選擇閘極端子 SG400、汲極端子D400以及源極端子S400，而記憶多位 元，可構成可隨機保存的非揮發性半導體記憶裝置4360。 藉由共同連接全部之非揮發性半導體記憶胞元 M4 1 1〜M4mn的源極端子，而可對全部的非揮發性半導體記 ❹ 憶胞元M411~M4mn —起進行拭除。又，藉由和記憶胞元 M411〜M4mn —樣地以標準CMOS製程設計感測放大電路 4352、控制電路4363、行解碼器、驅動器4354以及列解 碼器、驅動器4365 — 1〜4365— m，而可減少製程數，可降 低製造費用。又，可構成每一位元使用複數個記億元件之 可靠性高的非揮發性半導體記憶裝置4360。 此外，亦可作成按照列單位將記憶胞元陣列分成幾個 方塊，並在各個方塊具備有源極驅動器4366之構成。在此 〇情況，可對所分開的方塊進行拭除。 [第40實施形態] 第75A圖〜第75C圖係表示第40實施形態之非揮發性 半導體記憶胞元4004之構成的示意圖。第75 A圖係非揮發 性半導體記憶胞元4004的平面圖，第75B圖係非揮發性半 導體記憶胞元4004之沿著第75A圖之C40— C40’的剖面 圖，第75C圖係表示由第75A圖及第75B圖所構成之非揮 發性半導體記憶胞元4004的等價電路圖。 首先，如第75C圖所示，非揮發性半導體記憶胞元4004 -235- 201010062 具有汲極端子 D400、源極端子 S400、選擇閘極端子 SG400、是MOS電晶體的選擇電晶體Tr441以及是浮動閘 極型之1層多晶矽電晶體的非揮發性半導體記憶元件 Tr442、Tr443、Tr444。此外，記憶元件 Tr442、Tr443、Tr444 具有和第63 A圖〜第63C圖所示之記憶元件400 1相同的特 性，並進行動作。 選擇電晶體Tr4 41的汲極和汲極端子D400連接，而源 極和記憶元件Tr442、Tr443、Tr444的汲極連接。記憶元 件Tr442、Tr443、Tr444的源極和源極端子S400連接。即， 記憶元件Tr442、Tr443、Tr444彼此並列地連接。又，非 揮發性半導體記憶元件Tr442、Tr443、Tr444和選擇電晶 體Tr441串列地連接。 其次，使用第75Α圖及第75Β圖，說明非揮發性半導 體記憶胞元4004的構造。在ρ型半導體基板44 00之表面 上的電晶體形成部4040，按照η型擴散層440 1(第In型擴 散層）、閘極區域部4406、η型擴散層44 02(第2η型擴散 層）、閘極區域部4407、η型擴散層4403(第3η型擴散層）、 閘極區域部44 08、η型擴散層44 04(第4η型擴散層）、閘極 區域部44 09、以及η型擴散層4405(第5η型擴散層）的順 序形成區域。 在非揮發性半導體記億胞元4004, η型擴散層440 1形 成選擇電晶體Tr 441的汲極。η型擴散層4402形成選擇電 晶體Tr441的源極及記憶元件Tr442的汲極。η型擴散層 4403形成記憶元件ΤΜ42、Tr443的源極。η型擴散層4404 形成記憶元件Tr442、Tr443的汲極。η型擴散層4405形 -236- 201010062 成記憶元件Tr443的源極。 閘極區域部4406是η型擴散層4401、4402之間的區 域，是形成選擇電晶體Tr44 1之通道的區域。閘極區域部 4407是η型擴散層4402、4403之間的區域，是形成記億 元件Tr 4 42之通道的區域。閘極區域部44 08是η型擴散層 4403、4404之間的區域，是形成記憶元件Tr443之通道的 區域。閘極區域部4409是η型擴散層4404、4405之間的 區域，是形成記憶元件ΤΜ44之通道的區域。Therefore, when the non-volatile semiconductor memory cells M411 to M4mn are disposed, the space between the upper and lower sides must be reduced, and the n-type diffusion layer 4301, the contact 4314, and the metal wiring 4311 can be shared. The area required for volatile semiconductor memory cells becomes smaller. Moreover, the area of the memory cell array is reduced, and the area of the non-volatile semiconductor memory device 435 is reduced, and the number of non-volatile semiconductor memory devices 4350 that can be fabricated from one semiconductor wafer can be increased. Moreover, manufacturing costs can also be reduced. (39th embodiment) Fig. 74 is a view showing the configuration of the nonvolatile semiconductor memory device 4360 of the 39th embodiment. The non-volatile semiconductor memory device 4360 is connected to the source connected to the source terminal S400 of the non-volatile semiconductor memory cells M411 to M4mn by -228 - 201010062 as compared with the non-volatile semiconductor device 43 50 of the 38th embodiment. Polar lines S401 to S40m. It is shared into one source line. In the non-volatile semiconductor memory device 4360, the control unit 436, the control circuit 433, the column decoder, the driver 4365-1 to 4365-m, and the source driver are different from the non-volatile semiconductor memory device 43 50. The configuration other than 4366 is denoted by the same reference numeral ', and the description is omitted'. The following description constitutes a different control circuit 43 63, column decoder, driver 4 3 6 5 - control ◎ computer ~ 43 65 - m and source driver 43 66 . The control unit 436 1 has a control circuit 43 63, a row decoder, a driver 4354, a column decoder, drivers 4365-1 - 4 365 - m, and a source driver 43 66. The columns of the non-volatile semiconductor memory cells M41 1 to M4mn are provided with column decoders, drivers 4365-1 - 4 365 - m, and are connected to the selected gate lines SG401 to SG40m of the respective columns. The control circuit 43 63 outputs to the respective row decoders, drivers 435 4, column decoders, drivers 4365-1 to 4 365 Q-m, and the source drivers 4366 according to the command signals input from the outside to indicate the corresponding actions. The control signal applied by the voltage. Here, the command signal is a signal indicating any one of the operations of writing, erasing 4-1, erasing 4-2, and reading. Further, the control circuit 4363 performs control for applying a voltage to the data input/output line Data400 or opening the connection with the data output/output line Data400 based on the input command signal. Further, the row decoder and driver 4354 applies a voltage to the row selection signal lines C401 to C40n based on the address signal of the selected memory area input from the outside and the control signal input from the control circuit 4363, and performs row selection. -229- 201010062 Switching on and off of gates SW401 to SW40n. When the row selection gate SW401~SW40n is selected to be turned on, the drain lines D401 to D40n and the data input/output line Data4 0 0 connected to the respective row selection gates SW401 to SW40n are turned on. Further, when the row selection gates SW4 01 to SW4 0H are selected to be non-conductive, the drain lines D401 to D40n and the data input/output line Data 400 to which the row selection gates SW401 to SW40n are connected are rendered non-energized. Here, the control signal is applied to the row selection signal lines C401 to C40n, the selection gate lines SG401 to SG40m, and the source corresponding to the operations of writing, erasing 4, 1, erasing 4-2, and reading. The signal of the voltage of the polar lines S401 to S40m. Further, the column decoder and driver 43 65 - 1 to 4 365 - m decode the address signals of the selected memory area input from the outside, and determine whether or not to apply voltages to the respective selected gate lines. At this time, the voltages applied to the respective selected gate lines by the column decoders and drivers 4365 - l to 4 365-m are determined based on the control signals input from the control circuit 43 63. The source driver 4366 applies a voltage to the source line to which the source terminals of the nonvolatile semiconductor memory cells M411 to M4mn are commonly connected, based on the control signal input from the control circuit 436. Here, the voltage applied to the source line by the source driver 4366 is the voltage corresponding to the operation of writing, erasing, and reading as shown in Fig. 71. Further, the voltages applied to the selection gate lines SG401 to SG40n by the column decoders and drivers 4365-1 to 4365-m are the voltages corresponding to the operations of writing, erasing, and reading shown in Fig. 71. Next, the operation of the nonvolatile semiconductor memory device 43 60 will be described. Here, the writing, erasing, and reading of the non-volatile semiconductor memory cell M412 are exemplified. -230- 201010062 (Write of non-volatile semiconductor memory cell M4 1 2 First, control circuit 4363 inputs the table number from the outside. Row decoder, driver 43 54 and column decoder 1 to 4 365 - m input address from the outside Further, the control circuit 43 63 applies a voltage of 5 V in accordance with the input command input/output line Data 400, and outputs a control signal corresponding to the writing to the line 4354, the column decoder, and the driver 4365-1 to 4365. The detector 43 54 applies a voltage of 7 V according to the input address signal and the control signal line C402. Further, the column decoding ί -1 applies a voltage of 7 V to the SG 401 according to the input address signal and the control signal. The other columns 43 65 — 2~4365 — m set the respective connected white SG402~SG40m to the open state. Therefore, the data input and output line Data400 is connected to the non-volatile and 〇M412~M4m2 connected to the drain line D402 via the row. The 汲 terminal D400 is connected, and the D400 applies a voltage of 5 V. Also, since the voltage of the selection gate is 7 V, the selective transistor Tr4 31 of the non-volatile semiconductor memory cell becomes conductive. The semiconductor memory cell M4 12 memory devices have a voltage of 5 V applied to the drain, and a floating gate FG402 and FG403 are applied to the source to inject hot electrons into the write state. (The wiping operation of the nonvolatile semiconductor memory cell M412 The command letter written by the city, the driver 43 6 5 — signal, and the data: the decoder, the driver m and the source drive row decoder, the drive E, and the row selector, the driver 43 65 and the selection gate The line decoder, the driver spoon selects the gate line selection gate SW402, and the S conductor memory cell applies i M41 1 to Μ41ιι to each of the 汲 extreme pole lines SG401, the voltage of the non-volatile Tr432 and Tr433 pairs, and for each, And the charge is stored, except for the 4 _ 1 action) -231 - 201010062 First, the control circuit 4363 inputs a command signal indicating the erase 4-1 from the outside. The row decoder, the driver 4354 and the column decoder, and the driver 4365 are input to the address signal from the outside. Moreover, the control circuit 4363 applies a voltage of 8 V to the data input/output line Data 400 according to the input command signal, and outputs to the row decoder, the driver 4354, the column decoder, and the drivers 4365-1 to 4365-m corresponding to the erase 4 — 1 control signal. Further, the row decoder and driver 43 54 applies a voltage of 10 V to the row selection signal line C4 02 based on the input address signal and the control signal. Further, the column decoder and driver 43 65-1 applies a voltage of 10 V to the selection gate line SG401 based on the input address signal and the control signal. Further, the source driver 43 66 sets the source line to an open state in accordance with the input control signal. At this time, the other column decoders and drivers 43 65 - 2 to 4365 - m set the respective selected gate lines SG402 to SG40m to an open state. Therefore, the data input/output line Data400 is connected to the drain terminal D400 of the nonvolatile semiconductor memory cells M412 to M4m2 connected to the drain line D402 via the row selection gate SW402, and applies a voltage of 8 V to the respective gate terminal D400. . Further, since a voltage of 10 V is applied to the selection gate line SG401, the selection transistor Tr43 1 of the nonvolatile semiconductor memory cells M41 1 to M41I1 is turned on. As a result, the memory elements Tr432 and Tr4 3 3 of the non-volatile semiconductor memory cell M412 apply a voltage of 8 V to the drain, and the source becomes an open state, and the floating gates FG402 and FG403 are injected with hot electrons. And the charge is stored and becomes the erased state. (Abrasion 4-2 operation of non-volatile semiconductor memory cell M4 12) -232- 201010062 First, the control circuit 4363 inputs a command signal indicating the erasure of 4-2 from the outside. The row decoder, the driver 43 54 and the column decoder, and the drivers 4365 -1 to 4 365 —m input the address signals from the outside. Further, the control circuit 4363 sets the data output/output line Data400 to an open state based on the input command signal, and outputs the data to the row decoder, the driver 4354, the column decoder, the driver 4365-1 to 4365-m, and the source driver. To erase the 4- 2 control signal. Further, the row decoder and driver 43 54 applies a voltage of 0 V to the row selection signal line C402 based on the input address signal and the control signal. Further, the column decoder and driver 43 65-1 applies a voltage of 0 V to the selection gate line SG401 based on the input address signal and the control signal. Further, the source driver 4366 applies a voltage of 8 V to the source line in accordance with the input control signal. At this time, the other column decoders and drivers 4365-2 to 4365-m have the selected gate lines SG402 to SG40m and the source lines S402 to S40m connected to each other in an open state. Therefore, all of the drain lines D401 to D40n are in an open state. Further, since the voltage of 0 V is applied to the selection gate line SG401, the selection transistor TΓ43 1 of the nonvolatile 半导体 semiconductor memory cells M411 to M41l becomes a non-conduction state. As a result, the memory elements Tr432 and Tr433 of the nonvolatile semiconductor memory cell M411 to M41n are extremely open, and the source is applied with a voltage of 8V. As a result, the floating gates FG402 and FG4 0 of the non-volatile semiconductor memory cells M411 to M4mn are injected with hot electrons, and the charges are stored to be erased. That is, all of the nonvolatile semiconductor memory cells M411 to M4mn are erased together (the read operation of the nonvolatile semiconductor cell M4 12) -233 - 201010062 First, the control circuit 4363 inputs from the outside to indicate reading. The command signal. The row decoder, the driver 4354 and the column decoder, and the drivers 4365 -1 to 4 365 - m input the address signals from the outside. Moreover, the control circuit 4363 sets the data input/output line Data4 00 to an open state according to the input command signal, and supplies the line decoder, the driver 4354 and the column decoder, the driver 4365-1 to 4 365~m, and the source driver. The 4366 output corresponds to the read control signal. The row decoder and driver 4354 applies a voltage of 3 V to the row selection signal line C402 in accordance with the input address signal and control signal. Further, the column decoder and driver 4365-1 applies a voltage of 3 V to the selection gate line SG401 based on the input address signal and the control signal. Further, the source driver 4366 applies a voltage of 0 V to the source line S401 in accordance with the input control signal. At this time, the other column decoders and drivers 4365 - 2-4 365 - m set the respective selected gate lines SG402 to SG40m and the source lines S402 to S40m to an open state. Therefore, the data input/output line Data400 is connected to the drain line D402 via the row selection gate SW402. Further, the selection transistor Tr43 1 of the nonvolatile semiconductor memory cell M4 12 is turned on, and the drain of the memory elements Tr432 and Tr43 3 of the nonvolatile semiconductor memory cell 412 and the data input/output line Data400 are connected. The memory elements Tr432 and TM33 are in a write state, that is, when the memory elements Tr432 and Tr433 are in a non-conducting state due to charges stored in the respective floating gates, current does not flow. Further, the memory elements Tr432 and Tr4 33 are in a erased state, that is, when the elements Tr432 and Tr43 3 are in an on state due to the charge stored in the respective floating gates, a current flows. -234- 201010062 The sense amplifier circuit 43 52 amplifies and detects the current of the data input and output line Data400, and outputs the data to the external device. In this way, a plurality of non-volatile semiconductor memory cells M4 11 to M4mn are arranged, and by connecting the respective selection gate terminals SG400, the terminal terminal D400, and the source terminal S400 as described above, the multi-bits are memorized. A non-volatile semiconductor memory device 4360 that can be randomly stored. All of the non-volatile semiconductor memory cells M411 to M4mn can be erased by collectively connecting the source terminals of all the non-volatile semiconductor memory cells M4 1 1 to M4mn. Further, the sensing amplifying circuit 4352, the control circuit 4363, the row decoder, the driver 4354, and the column decoder and the drivers 4365-1 to 4365-m are designed in a standard CMOS process by the memory cells M411 to M4mn. It can reduce the number of processes and reduce manufacturing costs. Further, it is possible to constitute a highly reliable nonvolatile semiconductor memory device 4360 which uses a plurality of elements in each bit. Alternatively, the memory cell array may be divided into a plurality of blocks in units of columns, and each of the blocks may be provided with a source driver 4366. In this case, the separated squares can be erased. [40th embodiment] Figs. 75A to 75C are views showing the configuration of the nonvolatile semiconductor memory cell 4004 of the 40th embodiment. Figure 75A is a plan view of a non-volatile semiconductor memory cell 4004, and Figure 75B is a cross-sectional view of the non-volatile semiconductor memory cell 4004 along C40-C40' of Figure 75A, and Figure 75C shows the An equivalent circuit diagram of the non-volatile semiconductor memory cell 4004 formed by the 75A and 75B. First, as shown in Fig. 75C, the non-volatile semiconductor memory cell 4004 - 235 - 201010062 has a 汲 terminal D400, a source terminal S400, a selection gate terminal SG400, a selection transistor Tr441 which is a MOS transistor, and is floating. A non-volatile semiconductor memory element Tr442, Tr443, Tr444 of a gate type one-layer polycrystalline germanium transistor. Further, the memory elements Tr442, Tr443, and Tr444 have the same characteristics as those of the memory element 4001 shown in Figs. 63A to 63C, and operate. The drain of the transistor Tr4 41 is selected to be connected to the drain terminal D400, and the source is connected to the drain of the memory elements Tr442, Tr443, Tr444. The sources of the memory elements Tr442, Tr443, Tr444 are connected to the source terminal S400. That is, the memory elements Tr442, Tr443, and Tr444 are connected to each other in parallel. Further, the nonvolatile semiconductor memory elements Tr442, Tr443, Tr444 and the selective transistor Tr441 are connected in series. Next, the construction of the non-volatile semiconductor memory cell 4004 will be described using the 75th and 75th views. The transistor forming portion 4040 on the surface of the p-type semiconductor substrate 44 00 is an n-type diffusion layer 440 1 (in-type diffusion layer), a gate region portion 4406, and an n-type diffusion layer 44 02 (second η-type diffusion layer) a gate region 4407, an n-type diffusion layer 4403 (third n-type diffusion layer), a gate region portion 44 08, an n-type diffusion layer 44 04 (fourth n-type diffusion layer), a gate region portion 44 09, and The n-type diffusion layer 4405 (the fifth n-type diffusion layer) forms a region sequentially. In the non-volatile semiconductor memory cell 4004, the n-type diffusion layer 440 1 forms the drain of the selection transistor Tr 441. The n-type diffusion layer 4402 forms the source of the selection transistor Tr441 and the drain of the memory element Tr442. The n-type diffusion layer 4403 forms the sources of the memory elements ΤΜ42 and Tr443. The n-type diffusion layer 4404 forms the drain of the memory elements Tr442 and Tr443. The n-type diffusion layer 4405 is shaped as -236 - 201010062 into the source of the memory element Tr443. The gate region portion 4406 is a region between the n-type diffusion layers 4401 and 4402, and is a region in which a channel for selecting the transistor Tr44 1 is formed. The gate region portion 4407 is a region between the n-type diffusion layers 4402 and 4403, and is a region in which the channel of the cell Tr 4 42 is formed. The gate region portion 44 08 is a region between the n-type diffusion layers 4403 and 4404 and is a region where the channel of the memory element Tr443 is formed. The gate region portion 4409 is a region between the n-type diffusion layers 4404 and 4405, and is a region where the channel of the memory element ΤΜ 44 is formed.
多晶矽4410(第1多晶矽）形成選擇電晶體Tr441的閘 極。多晶矽441 1(第2多晶矽）形成記憶元件Tr442之浮動 閘極的電極。多晶矽4412(第3多晶矽）形成記憶元件Tr443 之浮動閘極的電極。多晶矽44 13(第4多晶矽）形成記憶元 件Tr444之浮動閘極的電極。 金屬配線4414(第1金屬配線）是經由接點4418而和是 選擇電晶體Tr441之汲極的η型擴散層4401連接的汲極端 子D400。金屬配線4415(第2金屬配線）經由接點4419、 4421而連接η型擴散層4402和η型擴散層4404。金屬配 線4416(第3金屬配線）是經由接點444 20而和η型擴散層 4403連接的源極端子S400 a。金屬配線4417(第4金屬配線） 是經由接點44422而和η型擴散層4405連接的源極端子 S400b » 此外，金屬配線4416、4417配置成與p型半導體基板 44 00的表面保持固定之距離。金屬配線4414、4415配置 成保持比金屬配線4416、4417更遠離p型半導體基板4400 之表面的距離。 -237 - 201010062 又，源極端子S400由是源極端子S400a的金屬配線 4416及是源極端子S400b的金屬配線4417所構成，在使 用非揮發性半導體記憶胞元4004時，在電晶體形成部4040 的外部將金屬配線44 16、4417互相連接，而構成源極端子 S400 〇 每一位元使用3個記憶元件Tr442、Tr443、Tr444來 構成如上述所構成之非揮發性半導體記憶胞元4004。因 而，和第38實施形態之第70A圖〜第70C圖所示的非揮發 性半導體記憶胞元4003相比，藉由增加記憶元件的個數， 而可對製造不良、老化以及因使用之劣化所引起的故障得 到高可靠性。 (非揮發性半導體記憶裝置4004之布置） 其次，第76圖係表示使用非揮發性半導體記憶胞元 40 04之記憶胞元陣列之配置的示意圖。在記憶胞元陣列， 將複數個第75A圖所示的非揮發性半導體記憶胞元4004 平行地配置成陣列狀。 在非揮發性半導體記憶胞元4004a，在電晶體形成部 4040a，雖未圖示，如第75B圖所示，將η型擴散層和閘極 區域部交互串列地配置於Ρ型半導體基板上，並在串列方 向形成長條形的區域。 多晶矽4410a是選擇閘極線SG400al，並是選擇電晶 體Tr441的閘極。多晶矽4411a是記憶元件Tr442的浮動 閘極。多晶矽4412a是記憶元件Tr443的浮動閘極。多晶 矽4413a是記憶元件Tr444的浮動閘極。 金屬配線4414a是經由選擇電晶體Tr441的汲極及接 -238- 201010062 點4418a而和汲極端子D400連接，並和串列方向垂直地配 置。金屬配線4415a經由接點4419a、4421a而連接η型擴 散層4402(第75Β圖）和η型擴散層4404(第75Β圖），並在 串列方向配置。金屬配線4416a經由接點4420a而連接η 型擴散層4403(第75Β圖）和源極線S400al，並在和串列方 向垂直的方向配置。金屬配線4417a經由接點4422a而連 接η型擴散層4405(第75B圖）和源極線S400bl，並在和串 列方向垂直的方向配置。The polysilicon 4410 (first polysilicon) forms the gate of the selection transistor Tr441. The polysilicon 441 1 (the second polysilicon) forms the electrode of the floating gate of the memory element Tr442. The polysilicon 4412 (third polysilicon) forms the electrode of the floating gate of the memory element Tr443. The polysilicon 44 13 (the fourth polysilicon) forms the electrode of the floating gate of the memory element Tr444. The metal wiring 4414 (first metal wiring) is a gate terminal D400 that is connected to the n-type diffusion layer 4401 which is the drain of the transistor Tr441 via the contact 4418. The metal wiring 4415 (second metal wiring) connects the n-type diffusion layer 4402 and the n-type diffusion layer 4404 via the contacts 4419 and 4421. The metal wiring 4416 (third metal wiring) is a source terminal S400 a connected to the n-type diffusion layer 4403 via the contact 444 20 . The metal wiring 4417 (fourth metal wiring) is a source terminal S400b that is connected to the n-type diffusion layer 4405 via the contact 44242. Further, the metal wirings 4416 and 4417 are disposed to be fixed to the surface of the p-type semiconductor substrate 44 00. . The metal wirings 4414, 4415 are arranged to maintain a distance further from the surface of the p-type semiconductor substrate 4400 than the metal wirings 4416, 4417. -237 - 201010062 Further, the source terminal S400 is composed of a metal wiring 4416 which is the source terminal S400a and a metal wiring 4417 which is the source terminal S400b. When the nonvolatile semiconductor memory cell 4004 is used, the transistor is formed in the transistor forming portion. The metal wirings 44 16 and 4417 are connected to each other outside the 4040, and the source terminal S400 is formed. Each of the three elements Tr442, Tr443, and Tr444 is used to form the nonvolatile semiconductor memory cell 4004 constructed as described above. Therefore, compared with the nonvolatile semiconductor memory cell 4003 shown in Figs. 70A to 70C of the 38th embodiment, the number of memory elements can be increased, resulting in poor manufacturing, aging, and deterioration due to use. The resulting fault is highly reliable. (Arrangement of Nonvolatile Semiconductor Memory Device 4004) Next, Fig. 76 is a view showing the configuration of a memory cell array using a nonvolatile semiconductor memory cell 40 04. In the memory cell array, a plurality of non-volatile semiconductor memory cells 4004 shown in Fig. 75A are arranged in parallel in an array. In the non-volatile semiconductor memory cell 4004a, the transistor forming portion 4040a is not shown, as shown in FIG. 75B, the n-type diffusion layer and the gate region portion are alternately arranged in series on the germanium-type semiconductor substrate. And form an elongated strip in the direction of the string. The polysilicon 4410a is a gate line SG400al selected and is a gate for selecting the transistor Tr441. The polysilicon 4411a is a floating gate of the memory element Tr442. The polysilicon 4412a is a floating gate of the memory element Tr443. Polycrystalline germanium 4413a is the floating gate of memory element Tr444. The metal wiring 4414a is connected to the 汲 terminal D400 via the drain of the selection transistor Tr441 and the -238-201010062 point 4418a, and is arranged perpendicularly to the serial direction. The metal wiring 4415a is connected to the n-type diffusion layer 4402 (Fig. 75) and the n-type diffusion layer 4404 (Fig. 75) via the contacts 4419a and 4421a, and is arranged in the serial direction. The metal wiring 4416a is connected to the n-type diffusion layer 4403 (Fig. 75) and the source line S400al via the contact 4420a, and is disposed in a direction perpendicular to the tandem direction. The metal wiring 4417a is connected to the n-type diffusion layer 4405 (Fig. 75B) and the source line S400b1 via the contact 4422a, and is disposed in a direction perpendicular to the serial direction.
其次，在非揮發性半導體記憶胞元4004b，在電晶體 形成部4040b，雖未圖示，如第75B圖所示，在半導體基 板上形成交互串列地配置η型擴散層和閘極區域部之方形 的區域。 多晶矽4410b是選擇電晶體Tr441的閘極，並是選擇 閘極線SG400a2。多晶矽4411b是記憶元件Tr4 42的浮動 閘極。多晶矽4412b是記憶元件Tr443的浮動閘極。多晶 矽4413b是記憶元件TM44的浮動閘極。 Ο 金屬配線4414b是經由接點4418b而和選擇電晶體Next, in the non-volatile semiconductor memory cell 4004b, the transistor forming portion 4040b is not shown, as shown in FIG. 75B, and the n-type diffusion layer and the gate region portion are alternately arranged on the semiconductor substrate. Square area. The polysilicon 4410b is a gate for selecting the transistor Tr441, and is a gate line SG400a2. The polysilicon 4411b is a floating gate of the memory element Tr4 42. The polysilicon 4412b is a floating gate of the memory element Tr443. Polysilicon 4413b is the floating gate of memory element TM44. Ο metal wiring 4414b is via contact 4418b and selects the transistor
Tr 4 41的汲極連接的汲極端子D400。金屬配線4415b經由 接點4419b、4421a而連接η型擴散層4402(第75B圖）和η 型擴散層4404(第75Β圖）。金屬配線4416b經由接點4420b 而和是記憶元件Tr442、Tr443之源極的η型擴散層連接的 源極線S400a2。金屬配線4417b是經由接點4422b而和是 記憶元件Tr444之源極的η型擴散層連接的源極線S400b2。 其次，在非揮發性半導體記憶胞元40 04c，在電晶體 形成部4040c，雖未圖示，如第75B圖所示，在半導體基 -239 - 201010062 板上形成交互串列地配置η型擴散層和閘極區域部之方形 的區域。 多晶矽4410c是選擇閘極線SG400a3，並是選擇電晶 體Tr 441的閘極。多晶矽4411c是記憶元件Tr442的浮動 閘極。多晶矽4412c是記憶元件Tr443的浮動閘極。多晶 矽44 13c是記憶元件Tr444的浮動閘極。 金屬配線4414c是經由接點4418c而和選擇電晶體 Tr441的汲極連接的汲極端子D400。金屬配線4415c經由 接點4419c、4421c而連接η型擴散層4402(第75B圖）和η © 型擴散層4404(第75Β圖）。金屬配線4416c經由接點4420c 而和是記憶元件Tr442、Tr443之源極的η型擴散層連接的 源極線S400a3。金屬配線4417c是經由接點4422c而和是 記憶元件Tr4 44之源極的η型擴散層連接的源極線S400b3。 在所圖示的配置，共用非揮發性半導體記憶胞元4004a 之是汲極端子D400的金屬配線4414a和非揮發性半導體記 憶胞元40 04b之是汲極端子的金靥配線4414b。又，共用 接點44 18a、4418b，此外，非揮發性半導體記憶胞元 ❹ 4004a、40 04 b各自之形成選擇電晶體Tr 4 44之源極的η型 擴散層亦共用。 又，共用非揮發性半導體記憶胞元4004b、4004各自 之成爲源極端子S400b的金靥配線4417b、4417c，亦共用 接點 4422b、4422c。此外，非揮發性半導體記憶胞元 400 4b、4004c各自之是選擇電晶體Tr4 41之汲極的η型擴 散層亦共用。 在上下方向相鄰地配置之非揮發性半導體記憶胞元 -240- 201010062 4004共用成爲選擇電晶體Tr431之汲極的η型擴散層 4401、成爲汲極端子D400的金屬配線4414以及接點 4418，並對金屬配線4414上下對稱地配置。 此外’在上下方向相鄰地配置之非揮發性半導體記憶 胞元4004共用成爲記憶元件Tr444之源極的η型擴散層 4405、成爲源極端子S400b的金屬配線4417以及接點 4422’並對金屬配線4417上下對稱地配置。 如此，將複數個非揮發性半導體記憶胞元4004配置成 ® 陣列狀的記憶胞元陣列，彼此共用第75A圖及第75B圖所 示之非揮發性半導體記憶胞元4004之布置的η型擴散層 4401，又彼此共用η型擴散層4405，藉此，在上下方向對 稱地配置在上下方向相鄰之各個非揮發性半導體記憶胞元 4004而構成。 又，在上下方向所配置之各個非揮發性半導體記憶胞 元4004之作爲汲極端子D400的金屬配線4414a、4414b、 44 14c和在非揮發性半導體記憶胞元4004沿著上下方向所 Ο 配置之共用的汲極線D400al連接。一樣地，在其他的行， 亦設置汲極線D400a2、汲極線D400a3、汲極線D400a4, 並連接作爲汲極端子D400的金屬配線4414。 此外，和左右方向平行地排列配置如上述所示在上下 方向所配置之非揮發性半導體記憶胞元4004的行，各自的 源極線 S400al、S400b 1、S400a2、S400b2、S400a3、S400b3 在左右方向直線狀地連接。一樣地’選擇閛極配線 SG400al ' SG400a2 > SG4 00a3在左右方向直線狀地連接。 如此，藉由在上下方向相鄰之各個非揮發性半導體記 -241 - 201010062 憶胞元4004之間設置共用部分，不必設置用以隔開各個的 區域，就可構成記憶胞元陣列。因而，可減少配置非揮發 性半導體記憶胞元40 04時之上下方向的區域。又，在第 73圖所示之第38實施形態的配置，在第2列的配置和第3 列的配置之間設置用以隔開各自之η型擴散層的空間。另 一方面，本實施形態的配置，可不必配置那種空間，而可 更減少配置面積。 此外，亦可將第40實施形態所示之記憶胞元陣列用作 第3 8實施形態及第3 9實施形態所示之非揮發性半導體記 憶裝置的記憶胞元陣列。在此情況，共同連接源極端子 S400a、S400b，並和列驅動器或源極驅動器連接。 因而，可構成可靠性比第38實施形態及第39實施形 態之非揮發性半導體記憶裝置高的非揮發性半導體記憶裝 置。 雖然以上說明了本發明之實施形態，但是本發明之非 揮發性半導體記憶元件、非揮發性半導體記憶胞元以及非 揮發性半導體記憶裝置未僅限定爲上述的圖示例，當然在 不超出本發明之主旨的範圍內可施加各種變更。 (工業上之可應用性） 本發明可應用於以標準邏輯元件的CMOS製程實現非 揮發性記憶體，可緊密地配置電容器，並使面積變成最小 限度之非揮發性半導體記憶元件等。 【圖式簡單說明】 第1A圖係本發明之第1實施形態之非揮發性半導體 記憶元件的平面圖。 -242- 201010062 第1B圖係本發明之第1實施形態之非揮發性半導體記 憶元件的等價電路圖。 第1C圖係本發明之第1實施形態之非揮發性半導體記 憶元件的A10— A10’剖面圖。 第1D圖係本發明之第1實施形態之非揮發性半導體 記憶元件的BIO— B10’剖面圖。 第1 E圖係本發明之第1實施形態之非揮發性半導體記 憶元件的C10-C10’剖面圖。 Ο 第2A圖係第1A圖所示之記憶胞元的等價電路圖。 第2B圖係說明第1A圖所示之記億胞元的動作的表。 第3A圖係表示第1A圖所示之記憶胞元之電晶體T1 02 的特性圖。 第3B圖係表示第1A圖所示之記憶胞元之電晶體T1 02 的構成圖。 第4A圖係表示第1A圖所示之記憶胞元之電晶體T101 及T102的特性圖。 Ο 第4B圖係表示第1A圖所示之記憶胞元之電晶體T101 及T102的構成圖。 第5A圖係表示記憶胞元之耦合系統的等價電路圖。 第5B圖係表示第5A圖之記憶胞元的構成圖。 第6圖係表示本發明之第2實施形態的非揮發性半導 體記憶裝置的構成圖。 第7圖係表示電源電壓控制電路之構成圖。 第8A圖係表示寫入時之VP 102的電壓的波形圖。 第8B圖係表示寫入信號Write的波形圖。 -243 - 201010062 第8C圖係表示控制閘極CG100之信號波形圖。 第9圖係表示本發明之第3實施形態的非揮發性半導 體記憶裝置的構成圖。 第10圖係表示本發明之第4實施形態的非揮發性半導 體記憶裝置的構成圖。 第11圖係表示本發明之第5實施形態的非揮發性半導 體記憶裝置的構成圖。 第12圖係表示本發明之第6實施形態的非揮發性半導 體記憶裝置的構成圖。 Θ 第1 3 A圖係表示本發明之第7實施形態的非揮發性半 導體記憶元件之構成的平面圖。 第13B圖係表示本發明之第7實施形態的非揮發性半 導體記憶元件之構成的BIO-B10’剖面圖。 第14圖係表示本發明之第8實施形態的非揮發性半導 體記憶裝置的構成圖。 第15圖係表示本發明之第9實施形態的非揮發性半導 體記憶裝置的構成圖。 ϋ 第16圖係表示本發明之第10實施形態的非揮發性半 導體記憶裝置的構成圖。 第17圖係表示本發明之第11實施形態的非揮發性半 導體記憶裝置的構成圖。 第18圖係表示本發明之第12實施形態的非揮發性半 導體記憶裝置的構成圖。 第19圖係表示本發明之第13實施形態的非揮發性半 導體記憶裝置的構成圖。 -244- 201010062 第20 A圖係表示本發明之第14實施形態的非揮發性 半導體記憶元件之構成的平面圖。 第20B圖係表示本發明之第14實施形態的非揮發性半 導體記憶元件之構成的等價電路圖。 第20C圖係表示本發明之第14實施形態的非揮發性半 導體記憶元件之構成的A10— A10’剖面圖。 第20D圖係表示本發明之第1 4實施形態的非揮發性 半導體記憶元件之構成的B10—B10’剖面圖。 Ο 第20E圖係表示本發明之第14實施形態的非揮發性半 導體記憶元件之構成的CIO— C10’剖面圖。 第20F圖係表示本發明之第14實施形態的非揮發性半 導體記憶元件之構成的E10— E 10’剖面圖。 第21圖係用以說明第20A圖〜第20F圖所示之記憶胞 元的動作圖。 第22圖係表示本發明之第15實施形態的非揮發性半 導體記憶裝置的構成圖。 Ο 第23圖係表示本發明之第1 6實施形態的非揮發性半 導體記憶裝置的構成圖。 第24圖係表示第23圖所示之記憶胞元陣列之動作表 的圖。 第25A圖係表示本發明之第17實施形態的非揮發性 半導體記憶元件的平面圖。 第25B圖係表示本發明之第17實施形態的非揮發性半 導體記憶元件的等價電路圖》 第25 C圖係表示本發明之第17實施形態的非揮發性半 -245- 201010062 導體記憶元件的A20— A20’剖面圖。 第25D圖係表示本發明之第1 7實施形態的非揮發性 半導體記憶元件的B20-B20’剖面圖。 第26A圖係用以說明第25A圖〜第25D圖所示之記憶 胞元之OTP的情況的動作圖。 第26B圖係用以說明第25 A圖〜第2 5D圖所示之記憶 胞元之MTP的情況的動作圖。 第26C圖係用以說明第25A圖~第25D圖所示之記憶 胞元的等價電路圖。 © 第27A圖係用以說明第25A圖~第25D圖所示之記憶 胞元之電晶體T201的特性圖。 第27B圖係用以說明第25 A圖〜第25D圖所示之記憶 胞元之電晶體T201的構成圖。 第28A圖係表示根據弱寫入（drain stress)之臨限値的 自收歛特性的圖。 第28B圖係表示第28 A圖之特性的電路構成圖。The drain terminal D400 of the Tr 4 41 is connected to the drain. The metal wiring 4415b is connected to the n-type diffusion layer 4402 (Fig. 75B) and the n-type diffusion layer 4404 (Fig. 75) via the contacts 4419b and 4421a. The metal wiring 4416b is connected to the source line S400a2 which is the n-type diffusion layer of the source of the memory elements Tr442 and Tr443 via the contact 4420b. The metal wiring 4417b is a source line S400b2 connected to the n-type diffusion layer which is the source of the memory element Tr444 via the contact 4422b. Next, in the non-volatile semiconductor memory cell 40 04c, although not shown, as shown in FIG. 75B, the n-type diffusion is alternately arranged on the semiconductor substrate -239 - 201010062. The square area of the layer and gate region. The polysilicon 4410c is a gate electrode SG400a3 selected and is a gate for selecting the transistor Tr 441. The polysilicon 4411c is a floating gate of the memory element Tr442. The polysilicon 4412c is a floating gate of the memory element Tr443. The polysilicon 矽 44 13c is the floating gate of the memory element Tr444. The metal wiring 4414c is a gate terminal D400 connected to the drain of the selection transistor Tr441 via the contact 4418c. The metal wiring 4415c is connected to the n-type diffusion layer 4402 (Fig. 75B) and the n-type diffusion layer 4404 (Fig. 75) via the contacts 4419c and 4421c. The metal wiring 4416c is connected to the source line S400a3 which is the n-type diffusion layer of the source of the memory elements Tr442 and Tr443 via the contact 4420c. The metal wiring 4417c is a source line S400b3 connected to the n-type diffusion layer which is the source of the memory element Tr4 44 via the contact 4422c. In the illustrated configuration, the shared non-volatile semiconductor memory cell 4004a is the metal wiring 4414a of the drain terminal D400 and the metal wiring 4414b of the non-volatile semiconductor memory cell 40 04b which is the drain terminal. Further, the contacts 44 18a and 4418b are shared, and the n-type diffusion layers of the non-volatile semiconductor memory cells ❹ 4004a and 40 04 b which form the source of the selection transistor Tr 4 44 are also shared. Further, the shared nonvolatile semiconductor memory cells 4004b and 4004 are the metal ridge wires 4417b and 4417c of the source terminal S400b, and the contacts 4422b and 4422c are also shared. Further, the non-volatile semiconductor memory cells 400 4b, 4004c are each an n-type diffusion layer which selectively selects the drain of the transistor Tr4 41. The non-volatile semiconductor memory cell-240-201010062 4004 disposed adjacent to each other in the vertical direction shares the n-type diffusion layer 4401 which is the drain of the selection transistor Tr431, and the metal wiring 4414 which becomes the gate terminal D400 and the contact 4418. The metal wiring 4414 is arranged vertically symmetrically. Further, the non-volatile semiconductor memory cell 4004 disposed adjacent to each other in the vertical direction shares the n-type diffusion layer 4405 serving as the source of the memory element Tr444, the metal wiring 4417 serving as the source terminal S400b, and the contact 4422' and the metal. The wiring 4417 is arranged vertically symmetrically. Thus, a plurality of non-volatile semiconductor memory cells 4004 are arranged in an array-like memory cell array, and the n-type diffusion of the arrangement of the non-volatile semiconductor memory cells 4004 shown in FIGS. 75A and 75B is shared with each other. The layer 4401 further shares the n-type diffusion layer 4405, and is configured by arranging each of the non-volatile semiconductor memory cells 4004 adjacent in the vertical direction symmetrically in the vertical direction. Further, the metal wirings 4414a, 4414b, and 4414c of the nonvolatile semiconductor memory cells 4004 disposed in the vertical direction are disposed in the vertical direction of the nonvolatile semiconductor memory cells 4004. The shared bungee line D400al is connected. Similarly, in other rows, the drain line D400a2, the drain line D400a3, and the drain line D400a4 are also provided, and the metal wiring 4414 as the drain terminal D400 is connected. Further, rows of the non-volatile semiconductor memory cells 4004 arranged in the vertical direction as described above are arranged in parallel with the left-right direction, and the respective source lines S400al, S400b1, S400a2, S400b2, S400a3, and S400b3 are in the left-right direction. Connected in a straight line. Similarly, 'selecting the drain wiring SG400al' SG400a2 > SG4 00a3 is connected linearly in the left-right direction. Thus, by providing a common portion between the respective non-volatile semiconductor cells adjacent to each other in the up-and-down direction, it is not necessary to provide a region for separating the cells, thereby forming a memory cell array. Therefore, the area in the upper and lower directions when the nonvolatile semiconductor memory cell 40 04 is disposed can be reduced. Further, in the arrangement of the 38th embodiment shown in Fig. 73, a space for partitioning the respective n-type diffusion layers is provided between the arrangement of the second column and the arrangement of the third column. On the other hand, in the configuration of this embodiment, it is not necessary to configure such a space, and the arrangement area can be further reduced. Further, the memory cell array shown in the 40th embodiment can be used as the memory cell array of the nonvolatile semiconductor memory device shown in the 38th embodiment and the ninth embodiment. In this case, the source terminals S400a, S400b are commonly connected and connected to the column driver or the source driver. Therefore, it is possible to constitute a nonvolatile semiconductor memory device having higher reliability than the nonvolatile semiconductor memory devices of the 38th and 39th embodiments. Although the embodiments of the present invention have been described above, the nonvolatile semiconductor memory device, the nonvolatile semiconductor memory cell, and the nonvolatile semiconductor memory device of the present invention are not limited to the above-described example of the drawings, and of course, Various changes can be made within the scope of the gist of the invention. (Industrial Applicability) The present invention can be applied to a non-volatile memory in which a standard logic element is implemented in a CMOS process, a capacitor can be closely arranged, and a non-volatile semiconductor memory element in which an area is minimized. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a plan view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. -242- 201010062 Fig. 1B is an equivalent circuit diagram of the nonvolatile semiconductor memory device of the first embodiment of the present invention. Fig. 1C is a cross-sectional view taken along line A10 - A10' of the nonvolatile semiconductor memory device of the first embodiment of the present invention. Fig. 1D is a cross-sectional view taken along line BIO-B10' of the nonvolatile semiconductor memory device of the first embodiment of the present invention. Fig. 1E is a cross-sectional view taken along line C10-C10' of the nonvolatile semiconductor memory device of the first embodiment of the present invention. Ο Figure 2A is an equivalent circuit diagram of the memory cell shown in Figure 1A. Fig. 2B is a table showing the operation of the billion cell shown in Fig. 1A. Fig. 3A is a characteristic diagram showing the transistor T1 02 of the memory cell shown in Fig. 1A. Fig. 3B is a view showing the configuration of the transistor T1 02 of the memory cell shown in Fig. 1A. Fig. 4A is a characteristic diagram showing the transistors T101 and T102 of the memory cell shown in Fig. 1A. Ο Fig. 4B is a view showing the configuration of the transistors T101 and T102 of the memory cells shown in Fig. 1A. Fig. 5A is an equivalent circuit diagram showing a coupling system of memory cells. Fig. 5B is a view showing the configuration of the memory cell of Fig. 5A. Fig. 6 is a view showing the configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Fig. 7 is a view showing the configuration of a power supply voltage control circuit. Fig. 8A is a waveform diagram showing the voltage of the VP 102 at the time of writing. Fig. 8B is a waveform diagram showing the write signal Write. -243 - 201010062 Figure 8C shows the signal waveform of the control gate CG100. Fig. 9 is a view showing the configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention. Fig. 10 is a view showing the configuration of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. Figure 11 is a view showing the configuration of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. Fig. 12 is a view showing the configuration of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention. Fig. 13A is a plan view showing the configuration of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention. Fig. 13B is a cross-sectional view showing the configuration of BIO-B10' of the nonvolatile semiconductor memory device according to the seventh embodiment of the present invention. Fig. 14 is a view showing the configuration of a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention. Fig. 15 is a view showing the configuration of a nonvolatile semiconductor memory device according to a ninth embodiment of the present invention. Fig. 16 is a view showing the configuration of a nonvolatile semiconductor memory device according to a tenth embodiment of the present invention. Figure 17 is a view showing the configuration of a nonvolatile semiconductor memory device according to an eleventh embodiment of the present invention. Figure 18 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twelfth embodiment of the present invention. Figure 19 is a view showing the configuration of a nonvolatile semiconductor memory device according to a thirteenth embodiment of the present invention. -244- 201010062 Fig. 20A is a plan view showing the configuration of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention. Fig. 20B is an equivalent circuit diagram showing the configuration of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention. Fig. 20C is a cross-sectional view showing the structure of the non-volatile semiconductor memory device according to the fourteenth embodiment of the present invention, taken along line A10-A10'. Fig. 20D is a cross-sectional view showing the configuration of B10-B10' of the nonvolatile semiconductor memory device according to the fourteenth embodiment of the present invention. Fig. 20E is a cross-sectional view showing the configuration of a non-volatile semiconductor memory device according to a fourteenth embodiment of the present invention, taken along the line CIO-C10'. Fig. 20F is a cross-sectional view showing the structure of the nonvolatile semiconductor memory device according to the fourteenth embodiment of the present invention, taken along the line E10 - E 10'. Fig. 21 is a view for explaining the operation of the memory cell shown in Figs. 20A to 20F. Fig. 22 is a view showing the configuration of a nonvolatile semiconductor memory device according to a fifteenth embodiment of the present invention. Fig. 23 is a view showing the configuration of a nonvolatile semiconductor memory device according to a sixteenth embodiment of the present invention. Fig. 24 is a view showing an action table of the memory cell array shown in Fig. 23. Fig. 25A is a plan view showing a nonvolatile semiconductor memory device according to a seventeenth embodiment of the present invention. Fig. 25B is an equivalent circuit diagram showing a nonvolatile semiconductor memory device according to a seventeenth embodiment of the present invention. Fig. 25C is a view showing a nonvolatile half-245-201010062 conductor memory element according to a seventeenth embodiment of the present invention. A20-A20' section view. Fig. 25D is a cross-sectional view showing the B20-B20' of the nonvolatile semiconductor memory device of the seventeenth embodiment of the present invention. Fig. 26A is an operation diagram for explaining the case of the OTP of the memory cell shown in Figs. 25A to 25D. Fig. 26B is an operation diagram for explaining the case of the MTP of the memory cell shown in Figs. 25A to 2BD. Fig. 26C is an equivalent circuit diagram for explaining the memory cells shown in Figs. 25A to 25D. © Fig. 27A is a characteristic diagram for explaining the transistor T201 of the memory cell shown in Figs. 25A to 25D. Fig. 27B is a view showing the configuration of the transistor T201 for the memory cell shown in Figs. 25A to 25D. Fig. 28A is a diagram showing the self-convergence characteristic according to the threshold of the drain stress. Fig. 28B is a circuit configuration diagram showing the characteristics of Fig. 28A.
第29A圖係表示記憶胞元之耦合系統的等價電路圖。 Q 第29B圖係表示第29A圖的電路構成圖。 第30圖係表示本發明之第18實施形態的非揮發性半 導體記憶裝置的構成圖。 第31圖係表示本發明之第19實施形態的非揮發性半 導體記憶裝置的構成圖。 第32A圖係表示第31圖所示之列解碼器的構成圖。 第3 2B圖係用以說明第3 1圖所示之列解碼器的圖。 第33圖係表示第32A圖所示之列解碼器的動作表。 -246- 201010062 第34圖係表示本發明之第20實施形態的非揮發性半 導體記憶裝置的構成圖。 第3 5圖係表示本發明之第2 1實施形態的非揮發性半 導體記憶裝置的構成圖。 第36圖係表示第35圖所示之列解碼器的構成圖。 第37圖係表示第36圖所示之列解碼器的動作表。 第3 8圖係表示本發明之第22實施形態的非揮發性半 導體記憶裝置的構成圖。 ^ 第39A圖係表示本發明之第23實施形態的非揮發性 半導體記憶元件之構成的平面圖。 第39B圖係表示本發明之第23實施形態的非揮發性半 導體記憶元件之構成的B20— B20’剖面圖。 第40圖係表示本發明之第24實施形態的非揮發性半 導體記憶裝置的構成圖。 第4 1圖係表示本發明之第2 5實施形態的非揮發性半 導體記憶裝置的構成圖。 Ο 第42圖係表示本發明之第26實施形態的非揮發性半 導體記憶裝置的構成圖。 第43圖係表示本發明之第27實施形態的非揮發性半 導體記億裝置的構成圖。 第44圖係表示本發明之第28實施形態的非揮發性半 導體記憶裝置的構成圖。 第45A圖係表示本發明之第29實施形態的非揮發性 半導體記憶元件之構成的平面圖。 第45B圖係表示本發明之第29實施形態的非揮發性半 -247- 201010062 導體記憶元件之構成的等價電路圖。 第45C圖係表示本發明之第29實施形態的非揮發性半 導體記憶元件之構成的A20— A20’剖面圖。 第45D圖係表示本發明之第29實施形態的非揮發性 半導體記憶元件之構成的B20— B20’剖面圖。 第45E圖係表示本發明之第29實施形態的非揮發性半 導體記憶元件之構成的E20— E20’剖面圖。 第46A圖係用以說明第45A圖~第45E圖所示之記憶 胞元之OTP的情況的動作圖。 第46B圖係用以說明第45 A圖〜第45E圖所示之記憶 胞元之MTP的情況的動作圖。 第47圖係表示本發明之第30實施形態的非揮發性半 導體記憶裝置的構成圖。 第48圖係表示本發明之第31實施形態的非揮發性半 導體記憶裝置的構成圖。 第49A圖係用以說明第47圖所示之記憶胞元陣列之 OTP的情況的動作圖。 第49B圖係用以說明第47圖所示之記憶胞元陣列之 MTP的情況的動作圖。 第50A圖係表示在本發明之第32〜第36實施形態所使 用之非揮發性半導體記憶胞元的平面圖。 第5 0B圖係表示在本發明之第32~第36實施形態所使 用之非揮發性半導體記憶胞元的等價電路圖。 第50C圖係表示本發明之第32~第36實施形態的非揮 發性半導體記憶胞元之構成的A30— A30’剖面圖。 -248- 201010062 第50D圖係表示本發明之第32~第36實施形態的非揮 發性半導體記憶胞元之構成的B30-B30’剖面圖。 第5 0E圖係表示本發明之第32~第36實施形態的非揮 發性半導體記億胞元之構成的C30— C30’剖面圖。 第51圖係以一覽表示第50A圖〜第50E圖所示之基本 之構成之非揮發性半導體記憶胞元的動作狀態圖。 第52A圖係用以說明第50A圖〜第50E圖所示之基本 之構成之非揮發性半導體記憶胞元的特性圖。 Ο 第52B圖係用以說明第50A圖〜第50E圖所示之基本 之構成之非揮發性半導體記憶胞元的電路圖。 第53A圖係用以說明第50 A圖〜第50E圖所示之基本 之構成之非揮發性半導體記憶胞元之其他的特性圖。 第53B圖係用以說明第50A圖〜第50E圖所示之基本 之構成之非揮發性半導體記憶胞元的電路圖。 第54A圖係用以說明第50A圖〜第50E圖所示之基本 之構成之非揮發性半導體記憶胞元之耦合系統的等價電路 Ο圖。 第5 4B圖係表示第50A圖~第50E圖所示之基本之構 成之非揮發性半導體記憶胞元的電路圖。 第55圖係表示第50八圖~第50E圖所示之基本之構成 之非揮發性半導體記憶胞元之耦合的計算式的圖。 第56A圖係表示本發明之第32實施形態之非揮發性 半導體記憶胞元的平面示意構造圖。 第56B圖係表示本發明之第32實施形態之非揮發性半 導體記憶胞元的等價電路圖。 -249- 201010062 第56C圖係表示本發明之第32實施形態之非揮發性半 導體記憶胞元的剖面構造圖。 第57A圖係表示第56A圖〜第56C圖所示之非揮發性 半導體記憶胞元的B30— B30’剖面圖。 第57B圖係表示第56A圖〜第56C圖所示之非揮發性 半導體記憶胞元的C30— C30’剖面圖。 第57C圖係表示第56A圖〜第56C圖所示之非揮發性 半導體記憶胞元的D30— D30’剖面圖。 第58圖係表示將第56A圖〜第5 6C圖所示之非揮發性 半導體記憶胞元進行陣列配置之例子（第33實施形態）的示 意平面圖。 第59A圖係表示本發明之第34實施形態之非揮發性 半導體記憶胞元的平面示意構造圖。 第59B圖係表示本發明之第34實施形態之非揮發性半 導體記憶胞元的等價電路圖。 第59C圖係表示本發明之第34實施形態之非揮發性半 導體記憶胞元的剖面構造圖》 第60圖係表示將第59A圖〜第59C圖所示之非揮發性 半導體記憶胞元進行陣列配置之例子（第35實施形態）的示 意平面圖。 第61圖係表示本發明之第3 6實施形態之非揮發性半 導體記憶裝置的電路圖。 第62圖係以一覽表示第61圖所示之非揮發性半導體 記憶裝置的動作狀態圖。 第63A圖係表示在第37實施形態之記憶元件的平面 -250- 201010062 圖。 第63B圖係表示在第37實施形態之記憶元件的剖面 圖。 第63 C圖係表示在第37實施形態之記憶元件的等價電 路圖。 第64圖係表示在第37實施形態之記億元件之耦合系 統之等價電路的示意圖》 第65圖係表示在第37實施形態之記憶元件之特性的 Ο圖形。 第66圖係表示在第37實施形態之記憶元件之其他的 特性的圖形。 第67圖係表示在第37實施形態之記憶元件的動作圖。 第68A圖係表示在第37實施形態之非揮發性半導體 記憶胞元的平面圖。 第6 8B圖係表示在第37實施形態之非揮發性半導體記 憶胞元的剖面圖。Figure 29A is an equivalent circuit diagram showing a coupling system of memory cells. Q Figure 29B shows the circuit configuration of Figure 29A. Figure 30 is a view showing the configuration of a nonvolatile semiconductor memory device according to an eighteenth embodiment of the present invention. Figure 31 is a view showing the configuration of a nonvolatile semiconductor memory device according to a nineteenth embodiment of the present invention. Fig. 32A is a view showing the configuration of the column decoder shown in Fig. 31. Fig. 3B is a diagram for explaining the column decoder shown in Fig. 31. Fig. 33 is a diagram showing the operation of the column decoder shown in Fig. 32A. -246- 201010062 Fig. 34 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twentieth embodiment of the present invention. Fig. 3 is a view showing the configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Fig. 36 is a view showing the configuration of the column decoder shown in Fig. 35. Fig. 37 is a diagram showing the operation of the column decoder shown in Fig. 36. Fig. 3 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty-second embodiment of the present invention. Fig. 39A is a plan view showing the configuration of a nonvolatile semiconductor memory device according to a twenty-third embodiment of the present invention. Fig. 39B is a cross-sectional view showing the structure of B20 - B20' of the nonvolatile semiconductor memory device of the twenty third embodiment of the present invention. Figure 40 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty-fourth embodiment of the present invention. Fig. 4 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty fifth embodiment of the present invention. Fig. 42 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty sixth embodiment of the present invention. Figure 43 is a view showing the configuration of a non-volatile semiconductor device according to a twenty-seventh embodiment of the present invention. Figure 44 is a view showing the configuration of a nonvolatile semiconductor memory device according to a twenty-eighthth embodiment of the present invention. Fig. 45A is a plan view showing the configuration of a nonvolatile semiconductor memory device according to a twenty-ninth embodiment of the present invention. Fig. 45B is an equivalent circuit diagram showing the configuration of a nonvolatile half-247-201010062 conductor memory element according to a twenty-ninth embodiment of the present invention. Fig. 45C is a cross-sectional view showing the structure of the non-volatile semiconductor memory device according to the twenty-ninth embodiment of the present invention, taken along the line A20-A20'. Fig. 45D is a cross-sectional view showing the structure of B20-B20' of the nonvolatile semiconductor memory device of the twenty-ninth embodiment of the present invention. Fig. 45E is a cross-sectional view showing the structure of the non-volatile semiconductor memory device according to the twenty-ninth embodiment of the present invention, taken along the line E20-E20'. Fig. 46A is an operation diagram for explaining the case of the OTP of the memory cell shown in Figs. 45A to 45E. Fig. 46B is an operation diagram for explaining the case of the MTP of the memory cell shown in Figs. 45A to 45E. Figure 47 is a view showing the configuration of a nonvolatile semiconductor memory device according to a 30th embodiment of the present invention. Figure 48 is a view showing the configuration of a nonvolatile semiconductor memory device according to a 31st embodiment of the present invention. Fig. 49A is an operation diagram for explaining the case of the OTP of the memory cell array shown in Fig. 47. Fig. 49B is an operation diagram for explaining the case of the MTP of the memory cell array shown in Fig. 47. Fig. 50A is a plan view showing the nonvolatile semiconductor memory cells used in the 32nd to 36th embodiments of the present invention. Fig. 50B is an equivalent circuit diagram showing the nonvolatile semiconductor memory cells used in the 32nd to 36th embodiments of the present invention. Fig. 50C is a cross-sectional view showing the structure of A30-A30' of the non-volatile semiconductor memory cell of the 32nd to 36th embodiments of the present invention. -248- 201010062 Fig. 50D is a cross-sectional view showing the structure of B30-B30' of the non-volatile semiconductor memory cell of the 32nd to 36th embodiments of the present invention. Fig. 5E is a cross-sectional view showing the configuration of C30-C30' of the non-volatile semiconductor cells of the 32nd to 36th embodiments of the present invention. Fig. 51 is a view showing an operation state of a nonvolatile semiconductor memory cell having a basic configuration shown in Figs. 50A to 50E. Fig. 52A is a characteristic diagram for explaining the basic configuration of the nonvolatile semiconductor memory cells shown in Figs. 50A to 50E. Ο Section 52B is a circuit diagram for explaining the basic configuration of the nonvolatile semiconductor memory cells shown in Figs. 50A to 50E. Fig. 53A is a view showing other characteristics of the nonvolatile semiconductor memory cells of the basic constitution shown in Figs. 50A to 50E. Fig. 53B is a circuit diagram for explaining the basic configuration of the nonvolatile semiconductor memory cells shown in Figs. 50A to 50E. Fig. 54A is an equivalent circuit diagram for explaining a coupling system of a nonvolatile semiconductor memory cell of the basic configuration shown in Figs. 50A to 50E. Fig. 5B is a circuit diagram showing the basic constituent nonvolatile semiconductor memory cells shown in Figs. 50A to 50E. Fig. 55 is a diagram showing the calculation formula of the coupling of the basic constituent nonvolatile semiconductor memory cells shown in Figs. 50 to 50E. Fig. 56A is a plan schematic view showing the structure of a nonvolatile semiconductor memory cell in the 32nd embodiment of the present invention. Fig. 56B is an equivalent circuit diagram showing a nonvolatile semiconductor memory cell of a 32nd embodiment of the present invention. -249- 201010062 Figure 56C is a cross-sectional structural view showing a nonvolatile semiconductor memory cell of a 32nd embodiment of the present invention. Fig. 57A is a cross-sectional view showing the B30-B30' of the nonvolatile semiconductor memory cells shown in Figs. 56A to 56C. Fig. 57B is a cross-sectional view showing the C30-C30' of the nonvolatile semiconductor memory cells shown in Figs. 56A to 56C. Fig. 57C is a cross-sectional view showing the D30-D30' of the nonvolatile semiconductor memory cells shown in Figs. 56A to 56C. Fig. 58 is a schematic plan view showing an example (the thirty-third embodiment) in which the nonvolatile semiconductor memory cells shown in Figs. 56A to 5C are arranged in an array. Fig. 59A is a plan view showing the configuration of a nonvolatile semiconductor memory cell according to a thirty-fourth embodiment of the present invention. Fig. 59B is an equivalent circuit diagram showing the nonvolatile semiconductor memory cell of the 34th embodiment of the present invention. Fig. 59C is a cross-sectional structural view showing a nonvolatile semiconductor memory cell according to a thirty-fourth embodiment of the present invention. Fig. 60 is a view showing an array of nonvolatile semiconductor memory cells shown in Figs. 59A to 59C. A schematic plan view of an example of the arrangement (35th embodiment). Figure 61 is a circuit diagram showing a non-volatile semiconductor memory device according to a thirty-sixth embodiment of the present invention. Fig. 62 is a view showing the operation state of the nonvolatile semiconductor memory device shown in Fig. 61 in a list. Fig. 63A is a view showing a plane -250 - 201010062 of the memory element of the 37th embodiment. Fig. 63B is a cross-sectional view showing the memory element of the thirty-seventh embodiment. Fig. 63C is an equivalent circuit diagram showing the memory element of the thirty-seventh embodiment. Fig. 64 is a view showing an equivalent circuit of the coupling system of the mega element in the thirty-seventh embodiment. Fig. 65 is a Ο pattern showing the characteristics of the memory element in the thirty-seventh embodiment. Fig. 66 is a view showing another characteristic of the memory element of the thirty-seventh embodiment. Fig. 67 is a view showing the operation of the memory element in the thirty-seventh embodiment. Fig. 68A is a plan view showing the nonvolatile semiconductor memory cell of the 37th embodiment. Fig. 6B is a cross-sectional view showing the nonvolatile semiconductor memory cell of the 37th embodiment.
第68C圖係表示在第37實施形態之非揮發性半導體記 憶胞元的等價電路圖。 第69圖係表示在第37實施形態之非揮發性半導體記 憶胞元的動作表。 第70A圖係表示在第38實施形態之非揮發性半導體 記憶胞元的平面圖。 第70B圖係表示在第38實施形態之非揮發性半導體記 憶胞元的剖面圖。 第70C圖係表示在第38實施形態之非揮發性半導體記 -251 - 201010062 憶胞元的等價電路圖。 第71圖係表示在第38實施形態之非揮發性半導體記 憶胞元的動作表的圖。 第72圖係表示在第38實施形態之非揮發性半導體記 憶裝置之構成的示意圖。 第73圖係表示在第38實施形態之非揮發性半導體記 憶裝置之配置構成的示意圖。 第74圖係表示在第39實施形態之非揮發性半導體記 憶裝置之構成的示意圖。 第75A圖係表示在第40實施形態之非揮發性半導體 記憶胞元的平面圖。 第75B圖係表示在第40實施形態之非揮發性半導體記 憶胞元的剖面圖。 第75C圖係表示在第40實施形態之非揮發性半導體記 憶胞元的等價電路圖。 第76圖係表示在第40實施形態之記憶胞元陣列之記 憶胞元之配置構成的示意圖。 第77A圖係表示在本發明之先前技術之非揮發性半導 體記憶胞元的平面示意構造圖。 第7 7B圖係表示在本發明之先前技術之非揮發性半導 體記憶胞元的等價電路圖。 第77C圖係表示在本發明之先前技術之非揮發性半導 體記憶胞元之第77A圖的A30— A30’剖面圖。 第7 7D圖係表示在本發明之先前技術之非揮發性半導 體記憶胞元之第77A圖的D30— D30’剖面圖。 -252- 201010062 第7 8圖係用以說明在本發明之先前技術之非揮發性 半導體記憶胞元之資料保持特性的圖。 第79圖係表示在本發明之先前技術之非揮發性半導 體記憶胞元的等價電路圖。Fig. 68C is an equivalent circuit diagram showing the nonvolatile semiconductor memory cells in the thirty-seventh embodiment. Fig. 69 is a view showing the operation table of the nonvolatile semiconductor memory cells in the thirty-seventh embodiment. Fig. 70A is a plan view showing the nonvolatile semiconductor memory cell of the 38th embodiment. Fig. 70B is a cross-sectional view showing the nonvolatile semiconductor memory cell of the 38th embodiment. Fig. 70C is an equivalent circuit diagram showing the non-volatile semiconductor memory of the thirty-seventh embodiment. Fig. 71 is a view showing an operation table of the nonvolatile semiconductor memory cells in the 38th embodiment. Fig. 72 is a view showing the configuration of the nonvolatile semiconductor memory device of the 38th embodiment. Fig. 73 is a view showing the arrangement of the nonvolatile semiconductor memory device of the 38th embodiment. Fig. 74 is a view showing the configuration of the nonvolatile semiconductor memory device of the 39th embodiment. Fig. 75A is a plan view showing the nonvolatile semiconductor memory cell of the 40th embodiment. Fig. 75B is a cross-sectional view showing the nonvolatile semiconductor memory cell of the 40th embodiment. Fig. 75C is an equivalent circuit diagram showing a nonvolatile semiconductor memory cell of the 40th embodiment. Fig. 76 is a view showing the arrangement of the memory cells of the memory cell array of the 40th embodiment. Figure 77A is a schematic plan view showing the structure of the non-volatile semiconductor memory cells of the prior art of the present invention. Figure 7B is an equivalent circuit diagram showing the prior art non-volatile semiconductor memory cells of the present invention. Figure 77C is a cross-sectional view showing the A30-A30' of Figure 77A of the prior art non-volatile semiconductor memory cell of the present invention. The 7 7D drawing shows a cross-sectional view of D30-D30' of the 77A chart of the prior art non-volatile semiconductor memory cell of the present invention. -252- 201010062 Figure 7 is a diagram for explaining the data retention characteristics of the non-volatile semiconductor memory cells of the prior art of the present invention. Figure 79 is an equivalent circuit diagram showing the non-volatile semiconductor memory cells of the prior art of the present invention.
-253 - 201010062-253 - 201010062
【主要元件符號說明】 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010、1011、1016、1018 1012 ' 1013 1014 1015 1015， 1015A 1015B 1017 1019 1020 1021、1021A、1021B P型半導體基板 η型井 MOS電晶體（第1閘極區域部） 浮動閘極型電晶體（第2閘極區域 部） η型擴散層（Τ101的汲極、第1 η 型擴散層） η型擴散層（Τ101的源極及Τ102 的汲極、第2η型擴散層） η型擴散層（Τ 102的源極、第3η型 擴散層） 多晶矽層（Τ101的閘極） 浮動閘極 接點 金屬配線 電容器 Ρ型擴散層 η型擴散層（第4η型擴散層） η型擴散層（第5η型擴散層） η型擴散層（第6η型擴散層） η型擴散層 控制閘極配線（金屬配線） 分離用氧化膜 通道注入 -254- 201010062 1022 ' 1023 副接點 1024 副接點配線 1025 P型擴散層區域 1026 η型擴散層（第7n型擴散層） 1027 接點 1028 金屬配線 1030 電晶體形成部 1100-1-1100-Π ' 1100 - 0-1100 記憶胞元陣列（記憶胞元方塊）[Description of main component symbols] 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010, 1011, 1016, 1018 1012 ' 1013 1014 1015 1015, 1015A 1015B 1017 1019 1020 1021, 1021A, 1021B P-type semiconductor substrate n-type well MOS transistor ( First gate region) Floating gate transistor (second gate region) n-type diffusion layer (dip of Τ101, first η-type diffusion layer) n-type diffusion layer (source of Τ101 and Τ102) Deuterium, 2nd n-type diffusion layer) n-type diffusion layer (source of Τ102, third n-type diffusion layer) polysilicon layer (gate of Τ101) floating gate contact metal wiring capacitor Ρ type diffusion layer n-type diffusion layer (4th n-type diffusion layer) n-type diffusion layer (5th n-type diffusion layer) n-type diffusion layer (sixth n-type diffusion layer) n-type diffusion layer control gate wiring (metal wiring) separation oxide film channel injection -254- 201010062 1022 ' 1023 Sub-contact 1024 Sub-contact wiring 1025 P-type diffusion layer region 1026 n-type diffusion layer (7n-type diffusion layer) 1027 Contact 1028 Metal wiring 1030 Transistor forming portion 1100-1-1100-Π ' 1100 - 0-1100 memory Cell array (memory cell block membered)
-7 1200-1-1200-m 1201 1202 1203 、 1205 1204 1300 1301 ' 1303 1302 ' 1304 ' 1312 1310 1311 1400-1-1400-n 1401 1402 1403、1405 1404-7 1200-1-1200-m 1201 1202 1203 , 1205 1204 1300 1301 ' 1303 1302 ' 1304 ' 1312 1310 1311 1400-1-1400-n 1401 1402 1403, 1405 1404
列解碼器 解碼電路 反相器 位準挪移電路 NAND電路 選擇電路 傳輸閘極電晶體 開關用電晶體 PMOS電晶體 N Μ 0 S電晶體 列解碼器 解碼電路 反相器 位準挪移電路 NAND電路 資料輸入變換電路 255- 1500 201010062 1600 1700 2001 2002 2003 2004 2005 2006 2009 2009A 2010'2011 2012 2013 2014 2015 2015’ 2019 2021 2023 2024 2025 2100 - 0-2100 -7 2101 —1-2101-η 感測放大器 電源電壓控制電路 Ρ型半導體基板 η型井 電晶體形成部 電晶體的通道形成部（閘極區域 部） η型擴散層（第In型擴散層） η型擴散層（第2n型擴散層） 浮動閘極 面積擴張部 接點 金屬配線（第1金屬配線） 金屬配線（第2金屬配線） 電容器 P型擴散層 η型擴散層（第3n型擴散層） 控制閘極配線 空乏型（depletion — type)通道注入 η型擴散層（第4n型擴散層） 接點 金屬配線（第3金屬配線） 記憶胞元方塊 記憶胞元方塊 2200、2200A、2200—1〜2200—m 列解碼器 -256- 201010062 2201 2202 2203 2209-1、2209-2、2209—m 2220 2300-1-2300-η 2301Column decoder decoding circuit inverter level shift circuit NAND circuit selection circuit transmission gate transistor switch transistor PMOS transistor N Μ 0 S transistor column decoder decoding circuit inverter level shift circuit NAND circuit data input Conversion Circuit 255- 1500 201010062 1600 1700 2001 2002 2003 2004 2005 2006 2009 2009A 2010'2011 2012 2013 2014 2015 2015 2019 2021 2023 2024 2025 2100 - 0-2100 -7 2101 —1-2101-η Sense Amplifier Power Supply Voltage Control Circuit type semiconductor substrate n-type well transistor forming portion transistor channel forming portion (gate region) n-type diffusion layer (in-type diffusion layer) n-type diffusion layer (second-n-type diffusion layer) floating gate area Expansion part contact metal wiring (first metal wiring) Metal wiring (second metal wiring) Capacitor P-type diffusion layer n-type diffusion layer (3n-type diffusion layer) Control gate wiring depletion-type channel injection η Diffusion layer (4n-type diffusion layer) Contact metal wiring (3rd metal wiring) Memory cell memory cell block 2200, 2200A, 2200-1 ~2200-m column decoder -256- 201010062 2201 2202 2203 2209-1, 2209-2, 2209-m 2220 2300-1-2300-η 2301
2303 2400 2500 3001 3002、3002a、3002b 30032303 2400 2500 3001 3002, 3002a, 3002b 3003
3005 3006 3007 3008 3009 3010 3011 3012 位址解碼器 反相器 位準挪移電路（第1位準挪移電 路） 開關用電晶體 列解碼器 行解碼器 位址解碼器 反相器 位準挪移電路（第2位準挪移電 路） 資料變換電路 感測放大電路 p型半導體基板 η型井 電晶體 浮動閘極型電晶體 η型汲極擴散層 η型擴散層 η型擴散層 多晶砂層 多晶矽層 接點 接點 金屬配線 257- 201010062 3013 金屬配線 3014 電容器 3015、 3015a、 3015b n型擴散層 3055 η型擴散層 3016 接點 3017 η型擴散層 3018 接點 3019、 3019a、 3019b 金屬配線 3020 分離用絕緣 氧 化 膜 3100 記憶胞元陣 列 3200- _1 〜3200—in 列解碼器 3201 解碼部 3202 反相器 3203 位準挪移器 兼 仲 跋 衝 器 3204 NAND電路 3205 位準挪移器 兼 緩 衝 器 3300 行選擇閘電 路 3400 — 1 〜3400—η 行解碼器 3401 解碼部 3402 反相器 3403 位準挪移器 兼 緩 衝 器 3500 寫入、拭除 控 制 電 路 3600 感測放大器 3700 內部電源用 電 路 4001 記憶元件 258- 2010100623005 3006 3007 3008 3009 3010 3011 3012 address decoder inverter level shift circuit (first level shift circuit) switch transistor column decoder row decoder address decoder inverter level shift circuit (first 2-bit quasi-migration circuit) data conversion circuit sense amplifier circuit p-type semiconductor substrate n-type well crystal floating gate type transistor n-type drain diffusion layer n-type diffusion layer n-type diffusion layer polycrystalline sand layer polycrystalline germanium layer contact Point metal wiring 257- 201010062 3013 Metal wiring 3014 Capacitor 3015, 3015a, 3015b n-type diffusion layer 3055 n-type diffusion layer 3016 contact 3017 n-type diffusion layer 3018 contact 3019, 3019a, 3019b metal wiring 3020 insulating oxide film 3100 for separation Memory cell array 3200-_1~3200-in column decoder 3201 decoding unit 3202 inverter 3203 level shifter and interrupter 3204 NAND circuit 3205 level shifter and buffer 3300 row select gate circuit 3400-1 ~3400—η row decoding 3401 decoding unit 3402 of the inverter 3403 and is a quasi-stealing write buffer 3500, 3700 internal erase control circuit 3600 using sense amplifier power supply circuit memory element 4001 258-201010062
4002 4003 4004 4020 4030 4040 4200 4201 ' 4202'4203 4204 ' 4205 4206 ' 4207 4208 、 4209 4210、4211 4300 4301、4302、4303、4304 4305 、 4306 、 4307 4308、4309、4310 4311、4312、4313 4314 、 4315 、 4316 、 4317 4350 4351 4352 4353 4354 4355-1 4355—m 非揮發性半導體記憶胞元 非揮發性半導體記憶胞元 非揮發性半導體記憶胞元 電晶體形成部 電晶體形成部 電晶體形成部 P型半導體基板 η型擴散層 閘極區域部 多晶矽 金屬配線 接點 Ρ型半導體基板 η型擴散層 閘極區域部 多晶矽 金屬配線 接點 非揮發性半導體記憶裝置 控制部 感測放大電路 控制電路 行驅動器 列驅動器 列驅動器 -259 - 201010062 4361 4365-1 4365—m 4366 4401 ' 4402'4403'4404'4405 4406、4407、4408、4409 4410、4411、4412、4413 4414、4415、4416、4417 4418'4419'4420'4421 ' 4422 C101 C101-0〜C10n—7 C301 ' C302 C401 ' C402 ' C40n CG100 CG201 -0~ CG201 —7、CG20n-0 〜 CG20n-7 CG300、CG301、CG302 D200-D207 D300 D401、D402、D40n Data400 FG300 ' FG301 > FG302 M311-M314 ' M321-M324 ' M331~M334、M311~M3mn、 M411、M412、M41n、M4ml、M4mn 控制部 列驅動器 列驅動器 行驅動器 η型擴散層 閘極區域部 多晶矽 金屬配線 接點 電容器 行選擇電晶體 電容器 行選擇信號線 控制閘極 行選擇電晶體 控制閘極 資料輸出入線 記憶胞元的汲極 汲極線 資料輸出入線 浮動閘極 記憶胞元 非揮發性半導體記憶胞元 -260- 201010062 S300 記憶胞元的源極 S401 ' S402 ' S40m 源極線 〇 SG100 SG300 SG401、SG402、SG40m SW401、SW402、SW403 T101 T102 T301 T302、T303、T304 Tr421 Tr422 Tr431 選擇閘極 選擇閘極 選擇閘極線 行選擇閘 電晶體（第1電晶體） 浮動閘極型電晶體（第2電晶體） 電晶體（MOS電晶體） 浮動閘極型電晶體（浮動閘極型 Μ 0 S電晶體） 選擇電晶體 記憶元件 選擇電晶體4002 4003 4004 4020 4030 4040 4200 4201 ' 4202'4203 4204 ' 4205 4206 ' 4207 4208 , 4209 4210 , 4211 4300 4301 , 4302 , 4303 , 4304 4305 , 4306 , 4307 4308 , 4309 , 4310 4311 , 4312 , 4313 4314 , 4315 , 4316 , 4317 4350 4351 4352 4353 4354 4355-1 4355—m Non-volatile semiconductor memory cell non-volatile semiconductor memory cell non-volatile semiconductor memory cell transistor formation part transistor formation part transistor formation part P type Semiconductor substrate n-type diffusion layer gate region polycrystalline germanium metal wiring contact germanium type semiconductor substrate n-type diffusion layer gate region polycrystalline germanium metal wiring contact non-volatile semiconductor memory device control portion sense amplifier circuit control circuit row driver column driver Column driver-259 - 201010062 4361 4365-1 4365-m 4366 4401 ' 4402'4403'4404'4405 4406, 4407, 4408, 4409 4410, 4411, 4412, 4413 4414, 4415, 4416, 4417 4418 '4419 '4420' 4421 ' 4422 C101 C101-0~C10n—7 C301 ' C302 C401 ' C402 ' C40n CG100 CG201 -0~ CG201 —7, CG20n-0 ～ CG20n-7 CG300, CG301, CG 302 D200-D207 D300 D401, D402, D40n Data400 FG300 ' FG301 > FG302 M311-M314 ' M321-M324 ' M331~M334, M311~M3mn, M411, M412, M41n, M4ml, M4mn Control column drive column driver row driver Η-type diffusion layer gate region polycrystalline 矽 metal wiring contact capacitor row selection transistor capacitor row selection signal line control gate row selection transistor control gate data input line memory cell bungee bungee line data input line floating gate Polar memory cell non-volatile semiconductor memory cell -260- 201010062 S300 memory cell source S401 ' S402 ' S40m source line 〇 SG100 SG300 SG401, SG402, SG40m SW401, SW402, SW403 T101 T102 T301 T302, T303, T304 Tr421 Tr422 Tr431 Select gate select gate select gate line select gate transistor (1st transistor) Floating gate type transistor (2nd transistor) Transistor (MOS transistor) Floating gate type transistor (Floating gate type Μ 0 S transistor) Selecting the transistor memory element to select the transistor
Tr432 ' Tr433 記憶元件Tr432 ' Tr433 memory component
Tr441 Tr442 > Tr443 ' Tr444 選擇電晶體 記憶元件 261 -Tr441 Tr442 > Tr443 ' Tr444 Selecting the transistor Memory element 261 -
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| JP2008241044A JP5629968B2 (en) | 2008-09-19 | 2008-09-19 | Nonvolatile semiconductor memory cell and nonvolatile semiconductor memory device |
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| CN103094282A (en) * | 2011-10-28 | 2013-05-08 | 上海华虹Nec电子有限公司 | P-type disposable programmable device structure |
| TWI690063B (en) * | 2018-04-27 | 2020-04-01 | 日商東芝記憶體股份有限公司 | Semiconductor memory device |
| TWI729449B (en) * | 2018-12-19 | 2021-06-01 | 日商東芝記憶體股份有限公司 | Semiconductor device |
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| JP2007335718A (en) * | 2006-06-16 | 2007-12-27 | Toppan Printing Co Ltd | Non-volatile memory and manufacturing method thereof |
| JP2008141150A (en) * | 2006-11-10 | 2008-06-19 | Sharp Corp | Memory cell, method of clearing information stored in the same, and nonvolatile semiconductor storage apparatus with the same |
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| CN103094282A (en) * | 2011-10-28 | 2013-05-08 | 上海华虹Nec电子有限公司 | P-type disposable programmable device structure |
| CN103094282B (en) * | 2011-10-28 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | P type disposal programmable device structure |
| TWI690063B (en) * | 2018-04-27 | 2020-04-01 | 日商東芝記憶體股份有限公司 | Semiconductor memory device |
| TWI729449B (en) * | 2018-12-19 | 2021-06-01 | 日商東芝記憶體股份有限公司 | Semiconductor device |
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