JP2010050353A - Semiconductor wafer, method of manufacturing the same, and method of evaluating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a semiconductor wafer which is improved in GOI characteristics of a gate oxide film; a method of manufacturing the semiconductor wafer; and a method of evaluating the semiconductor wafer, in which absence of deterioration in GOI is evaluated easier than in a TDDB method etc. <P>SOLUTION: The method of manufacturing the semiconductor wafer includes at least a step of growing a silicon single-crystal ingot, a step of fabricating a wafer by slicing the silicon single-crystal ingot, a step of carrying out at least one of lapping, etching, and polishing on the sliced wafer, a step of measuring surface roughness of the wafer, and a step of obtaining a wavelength of surface roughness cycles at which the measured surface roughness is largest, and determining and selecting for acceptance a wafer having surface roughness such that the thickness of the gate oxide film is ≥1/4 as large as the wavelength of surface roughness cycles at which the measured surface roughness is largest. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer, a method for manufacturing a semiconductor wafer, and a method for evaluating a semiconductor wafer. More particularly, the present invention relates to a semiconductor wafer having improved breakdown voltage (GOI) characteristics of a gate oxide film, a method for manufacturing a semiconductor wafer, and a method for evaluating a semiconductor wafer. Is.

  Semiconductor elements such as MOS (Metal Oxide Semiconductor) capacitors and transistors are formed on the main surface of the semiconductor wafer. Insulating films such as gate oxide films formed on these semiconductor elements are reduced in thickness as the density of semiconductor elements increases, but it is difficult to lower the power supply voltage. Used under. Therefore, a higher quality insulating film is required.

As a method for evaluating the reliability of this insulating film, there is GOI (Gate Oxide Integrity) evaluation (for example, see Non-Patent Document 1). This evaluation is performed in the following procedure.
First, a silicon oxide film serving as an insulating film is formed on the main surface of the semiconductor wafer, a polysilicon layer is grown directly on the silicon oxide film, and then etched so as to leave the polysilicon layer in an island shape. Thereby, a capacitor having a MOS structure is formed, and the island-like polysilicon layer is utilized as an electrode.

  By applying a voltage to the insulating film through the polysilicon electrode of this MOS capacitor, the dielectric breakdown electric field strength represented by (dielectric breakdown voltage / insulating film thickness) is measured to perform GOI evaluation. As a method for measuring the breakdown electric field strength, there is a TZDB (Time Zero Dielectric Breakdown) method.

  In this method, while changing the electric field strength stepwise from about 0 to 15 MV / cm, the current value flowing through the MOS capacitor is monitored, and the electric field strength when the insulating film of the MOS capacitor is broken, that is, when breakdown occurs. Measure. The insulation film having a dielectric breakdown electric field strength of a predetermined value or more, for example, 8 MV / cm or more is regarded as good, and the others are regarded as defective. Evaluate the quality.

  As described above, in the GOI evaluation, the TZDB method is a method capable of performing the evaluation in a short time, but there is a problem that the evaluation according to the use state of the semiconductor element, that is, the evaluation over time cannot be performed. Therefore, a dielectric breakdown voltage measurement method called a TDDB (Time Dependent Dielectric Breakdown) method may be used.

  The TDDB method is a method in which a constant voltage or current is continuously applied to an insulating film, a current or voltage is detected at a predetermined time interval to obtain a change over time, and a time until dielectric breakdown is reached. It is a method for evaluating the details.

  In these evaluation methods, the cause of failure of a semiconductor element such as a MOS capacitor is a crystal defect called COP (Crystal Originated Particle) present on the main surface of the semiconductor wafer. Here, COP is a cavity defect having an octahedral structure that occurs during crystal growth. If this COP exists on the main surface of the semiconductor wafer, a silicon oxide film is also generated on the inner wall of the COP cavity when a silicon oxide film is generated on the main surface of the semiconductor wafer by the reaction of oxygen and silicon. In this COP inner wall oxide film, the corner portion of the octahedron is thin, and it is considered that breakdown occurs due to concentration of electrical stress in this portion.

On the other hand, it has been reported that surface roughness affects the channel mobility directly under the gate and affects the GOI characteristics (see, for example, Non-Patent Documents 2 and 3). Considering that the channel layer formed directly under the gate, that is, the inversion layer has a thickness of several nanometers, it is considered that if the surface roughness is large, carriers are scattered, thereby affecting channel mobility.
Further, it is said that the influence on GOI deteriorates as Ra increases. For example, in a wafer manufactured by the CZ method, TZDB evaluation is performed for two types of Ra = 0.17 nm and 0.46 nm, and it is shown that the smaller the Ra, the higher the dielectric breakdown electric field strength of the oxide film. .

  Therefore, in order to supply a semiconductor wafer capable of forming a high-quality insulating film, it is necessary to evaluate the GOI of the gate oxide film. The TZDB method and the TDDB method as described above are destructive inspections. Therefore, there is a problem that the wafers evaluated by these methods cannot be used as products because they are used for destructive inspection.

M.M. Tamatsuka et al. “Medium Field Breakdown on Metal Oxide Semiconductor Capacitor Containing Growing-in Czochralski Silicon Crystal Defect”, JPN. J. et al. Appl. Phys. 37, 1236 (1998). T.A. Ohmi, “Ultra-Clean Low Temperature Si Processes under the Assistance of Energy Controled Ion Bombardment”, Ext. Abst. 1991 Inter. Conf. SSDM, 481-483 (1991). M.M. Miyashita, et. al. "Dependence of Surface Microness of CZ, FZ and EPI Wafers on Wet Chemical Processing", J. Electrochem. Soc. , 139, 2133-2142 (1989).

  The present invention has been made in view of the above problems, and it is easier to evaluate the semiconductor wafer with improved GOI characteristics of the gate oxide film, the method of manufacturing the semiconductor wafer, and the absence of GOI compared to the TDDB method or the like. It aims at providing the evaluation method which can do.

  In order to solve the above-described problems, the present invention provides a semiconductor wafer in which at least a gate oxide film is formed on a semiconductor wafer, and the wavelength of the surface roughness period having the strongest thickness of the gate oxide film and the semiconductor wafer is strongest. Wherein the thickness of the gate oxide film has a surface roughness that is at least 1/4 of the wavelength of the strongest surface roughness period of the semiconductor wafer. A wafer is provided (claim 1).

  Thus, the thickness of the gate oxide film has a surface roughness that has a relationship of 1/4 or more with respect to the wavelength of the strongest surface roughness period of the semiconductor wafer, so that the curvature of the oxide film can be reduced. Since the influence is alleviated, it is possible to provide a semiconductor wafer capable of preventing electric field concentration and deterioration of GOI characteristics. Therefore, a semiconductor wafer suitable for forming a highly reliable gate oxide film can be obtained.

  In this case, the wavelength of the surface roughness period is preferably 100 nm or less.

  Thus, when the wavelength of the surface roughness period is 100 nm or less, the influence of the curvature of the oxide film can be reduced and the electric field concentration can be suppressed in the wavelength range that greatly affects the breakdown voltage of the gate oxide film. Thus, the deterioration of the GOI characteristic can be prevented.

  According to the present invention, there is also provided a semiconductor wafer manufacturing method in which at least a gate oxide film is formed on a semiconductor wafer, comprising at least a step of growing a silicon single crystal ingot, and slicing the silicon single crystal ingot. A step of manufacturing, a step of performing at least one of lapping, etching, and polishing on the sliced wafer, a step of measuring the surface roughness of the wafer, and a surface roughness cycle having the strongest strength of the measured surface roughness The thickness of the gate oxide film is determined, and a wafer having a surface roughness having a relationship of 1/4 or more with respect to the wavelength of the surface roughness period having the strongest intensity of the measured surface roughness is determined to be acceptable. And a method for producing a semiconductor wafer, characterized in that the method comprises:

  In this way, having the process of measuring the surface roughness of the wafer, specifically, measuring the surface roughness of the wafer and separating it into each frequency component by power spectrum analysis, how much intensity each frequency component exists Can be quantitatively evaluated.

  Then, the thickness of the gate oxide film and the wavelength of the surface roughness cycle with the strongest surface roughness measured are obtained, and the thickness of the gate oxide film is determined to be the wavelength of the surface roughness cycle with the strongest surface roughness measured. On the other hand, by selecting a wafer having a surface roughness that has a relation of 1/4 or more as acceptable, it is possible to reliably manufacture a semiconductor wafer having no deterioration in GOI characteristics without performing GOI evaluation of destructive inspection. Can do. Therefore, a semiconductor wafer suitable for forming a highly reliable gate oxide film can be manufactured.

  In this case, the wavelength of the surface roughness period is preferably 100 nm or less.

  As described above, by setting the wavelength of the surface roughness period to 100 nm or less, it is possible to perform pass / fail judgment of the wafer in a wavelength range that greatly affects the breakdown voltage of the gate oxide film, and a semiconductor that does not deteriorate GOI characteristics. Wafers can be manufactured.

  Furthermore, the present invention provides a method for evaluating a semiconductor wafer in which at least a gate oxide film is formed on a semiconductor wafer, the surface roughness of the semiconductor wafer being measured, and the surface roughness having the strongest strength of the measured surface roughness being measured. When the wavelength of the period is obtained and the thickness of the gate oxide film satisfies the relationship of 1/4 or more with respect to the wavelength of the surface roughness period having the strongest intensity of the measured surface roughness, the breakdown voltage of the gate oxide film The present invention provides a method for evaluating a semiconductor wafer, characterized in that the semiconductor wafer is evaluated not to deteriorate.

  In this way, the surface roughness of the semiconductor wafer is measured, the wavelength of the surface roughness cycle having the strongest measured surface roughness is obtained, and it is evaluated that the breakdown voltage of the gate oxide film does not deteriorate when a predetermined condition is satisfied. Thus, a semiconductor wafer can be evaluated without actually forming a MOS structure on the wafer surface and performing GOI evaluation, and can be evaluated more easily than the TDDB method or the like.

  Further, as a condition that the breakdown voltage of the gate oxide film does not deteriorate, the thickness of the gate oxide film satisfies a relation that is 1/4 or more with respect to the wavelength of the surface roughness cycle having the strongest surface roughness. As a result, the influence of the curvature of the oxide film can be alleviated to suppress the concentration of the electric field, and a semiconductor wafer having no deterioration in the GOI characteristics can be reliably evaluated.

  In this case, the wavelength of the surface roughness period is preferably 100 nm or less.

  This makes it possible to evaluate the GOI without performing a destructive inspection as in the TDDB method in a period with a short surface roughness.

  As described above, the semiconductor wafer of the present invention is a semiconductor wafer in which at least a gate oxide film is formed on a semiconductor wafer, and the wavelength of the surface roughness period having the strongest thickness of the gate oxide film and the semiconductor wafer is the same. The surface roughness is such that the thickness of the gate oxide film has a relationship of 1/4 or more with respect to the wavelength of the strongest surface roughness period of the semiconductor wafer. Thus, a semiconductor wafer that can prevent the GOI characteristics from being deteriorated can be obtained, and a semiconductor wafer suitable for forming a highly reliable gate oxide film can be selected and evaluated.

Hereinafter, the present invention will be described more specifically.
As described above, in order to supply a semiconductor wafer capable of forming a high-quality insulating film, it is necessary to evaluate the GOI of the gate oxide film, but it is evaluated by a destructive inspection such as the TZDB method or the TDDB method. Therefore, the wafers evaluated by these methods could not be used as products.
On the other hand, although it has been reported that the surface roughness affects the GOI, it is only disclosed that the smaller the surface roughness Ra, the higher the dielectric breakdown electric field strength of the oxide film. I didn't understand.

Accordingly, the present inventors paid attention to the relationship between the surface roughness of the semiconductor wafer and the GOI, measured the surface roughness of the semiconductor wafer to obtain Ra, and further evaluated the wafer's GOI characteristic by the TDDB method. However, it turned out that it became a relationship like FIG.
Here, FIG. 1 is a diagram showing the relationship between the surface roughness Ra obtained by AFM and Qbd obtained by TDDB measurement.

  As can be seen from FIG. 1, just because Ra is large, the GOI characteristic is not necessarily bad, and even when Ra is large, there is a large Qbd and good GOI characteristic. Here, as shown in FIG. 2, Ra is an average of the roughness (roughness) of the measurement range, and is information in the height direction. From this, it was found that the surface roughness affecting the GOI is not shown only by the information in the height direction, but another characteristic is very important.

  Therefore, the present inventors paid attention to the relationship between the thickness of the gate oxide film and the wavelength of the surface roughness period. And if there is a corner in the gate oxide film, curvature will occur in the corner, concentration of the applied electric field will occur, and dielectric breakdown will occur, so the thickness of the gate oxide film will be the surface roughness period It is conceived that the electric field concentration can be relaxed if it is 1/4 or more, and the thickness of the gate oxide film to be used is 1/4 or more of the strongest surface roughness period forming the wafer surface. An attempt was made to fabricate a semiconductor wafer.

As a result, it has been found that if the thickness of the gate oxide film is ¼ or more of the surface roughness period, the electric field concentration is relaxed, the influence on the GOI characteristics is not seen, and the GOI characteristics are improved.
Then, in the manufacturing process of the semiconductor wafer, the surface roughness is measured, and the thickness of the gate oxide film is more than 1/4 with respect to the wavelength of the surface roughness cycle having the strongest surface roughness. By selecting a wafer having surface roughness as acceptable, it is possible to reliably manufacture a semiconductor wafer having no deterioration in GOI characteristics without performing GOI evaluation as a destructive inspection. By evaluating that the breakdown voltage of the gate oxide film does not deteriorate when the condition is satisfied, a semiconductor wafer can be evaluated without actually forming a MOS structure on the wafer surface and performing GOI evaluation. It was found that it can be evaluated more easily than that.

  The present invention has been completed based on the above findings and findings, and the present invention will be described below in more detail with reference to the drawings. However, the present invention is not limited to these.

  The semiconductor wafer of the present invention is a semiconductor wafer in which at least a gate oxide film is formed on the semiconductor wafer, and the relationship between the thickness of the gate oxide film and the wavelength of the strongest surface roughness period of the semiconductor wafer is the gate oxidation. The film has a surface roughness in which the thickness of the film has a relationship of 1/4 or more with respect to the wavelength of the strongest surface roughness period of the semiconductor wafer.

By having the surface roughness that is the relationship between the thickness of the gate oxide film and the wavelength of the surface roughness cycle with the strongest strength of the semiconductor wafer, the influence of the curvature of the oxide film is alleviated. The semiconductor wafer can prevent the GOI characteristics from deteriorating.
Here, FIG. 3 is a schematic diagram showing relaxation of the electric field concentration of the gate oxide film. As shown in FIG. 3B, when the thickness of the gate oxide film has a relationship of 1/4 or more with respect to the wavelength of the surface roughness period, unlike FIG. 3A, electric field concentration occurs due to the curvature of the oxide film. Hateful. That is, the middle of the peak of the wavelength of the surface roughness period is ½ of the wavelength, and the oxide film grows from both sides of this intermediate point (valley) to fill the valley and relax the curvature at the peak. . Therefore, as shown in FIG. 3B, the electric field concentration due to the curvature of the oxide film is relaxed, thereby preventing the deterioration of the GOI characteristics. For this reason, the thickness of the gate oxide film has a surface roughness that has a relationship of 1/4 or more with respect to the wavelength of the surface roughness period, which is suitable for forming a highly reliable gate oxide film. It can be a semiconductor wafer.

Further, in the semiconductor wafer of the present invention, the wavelength of the surface roughness period is preferably 100 nm or less.
Thus, when the wavelength of the surface roughness period is 100 nm or less, the influence of the curvature of the oxide film can be reduced and the electric field concentration can be suppressed in the wavelength range that greatly affects the breakdown voltage of the gate oxide film. Thus, a semiconductor wafer that prevents the deterioration of the GOI characteristics can be manufactured.

  Next, although an example of the manufacturing method of the semiconductor wafer of this invention is demonstrated referring FIG. 4, 5, this invention is not necessarily limited to these.

First, a silicon single crystal ingot is prepared. As this silicon single crystal ingot, a general one may be prepared, for example, it can be grown by the Czochralski method.
Next, the silicon single crystal ingot is sliced to produce a wafer. This slice may be a general one, and can be sliced by a cutting device such as an inner peripheral slicer or a wire saw.

  Then, at least one of lapping, etching, and polishing is performed on the sliced wafer. The lapping, etching, and polishing may be performed under general conditions, and can be appropriately selected according to the specifications of the semiconductor wafer to be manufactured. In addition, surface grinding, chamfering, cleaning, and the like may be performed as necessary.

  Thereafter, the surface roughness of the wafer is measured. Here, the surface roughness is measured using an AFM, and the complex surface roughness is separated into frequency components by power spectrum analysis. Then, the intensity of each frequency component is quantitatively evaluated.

Here, examples of measurement results of the surface roughness are shown in FIGS. The left figure is the 3D image of the surface roughness measurement result, and the right figure is the power spectrum analysis result. The scanning range is 1 μm square. 4 and 5, the surface of FIG. 4 is rougher and Ra = 0.18 nm, whereas the surface of FIG. 5 has Ra = 0.11 nm.
From the power spectrum analysis, the peak in FIG. 4 is 25 nm, whereas in the case of FIG. 5, it is 110 nm.

  4 and 5, the wavelength of the surface roughness cycle having the strongest surface roughness measured is obtained, and the surface roughness cycle having the strongest surface roughness measured by the thickness of the gate oxide film to be used is obtained. Wafers having a surface roughness that has a relationship of 1/4 or more with respect to the wavelength of are determined to be acceptable and are selected.

  As described above, the surface roughness of the wafer is measured using the thickness of the gate oxide film and the AFM, and is separated into each frequency component by power spectrum analysis, and the wavelength of the surface roughness cycle having the strongest surface roughness is obtained. By selecting a wafer having a surface roughness that has a relationship of 1/4 or more with respect to the wavelength of the strongest surface roughness period of the surface roughness measured by the thickness of the gate oxide film as acceptable, Without performing GOI evaluation, which is a destructive inspection, it is possible to reliably manufacture a semiconductor wafer having no deterioration in GOI characteristics. Therefore, a semiconductor wafer suitable for forming a highly reliable gate oxide film can be manufactured.

In the method for producing a semiconductor wafer according to the present invention, the wavelength of the surface roughness period used for the wafer pass / fail judgment is preferably 100 nm or less.
As described above, by setting the wavelength of the surface roughness period to 100 nm or less, it is possible to perform pass / fail judgment of the wafer in a wavelength range that greatly affects the breakdown voltage of the gate oxide film, and a semiconductor that does not deteriorate GOI characteristics. Wafers can be manufactured.

  Next, although an example of the evaluation method of the semiconductor wafer of this invention is demonstrated, this invention is not necessarily limited to these.

First, a wafer to be evaluated is prepared.
Then, the surface roughness of the wafer is measured using AFM, and the wavelength of the surface roughness cycle having the strongest intensity is obtained by power spectrum analysis as shown in FIGS.
Subsequently, if the thickness of the gate oxide film satisfies the relationship of 1/4 or more with respect to the wavelength of the surface roughness cycle having the strongest surface roughness, the breakdown voltage of the gate oxide film is not deteriorated. Evaluate semiconductor wafers.

  In this way, the surface roughness of the semiconductor wafer is measured, the wavelength of the surface roughness period having the strongest intensity of the measured surface roughness is obtained, and it is evaluated that the breakdown voltage of the gate oxide film does not deteriorate when the above predetermined condition is satisfied. As a result, the semiconductor wafer can be evaluated without actually forming a MOS structure on the wafer surface and performing GOI evaluation, and can be evaluated more easily than the TDDB method or the like.

  Further, as a condition for evaluating that the breakdown voltage of the gate oxide film is not deteriorated, the relation that the thickness of the gate oxide film is 1/4 or more with respect to the wavelength of the surface roughness cycle having the strongest surface roughness is satisfied. In this case, the influence of the curvature of the oxide film can be alleviated to suppress electric field concentration, and a semiconductor wafer that does not deteriorate in GOI characteristics can be reliably evaluated.

  In the method for evaluating a semiconductor wafer of the present invention, the wavelength of the surface roughness period is preferably 100 nm or less.

  As a result, it is possible to evaluate the GOI without performing a destructive inspection like the TDDB method for the influence on the breakdown voltage of the gate oxide film, which is a problem because the influence is particularly large at the wavelength of the short period of the surface roughness. it can.

Here, the constant current TDDB method will be described with reference to FIGS. FIG. 8 is a schematic diagram showing the configuration of an insulated electric field strength measuring apparatus.
First, in order to evaluate the insulating electric field strength of the insulating film (gate oxide film), the MOS capacitor type semiconductor element 11 placed on the insulating electric field strength measuring apparatus is manufactured by the following procedure.

  First, the insulating film 12 made of a silicon oxide film is formed on the semiconductor wafer 13. The insulating film 12 can be formed by placing a plurality of semiconductor wafers 13 on a boat, placing them in a horizontal heat treatment furnace or a vertical heat treatment furnace, and performing heat treatment in an oxygen atmosphere. Next, a polysilicon film 14 serving as an electrode is grown immediately above the insulating film 12. The polysilicon film 14 is grown by introducing the semiconductor wafer 13 taken out from the heat treatment furnace into a CVD (Chemical Vapor Deposition) apparatus and introducing a growth gas such as monosilane into the reaction vessel of the apparatus under reduced pressure or normal pressure. be able to. Then, the polysilicon film 14 on the insulating film 12 is formed in an island shape by using a photolithography technique and an etching technique, and is arranged at a desired position as the polysilicon electrode 14.

  The semiconductor wafer 13 having the plurality of MOS capacitor type semiconductor elements 11 thus fabricated arranged on the main surface thereof is placed on a stage (not shown) of the dielectric breakdown strength measuring device 15. Then, the lower end of the probe 17 supported so as to be movable back and forth and right and left is brought into contact with the polysilicon electrode 14 of the MOS capacitor type semiconductor element 11. The probe 17 is connected to one terminal of a variable power supply 16 that can change the magnitude of the applied voltage, while the other terminal of the variable power supply 16 is connected to the stage of the dielectric breakdown strength measuring device 15. As described above, since the MOS capacitor type semiconductor element 11 is placed on the stage, the back surface of the MOS capacitor type semiconductor element 11 functions as an electrode corresponding to the polysilicon electrode 14. Further, a voltmeter 18 for measuring the applied voltage is connected in parallel to the variable power supply 16, and an ammeter 19 is interposed between the probe 7 and the variable power supply 16.

When the probe 17 is brought into contact with the polysilicon electrode 14, the variable power supply 16 is turned on, and the constant current density as shown in FIG. 9A (the transition of the voltage value with respect to the current density at that time is shown in FIG. 9B). ) Is applied. In the dielectric breakdown strength measuring device 15, the thickness of the insulating layer 12 and the threshold voltage are set in advance. The dielectric breakdown is detected from the change in voltage value caused by the dielectric breakdown, and the applied current density (A / cm ^2). ) And the time (sec.) Until dielectric breakdown, that is, the amount of charge Qbd (C / cm ² ) injected into the oxide film before the breakdown. Such an operation is performed on all the MOS capacitor type semiconductor elements 11 at a predetermined position, and the relationship between Qbd and cumulative failure is plotted, thereby evaluating the GOI characteristics of the semiconductor wafer.

Next, the present invention will be described more specifically with reference to Examples and Comparative Examples of the present invention, but the present invention is not limited to these.
(Example)
First, a P-type semiconductor wafer having a diameter of 200 mm doped with boron and having two different levels of surface roughness was prepared. The results of measuring the surface roughness of each wafer at this time are shown in FIGS. From the power spectrum analysis results of FIGS. 4 and 5, the respective peaks were 25 nm (1 / 4λ = 6.25 nm) and 110 nm (1 / 4λ = 27.5 nm).

  Subsequently, the semiconductor wafer was placed on a boat and placed in a vertical heat treatment furnace, and heat-treated at 800 ° C. in a dry atmosphere to form a gate oxide film having a thickness of 7 nm on the main surface of the wafer. Next, these semiconductor wafers were put into a CVD furnace, and a polysilicon layer was grown on the gate oxide film while doping phosphorus. The grown polysilicon layer has a thickness of about 300 nm and a resistance value of about 25 Ω / sq. Met. Subsequently, the polysilicon layer was removed by patterning and etching using a photolithography technique on these semiconductor wafers, and 100 MOS capacitors using the polysilicon layer as an electrode were fabricated in the semiconductor wafer surface. Note that the polysilicon etching after photolithography was performed by wet etching with hydrofluoric acid. Finally, in order to remove the silicon oxide film formed on the backside of the semiconductor wafer, a resist was applied to the main surface of the semiconductor wafer, and wet etching with dilute hydrofluoric acid was performed to remove the silicon oxide film on the backside of the wafer.

Then, a constant current is connected to the semiconductor wafer subjected to the above-described treatment with a tester and a full auto prober as shown in FIG. 8, and gate oxidation is performed using a constant current TDDB method applied until the gate oxide film is broken. An electric field stress was applied to the film. FIG. 9 shows the state of stress application. Stress is applied at a constant current density (FIG. 9A), and the voltage at that time is monitored (FIG. 9B). When dielectric breakdown occurs, a rapid voltage change occurs and the breakdown can be known. The applied current stress was 0.01 A / cm ² and the measurement temperature was 100 ° C. The electrode area was 4 mm ² .

(Comparative example)
A wafer having the same specifications as in the example was placed on a boat, placed in a vertical heat treatment furnace, and heat-treated in a dry atmosphere at 800 ° C. to form a gate oxide film having a thickness of 5 nm on the main surface of the wafer. Thereafter, the same processing as in the example was performed, and the GOI characteristics were similarly evaluated using the constant current TDDB method.

  FIG. 6 shows the results of GOI evaluation using the TDDB method in the example, and FIG. 7 shows the results of GOI evaluation using the TDDB method in the comparative example. 6 and 7 show the relationship between the cumulative defect index and the charge amount Qbd, and the cumulative defect index 1 indicates 80% of the cumulative defects. Further, the value of the charge amount Qbd is measured by TDDB at a constant current, and can be regarded as the time until dielectric breakdown as it is from the relationship of J × t = Q. That is, when the same cumulative defect index is seen, it can be seen that the larger the value of the charge amount Qbd, the longer the insulating film.

6 and 7, when the surface roughness peak is 25 nm (1 / 4λ = 6.25 nm), the GOI characteristics are not degraded when the gate oxide film thickness is 7 nm, but the gate oxide film thickness is 5 nm. Then, it can be seen that the GOI characteristics are deteriorated. 6 and 7, it can be seen that when the surface roughness peak is 110 nm (1 / 4λ = 27.5 nm), the GOI characteristics are not deteriorated in both the gate oxide thicknesses of 5 nm and 7 nm. From this, it can be seen that the GOI characteristic does not deteriorate when the thickness of the gate oxide film is ¼ or more of the wavelength of the peak period of the surface roughness, particularly when the peak of the surface roughness is a short period.
When the wavelength of the surface roughness period is 100 nm or less, the thickness of the gate oxide film needs to be ¼λ or more. However, when the wavelength of the surface roughness period exceeds 100 nm, the relationship with the surface roughness period is not observed. .

From the above, according to the semiconductor wafer of the present invention, the thickness of the gate oxide film has a surface roughness that is more than 1/4 of the wavelength of the strongest surface roughness period of the semiconductor wafer. As a result, the influence of the curvature of the oxide film is alleviated, so that it is possible to obtain a semiconductor wafer capable of preventing electric field concentration and deterioration of GOI characteristics.
Also, in the semiconductor wafer manufacturing process, the surface roughness of the wafer is measured, and the wafer is selected by determining pass / fail based on the relationship between the thickness of the gate oxide film and the wavelength of the measured surface roughness with the strongest surface roughness period. By doing so, it is possible to reliably manufacture a semiconductor wafer having no deterioration in GOI characteristics without performing GOI evaluation for destructive inspection. A semiconductor wafer suitable for forming a highly reliable gate oxide film can be manufactured.
Furthermore, the surface roughness of the semiconductor wafer is measured, the thickness of the gate oxide film and the wavelength of the surface roughness period with the strongest surface roughness measured are obtained, and the breakdown voltage of the gate oxide film is satisfied when the above predetermined condition is satisfied. It is possible to evaluate a semiconductor wafer without actually forming a MOS structure on the wafer surface and performing a GOI evaluation, and can be evaluated more easily than the TDDB method. .

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

It is a figure which shows the relationship between surface roughness Ra obtained by AFM, and Qbd obtained by TDDB measurement. It is explanatory drawing of surface roughness Ra. It is a schematic diagram which shows relaxation of the electric field concentration of a gate oxide film. It is a figure which shows the measurement result (when Ra = 0.18nm) of surface roughness. It is a figure which shows the measurement result (when Ra = 0.11nm) of surface roughness. It is a figure which shows the result of GOI evaluation using the TDDB method in an Example. It is a figure which shows the result of GOI evaluation using the TDDB method in a comparative example. It is a schematic diagram of an insulation electric field strength measuring device. (A) It is a figure showing the relationship between the current density and time in TDDB method. (B) It is a graph showing the relationship between the voltage and time in the TDDB method.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... MOS capacitor type semiconductor element, 12 ... Insulating film, 13 ... Semiconductor wafer, 14 ... Polysilicon electrode (polysilicon film), 15 ... Insulating electric field strength measuring device, 16 ... Variable power supply, 17 ... Probe, 18 ... Voltmeter 19 ... Ammeter.

Claims (6)

  A semiconductor wafer in which at least a gate oxide film is formed on a semiconductor wafer, and the relationship between the thickness of the gate oxide film and the wavelength of the strongest surface roughness period of the semiconductor wafer is the thickness of the gate oxide film. The semiconductor wafer is characterized in that the semiconductor wafer has a surface roughness having a relation of 1/4 or more with respect to the wavelength of the strongest surface roughness period of the semiconductor wafer.   The semiconductor wafer according to claim 1, wherein a wavelength of the surface roughness period is 100 nm or less.   A method for manufacturing a semiconductor wafer in which at least a gate oxide film is formed on a semiconductor wafer, comprising at least a step of growing a silicon single crystal ingot, a step of slicing the silicon single crystal ingot, and producing a wafer, A step of performing at least one of lapping, etching and polishing on the sliced wafer, a step of measuring the surface roughness of the wafer, and determining the wavelength of the surface roughness cycle having the strongest intensity of the measured surface roughness, A step of selecting a wafer having a surface roughness in which the thickness of the gate oxide film has a relationship of ¼ or more with respect to the wavelength of the surface roughness cycle having the strongest surface roughness measured as above, and selecting it. A method for producing a semiconductor wafer, comprising:   4. The method of manufacturing a semiconductor wafer according to claim 3, wherein the wavelength of the surface roughness period is 100 nm or less.   A semiconductor wafer evaluation method in which at least a gate oxide film is formed on a semiconductor wafer, measuring the surface roughness of the semiconductor wafer, and determining the wavelength of the surface roughness cycle having the strongest intensity of the measured surface roughness, It is evaluated that the breakdown voltage of the gate oxide film does not deteriorate when the thickness of the gate oxide film satisfies a relation of 1/4 or more with respect to the wavelength of the surface roughness period having the strongest surface roughness measured. A method for evaluating a semiconductor wafer.   6. The method for evaluating a semiconductor wafer according to claim 5, wherein the wavelength of the surface roughness period is 100 nm or less.

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