JP5217353B2 - Insulating film formation method - Google Patents

Insulating film formation method

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JP5217353B2
JP5217353B2 JP2007268045A JP2007268045A JP5217353B2 JP 5217353 B2 JP5217353 B2 JP 5217353B2 JP 2007268045 A JP2007268045 A JP 2007268045A JP 2007268045 A JP2007268045 A JP 2007268045A JP 5217353 B2 JP5217353 B2 JP 5217353B2
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insulating film
oxide film
silicon
silicon oxide
nitrogen
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JP2009099673A (en
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剛 大槻
敏視 戸部
康 水澤
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Shin Etsu Handotai Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

本発明は、半導体シリコンウェーハ表面に形成された半導体素子の絶縁膜を形成する方法及び該絶縁膜を具備する半導体素子に関する。   The present invention relates to a method for forming an insulating film of a semiconductor element formed on the surface of a semiconductor silicon wafer and a semiconductor element having the insulating film.

半導体シリコンウェーハの主表面にはMOS(Metal Oxide Semiconductor)キャパシタやトランジスタ等の半導体素子が形成される。それら半導体素子に形成されるゲート酸化膜等の絶縁膜は、半導体素子の高密度化に伴いその厚みが減る一方、電源電圧を低くすることは困難であるため、絶縁膜は高い電界強度の下で使用されている。そのためより品質の高い絶縁膜が必要とされている。   Semiconductor elements such as MOS (Metal Oxide Semiconductor) capacitors and transistors are formed on the main surface of the semiconductor silicon wafer. Insulating films such as gate oxide films formed on these semiconductor elements are reduced in thickness as the density of semiconductor elements increases, but it is difficult to lower the power supply voltage. Used in. Therefore, a higher quality insulating film is required.

この絶縁膜の信頼性評価方法としてGOI(Gate Oxide Integrity)評価がある(たとえば非特許文献1参照)。この評価は以下のような手順で行われる。まず、半導体シリコンウェーハ主表面に絶縁膜となるシリコン酸化膜を形成し、その直上にポリシリコン層を成長させた後、該ポリシリコン層を島状に残すようにエッチングする。これによりMOS構造のキャパシタが形成され、前記島状ポリシリコン層は電極として活用される。   As a method for evaluating the reliability of the insulating film, there is a GOI (Gate Oxide Integrity) evaluation (see, for example, Non-Patent Document 1). This evaluation is performed according to the following procedure. First, a silicon oxide film serving as an insulating film is formed on the main surface of a semiconductor silicon wafer, and a polysilicon layer is grown directly on the silicon oxide film, followed by etching so that the polysilicon layer remains in an island shape. Thereby, a MOS structure capacitor is formed, and the island-like polysilicon layer is used as an electrode.

このMOSキャパシタのポリシリコン電極を通して絶縁膜に電圧を印加することにより、(絶縁破壊電圧/絶縁膜の厚み)で表される絶縁破壊電界強度を測定してGOI評価を行うのであるが、この絶縁破壊電界強度を測定する方法としては、TZDB(Time Zero Dielectric Breakdown)法がある。この方法では、0〜15MV/cm程度まで階段状に電界強度を変化させながら、MOSキャパシタに流れる電流値をモニタし、MOSキャパシタの絶縁膜が破壊されたとき、すなわちブレイクダウンしたときの電界強度を測定する。この絶縁破壊電界強度が所定の値以上、例えば8MV/cm以上である絶縁膜を良とし、そうでないものを不良として、印加したMOSキャパシタ総数に対する良であったキャパシタ数の割合にもとづいて絶縁膜の品質を評価する。   By applying a voltage to the insulating film through the polysilicon electrode of this MOS capacitor, the dielectric breakdown electric field strength represented by (dielectric breakdown voltage / insulating film thickness) is measured to perform GOI evaluation. As a method for measuring the breakdown electric field strength, there is a TZDB (Time Zero Dielectric Breakdown) method. In this method, while changing the electric field strength stepwise from about 0 to 15 MV / cm, the current value flowing through the MOS capacitor is monitored, and the electric field strength when the insulating film of the MOS capacitor is broken, that is, when breakdown occurs. Measure. An insulating film having a dielectric breakdown field strength of a predetermined value or higher, for example, 8 MV / cm or higher is regarded as good, and a non-defective one is regarded as defective. Evaluate the quality.

このようにGOI評価においてTZDB法は短時間で評価を行うことができる手法であるが、半導体素子の使用状態に応じた評価,即ち経時的な評価を行うことができないという問題があった。そのため、TDDB(Time Dependent Dielectric Breakdown)法という絶縁破壊耐圧測定法が用いられることがある。TDDB法とは、絶縁膜に一定の電圧ないしは電流を連続的に印加し続け、所定の時間間隔で電流ないしは電圧を検出して経時的な変化を求め、絶縁破壊に至るまでの時間、その経過等を詳細に評価する方法である。すなわち特定ストレス印加時の絶縁膜寿命を評価しており、FLASHメモリはもとより各種デバイスの動作と密接な係わりがあり、より長寿命の酸化膜を形成することは先端デバイスのみならず、非常に大切なことである。   As described above, in the GOI evaluation, the TZDB method is a method that can be evaluated in a short time, but there is a problem that evaluation according to the use state of the semiconductor element, that is, evaluation over time cannot be performed. Therefore, a dielectric breakdown voltage measurement method called a TDDB (Time Dependent Dielectric Breakdown) method may be used. The TDDB method is a method in which a constant voltage or current is continuously applied to an insulating film, a current or voltage is detected at a predetermined time interval to obtain a change over time, and a time until dielectric breakdown is reached. It is a method for evaluating the details. In other words, it evaluates the life of the insulation film when a specific stress is applied. It is closely related to the operation of various devices as well as the FLASH memory, and it is very important to form an oxide film with a longer life, not only for advanced devices. It is a thing.

TDDB法による酸化膜寿命について、一定電流密度J(A/cm)をMOSキャパシタに印加し、破壊までの時間t(sec)を測定し、これらの積 J×t=Q をもって表現することが良く行なわれる。これは、絶縁膜が破壊されるまでに印加された電荷量Qbd(C/cm)である。この電荷量が大きい絶縁膜程長寿命・高信頼性といえる。 The oxide film lifetime by the TDDB method can be expressed by applying a constant current density J (A / cm 2 ) to the MOS capacitor, measuring the time t (sec) until breakdown, and multiplying these times by J × t = Q Well done. This is the amount of charge Q bd (C / cm 2 ) applied until the insulating film is destroyed. It can be said that an insulating film having a larger amount of charge has a longer life and higher reliability.

非特許文献1にもあるがこのQbdは大きく3つのモードに分解される。一つは比較的短時間で破壊される初期不良と呼ばれるものであり、シリコン基板に存在するCOP(Crystal Originated Particle)などが影響する。二つ目は真性破壊と呼ばれるもので、絶縁膜そのものがもつ寿命によるものである。最後の一つが真性破壊と初期不良の中間に位置するものである。初期不良低減はもちろん重要であるが、スクリーニング等で排除可能であり、寿命、すなわち長期信頼性の観点からは、より真性破壊領域が重要である。すなわちよりQbd値が大きい絶縁膜が求められる。 Although also in Non-Patent Document 1, this Q bd is largely decomposed into three modes. One is called an initial failure that is destroyed in a relatively short time, and is influenced by COP (Crystal Originated Particle) existing in the silicon substrate. The second is called intrinsic destruction and is due to the lifetime of the insulating film itself. The last one is located between intrinsic destruction and initial failure. Of course, it is important to reduce initial defects, but it can be eliminated by screening or the like. From the viewpoint of lifetime, that is, long-term reliability, the intrinsic fracture region is more important. That is, an insulating film having a larger Q bd value is required.

このようにTDDB法などにより評価されるQbd等に代表されるように長期信頼性のある絶縁膜を形成することはデバイス作製上の観点から非常に有用である。 In this way, it is very useful from the viewpoint of device fabrication to form an insulating film with long-term reliability as represented by Q bd and the like evaluated by the TDDB method.

SEMI STANDARD M60SEMI STANDARD M60

本発明はかかる事情に鑑みてなされたものであって、通常の絶縁膜の形成に用いる抵抗加熱炉をそのまま使用し、特別なガスなどを使うことなく信頼性の高い絶縁膜をシリコンウェーハ上に形成する方法及び該方法により絶縁膜の形成された半導体素子を提供することを目的とする。   The present invention has been made in view of such circumstances, and a resistance heating furnace used for forming a normal insulating film is used as it is, and a highly reliable insulating film is formed on a silicon wafer without using a special gas. It is an object of the present invention to provide a method for forming a semiconductor element and an insulating film formed by the method.

上記課題を解決するため、本発明は、シリコンウェーハを雰囲気ガス中で熱処理することにより絶縁膜を形成する絶縁膜の形成方法において、
前記雰囲気ガスは窒素で希釈した酸素を使用し、前記熱処理は、前記雰囲気ガスの下、抵抗加熱炉を使用して700〜900℃の温度で前記シリコンウェーハに熱処理を施し、
前記絶縁膜として10nm以下の膜厚のシリコン酸化膜を形成することを特徴とする絶縁膜の形成方法を提供する。
In order to solve the above problems, the present invention provides an insulating film forming method for forming an insulating film by heat-treating a silicon wafer in an atmospheric gas.
The atmosphere gas uses oxygen diluted with nitrogen, and the heat treatment is performed on the silicon wafer at a temperature of 700 to 900 ° C. using a resistance heating furnace under the atmosphere gas,
That provides a method of forming an insulating film and forming a less thickness silicon oxide film of 10nm as the insulating film.

このように本発明は雰囲気ガスとして窒素で希釈した酸素を使用し、この雰囲気ガスの下、抵抗加熱炉を使用して700〜900℃の温度でシリコンウェーハに熱処理を施して、10nm以下の膜厚のシリコン酸化膜を絶縁膜として形成する。   As described above, the present invention uses oxygen diluted with nitrogen as the atmospheric gas, and heat-treats the silicon wafer at a temperature of 700 to 900 ° C. using the resistance heating furnace under the atmospheric gas to form a film of 10 nm or less. A thick silicon oxide film is formed as an insulating film.

上記のように絶縁膜を形成する際、雰囲気ガスを酸素を窒素で希釈したものとすることにより、シリコンウェーハ表面付近に窒素が存在することにより、シリコン酸化膜/シリコン界面付近に空孔が供給され、シリコンが酸化されるときに放出される格子間シリコンを消滅させることが可能となり、この格子間シリコンによる体積変化を緩和することができる。従って、シリコン酸化膜/シリコン界面に生じるストレスを緩和することができる。また、実際のゲート酸化膜となって電気ストレス印加を受ける際、電子注入による酸化膜へのダメージをシリコン酸化膜中に窒素が存在することで、緩和することができる。   When the insulating film is formed as described above, oxygen is diluted with nitrogen as the atmospheric gas, so that nitrogen is present near the silicon wafer surface, so that vacancies are supplied near the silicon oxide film / silicon interface. Then, it becomes possible to eliminate the interstitial silicon released when the silicon is oxidized, and the volume change due to the interstitial silicon can be mitigated. Therefore, the stress generated at the silicon oxide film / silicon interface can be alleviated. Further, when an electrical stress is applied as an actual gate oxide film, damage to the oxide film due to electron injection can be mitigated by the presence of nitrogen in the silicon oxide film.

また、上記雰囲気ガスの下、抵抗加熱炉を使用して700〜900℃の温度でシリコンウェーハに熱処理を施すので、窒化膜を成長させることなく、また、コストを必要以上にかけることもなく、シリコン酸化膜を絶縁膜としてシリコンウェーハ上に形成することができる。
さらに、10nm以下の膜厚のシリコン酸化膜を絶縁膜としてシリコンウェーハに形成すれば、シリコン酸化膜/シリコン界面に窒素を到達させることができ、窒素をシリコン酸化膜中に十分に拡散させることができる。
従って、通常の絶縁膜(シリコン酸化膜)の形成に用いる抵抗加熱炉をそのまま使用し、特別なガスを使うことなく信頼性の高い絶縁膜をシリコンウェーハ上に形成することができる。
In addition, since the silicon wafer is subjected to heat treatment at a temperature of 700 to 900 ° C. using the resistance heating furnace under the above atmospheric gas, without growing a nitride film, and without increasing the cost more than necessary, A silicon oxide film can be formed as an insulating film on a silicon wafer.
Furthermore, if a silicon oxide film having a thickness of 10 nm or less is formed on a silicon wafer as an insulating film, nitrogen can reach the silicon oxide film / silicon interface, and nitrogen can be sufficiently diffused into the silicon oxide film. it can.
Therefore, a resistance heating furnace used for forming a normal insulating film (silicon oxide film) can be used as it is, and a highly reliable insulating film can be formed on a silicon wafer without using a special gas.

この場合、前記雰囲気ガスは酸素の分圧を0.5〜0.01atmとすることが好ましい。
このように、雰囲気ガス中の酸素分圧を0.5〜0.01atmとすることにより、窒素による効果を十分に引き出すことができる。
In this case, the atmospheric gas is not preferable be 0.5~0.01atm the partial pressure of oxygen.
Thus, the effect by nitrogen can fully be drawn out by making oxygen partial pressure in atmospheric gas into 0.5-0.01 atm.

また本発明は、前記絶縁膜の形成方法によって形成された絶縁膜を具備する半導体素子である。
このように、上記本発明の絶縁膜の形成方法によってシリコンウェーハ上に絶縁膜が形成された半導体素子であれば、絶縁膜形成時のシリコン酸化膜/シリコン界面に生じるストレスが緩和されており、さらには、ゲート酸化膜となって電気ストレス印加を受ける際、電子注入によるシリコン酸化膜へのダメージがシリコン酸化膜中の窒素により緩和されるので、より寿命の長い半導体素子となる。
The present invention is, Oh Ru in the semiconductor device comprising an insulating film formed by the method for forming the insulating film.
As described above, if the semiconductor element has an insulating film formed on the silicon wafer by the insulating film forming method of the present invention, the stress generated at the silicon oxide film / silicon interface during the formation of the insulating film is reduced. Furthermore, when the gate oxide film is subjected to electrical stress application, damage to the silicon oxide film due to electron injection is alleviated by nitrogen in the silicon oxide film, so that the semiconductor device has a longer lifetime.

本発明の絶縁膜の形成方法及び半導体素子であれば、特殊なガスを使用することなく従来からある設備を使用して信頼性の高い絶縁膜をシリコンウェーハ上に形成することができ、寿命のより長い半導体素子を得ることができる。   With the insulating film forming method and semiconductor element of the present invention, a highly reliable insulating film can be formed on a silicon wafer using conventional equipment without using a special gas, and the lifetime A longer semiconductor element can be obtained.

以下、本発明の実施形態について図面を参照しながら具体的に説明するが、本発明はこれらに限定されるものではない。
図1は、本発明に係る方法により形成された絶縁膜を絶縁電界強度測定装置により評価する構成を示す図である。
図1の評価用MOSキャパシタ型半導体素子1は、半導体シリコンウェーハ3上に本発明の方法によって絶縁膜2が形成され、その上にポリシリコン電極4が形成されたものである。
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is a diagram showing a configuration in which an insulating film formed by the method according to the present invention is evaluated by an insulating electric field strength measuring apparatus.
The evaluation MOS capacitor type semiconductor device 1 of FIG. 1 is obtained by forming an insulating film 2 on a semiconductor silicon wafer 3 by the method of the present invention and forming a polysilicon electrode 4 thereon.

まず、本発明に係る絶縁膜2の形成は、以下のような手順で形成される。
用意された半導体シリコンウェーハ3をボートに載置して抵抗加熱炉(不図示)に投入する。この抵抗加熱炉は、従来と同じものを使用することができ、横型炉でも縦型炉であってもよい。
First, the insulating film 2 according to the present invention is formed by the following procedure.
The prepared semiconductor silicon wafer 3 is placed on a boat and put into a resistance heating furnace (not shown). This resistance heating furnace can be the same as the conventional one, and may be a horizontal furnace or a vertical furnace.

次に雰囲気ガスを供給しながら、半導体シリコンウェーハ3に熱処理を施し、該ウェーハ3上にシリコン酸化膜からなる絶縁膜2を形成する。
このとき、供給する雰囲気ガスは窒素で希釈した酸素を使用する。
この窒素で希釈した酸素を雰囲気ガスとして使用すれば、一般的に使用されるガスを混合しているので、従来から使用されている抵抗加熱炉を適用することができ、特殊なガスを使用する場合に必要となる設備を省略することができる。
Next, the semiconductor silicon wafer 3 is subjected to heat treatment while supplying the atmospheric gas, and the insulating film 2 made of a silicon oxide film is formed on the wafer 3.
At this time, the atmosphere gas supplied uses oxygen diluted with nitrogen.
If oxygen diluted with nitrogen is used as the atmospheric gas, commonly used gas is mixed, so the conventional resistance heating furnace can be applied and special gas is used. The equipment required in some cases can be omitted.

そして上記熱処理は、このような雰囲気ガスの下において、700〜900℃の温度で加熱される。
熱処理温度が700℃より低温ではシリコンの酸化反応の進行が遅いため、必要とする酸化膜厚を得るのに時間がかかってしまい、コストがかさむ等の理由により実用的ではない。一方、窒素雰囲気中において900℃より高温、特には1100℃以上の高温にシリコンウェーハをさらすと、シリコンウェーハ上に熱窒化膜が成長することが知られている。すなわち、900℃より高温で半導体シリコンウェーハ3を熱処理すると、絶縁膜としてシリコン酸化膜でなくシリコン窒化膜が形成する可能性がある。
従って、本発明では、絶縁膜としてシリコン酸化膜を形成することを目的としているため、本発明のように窒素で酸素を希釈した雰囲気ガスを使用し、シリコン酸化膜を絶縁膜2として形成するには、シリコン窒化膜が成長せず、実用的な700〜900℃の範囲の温度で熱処理する必要がある。
And the said heat processing is heated at the temperature of 700-900 degreeC under such atmospheric gas.
When the heat treatment temperature is lower than 700 ° C., the progress of the oxidation reaction of silicon is slow, so that it takes time to obtain the required oxide film thickness, which is not practical for reasons such as high cost. On the other hand, it is known that when a silicon wafer is exposed to a temperature higher than 900 ° C., particularly 1100 ° C. or higher in a nitrogen atmosphere, a thermal nitride film grows on the silicon wafer. That is, when the semiconductor silicon wafer 3 is heat-treated at a temperature higher than 900 ° C., a silicon nitride film may be formed as an insulating film instead of a silicon oxide film.
Therefore, in the present invention, the purpose is to form a silicon oxide film as an insulating film. Therefore, as in the present invention, an atmosphere gas diluted with nitrogen is used to form a silicon oxide film as the insulating film 2. The silicon nitride film does not grow, and it is necessary to perform heat treatment at a practical temperature in the range of 700 to 900 ° C.

そして、10nm以下の膜厚のシリコン酸化膜を絶縁膜として形成するため、例えば約250分程度、抵抗加熱炉で半導体シリコンウェーハ3を上記条件で熱処理を施す。
このとき、10nmより厚くシリコン酸化膜を形成すると、窒素がシリコン酸化膜中を拡散してシリコン酸化膜/シリコン界面に到達しにくくなるため、窒素による空孔の効果が期待出来ない。
従って、本発明では、シリコン酸化膜中に窒素を十分に拡散させるため、10nm以下の膜厚でシリコン酸化膜を形成する。このような膜厚のシリコン酸化膜を絶縁膜とすれば、シリコン酸化膜中に十分に窒素が拡散された絶縁膜を形成することができ、発生する格子間シリコンによるウェーハ全体のストレスを緩和したり、デバイスを使用した際の電子注入によるシリコン酸化膜へのダメージを抑制するといった窒素による効果を得ることができる。
なお、本発明において、RTA(Rapid Thermal Anneal)のような短時間の熱処理では、必要なシリコン酸化膜厚を得ることができない。
Then, in order to form a silicon oxide film having a thickness of 10 nm or less as an insulating film, the semiconductor silicon wafer 3 is subjected to heat treatment under the above conditions in a resistance heating furnace, for example, for about 250 minutes.
At this time, if the silicon oxide film is formed thicker than 10 nm, nitrogen diffuses in the silicon oxide film and does not easily reach the silicon oxide film / silicon interface, so that the effect of vacancies due to nitrogen cannot be expected.
Therefore, in the present invention, in order to sufficiently diffuse nitrogen in the silicon oxide film, the silicon oxide film is formed with a thickness of 10 nm or less. If the silicon oxide film having such a thickness is used as an insulating film, an insulating film in which nitrogen is sufficiently diffused can be formed in the silicon oxide film, and the stress on the entire wafer due to the generated interstitial silicon can be reduced. In addition, it is possible to obtain an effect of nitrogen such as suppressing damage to the silicon oxide film due to electron injection when the device is used.
In the present invention, a necessary silicon oxide film thickness cannot be obtained by short-time heat treatment such as RTA (Rapid Thermal Anneal).

このように、絶縁膜の形成の際、窒素で酸素を希釈することにより空孔を供給し、シリコンが酸化されるときに放出される格子間シリコンを消滅させることが可能となる。また、酸化時に放出される格子間シリコンによる体積変化を緩和することが可能になり酸化膜/シリコン界面に生じるストレスを緩和することが可能である。
なお、シリコン酸化膜形成後に窒素中でアニールしても、本発明で得られるような窒素による効果と同等の効果を期待することは出来ない。
As described above, when forming the insulating film, it is possible to supply voids by diluting oxygen with nitrogen and to eliminate interstitial silicon released when silicon is oxidized. Further, it is possible to relieve the volume change due to interstitial silicon released during oxidation, and it is possible to relieve stress generated at the oxide film / silicon interface.
Note that even if annealing is performed in nitrogen after the formation of the silicon oxide film, it is not possible to expect the same effect as that obtained by the present invention.

さらに本発明の雰囲気ガスは、酸素の分圧を0.5〜0.01atmとすることが好ましい。
酸素分圧は、あまりに酸素が多いとシリコン酸化膜が急激に成長してしまうため、窒素が拡散しにくくなり、シリコン酸化膜/シリコン界面に窒素が到達し難くなる。そのため、酸素分圧が0.5atm以下であれば、シリコン酸化膜/シリコン界面まで十分に窒素が行き渡り、窒素による効果をより発揮できる。
逆に酸素分圧の下限は、実際に装置で制御可能な量として0.01atm程度が下限となる。この分圧範囲の中で目的とする酸化膜厚の制御性等を勘案して酸素分圧を決定するのが好ましい。
Furthermore, the atmospheric gas of the present invention preferably has an oxygen partial pressure of 0.5 to 0.01 atm.
When the oxygen partial pressure is too much oxygen, the silicon oxide film grows abruptly, making it difficult for nitrogen to diffuse and making it difficult for nitrogen to reach the silicon oxide film / silicon interface. Therefore, if the oxygen partial pressure is 0.5 atm or less, nitrogen is sufficiently distributed to the silicon oxide film / silicon interface, and the effect of nitrogen can be further exhibited.
Conversely, the lower limit of the oxygen partial pressure is about 0.01 atm as the amount that can be actually controlled by the apparatus. It is preferable to determine the oxygen partial pressure in consideration of the controllability of the target oxide film thickness within this partial pressure range.

上記絶縁膜2の形成方法によって形成された絶縁膜2を具備する半導体素子1であれば、絶縁膜形成時のシリコン酸化膜/シリコン界面に生じるストレスが緩和されており、さらには、ゲート酸化膜となって電気ストレス印加を受ける際、電子注入によるシリコン酸化膜へのダメージがシリコン酸化膜中に拡散した窒素により緩和されるので、より寿命の長い半導体素子となる。   In the case of the semiconductor element 1 having the insulating film 2 formed by the method for forming the insulating film 2, the stress generated at the silicon oxide film / silicon interface during the formation of the insulating film is alleviated, and further, the gate oxide film Thus, when an electrical stress is applied, damage to the silicon oxide film due to electron injection is alleviated by nitrogen diffused in the silicon oxide film, so that the semiconductor device has a longer life.

従って、本発明の絶縁膜の形成方法及び半導体素子であれば、信頼性の高い絶縁膜を従来からある設備を使用し、また特殊なガスを使用することもなくシリコンウェーハ上に形成することができ、寿命のより長い半導体素子を得ることができる。   Therefore, according to the method of forming an insulating film and a semiconductor element of the present invention, a highly reliable insulating film can be formed on a silicon wafer without using special equipment and using a special gas. And a semiconductor device having a longer lifetime can be obtained.

そして、本発明により形成された絶縁膜2を図1の絶縁電界強度測定装置5を用いてTDDB特性の評価をするにあたっては、まず、絶縁膜2上に電極となるポリシリコン膜を成長させる。ポリシリコン膜は、熱処理炉から取り出した半導体シリコンウェーハ3をCVD(Chemical Vapor Deposition)装置に投入し、減圧下もしくは常圧下でモノシラン等の成長ガスを装置の反応容器内ヘ導入することにより成長させることができる。そして、フォトリソグラフィ技術とエッチング技術を用いて絶縁膜2上のポリシリコン膜を島状に形成し、ポリシリコン電極4として所望の位置に配置する。   Then, when evaluating the TDDB characteristics of the insulating film 2 formed according to the present invention using the insulating electric field strength measuring device 5 of FIG. 1, a polysilicon film serving as an electrode is first grown on the insulating film 2. The polysilicon film is grown by introducing the semiconductor silicon wafer 3 taken out from the heat treatment furnace into a CVD (Chemical Vapor Deposition) apparatus and introducing a growth gas such as monosilane into the reaction vessel of the apparatus under reduced pressure or normal pressure. be able to. Then, a polysilicon film on the insulating film 2 is formed in an island shape by using a photolithography technique and an etching technique, and arranged as a polysilicon electrode 4 at a desired position.

複数のMOSキャパシタ型半導体素子1をその主表面に配置された半導体シリコンウェーハ3は、絶縁破壊電界強度測定装置5のステージ(図示せず)上に載置される。そして、MOSキャパシタ型半導体素子1のポリシリコン電極4に前後左右移動自在に支持されているプローブ7の下端を接触させる。プローブ7は印加電圧の大きさを変化させることができる可変電源6の一端子に接続されており、一方、可変電源6の他端子は絶縁破壊電界強度測定装置5のステージに接続されている。   A semiconductor silicon wafer 3 having a plurality of MOS capacitor type semiconductor elements 1 arranged on the main surface thereof is placed on a stage (not shown) of a dielectric breakdown field strength measuring device 5. Then, the lower end of the probe 7 supported so as to be movable back and forth and right and left is brought into contact with the polysilicon electrode 4 of the MOS capacitor type semiconductor element 1. The probe 7 is connected to one terminal of the variable power source 6 that can change the magnitude of the applied voltage, while the other terminal of the variable power source 6 is connected to the stage of the dielectric breakdown field strength measuring device 5.

前述したように、ステージには半導体シリコン基板1が載置されているので、半導体シリコン基板1の背面はポリシリコン電極4に対応する電極として作用する。また、可変電源6にはその印加電圧を測定する電圧計8が並列接続されており、プローブ7と可変電源6との間には電流計9が介装されている。   As described above, since the semiconductor silicon substrate 1 is placed on the stage, the back surface of the semiconductor silicon substrate 1 functions as an electrode corresponding to the polysilicon electrode 4. Further, a voltmeter 8 for measuring the applied voltage is connected in parallel to the variable power source 6, and an ammeter 9 is interposed between the probe 7 and the variable power source 6.

測定にあたっては、まず、プローブ7をポリシリコン電極4に接触させる。ここでは定電流TDDB測定について説明するが、可変電源6はオンとなり、図3(a)に示すような一定の電流(そのときの時間に対する電圧の推移は図3(b)に示す)を印加する。
図3は、定電流TDDB測定における電流、電圧の推移の一例を示す図であり、図3(a)は電流‐時間の関係であり、図3(b)は電圧‐時間の関係である。
絶縁破壊電界強度測定装置5内には閾値電圧が予め設定されており、絶縁破壊が起こると電圧変化が起こり絶縁破壊した時間を求めることが出来る。このような操作を所定の位置にあるMOSキャパシタ型半導体素子1全てに対して行なうことができる。
In the measurement, first, the probe 7 is brought into contact with the polysilicon electrode 4. Here, the constant current TDDB measurement will be described. The variable power source 6 is turned on, and a constant current as shown in FIG. 3A (voltage transition with respect to time is shown in FIG. To do.
FIG. 3 is a diagram showing an example of current and voltage transitions in the constant current TDDB measurement. FIG. 3A shows the current-time relationship, and FIG. 3B shows the voltage-time relationship.
A threshold voltage is set in advance in the dielectric breakdown electric field strength measuring device 5, and when dielectric breakdown occurs, a voltage change occurs and the time of dielectric breakdown can be obtained. Such an operation can be performed on all the MOS capacitor type semiconductor elements 1 in a predetermined position.

以下に本発明の実施例を挙げて、本発明をさらに詳細に説明するが、これらは本発明を限定するものではない。
<絶縁膜の形成>
(実施例)
ボロンをドープした直径200mmのP型半導体シリコンウェーハを準備し、鏡面研磨を施した(PW)。
そして、この鏡面研磨半導体シリコンウェーハを縦型ボートに載置して抵抗加熱熱処理炉に投入し、乾燥酸素雰囲気下(酸素分圧0.1atm:希釈窒素)、約800℃の温度でシリコン酸化膜が10nm以上とならないように約250分間の熱処理を施した。これにより、厚さ5nmのシリコン酸化膜が絶縁膜として前記ウェーハ主表面に形成された。
The present invention will be described in more detail below with reference to examples of the present invention, but these examples do not limit the present invention.
<Formation of insulating film>
(Example)
A P-type semiconductor silicon wafer having a diameter of 200 mm doped with boron was prepared and mirror-polished (PW).
Then, this mirror-polished semiconductor silicon wafer is placed on a vertical boat and placed in a resistance heating heat treatment furnace, and a silicon oxide film is formed at a temperature of about 800 ° C. in a dry oxygen atmosphere (oxygen partial pressure 0.1 atm: diluted nitrogen). Was heat-treated for about 250 minutes so that the thickness would not exceed 10 nm. As a result, a silicon oxide film having a thickness of 5 nm was formed as an insulating film on the main surface of the wafer.

(比較例)
比較のため、実施例と同じ条件の鏡面研磨半導体シリコンウェーハを準備した。そしてこのウェーハを縦型ボートに載置して抵抗加熱熱処理炉に投入し、乾燥酸素雰囲気のみ(100%酸素)の下、約800℃で32分間の熱処理をした。これにより、厚さ5nmのシリコン酸化膜が絶縁膜として前記ウェーハ主表面に形成された。
(Comparative example)
For comparison, a mirror-polished semiconductor silicon wafer having the same conditions as in the example was prepared. The wafer was placed on a vertical boat and placed in a resistance heating heat treatment furnace, and heat treatment was performed at about 800 ° C. for 32 minutes only in a dry oxygen atmosphere (100% oxygen). As a result, a silicon oxide film having a thickness of 5 nm was formed as an insulating film on the main surface of the wafer.

<絶縁膜評価用のMOSキャパシタ型半導体素子の作製>
次に、上記のように絶縁膜(ゲート酸化膜)の形成された実施例、比較例のウェーハをCVD炉に投入し、リンをドープしながらゲート酸化膜上にポリシリコン層を成長させた。この成長させたポリシリコン層厚さは約300nmで、抵抗値はシート抵抗にして約25Ω/sq.であった。
<Manufacture of MOS capacitor type semiconductor element for insulating film evaluation>
Next, the wafers of Examples and Comparative Examples in which the insulating film (gate oxide film) was formed as described above were put into a CVD furnace, and a polysilicon layer was grown on the gate oxide film while doping phosphorus. The grown polysilicon layer has a thickness of about 300 nm and a resistance value of about 25 Ω / sq. Met.

続いて実施例と比較例のそれぞれのウェーハに、フォトリソグラフィ技術を用いたパターンニングとエッチングによるポリシリコン層除去を行い、ポリシリコン層を電極としたMOSキャパシタを半導体シリコンウェーハ面内に100個ずつ作製した。なお、フォトリソグラフィ後のポリシリコンエッチングは、フッ硝酸によるウエットエッチングで行った。   Subsequently, the polysilicon layer is removed by patterning and etching using the photolithographic technique on each of the wafers of the example and the comparative example, and 100 MOS capacitors each having the polysilicon layer as an electrode are provided on the surface of the semiconductor silicon wafer. Produced. Note that the polysilicon etching after photolithography was performed by wet etching with hydrofluoric acid.

最後に、半導体シリコンウェーハ背面に形成されているシリコン酸化膜を除去するために、該半導体シリコンウェーハ主表面にレジストを塗布し、希フッ酸によるウエットエッチングを行って該ウェーハ背面のシリコン酸化膜を除去した。
そして、実施例、比較例のそれぞれにより形成された絶縁膜(ゲート酸化膜)を評価するためのMOSキャパシタ型半導体素子(サンプル)を作製した。
Finally, in order to remove the silicon oxide film formed on the back surface of the semiconductor silicon wafer, a resist is applied to the main surface of the semiconductor silicon wafer, and wet etching with dilute hydrofluoric acid is performed to remove the silicon oxide film on the back surface of the wafer. Removed.
Then, a MOS capacitor type semiconductor element (sample) for evaluating the insulating film (gate oxide film) formed in each of the example and the comparative example was manufactured.

<絶縁膜の評価1>
前記方法により作製された実施例、比較例のそれぞれのサンプルに対し、一定電流をゲート酸化膜が破壊するまで印加する定電流TDDB法を用いて、ゲート酸化膜に電界ストレスを印加した。印加した電流ストレスは0.001A/cmであり測定温度は測定時間短縮もあり100℃とした。測定には、フルオートプローバに接続したテスタを用いた。このとき、サンプルの電極面積は4mmであった。
<Evaluation 1 of insulating film>
Electric field stress was applied to the gate oxide film using the constant current TDDB method, in which a constant current was applied until the gate oxide film was destroyed, for each of the samples of Examples and Comparative Examples manufactured by the above method. The applied current stress was 0.001 A / cm 2 , and the measurement temperature was 100 ° C. due to the shortening of the measurement time. For the measurement, a tester connected to a full auto prober was used. At this time, the electrode area of the sample was 4 mm 2 .

測定結果を絶縁膜の寿命を示すワイブルプロットとして図4に示す。
図4は、TDDB評価結果のワイブルプロットを示す図である。
この図4は上記TDDB法を用いた測定により得られた累積不良指数と電荷量Qbdの関係であり、累積不良指数の数値1は累積不良80%を示している。また、電荷量Qbdの値は、定電流でTDDB測定を行っており、J×t=Qの関係から、そのまま絶縁破壊までの時間と見ることができる。すなわち、同じ累積不良指数を見た場合、電荷量Qbdの値が大きいほど寿命の長い絶縁膜であると見ることができる。
The measurement results are shown in FIG. 4 as a Weibull plot showing the lifetime of the insulating film.
FIG. 4 is a diagram showing a Weibull plot of the TDDB evaluation result.
FIG. 4 shows the relationship between the cumulative defect index and the charge amount Q bd obtained by the measurement using the TDDB method, and the numerical value 1 of the cumulative defect index indicates 80% of cumulative defects. The value of the charge amount Q bd is measured by TDDB at a constant current, and can be regarded as the time until dielectric breakdown as it is from the relationship of J × t = Q. That is, when the same cumulative defect index is seen, it can be regarded that the insulating film has a longer life as the value of the charge amount Q bd is larger.

上記実施例、比較例のサンプルについて図4を比較すると、窒素にて希釈した酸素雰囲気を使用して絶縁膜の形成を行なった実施例(実線)は、100%酸素雰囲気にて絶縁膜の形成を行なった比較例(点線)より、真性領域でのQbdが改善されている。これは、本発明のように窒素で酸素を希釈したことにより、シリコン酸化膜の膜質及びシリコン酸化膜/シリコン界面が改善されたことによるものである。 When comparing FIG. 4 with respect to the samples of the above-described examples and comparative examples, the example in which the insulating film was formed using the oxygen atmosphere diluted with nitrogen (solid line) is the formation of the insulating film in the 100% oxygen atmosphere. Q bd in the intrinsic region is improved compared to the comparative example (dotted line) in which is performed. This is because the film quality of the silicon oxide film and the silicon oxide film / silicon interface are improved by diluting oxygen with nitrogen as in the present invention.

<絶縁膜の評価2>
また、酸化温度800℃において種々の酸素分圧条件下で、絶縁膜に対するQbdへの影響を調べた。その結果を図5に示す。
図5は、累積不良指数1(累積不良80%)のときの電荷量Qbd値と酸素分圧の関係を示す図である。
この図5より、酸素分圧が0.5atm以下であれば窒素による効果を特に期待することができることが分かる。
尚、酸素分圧が0.1atmのときは上記実施例を示しており、酸素分圧が1atmのときは窒素で希釈しない100%酸素のみの上記比較例を示している。
<Evaluation 2 of insulating film>
In addition, the influence on Q bd on the insulating film was examined under various oxygen partial pressure conditions at an oxidation temperature of 800 ° C. The result is shown in FIG.
FIG. 5 is a graph showing the relationship between the charge amount Q bd value and the oxygen partial pressure when the cumulative failure index is 1 (cumulative failure is 80%).
From FIG. 5, it can be seen that the effect of nitrogen can be particularly expected if the oxygen partial pressure is 0.5 atm or less.
When the oxygen partial pressure is 0.1 atm, the above example is shown. When the oxygen partial pressure is 1 atm, the above comparative example of only 100% oxygen not diluted with nitrogen is shown.

<絶縁膜の評価3>
さらに、実施例、比較例で作製したサンプルと同様のものを用意し、それぞれのシリコン酸化膜直下のシリコン層の結晶乱れをIn−Plane X線回折により評価した。この評価は、リガク社製のIn−Plane X線回折装置を使用した。その結果を図2に示す。
図2は、シリコン酸化膜直下のシリコン層結晶性乱れをロッキングカーブの半値幅で示した図である。
<Evaluation of insulation film 3>
Furthermore, samples similar to those prepared in Examples and Comparative Examples were prepared, and crystal disorder of the silicon layer immediately below each silicon oxide film was evaluated by In-Plane X-ray diffraction. For this evaluation, an In-Plane X-ray diffractometer manufactured by Rigaku Corporation was used. The result is shown in FIG.
FIG. 2 is a diagram showing the crystallinity disorder of the silicon layer immediately below the silicon oxide film as a full width at half maximum of the rocking curve.

この格子乱れは、格子面傾斜と格子歪み(格子間隔の変化)の2つの成分からなっている。本結果より、図2を参照すれば、窒素で希釈した酸素を雰囲気ガスとして使用した実施例(図2真ん中の棒グラフ参照)の方が、100%酸素雰囲気を使用した比較例(図2一番左の棒グラフ参照)より格子乱れが小さいことが分かる。
また、比較例のように100%乾燥酸素雰囲気下で5nmの酸化膜形成した後にさらに920℃、窒素雰囲気下でアニールを行なってみたが、格子乱れの回復は起こらなかった(図2一番右の棒グラフ参照)。この100%酸素で酸化後窒素雰囲気下でアニールしても格子乱れの回復が起こらなかったのは、すでにSiOネットワークが形成されたあとであるためだと考えられる。
This lattice disturbance consists of two components: lattice plane inclination and lattice distortion (change in lattice spacing). From this result, referring to FIG. 2, the example using oxygen diluted with nitrogen as the atmospheric gas (see the bar graph in the middle of FIG. 2) is the comparative example using the 100% oxygen atmosphere (first in FIG. 2). It can be seen that the lattice disturbance is smaller than the left bar graph.
In addition, as in the comparative example, after forming a 5 nm oxide film in a 100% dry oxygen atmosphere, annealing was further performed in a nitrogen atmosphere at 920 ° C., but no recovery of lattice disturbance occurred (rightmost in FIG. 2). See bar chart). It is considered that the recovery of the lattice disorder did not occur even after annealing in a nitrogen atmosphere after oxidation with 100% oxygen because the SiO 2 network was already formed.

尚、本発明は上記実施形態に限定されるものではない。上記実施形態は単なる例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的思想に包含される。   The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has the same configuration as that of the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical idea of the invention.

本発明に係る方法により形成された絶縁膜を絶縁電界強度測定装置により評価する構成を示す図である。It is a figure which shows the structure which evaluates the insulating film formed by the method concerning this invention with an insulation electric field strength measuring apparatus. シリコン酸化膜直下のシリコン層結晶性乱れをロッキングカーブの半値幅で示した図である。It is the figure which showed the silicon layer crystal disorder right under a silicon oxide film by the half value width of the rocking curve. 定電流TDDB測定における電流、電圧の推移の一例を示す図であり、(a)は電流‐時間の関係、(b)は電圧‐時間の関係である。It is a figure which shows an example of transition of the electric current in the constant current TDDB measurement, (a) is a current-time relationship, (b) is a voltage-time relationship. TDDB評価結果のワイブルプロットを示す図である。It is a figure which shows the Weibull plot of a TDDB evaluation result. 酸素分圧とQbd値の関係を示す図である。It is a figure which shows the relationship between oxygen partial pressure and Qbd value.

符号の説明Explanation of symbols

1…MOSキャパシタ型半導体素子、 2…絶縁膜、
3…半導体シリコンウェーハ、 4…ポリシリコン電極、
5…絶縁破壊電界強度測定装置、 6…可変電源、 7…プローブ、
8…電圧計、 9…電流計。
DESCRIPTION OF SYMBOLS 1 ... MOS capacitor type semiconductor element, 2 ... Insulating film,
3 ... Semiconductor silicon wafer, 4 ... Polysilicon electrode,
5 ... Dielectric breakdown field strength measuring device, 6 ... Variable power supply, 7 ... Probe,
8 ... Voltmeter, 9 ... Ammeter.

Claims (1)

シリコンウェーハを雰囲気ガス中で熱処理することにより絶縁膜を形成する絶縁膜の形成方法において、
前記雰囲気ガスは窒素で希釈した酸素を使用し、かつ、全圧1atmのうち、酸素の分圧を0.5〜0.01atmとし、前記熱処理は、前記雰囲気ガスの下、抵抗加熱炉を使用して700〜900℃の温度で前記シリコンウェーハに熱処理を施し、
前記絶縁膜として10nm以下の膜厚のシリコン酸化膜を形成することを特徴とする絶縁膜の形成方法。
In a method for forming an insulating film, in which an insulating film is formed by heat-treating a silicon wafer in an atmospheric gas,
The atmosphere gas uses oxygen diluted with nitrogen, and the partial pressure of oxygen is 0.5 to 0.01 atm out of a total pressure of 1 atm. The heat treatment uses a resistance heating furnace under the atmosphere gas. And heat-treating the silicon wafer at a temperature of 700 to 900 ° C.,
A method of forming an insulating film, comprising forming a silicon oxide film having a thickness of 10 nm or less as the insulating film.
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