JP2010034312A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is less likely to malfunction with respect to high-frequency noise from the outside, and to provide its manufacturing method. <P>SOLUTION: This semiconductor device comprises: a p-type base layer 12b disposed on an n-type collector layer 11; an n-type emitter layer 13b disposed on the p-type base layer 12b; an n-type base contact layer 21 disposed so as to surround the p-type base layer 12b on the p-type base layer 12b; a p-type anode layer 12c disposed apart from the p-type base layer 12b on the n-type collector layer 11; an emitter electrode 16c connected to the n-type emitter layer 13b; a base electrode 16a, connected to the p-type base layer 12b and the n-type base contact layer 21; an anode electrode 16b, connected to the p-type anode layer 12c and connected in common to the emitter electrode 16c; a first resistor R1 connected between the emitter electrode 16c and the base electrode 16a; and a second resistor R2 connected to the base electrode 16a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device that is less likely to malfunction due to external high frequency noise and a method for manufacturing the same.

  As a semiconductor device capable of suppressing power breakdown, a base electrode is connected to the base region in the base contact region set on the surface of the base region, and has the same conductivity type as that of the emitter region below the boundary of the base contact region. A semiconductor device having a universal diode structure in which an n-type region is formed so as to surround a base contact region is disclosed (for example, refer to Patent Document 1). In the semiconductor device disclosed in Patent Document 1, a pn parasitic diode is formed by a p-type base region and an n-type region below the boundary portion of the base contact region.

The semiconductor device disclosed in Patent Document 1 has a problem in that it tends to malfunction due to high-frequency noise from the outside due to external radio wave radiation such as radio.
JP 2001-85443 A (page 3, FIG. 1)

  An object of the present invention is to provide a semiconductor device that is less likely to malfunction due to external high frequency noise and a method for manufacturing the same.

  According to one aspect of the present invention for achieving the above object, a transistor, a diode connected in antiparallel between main electrodes of the transistor, an anode of the diode, a common connection terminal of the emitter of the transistor, and the A semiconductor device is provided that includes a first resistor connected between a control electrode of a transistor and a second resistor connected to the control electrode of the transistor.

  According to another aspect of the present invention, a collector layer having a first conductivity type, a base layer having a second conductivity type disposed on the collector layer, and a first conductivity type disposed on the base layer. An emitter layer having a first conductivity type, spaced apart from the emitter layer and disposed on the base layer so as to surround the base layer; and the base layer on the collector layer An anode layer having a second conductivity type, spaced apart, an emitter electrode connected to the emitter layer, a base electrode connected to the base layer and the base contact layer, and connected to the collector layer A collector electrode; an anode electrode connected to the anode layer and commonly connected to the emitter electrode; a first resistor connected between the emitter electrode and the base electrode; The semiconductor device is provided and a second resistor connected over the source electrode.

  According to another aspect of the present invention, a step of forming a collector layer having a first conductivity type, a step of forming a base layer having a second conductivity type on the collector layer, a first layer on the base layer, Forming an emitter layer having one conductivity type; and forming a base contact layer having a first conductivity type on the base layer so as to surround the base layer and spaced apart from the emitter layer. A step of forming an anode layer having a second conductivity type on the collector layer and spaced apart from the base layer; a step of forming an emitter electrode on the emitter layer; and on the base layer and the base contact layer Forming a base electrode, forming an anode electrode commonly connected to the emitter electrode on the anode layer, and forming a first resistor between the emitter electrode and the base electrode And method of manufacturing a semiconductor device and a step of forming a second resistor connected to the base electrode.

  According to the present invention, it is possible to provide a semiconductor device that is less likely to malfunction due to external high-frequency noise and a method for manufacturing the same.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
As shown in FIG. 1, the circuit configuration of the semiconductor device according to the first embodiment of the present invention includes a bipolar transistor Q1, a diode D connected in antiparallel between the collector and emitter of the bipolar transistor Q1, and a diode A first resistor R1 connected between the anode of D and the emitter-anode common connection terminal EA of the emitter of the bipolar transistor Q1 and the base contact terminal BE of the bipolar transistor Q1, and the base contact terminal BE and the base terminal of the bipolar transistor Q1 And a second resistor R2 connected to B.

  The bipolar transistor Q1, the diode D, the first resistor R1, and the second resistor R2 may be integrated.

  The first resistor R1 and the second resistor R2 may be formed of polysilicon.

  The anode of the diode D and the emitter-anode common connection terminal EA of the emitter of the bipolar transistor Q1 are set to the ground potential, and the noise current induced in the collector of the bipolar transistor Q1 is caused by a capacitor formed between the anode and cathode of the diode D. Therefore, the semiconductor device according to the first embodiment is excellent in noise resistance.

  The cross-sectional structure corresponding to FIG. 1 of the semiconductor device according to the first embodiment is schematically represented as shown in FIG.

  As shown in FIG. 2, the semiconductor device according to the first embodiment includes an n-type collector layer 11, a p-type base layer 12b disposed on the n-type collector layer 11, and a p-type base layer 12b. An n-type emitter layer 13b, an n-type base contact layer 21 which is spaced apart from the n-type emitter layer 13b and surrounds the p-type base layer 12b on the p-type base layer 12b; A p-type anode layer 12c disposed on the collector layer 11 apart from the p-type base layer 12b, an emitter electrode 16c connected to the n-type emitter layer 13b, the p-type base layer 12b and the n-type base contact layer 21 A base electrode 16a connected to the p-type anode layer 12c, an anode electrode 16b connected in common with the emitter electrode 16c, and between the emitter electrode 16c and the base electrode 16a. It includes a first resistor R1 which is continued, and a second resistor R2 connected to the base electrode 16a.

The n-type collector layer 11 may be connected to the collector terminal C through a high impurity density n ⁺ -type collector layer 20 formed on the back surface of the n-type collector layer 11.

  The first resistor R1 may be formed of polysilicon 15 formed via the first insulating layer 17 disposed on the p-type anode layer 12c.

  The second resistor R2 may be formed of polysilicon 15 formed via the first insulating layer 17 disposed on the n-type collector layer 11.

A schematic cross-sectional structure of the bipolar transistor portion of the semiconductor device according to the first embodiment is expressed as shown in FIG. As shown in FIG. 3, a parasitic capacitance C _ob is formed between the base and collector of the bipolar transistor, and a collector series resistance R _C is formed in the n-type collector layer 11. Further, as shown in FIG. 3, the p-type base layer 12b and the n-type base contact layer 21 include a series resistance R _{B of} the p-type base layer 12b sandwiched between the n-type base contact layer 21 and the n-type base contact layer 21. A junction capacitance C _B between the base contact layer 21 and the p-type base layer 12b is formed. The series resistor R _B and the junction capacitor C _B are connected in parallel as shown in FIG.

  An equivalent circuit configuration of the bipolar transistor portion of the semiconductor device according to the first embodiment corresponding to FIG. 3 is expressed as shown in FIG.

In the equivalent circuit shown in FIG. 4, to connect the output resistance R _O on the collector side, if the externally to the collector of the bipolar transistor high-frequency noise voltage Vn is applied, some branches as a high-frequency noise voltage Vni to the input side, the remaining components are applied as high-frequency noise voltage Vnb to the base contact pin bE of the bipolar transistor through the parasitic capacitance C _ob. The high frequency noise voltage Vnb is absorbed by the ground potential. At the same time, the amplified high frequency noise current inc is conducted between the collector and the emitter. Cc represents the collector-emitter capacitance of the bipolar transistor. The high frequency noise current inc is reduced by increasing the collector-emitter capacitance C _c of the bipolar transistor.

The equivalent circuit configuration of the semiconductor device according to the first embodiment is expressed as shown in FIG. As shown in FIG. 1, the semiconductor device according to the first embodiment includes a diode D connected in antiparallel between the collector and emitter of the bipolar transistor Q1, an emitter-anode common connection terminal EA, and a bipolar transistor Q1. 4 includes a first resistor R1 connected between the base contact terminal BE and a second resistor R2 connected between the base contact terminal BE and the base terminal B of the bipolar transistor Q1. By combining with the equivalent circuit of the bipolar transistor portion, the equivalent circuit configuration of FIG. 5 can be obtained. A parasitic capacitance Ci _L between the base and emitter of the bipolar transistor Q1 also exists between the base contact terminal BE of the bipolar transistor Q1 and the emitter-anode common connection terminal EA, and is shown by a dotted line in FIG.

  The semiconductor device according to the first embodiment has a performance that is less likely to malfunction even with high-frequency noise of about 1 MHz to 200 MHz, for example. The current gain of the bipolar transistor Q1 is, for example, about 100 to 600, and a collector current of, for example, about 0.1 to 0.3 A is conducted between the collector and the emitter. The element size in which the bipolar transistor Q1, the diode D, the first resistor R1, and the second resistor R2 are integrated is, for example, about 0.37 mm square, 0.5 mm square, 0.7 mm square, 1.5 mm × 0.7 mm. And is set according to the current capacity.

For example, even when collector current noise of about 100 mA to 200 mA is applied as external high-frequency noise, such a disturbance is absorbed in the diode D, and a performance that prevents malfunction is obtained. .

In the semiconductor device according to the first embodiment, the capacitance C _c between the collector and the emitter can be increased by connecting the diode D in reverse parallel between the collector and the emitter of the bipolar transistor Q1, so that the external The performance that it is hard to malfunction by the high frequency noise from is obtained.

(Production method)
FIG. 6 shows diffusion patterns of the p-type outer peripheral layer 12a, the p-type base layer 12b, and the p-type anode layer 12c in the schematic planar pattern configuration showing one step of the method of manufacturing the semiconductor device according to the first embodiment. Represented as shown.

  The diffusion patterns of the n-type outer peripheral layer 13a and the n-type emitter layer 13b are expressed as shown in FIG.

  In a schematic planar pattern configuration showing a plurality of steps of the method of manufacturing a semiconductor device according to the first embodiment, contact regions 14a, 14b and 14c, a base electrode 16a, an anode electrode 16b and an emitter electrode 16c, and a polysilicon resistor 15a The plane patterns of (R1) and 15b (R2) are expressed as shown in FIG.

  The planar pattern of the openings 19a, 19b and 19c of the second insulating layer is expressed as shown in FIG.

  Further, the manufacturing process of the bipolar transistor part of the semiconductor device according to the first embodiment is expressed as shown in FIGS. 11 to 13 and FIG. 10, for example, and the manufacturing process of the diode part is shown in FIGS. It is expressed as shown in FIGS.

  The semiconductor device manufacturing method according to the first embodiment includes a step of forming an n-type collector layer 11 and a p-type base layer 12b on the n-type collector layer 11, as shown in FIGS. A step of forming an n-type emitter layer 13b on the p-type base layer 12b, and surrounding the p-type base layer 12b on the p-type base layer 12b at a distance from the n-type emitter layer 13b. A step of forming an n-type base contact layer 21, a step of forming a p-type anode layer 12c on the n-type collector layer 11 apart from the p-type base layer 12b, and an emitter on the n-type emitter layer 13b. A step of forming the electrode 16c, a step of forming the base electrode 16a on the p-type base layer 12b and the n-type base contact layer 21, and an anode commonly connected to the emitter electrode 16c on the p-type anode layer 12c. And a step of forming an electrode 16b, forming a first resistor R1 between the emitter electrode 16c and the base electrode 16a, and forming a second resistor R2 connected to the base electrode 16a.

  The step of forming the p-type base layer 12b and the step of forming the p-type anode layer 12c may be simultaneous steps.

  The step of forming n-type emitter layer 13b and the step of forming n-type base contact layer 21 may be simultaneous steps.

  The step of forming the first resistor R1 may include a step of forming polysilicon on the first insulating layer 17 formed on the p-type anode layer 12c.

  The step of forming the second resistor R2 may include a step of forming polysilicon on the first insulating layer 17 formed on the n-type collector layer 11.

-Bipolar transistor manufacturing method-
A schematic cross-sectional structure of the bipolar transistor portion of the semiconductor device according to the first embodiment is expressed as shown in FIG. FIG. 10 corresponds to a schematic cross-sectional structure taken along line II in the planar pattern configuration of FIGS. Below, the manufacturing method for forming the element structure of FIG. 10 is demonstrated.

(A) First, as shown in FIG. 11, a p-type outer peripheral layer 12 a and a p-type base layer 12 b are formed in the n-type collector layer 11. As the p-type impurity, for example, boron (B), aluminum (Al), gallium (Ga), or the like can be applied. Thermal diffusion, ion implantation, or the like can be applied to the formation process of the p-type outer peripheral layer 12a and the p-type base layer 12b. The diffusion depth of the p-type outer peripheral layer 12a and the p-type base layer 12b is, for example, about 3 μm. In the final process, the n-type collector layer 11 is thinned by back surface etching, and has a thickness of about several μm to several tens of μm, for example.

(B) Next, as shown in FIG. 12, an n-type outer peripheral layer 13a, an n-type emitter layer 13b, and an n-type base contact layer 21 are formed. As the n-type impurity, for example, phosphorus (P), arsenic (As), antimony (Sb), or the like can be applied. Thermal diffusion, ion implantation, or the like can be applied to the formation process of the n-type outer peripheral layer 13a, the n-type emitter layer 13b, and the n-type base contact layer 21. The diffusion depth of the n-type emitter layer 13b and the n-type base contact layer 21 is, for example, about 1 μm.

(C) Next, as shown in FIG. 13, after the first insulating layer 17 is formed, the first insulating layer 17 on the n-type outer peripheral layer 13a is removed by photolithography and patterning processes, and the contact region 14a and Open a window to form 14b. A silicon oxide film or the like can be applied to the first insulating layer 17. In addition, as a formation method of the 1st insulating layer 17, a thermal oxidation method or a chemical vapor deposition (CVD: Chemical Vapor Deposition) method etc. are applicable. Here, the dimension widths of the contact regions 14a and 14b are, for example, about 16 μm and 10 μm, respectively.

(D) Further, as shown in FIG. 13, after forming electrodes on the entire surface, a base electrode 16a and an emitter electrode 16c are formed on the contact regions 14a and 14b, respectively, by photolithography and patterning processes. In forming the electrode, a vacuum deposition method, a sputtering method, or the like can be applied. The material of the electrode is aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), or these A composite film, an electrode multilayer film, or the like can be applied. Further, a silicide film of these metals can also be applied.

(E) Next, as shown in FIG. 10, after forming the second insulating layer 18 on the entire surface, the opening 19a of the second insulating layer is formed by photolithography and patterning processes. For example, a nitride film can be used as the material of the second insulating layer 18. In FIG. 10, reference numeral 18a denotes a portion where the base electrode 16a is removed from the outer peripheral portion. Reference numeral 18b denotes openings of the base electrode 16a and the emitter electrode 16c. Here, the dimension width of the removed portion 18a of the base electrode 16a is, for example, about 35 to 40 μm, and the dimension width of the opening 18b of the base electrode 16a and the emitter electrode 16c is, for example, about 6 μm. . The dimension width of the opening 19a of the second insulating layer is, for example, about 25 μm.

―Diode manufacturing method―
A schematic cross-sectional structure of the diode portion of the semiconductor device according to the first embodiment is expressed as shown in FIG. FIG. 14 corresponds to a schematic cross-sectional structure taken along line II-II in the planar pattern configuration of FIGS. A manufacturing method for forming the element structure shown in FIG. 14 will be described below.

(A) First, as shown in FIG. 15, the p-type outer peripheral layer 12 a and the p-type anode layer 12 c are formed in the n-type collector layer 11. As the p-type impurity, for example, boron (B), aluminum (Al), gallium (Ga), or the like can be applied. Thermal diffusion, ion implantation, or the like can be applied to the formation process of the p-type outer peripheral layer 12a and the p-type anode layer 12c. The diffusion depth of the p-type anode layer 12c is also about 3 μm, for example.

(B) Further, as shown in FIG. 15, an n-type outer peripheral layer 13a is formed. As the n-type impurity, for example, phosphorus (P), arsenic (As), antimony (Sb), or the like can be applied. Thermal diffusion, ion implantation, or the like can be applied to the formation process of the n-type outer peripheral layer 13a.

(C) Next, as shown in FIG. 16, after forming the first insulating layer 17, the first insulating layer 17 on the n-type outer peripheral layer 13a is removed by photolithography and patterning processes, and the contact region 14c is formed. Open a window to form. A silicon oxide film or the like can be applied to the first insulating layer 17. As a method for forming the first insulating layer 17, a thermal oxidation method, a CVD method, or the like can be applied. Here, the dimension width of the contact region 14c is, for example, about 100 μm to 150 μm.

(D) Further, as shown in FIG. 16, after the polysilicon 15 is formed on the entire surface, a polysilicon resistor 15a (R1) is formed on the first insulating layer 17 by photolithography and patterning processes. Note that a CVD method, a sputtering method, a spin coating method of coating type polysilicon, or the like can be applied to the polysilicon forming step. When forming the polysilicon resistor 15a, a predetermined sheet resistance can be obtained by doping non-doped polysilicon. Alternatively, doped polysilicon can be applied in order to realize a predetermined sheet resistance in advance.

(E) Next, as shown in FIG. 17, after an electrode is formed on the entire surface, an anode electrode 16b is formed on the contact region 14c by photolithography and patterning processes. Further, the emitter electrode 16 c is patterned on the first insulating layer 17. In forming the electrode, a vacuum deposition method, a sputtering method, or the like can be applied. The material of the electrode is aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), or these A composite film, a multilayer film, or the like can be applied. Further, a silicide film of these metals can also be applied.

(E) Next, as shown in FIG. 14, after forming the second insulating layer 18 on the entire surface, the openings 19b, 19c, 19d of the second insulating layer are formed by photolithography and patterning processes. As a material for the second insulating layer 18, for example, a nitride film, an oxynitride film, an alumina film, a hafnium oxide film, a zirconium oxide film, or the like can be used.

In FIG. 14, 19b indicates an opening of the second insulating layer for forming a bonding region for the anode electrode 16b, and 19c indicates an opening of the second insulating layer for forming a bonding region for the emitter electrode 16c. 19d shows the opening part of the 2nd insulating layer in an outer peripheral part. The dimension width of the opening 19b of the second insulating layer is, for example, about 40 to 80 μm, and the dimension width of the opening 19c of the second insulating layer is, for example, about 40 to 80 μm. The dimension width of the opening 19d is, for example, about 50 to 80 μm.

(Modification)
A schematic planar pattern configuration showing one step of the method of manufacturing the semiconductor device according to the modification of the first embodiment is expressed as shown in FIG. Further, in FIG. 18, a schematic cross-sectional structure corresponding to the diode portion along the line II-II is expressed as shown in FIG.

  The semiconductor device according to the modification of the first embodiment is characterized in that the p-type anode layer 12c includes an opening 11a. Since other configurations are the same as those of the first embodiment, a duplicate description is omitted. The structure in which the p-type anode layer 12c includes the opening 11a can be formed simultaneously with the process of forming the p-type anode layer 12c, only by changing the mask.

  In the semiconductor device according to the modification of the first embodiment, since the p-type anode layer 12c includes the opening 11a, the junction capacitance between the p-type anode layer 12c and the n-type collector layer 11 is reduced to the opening. It can be increased by an area corresponding to the area of 11a. For this reason, compared with the semiconductor device according to the first embodiment shown in FIG. 14, the effect of absorbing external high frequency noise by the junction capacitance between the p-type anode layer 12c and the n-type collector layer 11 is further enhanced. Can do.

  According to the semiconductor device according to the modification of the first embodiment, it is possible to provide a semiconductor device that is less likely to malfunction due to external high-frequency noise and a method for manufacturing the same.

[Other embodiments]
As described above, the present invention has been described with reference to the first embodiment and its modifications. However, the discussion and the drawings that form a part of this disclosure are illustrative and are intended to limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, a semiconductor device having a structure in which n-type and p-type conductivity types are reversed may be formed. In the above embodiment, the semiconductor device having one bipolar transistor has been described as an example. However, the present invention can be applied to a semiconductor device having a plurality of bipolar transistors. Further, the present invention can be applied to a semiconductor device having a pn junction other than a bipolar transistor such as a thyristor, a triac, or a gate turn-off thyristor (GTO).

  As described above, the present invention includes various embodiments not described herein.

  Since the semiconductor device of the present invention is unlikely to malfunction due to high-frequency noise from the outside, it can be applied to a wide range of fields such as in-vehicle semiconductor devices.

1 is a circuit configuration diagram of a semiconductor device according to a first embodiment of the present invention. The typical cross-section figure corresponding to FIG. 1 of the semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a schematic cross-sectional structure diagram of a bipolar transistor portion of a semiconductor device according to a first embodiment of the present invention. The equivalent circuit block diagram of the bipolar transistor part of the semiconductor device which concerns on the 1st Embodiment of this invention corresponding to FIG. 1 is an equivalent circuit configuration diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a schematic planar pattern configuration diagram showing one process of the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic planar pattern configuration diagram showing one process of the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic planar pattern configuration diagram showing a plurality of steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a schematic planar pattern configuration diagram showing one process of the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 2 is a schematic cross-sectional structure diagram of a bipolar transistor portion taken along line II of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a schematic cross-sectional structure showing one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, corresponding to the bipolar transistor portion taken along line II in FIG. 6. FIG. 8 is a schematic cross-sectional structure showing one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, corresponding to a bipolar transistor portion taken along line II in FIG. 7. FIG. 9 is a schematic cross-sectional structure showing one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, corresponding to the bipolar transistor portion taken along line II in FIG. 8. The typical cross-section figure of the diode part which follows the II-II line of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 8 is a schematic cross-sectional structure showing one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and corresponds to a diode portion taken along line II-II in FIG. FIG. 9 is a schematic cross-sectional structure showing one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and corresponds to a diode portion taken along line II-II in FIG. 8. FIG. 10 is a schematic cross-sectional structure showing one step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and corresponds to a diode portion taken along line II-II in FIG. 9. The typical plane pattern block diagram which shows 1 process of the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. FIG. 19 is a schematic cross-sectional structure of a semiconductor device according to a modification of the first embodiment of the present invention, and corresponds to a diode portion taken along line II-II in FIG. 18.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... n-type semiconductor layer 11a ... Opening part 12a ... p-type outer periphery layer 12b ... p-type base layer 12c ... p-type anode layer 13a ... n-type outer periphery layer 13b ... n-type emitter layers 14a, 14b, 14c ... contact region 15 ... Polysilicon 15a ... Polysilicon resistor (R1)
15b: Polysilicon resistor (R2)
16a ... base electrode 16b ... anode electrode 16c ... emitter electrode 17 ... first insulating layer 18 ... second insulating layer 18a ... removed portion 18b of base electrode 16a ... openings 19a, 19b of base electrode 16a and emitter electrode 16c, 19c, 19d ... second insulating layer opening 20 ... n ⁺ -type collector layer 21 ... n-type base contact layer R1, R2 ... resistor EA ... emitter-anode common connection terminal BE ... base contact terminal B ... base terminal C ... collector Terminal D ... Diode Q1 ... Bipolar transistor

Claims (12)

A transistor,
A diode connected in antiparallel between the main electrodes of the transistor;
A first resistor connected between a common connection terminal of the anode of the diode, the emitter of the transistor, and a control electrode of the transistor;
A semiconductor device comprising: a second resistor connected to a control electrode of the transistor.   The semiconductor device according to claim 1, wherein the transistor, the diode, the first resistor, and the second resistor are integrated.   The semiconductor device according to claim 1, wherein the first resistor and the second resistor are made of polysilicon. A collector layer having a first conductivity type;
A base layer disposed on the collector layer and having a second conductivity type;
An emitter layer disposed on the base layer and having a first conductivity type;
A base contact layer having a first conductivity type, spaced apart from the emitter layer and disposed on the base layer so as to surround the base layer;
An anode layer disposed on the collector layer and spaced apart from the base layer and having a second conductivity type;
An emitter electrode connected to the emitter layer;
A base electrode connected to the base layer and the base contact layer;
An anode electrode connected to the anode layer and commonly connected to the emitter electrode;
A first resistor connected between the emitter electrode and the base electrode;
A semiconductor device comprising: a second resistor connected to the base electrode.   5. The semiconductor device according to claim 4, wherein the first resistor is made of polysilicon formed through an insulating layer disposed on the anode layer. 6.   The semiconductor device according to claim 4, wherein the second resistor is formed of polysilicon formed through an insulating layer disposed on the collector layer.   The semiconductor device according to claim 4, wherein the anode layer includes an opening. Forming a collector layer having a first conductivity type;
Forming a base layer having a second conductivity type on the collector layer;
Forming an emitter layer having a first conductivity type on the base layer;
Forming a base contact layer having a first conductivity type so as to surround the base layer on the base layer apart from the emitter layer;
Forming an anode layer having a second conductivity type apart from the base layer on the collector layer;
Forming an emitter electrode on the emitter layer;
Forming a base electrode on the base layer and the base contact layer;
Forming an anode electrode commonly connected to the emitter electrode on the anode layer;
Forming a first resistor between the emitter electrode and the base electrode;
Forming a second resistor connected to the base electrode. A method for manufacturing a semiconductor device, comprising:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the base layer and the step of forming the anode layer are simultaneous steps.   10. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the emitter layer and the step of forming the base contact layer are simultaneous steps.   11. The semiconductor device according to claim 8, wherein the step of forming the first resistor includes a step of forming polysilicon on an insulating layer formed on the anode layer. Manufacturing method.   12. The semiconductor device according to claim 8, wherein the step of forming the second resistor includes a step of forming polysilicon on an insulating layer formed on the collector layer. Manufacturing method.

Images