JP5282194B2 - Variable capacity device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable capacitance device having the reduced series resistance of a variable capacitance element and having an increased DC interrupting capacity even when an active region width is set to be large. <P>SOLUTION: The variable capacitance device is provided, wherein the variable capacitance element with a PN junction is formed by forming a first conductivity type low resistance layer 23 in first conductivity type semiconductor regions 21 and 22, and by successively laminating a first conductivity type diffusion region 26 and a second conductivity type diffusion region 27 in a region surrounded by field oxide films 25a provided on the surfaces of the semiconductor regions 21 and 22 located in accordance with and above the low resistance layer 23, and wherein a fixed capacitance element composed by successively laminating a lower electrode 29, an insulating film 30 and an upper electrode 31 through an insulating layer 28 on the variable capacitance element is formed, and wherein a gate capacitance element is configured by the second conductivity type diffusion region 27, and the insulating layer 28 and the lower electrode 29 laminated on it. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a variable capacitance device, and more particularly to a variable capacitance device mounted on a semiconductor integrated circuit.

  Conventionally, the fixed capacitor and variable capacitor are formed in different regions on the semiconductor substrate, resulting in inferior use efficiency of the area in the semiconductor substrate, and the lower electrode of the fixed capacitor and the semiconductor substrate In order to avoid the inconvenience that a parasitic capacitance is generated between them and the capacitance change rate is reduced, and the frequency variable width is reduced, the fixed capacitance element and the variable capacitance element are connected to the field oxide film on the semiconductor substrate. It has been proposed to form the same active region surrounded by the upper and lower layers.

Japanese Unexamined Patent Publication No. 2000-315915 (FIG. 1) JP 2000-323729 A (FIG. 3) Japanese Patent Laying-Open No. 2003-86692 (FIG. 2)

In the above improvement proposal, the fixed capacitor element is located on the variable capacitor element, and it is necessary to secure a wiring region and a contact region called a fringe area. It is set slightly smaller than the width. Therefore, unless the active region width is made as large as possible, the size of the upper electrode of the fixed capacitance element cannot be set to a sufficient size, resulting in a disadvantage that a desired capacitance value cannot be obtained. However, when the active region width is increased, there is a disadvantage that the series resistance of the variable capacitance element (for example, resistance between the active region and the P ⁺ -type diffusion region in Patent Document 3 and FIG. 2) increases. On the other hand, if the active region width is reduced in order to avoid this inconvenience, the wiring region and the contact region require a predetermined area regardless of the size of the active region width. There is a problem that the above inconvenience that the desired capacitance value cannot be obtained cannot be solved. It is an object of the present invention to provide a variable capacitance device that solves this problem.

  That is, in the variable capacitance device according to claim 1 of the present invention, a first conductive type low resistance layer is formed in the first conductive type semiconductor region, and the surface of the semiconductor region corresponding to above the low resistance layer is formed. A variable conductivity element having a PN junction is formed by sequentially laminating a first conductivity type diffusion region and a second conductivity type diffusion region in a region surrounded by a field oxide film provided on the substrate, and insulation is formed on the variable capacitance device. A fixed capacitance element is formed by sequentially laminating a lower electrode, an insulating film, and an upper electrode through layers, and the gate capacitance element is formed by the second conductive type diffusion region, the insulating layer laminated thereon, and the lower electrode. Is configured. By forming the low resistance layer, the series resistance of the variable capacitance element can be reduced even when the active region width is set large, and the gate capacitance element is interposed between the fixed capacitance element and the variable capacitance element. By providing them in an overlapping manner, the DC blocking capacity can be increased.

  In the above configuration, the variable capacitance element is positioned at the outer edge of the adjacent field oxide film, and the second first conductivity type diffusion region is formed so as to reach the low resistance layer from the surface of the semiconductor region. Reduction of the series resistance of the element can be further improved.

  Further, in each of the above configurations, the semiconductor region is configured by a semiconductor substrate and an epitaxial growth layer formed on the surface thereof, and the low resistance layer and the variable capacitance are provided by providing the upper portion of the low resistance layer and the variable capacitance element in the epitaxial growth layer. Impurity introduction at the time of forming an element can be performed by a high current ion implantation apparatus with high implantation efficiency.

  Still further, in each of the above-described structures, the variable capacitance element is located at the outer edge of the adjacent field oxide film, and a second second conductivity type diffusion region is formed on the surface of the semiconductor region, and this second second conductivity type diffusion region is formed. A third first conductivity type diffusion region is formed on the lower surface of the field oxide film so as to connect the variable capacitance element region to the second capacitance type diffusion region of the variable capacitance element, and the third first When the protective element is configured by the conductive type diffusion region and the second second conductive type diffusion region, the parasitic capacitance of the protective element itself is eliminated, and the parasitic capacitance applied from the protective element to the variable capacitive element is also eliminated, and thus the variable capacitance element is variable. The frequency characteristic of the capacity can be improved.

  According to the variable capacitance device of the present invention, by reducing the parasitic capacitance of the capacitive element, it is possible to prevent a decrease in the capacitance change rate and expand the frequency variable width. The series resistance of the element can be reduced, and the DC blocking capacity is increased by providing the gate capacitance element.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments when the present invention is applied to an oscillation circuit will be described with reference to the accompanying drawings. Here, FIG. 1 is a circuit diagram showing a basic configuration of an oscillation circuit, FIG. 2 is a sectional view showing a capacitive element structure, and FIGS. 3 to 8 are sectional views showing manufacturing steps of the capacitive element structure. First, the basic configuration of the circuit will be described with reference to FIG. The oscillation circuit 1 is provided with an externally attached crystal resonator 2, an amplification inverter 3 and its feedback resistor 4. On the output side of the inverter 3, an upper electrode which is a fixed capacitance element for cutting off DC (see FIG. 2 includes 31) and a lower electrode (29 in FIG. 2), and also includes an upper electrode (29 in FIG. 2) and a lower electrode (27 in FIG. 2), which are gate capacitance elements for DC blocking. The capacitor 6 is connected in series, and the cathode side of a PN junction diode 7 that is a variable capacitance element for controlling the oscillation frequency is connected to the capacitor 6. An external voltage VC for frequency control is applied to the cathode side (27 in FIG. 2) of the PN junction diode 7 via the load resistor 8, while the anode side (26 in FIG. 2) is grounded. .

  Further, on the input end side of the inverter 3, a capacitor 9 having an upper electrode and a lower electrode which are fixed capacitive elements for DC blocking, and an upper electrode and a lower electrode which are also gate capacitive elements for DC blocking are provided. The capacitors 10 and 10 are connected in parallel, and the capacitors 9 and 10 are connected to the cathode side of a PN junction diode 11 which is a variable capacitance element for controlling the oscillation frequency. An external voltage VC for frequency control is applied to the cathode side of the PN junction diode 11 via a load resistor 12, while the anode side is grounded.

Next, the capacitive element structure of the part surrounded by the broken line A in FIG. 1 will be described. As shown in FIG. 2, a P ⁻ type epitaxial growth layer 22 is formed on a P ⁻ type semiconductor substrate 21, and a P ⁺⁺ type low resistance layer 23 is provided so as to be embedded in the P ⁻ type epitaxial growth layer 22. The upper part of the P ⁺⁺ type low resistance layer 23 is located in the P ⁻ type epitaxial growth layer 22. The P ⁻ type epitaxial growth layer 22 is provided with a P ⁺⁺ type diffusion region 24 as a plug layer so as to be joined to the P ⁺⁺ type low resistance layer 23, and on the P ⁻ type epitaxial growth layer 22. Are provided with field oxide films 25a and 25b.

In the P ⁻ type epitaxial growth layer 22, which is an active region surrounded by the field oxide film 25 a, a variable composed of a PN junction diode (7 in FIG. 1) composed of a P ⁺ type diffusion region 26 and an N ⁺ type diffusion region 27. Capacitance elements are formed. On the N ⁺ -type diffusion region 27 of the PN junction diodes 26 and 27, an insulating film 28, a lower electrode 29, an insulating film 30, and an upper electrode 31 are sequentially stacked to form a capacitor (6 in FIG. 1). ) And a capacitor (5 in FIG. 1) which is a fixed capacitance element. The lower electrode of the capacitor which is the gate capacitance element is also used as the N ⁺ -type diffusion region 27 of the variable capacitance element, and the upper electrode is also used as the lower electrode 29 of the fixed capacitance element. The upper electrode 31 and the lower electrode 29 can be made of polysilicon, silicide material, refractory metal, or the like.

Subsequently, a manufacturing process of the above-described capacitive element structure will be described with reference to FIGS. First, as shown in FIG. 3, after an oxide film 32 is formed on the P ⁻ type semiconductor substrate 21, the oxide film 32 is etched to open a region where the low resistance layer is embedded.

Next, as shown in FIG. 4, a P ⁺⁺ type low resistance layer 23 is formed in the opening by an ion implantation method using a high current ion implantation apparatus, and the remaining oxide film 32 is removed. The high-concentration impurity introduction into the P ⁺⁺ type low resistance layer 23 may be performed near the surface of the P ⁻ type semiconductor substrate 21, so that the high acceleration used when performing in a deep position of the P ⁻ type semiconductor substrate 21. It is possible to efficiently perform ion implantation of 100 KeV or less using a high current ion implantation apparatus without using ion implantation of 1000 KeV or more using an implantation apparatus.

Next, as shown in FIG. 5, when a P ⁻ type epitaxial growth layer 22 is further laminated on the P ⁻ type semiconductor substrate 21 by an epitaxial method, the P ⁺⁺ ions of the P ⁺⁺ type low resistance layer 23 become P ⁻ type. By oozing out into the epitaxial growth layer 22, the upper part of the P ⁺⁺ type low resistance layer 23 is located in the P ⁻ type epitaxial growth layer 22. In this way, the P ⁺⁺ type low resistance layer 23 is buried with the P ⁻ type epitaxial growth layer 22.

Next, as shown in FIG. 6, a P ⁺⁺ type diffusion region 24 serving as a plug layer is provided in the P ⁻ type epitaxial growth layer 22 so as to be joined to the P ⁺⁺ type low resistance layer 23. The P ⁺⁺ type diffusion region 24 can be formed by a known means. For example, an oxide film (not shown) is formed on the surface of the P ⁻ type epitaxial growth layer 22, and this oxide film is etched. and exposing the region for forming a P ⁺⁺ type diffusion region 24, to form a P ⁺⁺ type diffusion region 24 in the opening portion by ion implantation, is to remove the remaining oxide film.

Next, as shown in FIG. 7, field oxide films 25 a and 25 b are provided on the P ⁻ -type epitaxial growth layer 22 by a known means.

Next, as shown in FIG. 8, impurities are introduced into the surface of the P ⁻ -type epitaxial growth layer 22 corresponding to the active region which is a portion surrounded by the field oxide film 25a by a known means, so that the variable capacitance element is formed. A certain P ⁺ -type diffusion region 26 and N ⁺ -type diffusion region 27 are sequentially formed. At this time, in order not to affect the variable characteristics of the variable capacitance element, the distance between the active region and the P ⁺⁺ type low resistance layer 23 and the P ⁺⁺ type diffusion region 24 is set larger than the maximum depletion layer. Specifically, the distance is preferably 3 μm or more.

  Next, an insulating film 28, a lower electrode 29, an insulating film 30, and an upper electrode 31 are sequentially stacked on the active region surrounded by the above-described field oxide film 25a by a known means, and the capacitance shown in FIG. It is an element structure.

  Next, an embodiment in which an NPN-type snapback transistor for protecting a breakdown voltage is provided as a protective element will be described. Since the basic configuration of the oscillation circuit is the same as that of the embodiment shown in FIG. 1, only the PN junction diode 7 as a variable capacitance element is shown in the circuit diagram shown in FIG. And description is abbreviate | omitted. As shown in FIG. 9, the collector terminal of the NPN type snapback transistor 13 is connected to the cathode of the PN junction diode 7, and the emitter terminal of the NPN type snapback transistor 13 is connected to the anode of the PN junction diode 7. Connected. Although not shown, the gate terminal and the emitter terminal of the NPN type snapback transistor 13 are grounded.

  Although not shown, the PN junction diode 11 shown in FIG. 1 is similarly provided with an NPN-type snapback transistor for protecting against breakdown voltage. That is, the collector terminal of the NPN type snapback transistor is connected to the cathode of the PN junction diode 11, while the emitter terminal of the NPN type snapback transistor is connected to the anode of the PN junction diode 11. The gate terminal and emitter terminal of the back transistor are grounded.

Next, the structure of the capacitive element and the NPN-type snapback transistor will be described with reference to FIG. 10. Since the capacitive element structure is the same as that of the above-described embodiment, the same reference numerals are assigned to the corresponding components. Detailed description is omitted. Under the field oxide film 25a on the side of the field oxide film 25b in the figure, a P ⁺ type diffusion region 32 is provided so as to be joined to the P ⁺ type diffusion region 26 and the N ⁺ type diffusion region 27 of the variable capacitance element. An N ⁺ type diffusion region 33 is provided between the oxide films 25a and 25b, and the N ⁺ type diffusion region 27 and 33 and the P ⁺ type diffusion region 32 form an NPN type snapback transistor (in FIG. 9). 13). That is, the N ⁺ type diffusion region 27 serves as both the collector of the NPN type snapback transistor and the cathode of the PN junction diode (7 in FIG. 9). The P ⁺ -type diffusion region 32 may be configured to be joined to only one of the P ⁺ -type diffusion region 26 and the N ⁺ -type diffusion region 27 of the variable capacitance element.

With conventionally provided a PN junction diode and the NPN snapback transistor independently of one another, and the N ⁺ -type diffusion region is a cathode of the PN junction diode, and an N ⁺ -type diffusion region is a collector of the NPN snapback transistor Since the connection is made, parasitic capacitance is generated in the N ⁺ diffusion region that is the collector of the NPN snapback transistor, and this parasitic capacitance is added to the PN junction diode. On the other hand, in the above-described embodiment, the N ⁺ type diffusion region that is the collector of the NPN type snapback transistor is also used as the cathode of the PN junction diode, and therefore the N ⁺ type diffusion region that is the collector of the NPN type snapback transistor. Therefore, there is an advantage that the parasitic capacitance is not added to the PN junction diode.

Note that the NPN snapback transistor 13 may be replaced with another protection element, and the protection element is not necessarily provided. Further, the P ⁺⁺ type low resistance layer 23 is only required to be formed in portions corresponding to the PN junction diodes 26 and 27 that are variable capacitance elements and the P ⁺⁺ type diffusion region 24 that is a plug layer. Further, in each of the above-described embodiments, the first conductivity type is P type and the second conductivity type is N type. However, the first conductivity type is N type and the second conductivity type is P type. It may be configured as.

FIG. 2 is a circuit diagram showing a basic configuration of an oscillation circuit with a crystal resonator attached externally. Sectional drawing which shows the capacitive element structure in the part enclosed with the chain line A of FIG. Sectional drawing which shows 1 process of the manufacturing process of capacitive element structure. Sectional drawing which similarly shows one process of the manufacturing process of a capacitive element structure. Sectional drawing which similarly shows one process of the manufacturing process of a capacitive element structure. Sectional drawing which similarly shows one process of the manufacturing process of a capacitive element structure. Sectional drawing which similarly shows one process of the manufacturing process of a capacitive element structure. Sectional drawing which similarly shows one process of the manufacturing process of a capacitive element structure. The circuit diagram which shows the variable capacitance element which provided the protection element. Sectional drawing which shows the capacitive element structure which provided the protective element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Oscillation circuit 2 Crystal oscillator 3 Inverter 5,9 Capacitor (fixed capacity element)
6,10 Capacitor (gate capacitance element)
7,11 PN junction diode (variable capacitance element)
13 NPN type snapback transistor 21 P ⁻ type semiconductor substrate 22 P ⁻ type epitaxial growth layer 23 P ⁺⁺ type low resistance layer 24 P ⁺⁺ type diffusion region 25a, 25b Field oxide film 26 P ⁺ type diffusion region 27 N ⁺ type diffusion Region 28, 30 Insulating film 29 Lower electrode 31 Upper electrode 32 P ⁺ type diffusion region 33 N ⁺ type diffusion region

Claims (4)

A first conductivity type low resistance layer is formed in the first conductivity type semiconductor region, and a region surrounded by a field oxide film provided on the surface of the semiconductor region corresponding to the upper side of the low resistance layer is formed in a first region. A conductive type diffusion region and a second conductive type diffusion region are sequentially stacked to form a variable capacitance element having a PN junction, and a lower electrode, an insulating film, and an upper electrode are formed on the variable capacitance element via an insulating layer. A variable capacitance device, wherein a fixed capacitance element is formed by sequentially laminating layers, and a gate capacitance element is constituted by the second conductivity type diffusion region, an insulating layer laminated thereon, and a lower electrode.   2. The variable capacitance element is located at an outer edge of an adjacent field oxide film, and the second first conductivity type diffusion region is formed so as to reach the low resistance layer from the surface of the semiconductor region. Variable capacity device.   3. The variable according to claim 1, wherein the semiconductor region is constituted by a semiconductor substrate and an epitaxial growth layer formed on the surface thereof, and an upper portion of the low resistance layer and a variable capacitance element are provided in the epitaxial growth layer. Capacity device.   A variable capacitance element is positioned on the outer edge of the adjacent field oxide film, a second second conductivity type diffusion region is formed on the surface of the semiconductor region, and the second second conductivity type diffusion region and the variable capacitance element region are connected to each other. As described above, a third first conductivity type diffusion region is formed on the lower surface of the field oxide film, the second conductivity type diffusion region of the variable capacitance element, the third first conductivity type diffusion region, and the first The variable capacitance device according to any one of claims 1 to 3, wherein a protective element is formed by the second conductive type diffusion region.

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