JP2000307129A - Variable capacitor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a variable capacitor circuit from deteriorating in capacitance change rate and the electrode resistance of a fixed capacitor from deteriorating a capacitance change rate, by a method wherein all or most of the projected planes of the third and second electrode are located inside the projected planes of the second and first electrode. SOLUTION: A MOS capacitor composed of a first electrode which comprises a low-concentration diffusion region 9 and a high-concentration diffusion region 11, a gate insulating film 13, and a second electrode 15 is formed on the surface of a semiconductor substrate 7. The MOS capacitor is set variable in capacitance. A capacitor composed of an interlayer insulating film 21 and a third electrode 23 is formed on a second electrode 15. This capacitor serves as a fixed capacitor 1. All or most of the projected plane of the third electrode 23 is so set as to be located inside the second electrode 15, and all or most of the projected plane of the second electrode 15 is so set as to be located inside the first electrode composed of the diffusion regions 9 and 11 so as not to generate a parasitic capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance circuit mounted on a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A variable capacitance circuit is connected to a crystal oscillation circuit,
A circuit having a variable oscillation frequency is referred to as a voltage-controlled crystal oscillation circuit.

A device equipped with such a voltage-controlled crystal oscillation circuit and using a temperature compensation signal for canceling the temperature characteristic of the crystal resonator as a control voltage for a variable capacitance circuit is a temperature compensation type crystal of an indirect compensation system. Called an oscillator.

A device using an external input voltage as a control voltage for a variable capacitance circuit is called a voltage-controlled crystal oscillator.

[0005] A variable capacitance circuit for such an application is configured using at least one variable capacitance element, and FIG. 4 shows an example of a conventional configuration.

As shown in FIG. 4, a fixed capacitor 1 for blocking a DC signal and a variable capacitor 3 are connected in series, and the other terminal of the variable capacitor 3 is connected to the ground.

Then, an input resistor 5 is connected to a connection point between the fixed capacitance 1 and the variable capacitance 3. The control signal for the variable capacitor 3 is applied via the input resistor 5.

The input resistor 5 serves to cut off the AC signal. If the output impedance of the circuit for generating the control signal is sufficiently high, the input resistor 5 may be omitted.

The variable capacitor 3 may be connected to a power supply (Vcc) on the high potential side, or may be a constant voltage generating circuit for outputting an arbitrary potential.

By the way, there has been a remarkable progress in miniaturization and weight reduction of portable communication devices such as portable telephones in recent years.
Demands for miniaturization and weight reduction of components mounted thereon have become extremely large. Temperature-compensated crystal oscillators and the like are large in size among components mounted on mobile phones, and the demands are particularly severe.

In order to reduce the size and weight of a temperature-compensated crystal oscillator and the like, attempts have been made to mount circuit components other than the crystal oscillator on a one-chip semiconductor integrated circuit.

When a variable capacitance circuit as shown in FIG. 4 is mounted on a semiconductor integrated circuit, the variable capacitance 3 is composed of a variable capacitance diode or a MOS type capacitor, and the fixed capacitance 1 is a two-layer polycrystalline silicon film or the like. In general, it is composed of One example of such a conventional configuration is shown in FIG.

FIG. 5 is a sectional view of a semiconductor integrated circuit when the variable capacitance is a MOS capacitor. However, in FIG. 5, the metal wiring film, the protective film, etc.
Illustration is omitted.

As shown in FIG. 5, a low concentration diffusion region 9 serving as a first electrode, a high concentration diffusion region 11 of the first electrode, a gate insulating film 13, A MOS capacitor including the second electrode 15 is configured as a variable capacitor 3 as shown in FIG.

On the field oxide film 17, a fourth
A capacitor including the electrode 19, the interlayer insulating film 21, and the third electrode 23 is configured as a fixed capacitor 1 as shown in FIG.

Further, on the field oxide film 17, an input resistor 5 composed of a polycrystalline silicon film containing an appropriate concentration of impurities is formed.

The second electrode 15, the fourth electrode 19, and the input resistor 5 are connected by a metal wiring film or the like. However, in order to avoid complication, the connection is shown as an electric circuit in FIG. ing.

The second electrode 15, the fourth electrode 19, and the input resistor 5 can be formed by using the same polycrystalline silicon film as a starting material and changing only the type and concentration of impurities. is there. Alternatively, the third electrode 23 and the input resistor 5 may be formed from the same polycrystalline silicon film.

Alternatively, the second electrode 15 and the fourth electrode 19 may be formed of a refractory metal polycide film or the like.

In any case, it is not difficult to mount the variable capacitance circuit shown in FIG. 4 together with an oscillation circuit and the like on a one-chip semiconductor integrated circuit.

[0021]

However, a variable capacitance circuit mounted on a semiconductor integrated circuit has a problem that the rate of change in capacitance is smaller than that of a variable capacitance circuit composed of discrete components.

[Object of the Invention] An object of the present invention is to provide a variable capacitance circuit that can be mounted on a one-chip semiconductor integrated circuit while maintaining the capacitance change rate.

[0023]

To achieve the above object, the configuration of a variable capacitance circuit according to the present invention is as follows.

That is, the configuration of the variable capacitance circuit according to the present invention comprises a first electrode made of a semiconductor having the same conductivity type and containing low-concentration and high-concentration impurities, and an insulating film interposed between the low-concentration portion of the first electrode. A second electrode made of a metal film or a semiconductor film containing a high concentration of impurities, and a second electrode made of a metal film or a semiconductor film containing a high concentration of the impurities facing the second electrode with an insulating film interposed therebetween. And all or most of the projection surface of the third electrode is inside the projection surface of the second electrode, and all or most of the projection surface of the second electrode is the first electrode.
Are located inside the projection surface of the electrode.

Alternatively, the configuration of the variable capacitance circuit according to the present invention is such that a first electrode made of a semiconductor containing low-concentration and high-concentration impurities of the same conductivity type and a low-concentration portion of the first electrode are in contact with and opposite to each other. A second electrode made of a semiconductor containing a high-concentration impurity of a conductivity type and a third electrode made of a metal film or a semiconductor film containing a high-concentration impurity opposing the second electrode with an insulating film interposed therebetween; And all or most of the projection surface of the third electrode is inside the projection surface of the second electrode, and all or most of the projection surface of the second electrode is inside the projection surface of the first electrode. There is a feature.

In these variable capacitance circuits,
The second electrode surface facing the third electrode is uneven or granular and non-planar.

[Operation] The present invention prevents the parasitic capacitance generated due to the configuration of the fixed capacitance from decreasing the rate of change in capacitance by connecting in parallel to the variable capacitance. This prevents the electrode resistance from decreasing the capacitance change rate.

In a conventional variable capacitance circuit formed on a semiconductor integrated circuit, since a fixed capacitance is formed on a field oxide film, a parasitic capacitance is generated between the lower electrode of the fixed capacitance and the semiconductor substrate. This parasitic capacitance has a substantially constant capacitance value in a normally used voltage range, and has a relation of variable capacitance and parallel connection on an electric circuit. That is, in the conventional variable capacitance circuit, a fixed capacitance is connected in parallel with the variable capacitance.

Further, in the conventional variable capacitance circuit,
As the AC signal passes through the fixed capacitance, the signal carrier must travel laterally over the lower electrode of the fixed capacitance. However, since the lower electrode of the fixed capacitor is formed of thin polycrystalline silicon or the like, the resistance component in the horizontal direction cannot be ignored.

Considering such parasitic capacitances and resistance components, a practical circuit diagram of the conventional variable capacitance circuit shown in FIG. 5 is as shown in FIG.

As shown in FIG. 6, an electrode resistor 29 is connected in series between the fixed capacitor 1 and the variable capacitor 3, and a parasitic capacitor 27 is connected in parallel with the series connection of the variable capacitor 3 and the electrode resistor 29. ing.

The electrode resistor 29 obstructs the AC signal flowing into the variable capacitor 3, and the parasitic capacitor 27 bypasses the AC signal. Therefore, when the parasitic capacitance 27 and the electrode resistance 29 exist, the ratio of the entire AC signal flowing through the variable capacitor 3 decreases.

Therefore, even if the rate of change of the capacitance of the variable capacitor 3 itself is the same, the rate of change of the AC signal decreases. This means that the capacitance change rate of the variable capacitance circuit decreases.

Therefore, in order to suppress a decrease in the rate of change in capacitance, a configuration may be adopted in which the parasitic capacitance 27 and the electrode resistance 29 do not exist. One such technique is the configuration of the present invention.

The greatest feature of the present invention is that the fixed capacitance is laminated on the variable capacitance, and the lower electrode of the fixed capacitance and the upper electrode of the variable capacitance are made common.

Even if the electrodes are simply stacked without sharing the electrodes, there is no portion that can serve as a parasitic capacitance between the lower electrode of the fixed capacitance and the semiconductor substrate, which is more advantageous than the conventional structure. However, the electrode resistance cannot be removed.

On the other hand, when the lower electrode of the fixed capacitance and the upper electrode of the variable capacitance are shared, the traveling distance of the carrier is very short because the AC signal only crosses the electrodes in the vertical direction. The resistance component of the electrode is extremely small.

Therefore, the transmission loss of the AC signal due to the resistance component of the electrode is eliminated, and the decrease in the rate of change in capacitance is suppressed.

Furthermore, it is possible to increase the capacitance change rate by increasing the area by making the upper surface of the upper electrode of the variable capacitor non-planar and increasing the capacitance value of the fixed capacitor.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the variable capacitance circuit according to the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a sectional view showing the configuration of the variable capacitance circuit according to the first embodiment of the present invention.

[Explanation of First Embodiment: FIG. 1] As shown in the sectional view of FIG. 1, a low-concentration diffusion region 9 of a first electrode and a first electrode , A MOS type capacitor including the high concentration diffusion region 11, the gate insulating film 13, and the second electrode 15. This MOS type capacitor is the variable capacitor 3 shown in FIG.

On the second electrode 15, a capacitor comprising the interlayer insulating film 21 and the third electrode 23 is formed. This capacitor is the fixed capacitance 1 shown in FIG.

Further, on the field oxide film 17, an input resistor 5 made of a polycrystalline silicon film containing an appropriate impurity is formed.
Is configured.

The second electrode 15 and the input resistor 5 are connected by a metal wiring film or the like. However, in order to avoid complication, FIG. 1 shows the connection as an electric circuit. Also, descriptions of a protective film and the like are omitted.

As is clear from FIG. 1, the second electrode 15
Is the lower electrode of the fixed capacitor 1 and the upper electrode of the variable capacitor 3. Therefore, the parasitic capacitance generated between the lower electrode of the fixed capacitor 1 and the semiconductor substrate 7 is the variable capacitor 3 itself. That is, the fixed capacitance 1 having the configuration shown in FIG. 1 has no parasitic capacitance.

In the configuration of the variable capacitance circuit shown in FIG. 1, the path of the AC signal is in the vertical direction.
Is a resistance in the thickness direction of the second electrode 15.

The second electrode 15 is formed of a polycrystalline silicon film containing a high concentration of impurities, a high melting point metal polycide film, or the like, and generally has a thickness of 0.5 μm or less.

Therefore, on the propagation path of the AC signal,
The second electrode 15 is a resistor having a very short length, and the resistance value can be regarded as substantially zero in practical use.

That is, in the configuration of the variable capacitance circuit shown in FIG. 1, there is no parasitic capacitance or a resistance component of the electrode which causes a reduction in the rate of change in capacitance. Therefore, according to the present invention, a decrease in the rate of change in capacitance of the variable capacitance circuit can be suppressed.

Incidentally, the third electrode 23 can be formed to protrude outside the second electrode 15 in terms of shape.

The second electrode 15 can be formed so as to protrude above the field oxide film 17.

However, these protruding portions are
Since a parasitic capacitance is generated between the semiconductor substrate 7 and the semiconductor substrate 7, the capacitance change rate is reduced.

Therefore, it is necessary to make the configuration such that such parasitic capacitance does not occur. For that, the third
All or most of the projected surface of the electrode 23 is located inside the projected surface of the second electrode 15, and all or most of the projected surface of the second electrode 15 is the first electrode. That is, the inside of a certain diffusion region 9 and a certain diffusion region 11 is set.

Next, a second embodiment of the present invention will be described. FIG. 2 is a sectional view showing the configuration of the variable capacitance circuit according to the second embodiment of the present invention.

[Explanation of the Second Embodiment: FIG. 2] As shown in the sectional view of FIG. 2, a low concentration diffusion region 9 of the first electrode and a first electrode A pn junction diode comprising a high concentration diffusion region 11 and a diffusion region 31 of the opposite conductivity type to the second electrode is formed. This pn junction diode is the variable capacitor 3 shown in FIG.

On the other hand, a capacitor comprising an interlayer insulating film 21 and a third electrode 23 is formed on the diffusion region 31 of the opposite conductivity type to the second electrode. This capacitor is the fixed capacitance 1 shown in FIG.

Further, on the field oxide film 17, an input resistor 5 made of a polycrystalline silicon film containing an appropriate impurity is formed.
Is configured.

The diffusion region 31 of the second electrode and the input resistor 5 are connected by a metal wiring film or the like. However, in order to avoid complication, FIG. 2 shows the connection as an electric circuit. . Also, descriptions of a protective film and the like are omitted.

As is apparent from FIG. 2, the diffusion region 31 of the second electrode is the lower electrode of the fixed capacitor 1 and the upper electrode of the variable capacitor 3 and is connected to the diffusion region 9 as the first electrode. Since it is surrounded, no parasitic capacitance exists between the lower electrode of the fixed capacitance 1 and the semiconductor substrate 7.

In the configuration of the variable capacitance circuit shown in FIG. 2, if the diffusion depth of the diffusion region 31 of the second electrode is made small, the area of the side surface of the junction surface with the diffusion region 9 becomes lower. Is negligibly small compared to the area of

Therefore, since almost all of the path of the AC signal is in the vertical direction, the resistance component from the fixed capacitance 1 to the variable capacitance 3 is the resistance in the diffusion depth direction of the diffusion region 31 of the second electrode.

Therefore, if the diffusion depth of the diffusion region 31 of the second electrode is made shallow, the diffusion region 31 of the second electrode becomes a resistor having a very short length on the propagation path of the AC signal. In practice, the resistance value can be regarded as substantially zero.

That is, in the configuration of the variable capacitance circuit shown in FIG. 2, there is no parasitic capacitance or a resistance component of the electrode which causes a decrease in the capacitance change rate. Therefore, also in the second embodiment, a decrease in the rate of change in capacitance of the variable capacitance circuit can be suppressed.

By the way, the third electrode 23 can be formed so as to protrude outside the diffusion region 31 of the second electrode.

However, the protruding part is the first part.
Since a parasitic capacitance is generated between the diffusion region 9 and the diffusion region 11, which are the electrodes, the capacitance change rate is reduced.

Therefore, it is necessary to make the configuration such that such a parasitic capacitance does not occur. For that, the third
All or most of the projection surface of the electrode 23 must be inside the diffusion region 31 of the second electrode.

When the diffusion region 31 of the second electrode and the semiconductor substrate 7 are of the same conductivity type, the diffusion region 9 and the diffusion region 11 as the first electrode cannot protrude. This is because a short circuit occurs with the semiconductor substrate 7.

Next, a third embodiment of the present invention will be described. FIG. 3 is a sectional view showing the configuration of the variable capacitance circuit according to the third embodiment of the present invention.

[Explanation of Third Embodiment: FIG. 3] As shown in the sectional view of FIG. 3, a low concentration diffusion region 9 of a first electrode and a first electrode , A MOS type capacitor including the high concentration diffusion region 11, the gate insulating film 13, and the second electrode 15. This MOS type capacitor is the variable capacitor 3 shown in FIG.

On the second electrode 15, a capacitor comprising the interlayer insulating film 21 and the third electrode 23 is formed. This capacitor is the fixed capacitance 1 shown in FIG.

Further, on the field oxide film 17, an input resistor 5 made of a polycrystalline silicon film containing appropriate impurities is formed.
Is configured.

The second electrode 15 and the input resistor 5 are connected by a metal wiring film or the like, but are shown as electrical circuit connections in FIG. 3 to avoid complication. Also, descriptions of a protective film and the like are omitted.

The difference between the third embodiment shown in FIG. 3 and the first embodiment shown in FIG. 1 lies in the shape of the upper surface of the second electrode 15, which is different from the first embodiment shown in FIG. The upper surface of the second electrode 15 has a non-planar shape.

Since the interlayer insulating film 21 and the third electrode 23 are formed along the upper surface of the second electrode 15,
These films are not flat but uneven.

The reason why the upper surface of the second electrode 15 is made non-planar is to increase the surface area to increase the capacitance value of the fixed capacitor 1.

Since the fixed capacitance 1 is connected in series to the variable capacitance 3, the larger the capacitance value of the fixed capacitance 1, the larger the rate of change in capacitance as a variable capacitance circuit.

However, since the fixed capacitor 1 is laminated on the variable capacitor 3, the area projected on the plane is
Is larger than the fixed capacity 1.

In order to increase the capacitance value of the fixed capacitor 1 under such conditions, it is necessary to reduce the thickness of the interlayer insulating film 21 or increase the effective area by making the upper surface of the second electrode 15 non-planar. There is no.

The third embodiment shown in FIG. 3 shows one example of the latter method.

There are various methods for making the upper surface of the second electrode 15 non-planar. For example, there are a method of selectively etching into a concavo-convex shape using a mask, and a method of wet-etching utilizing a high etch rate of a crystal grain boundary in a polycrystalline silicon film.

As described above, the present invention has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist of the present invention. Needless to say,

For example, in the third embodiment shown in FIG. 3, the variable capacitor 3 is a MOS capacitor, but it may be a variable capacitor diode in which the upper surface of the second electrode is non-planar.

[0083]

As described above, the variable capacitance and the fixed capacitance are stacked so as to share one electrode, and the projection surface of the fixed capacitance electrode is located within the variable capacitance projection surface. As a result, the parasitic capacitance and the electrode resistance can be eliminated,
A decrease in the rate of change in capacitance of the variable capacitance circuit formed in the semiconductor integrated circuit can be suppressed.

Furthermore, the capacitance change rate can be increased by increasing the area of the fixed electrode by making the surface on the fixed capacitance side of the shared electrode non-planar and increasing the capacitance value of the fixed capacitance.

Therefore, when applied to a temperature-compensated crystal oscillator, the temperature compensation range can be expanded, and when applied to a voltage-controlled crystal oscillator, the frequency variable width can be increased, and the effect is very large. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a variable capacitance circuit according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a variable capacitance circuit according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a configuration of a variable capacitance circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a variable capacitance circuit according to the related art.

FIG. 5 is a cross-sectional view illustrating a configuration of a variable capacitance circuit according to the related art.

FIG. 6 is a practical circuit diagram of a variable capacitance circuit according to the related art.

[Explanation of symbols]

 9: Low concentration diffusion region of the first electrode 11: High concentration diffusion region of the first electrode 13: Gate insulating film 15: Second electrode 21: Interlayer insulating film 23: Third electrode

Claims (3)

[Claims] A first electrode made of a semiconductor containing low-concentration and high-concentration impurities of the same conductivity type is opposed to a low-concentration portion of the first electrode with an insulating film interposed therebetween. A second electrode made of a semiconductor film containing an impurity, and a third electrode made of a metal film or a semiconductor film containing a high concentration of an impurity opposed to the second electrode with an insulating film interposed therebetween; All or most of the projection surface of the electrode is inside the projection surface of the second electrode, and all or most of the projection surface of the second electrode is inside the projection surface of the first electrode. Variable capacitance circuit. 2. A semiconductor device comprising: a first electrode formed of a semiconductor containing low-concentration and high-concentration impurities of the same conductivity type; and a semiconductor contacting a low-concentration portion of the first electrode and containing high-concentration impurities of an opposite conductivity type. And a third electrode made of a metal film or a semiconductor film containing a high-concentration impurity that is opposed to the second electrode with an insulating film interposed therebetween, and the entire projection surface of the third electrode is provided. Alternatively, the variable capacitance circuit is characterized in that most of the projection surface of the second electrode is inside the projection surface of the second electrode, and all or most of the projection surface of the second electrode is inside the low concentration portion of the first electrode. 3. The variable capacitance circuit according to claim 1, wherein the second electrode surface facing the third electrode has a non-planar or irregular non-planar surface. Variable capacitance circuit.