JP2008098301A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit which can extend the frequency variable width and can be miniaturized by reducing the area of the formation region for capacitor elements, moreover wherein a metal electrode is used for a fixed capacitor element to improve the function thereof as the capacitance, and further it is provided with the capacitor elements which do not have the fear of the occurrence of a silicon trench in the edge part of a polysilicon electrode due to overetching upon the patterning of the metal electrode. <P>SOLUTION: This oscillation circuit mounted on a semiconductor integrated circuit comprises an inverter for amplification, variable capacitor elements 101, 102 for controlling the oscillation frequency, fixed capacitor elements 71, 73, 74, 72 for cutting off a DC signal, a pair of terminals for an external vibrator, and terminals for inputting a frequency controlling signal. The variable capacitor elements 101, 102 are formed on the surface of the semiconductor substrate, and the fixed capacitor elements are formed by successively laminating the polysilicon electrode 72, insulating films 73 and 74, and the metal electrode 71 on a field oxide film 25a provided on the variable capacitor elements 101, 102. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an oscillation circuit, and more particularly to an oscillation circuit including a variable capacitance element for controlling an oscillation frequency and a fixed capacitance element for blocking a DC signal, which are mounted on a semiconductor integrated circuit.

  In a conventional general oscillation circuit of this type, a fixed capacitance element and a variable capacitance element are formed in different regions on a semiconductor substrate. However, according to such a configuration, since the fixed capacitance element and the variable capacitance element are formed in different regions on the semiconductor substrate, there is an inconvenience that the use efficiency of the area in the semiconductor substrate is inferior. In addition, the fixed capacitance element is usually formed on the field oxide film, but parasitic capacitance is generated between the lower electrode of the fixed capacitance element and the semiconductor substrate, the capacitance change rate is lowered, and the frequency is variable. There is also a disadvantage that the width becomes small. On the other hand, there is a demand to use a metal having excellent conductivity for one electrode of a fixed capacitance element.

  Conventionally, as a means for solving the above-described inconvenience, it has been proposed to form a fixed capacitor element and a variable capacitor element so as to overlap each other in the same region where no field oxide film exists on the semiconductor substrate. A metal electrode is not used for the fixed capacitance element.

JP 2000-323729 A (FIG. 3)

  In the above improvement proposal, the fixed capacitance element is located directly on the variable capacitance element, and is formed in substantially the same size and shape. In this case, if the third electrode (upper electrode) provided on the second electrode (lower electrode) of the fixed capacitance element via the insulating film is formed of a metal film, the metal film is formed on the entire surface of the semiconductor substrate. Then, when patterning the third electrode (metal electrode) by etching, overetching is performed so that the third electrode does not remain in the stepped portion of the second electrode. Are etched, eventually the silicon substrate is also etched to form silicon trenches. When a silicon-based material such as polysilicon is used for the upper electrode, it is easy to perform etching under conditions that have a good selection ratio with the underlying oxide film and to prevent the formation of silicon trenches. It is difficult to prevent this by using the same method. When a silicon trench is generated, it reaches a variable capacitance element that is a diffusion region formed in a semiconductor substrate, and this causes a problem that leakage occurs and the reliability of the variable capacitance element decreases. An object of the present invention is to provide an oscillation circuit that solves this problem.

  That is, an oscillation circuit according to claim 1 of the present invention includes an amplification inverter, an oscillation frequency control variable capacitor provided in series with each of the input and output terminals of the inverter, and a DC signal blocking fixed. A semiconductor integrated circuit including a capacitive element, a pair of terminals for externally attaching a vibrator, and a terminal for inputting a frequency control signal for adjusting a capacitance value of the variable capacitive element and controlling an oscillation frequency An oscillation circuit to be mounted, in which a variable capacitance element having a PN junction is formed in a region surrounded by a field oxide film on the surface of a semiconductor substrate, and insulated from a polysilicon electrode via an insulating layer on the variable capacitance element A fixed capacitance element is formed by sequentially laminating a film and a metal electrode, and extending so that an edge portion of the polysilicon electrode is positioned on the field oxide film. It is. As the metal electrode, molybdenum, tungsten, titanium, or the like can be used.

  According to a second aspect of the present invention, in the oscillation circuit according to the first aspect described above, the side surface of the polysilicon electrode constituting the fixed capacitance element is tapered.

  According to a third aspect of the present invention, in the oscillation circuit according to the first aspect, a snap-back transistor for protecting a breakdown voltage is formed at a position that does not overlap with each capacitive element on the surface of the semiconductor substrate. It is.

  According to a fourth aspect of the present invention, there is provided an oscillation circuit according to the third aspect, further comprising a first N-type diffusion layer provided on the surface of the semiconductor substrate below the field oxide film and the field oxide film. A second N-type diffusion layer formed on the outer side, and the N-type diffusion layer constituting the variable capacitance element is electrically connected to an external terminal via the first and second N-type diffusion layers. And the second N-type diffusion layer constitutes a collector region of the snapback transistor.

  According to the oscillation circuit of the present invention, by reducing the parasitic capacitance of the capacitive element, it is possible to prevent a decrease in the rate of change in capacitance and expand the frequency variable width, and to reduce the area of the capacitor element forming region. In addition to contributing to downsizing, metal is used for the electrode of the fixed capacitor element, so that the conductivity is excellent, the function as a capacitor is improved, and the end of the lower electrode of the fixed capacitor element is provided on the field oxide film. In the patterning of the metal electrode, there is no possibility that silicon trenches are generated due to over-etching at the edge of the polysilicon electrode. In addition, when the side surface of the polysilicon electrode is tapered, the metal electrode material does not remain on the side wall of the polysilicon electrode when the metal electrode is patterned. Furthermore, when a snapback transistor for protecting a circuit from a breakdown voltage input from the outside is provided, the occupied area can be reduced as compared with the case where another protection element, for example, an ESD protection diode is provided. Can contribute to downsizing.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings. Here, FIG. 1 is a circuit diagram showing the overall configuration of an oscillation circuit with an externally attached crystal resonator, FIG. 2 is a cross-sectional view showing a capacitive element structure in a portion surrounded by a chain line A in FIG. 1, and FIG. It is also a plan view. First, the overall configuration of the circuit will be described with reference to FIG. The oscillation circuit 1 is provided with terminals 3 and 4 for externally attaching the crystal resonator 2, an amplification inverter 5 and its feedback resistor 6, and between the input terminal of the inverter 5 and the terminal 3, A capacitor 7 including a molybdenum electrode (71 in FIG. 2) and a polysilicon electrode (72 in FIG. 2), which is a fixed capacitance element for DC blocking, is provided, and between the output terminal of the inverter 5 and the terminal 4 is provided. In addition, a damping resistor 8 connected in series and a capacitor 9 which is a fixed capacitance element for blocking DC are provided. The molybdenum electrode (71 in FIG. 2) is located on the terminal 3 side, and the polysilicon electrode (72 in FIG. 2) is located on the inverter 5 side.

  Further, between the terminal 3 and the capacitor 7, the cathode side of a PN junction diode 10 which is a variable capacitance element for controlling the oscillation frequency is connected. The cathode side (102 in FIG. 2) of the PN junction diode 10 is also connected to a control voltage terminal 14 for inputting an external voltage for frequency control via a load resistor 12, while the anode side (101 in FIG. 2). ) Is grounded (VSS potential). Similarly, the cathode side of a PN junction diode 11 which is a variable capacitance element for controlling the oscillation frequency is connected between the terminal 4 and the capacitor 9. The cathode side of the PN junction diode 11 is also connected to a control voltage terminal 14 for inputting an external voltage for frequency control via a load resistor 13, while the anode side is grounded (VSS potential). .

  Further, a collector terminal (151 in FIG. 2) of an NPN-type snapback transistor 15 for protecting a breakdown voltage is connected to the cathode of the PN junction diode 10, and the snapback transistor 15 is connected to the anode of the PN junction diode 10. Emitter terminals (153 in FIG. 2) are connected. The gate terminal (152 in FIG. 2) and the emitter terminal (153 in FIG. 2) of the snapback transistor 15 are grounded (VSS potential). Similarly, the collector terminal of an NPN-type snapback transistor 16 for protecting a breakdown voltage is connected to the cathode of the PN junction diode 11, and the emitter terminal of the snapback transistor 16 is connected to the anode of the PN junction diode 11. is doing. The gate terminal and the emitter terminal of the snapback transistor 16 are grounded (VSS potential).

  Subsequently, the capacitive element structure will be described. As shown in FIG. 2, a P-type well layer 21 of a semiconductor substrate (not shown) corresponding to a portion surrounded by a chain line A in FIG. A diffusion region 22, a P-type diffusion region 152 and N-type diffusion regions 23 and 24 having a higher diffusion concentration than the P-type diffusion region 22 are formed, and field oxide films 25 and 25 a are provided thereon. Further, a P-type diffusion region 27 and N-type diffusion regions 26, 151, and 153 having higher diffusion concentrations are provided in regions shallower than the respective regions 22, 152, 23, and 24. As described above, each of the N-type diffusion regions 151 and 153 and the P-type diffusion region 152 constitutes an NPN-type snapback transistor (15 in FIG. 1). The N-type diffusion regions 26, 151, and 153 can be formed in the same process as the formation of the source and drain diffusion layers of the N-type MOS transistor that constitutes the oscillation circuit. Since the source and drain diffusion layers of the P-type MOS transistor constituting the oscillation circuit can be formed in the same process, the NPN snap-back transistor can be provided with fewer processes.

  A region partitioned by the field oxide film 25a and the respective N-type diffusion regions 23 and 24 below the field oxide film 25a is a PN junction diode (10 in FIG. 1) composed of a high-concentration P-type diffusion region 101 and an N-type diffusion region 102. A configured variable capacitance element is formed. On the region corresponding to the PN junction diodes 101 and 102, there is a fixed capacitance element in which a polysilicon electrode 72, a silicon oxide film 74 and a silicon nitride film 73 which are insulators, and a molybdenum electrode 71 are sequentially laminated. A capacitor (7 in FIG. 1) is formed. An insulating film 75 is formed between the N-type diffusion region 102 constituting the variable capacitance element and the polysilicon electrode 72 constituting the fixed capacitance element.

  As can be understood from FIG. 3, the molybdenum electrode 71 is formed smaller than the polysilicon electrode 72 on the plane. The polysilicon electrode 72 is not clearly shown on the plan view of FIG. 3, but is formed in the lower layer in substantially the same shape as the rectangular silicon nitride film 73. The field oxide film 25a is formed in an annular shape outside the insulating film 75 surrounded by the upper chain line in FIG. The N-type diffusion region 26 and the N-type diffusion region 151 are at the same potential.

  As described above, the molybdenum electrode 71 is formed on a plane smaller than the polysilicon electrode 72 (see FIG. 2), but the edge portion of the polysilicon electrode 72 is located on the field oxide film 25a (see FIG. 2). Therefore, when the molybdenum electrode 71 is patterned, even if over-etching occurs during the formation of molybdenum, the etching is performed until the N-type diffusion regions 23 and 24 located immediately below the edge portion are reached due to the presence of the field oxide film 25a. There is nothing. As a result, no silicon trench is generated in the N-type diffusion regions 23 and 24, so that there is no risk of leakage. Further, by forming the side surface of the polysilicon electrode 72 in a tapered shape, it is possible to prevent the molybdenum electrode material from remaining on the sidewall of the polysilicon electrode 72 when the molybdenum electrode 71 is patterned.

  FIG. 2 shows the extraction portions a to f of the metal wiring. The connection relationship between the metal wirings will be described. The molybdenum electrode 71 is connected to the N-type diffusion region 151 and the N-type diffusion region 151 by connecting the extraction portion a and the extraction portion b. While connected to the mold diffusion region 102, it is connected to the terminal 3 via the extraction portion a, and the N-type diffusion region 151 is connected to the terminal 3 via the extraction portion a connected to the extraction portion b. Then, it is connected to the terminal 14 together with the N-type diffusion region 26 through the extraction portion c (see FIG. 1). Thus, since the extraction portions b and c for connecting to the terminals 3 and 14 are provided outside the capacitor element formation region, the wiring work is facilitated. In addition, a VSS potential is applied to the P-type diffusion region 27 from the extraction part d through the P-type well layer 21 so as to apply a potential to the semiconductor substrate, and the VSS potential is also applied to the N-type diffusion region 153 from the extraction part e. Has been granted. Further, the polysilicon electrode 72 is connected to the input terminal of the inverter 5 through the extraction portion f. The connection wiring with the other elements in the polysilicon electrode 72 can be easily formed because the upper molybdenum electrode 71 is formed small so that a space for forming a contact portion on the plane is secured.

  Although not shown, the capacitor 9 and the PN junction diode 11 are also formed in the same manner as the capacitor 7 and the PN junction diode 10 described above. Further, the NPN snapback transistors 15 and 16 may be replaced with other protective elements, and the protective elements are not necessarily provided.

The circuit diagram which shows the whole structure of the oscillation circuit of the state which attached the crystal oscillator externally. Sectional drawing which shows the capacitive element structure in the part enclosed with the chain line A of FIG. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Oscillation circuit 2 Crystal oscillator 3, 4, 14 Terminal 5 Inverter 7, 9 Capacitor (fixed capacity element)
10,11 PN junction diode (variable capacitor)
15, 16 NPN type snapback transistor 25, 25a Field oxide film 71 Molybdenum electrode 72 Polysilicon electrode 73 Silicon nitride film 74 Silicon oxide film 75 Insulating film 101 P-type diffusion region 102 N-type diffusion region 151, 153 N-type diffusion region 152 P-type diffusion region

Claims (4)

An inverter for amplification, a variable capacitance element for controlling oscillation frequency and a fixed capacitance element for blocking DC signal provided in series with each input / output terminal of the inverter, and a pair of external oscillators An oscillation circuit mounted on a semiconductor integrated circuit comprising a terminal and a terminal for inputting a frequency control signal for adjusting a capacitance value of the variable capacitance element and controlling an oscillation frequency;
A variable capacitor having a PN junction is formed in a region surrounded by a field oxide film on the surface of the semiconductor substrate, and a polysilicon electrode, an insulating film, and a metal electrode are sequentially formed on the variable capacitor via an insulating layer. An oscillation circuit comprising: a laminated capacitor, and a fixed capacitance element extending so that an edge portion of the polysilicon electrode is positioned on the field oxide film.   2. The oscillation circuit according to claim 1, wherein a side surface of the polysilicon electrode constituting the fixed capacitance element is formed in a tapered shape.   2. The oscillation circuit according to claim 1, wherein a snap-back transistor for protecting a breakdown voltage is formed at a position that does not overlap vertically with each capacitive element on the surface of the semiconductor substrate. The oscillation circuit further includes a first N-type diffusion layer provided on the surface of the semiconductor substrate below the field oxide film, and a second N-type diffusion layer formed on the outside partitioned by the field oxide film. The N-type diffusion layer constituting the variable capacitance element is electrically connected to an external terminal through the first and second N-type diffusion layers, and the second N-type diffusion layer is a snapback transistor. 4. The oscillation circuit according to claim 3, wherein the collector region is configured as follows.

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