JP3501664B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a lower electrode of a capacitor and a resistor formed of a polysilicon layer.

[0002]

2. Description of the Related Art Conventionally, in a crystal oscillator circuit or the like, a capacitor and a resistor are formed by a polysilicon region in a semiconductor device.

FIG. 10 is a diagram showing the structure of a crystal oscillation circuit, in which 30 is a semiconductor integrated circuit, 31 is a crystal oscillator, 32 is a variable capacitance diode, 34, 63 and 64 are bonding pads, 20, 36, 37, and 38 is a resistor, 22 and 24 are capacitors, 21, 23, 25, 44, 46, 47 and 48 are parasitic capacitors, and 50 is a transistor.

This crystal oscillator circuit is a semiconductor integrated circuit 30.
And a variable capacitance diode 32 for varying the oscillation frequency by acting on the crystal oscillator 31 and the crystal oscillator 31. Crystal oscillator 31 and variable capacitance diode 32
Both ends of which are not connected to each other are connected to the semiconductor integrated circuit 30 through the bonding pads 34 and 64.
In addition, parasitic capacitance is added in a distributed manner. For example,
The bonding pad 34 has a parasitic capacitance 44, the resistor 36 has a parasitic capacitance 46, the resistor 37 has a parasitic capacitance 47, the resistor 38 has a parasitic capacitance 48, the resistor 20 has a parasitic capacitance 21, the capacitor 22 has a parasitic capacitance 23, and the capacitor 24 has a parasitic capacitance 25. Is added.

Resistors 20, 36, 37, 3 in FIG.
8 and the lower electrodes of the capacitors 22 and 24 are formed of a polysilicon layer, and the structures below the polysilicon layer are the same,
The structure underneath the polysilicon layer is shown in FIG. FIG. 12 shows the connection of the parasitic capacitance added to the lower portion of the polysilicon layer forming the capacitance and resistance.

FIG. 11 is a view showing a sectional structure in the vicinity of a polysilicon region which is also a common structure of capacitance and resistance. Figure 11
In the above, 56 is a P-type semiconductor substrate made of P-type silicon. One end of this semiconductor substrate 56 is grounded.
54 is an N-type semiconductor (silicon) layer epitaxially grown on a P-type semiconductor substrate 56, and 55 is an N-type semiconductor layer 5.
An element isolation layer made of a P-type diffusion layer diffused from both upper and lower surfaces of the N-type semiconductor layer 54 in order to electrically isolate the element 4.
Is a polysilicon layer containing polysilicon as a main component and serving as a lower electrode of the capacitor or a resistor, and 52 is an insulating film for insulating the polysilicon layer 70 and the N-type semiconductor layer 54 in which a diffusion layer or the like is formed. As an example, the insulating film 52 is 15
It is formed of a silicon nitride film having a thickness of nm. Reference numeral 57 is an N-type buried diffusion layer having a higher impurity concentration than the N-type semiconductor layer 54. The N-type buried diffusion layer 5 is formed on the P-type semiconductor substrate 56.
After forming 7, the N-type semiconductor layer 54 is epitaxially grown. The N-type buried diffusion layer 57 reduces the resistance component of the epitaxially grown N-type semiconductor layer 54, and at the same time, the N-type semiconductor layer 54 and the P-type semiconductor layer (56,
55) to increase the breakdown voltage.

In the above structure, the parasitic capacitances formed between the capacitance and the P-type semiconductor substrate and between the resistance and the P-type semiconductor substrate are as shown in FIG. From the polysilicon layer 70 to be the N-type semiconductor layer 54
The capacitance value seen up to here is constituted by C1, and the capacitance value C2 at the junction of the N-type semiconductor layer 54 and the P-type semiconductor substrate 56.

In order to indicate the potential in the above structure, the virtual electrode A is connected to the polysilicon layer 70 and the virtual electrode B is connected.
Was connected to the N-type semiconductor layer 54.

FIG. 12 is an equivalent circuit diagram showing the connection of parasitic capacitances generated between the layers of FIG. 60 is an insulating film 5
2 and the polysilicon layer 70 and the N-type semiconductor layer 5 contacting both sides
4 indicates a parasitic capacitance formed between the N-type buried diffusion layer 57 and the N-type semiconductor layer 54 and the P-type semiconductor substrate 56 and the element isolation layer 55. It is a thing.

An equivalent circuit between the electrode A connected to the polysilicon layer 70 and the grounded P-type semiconductor substrate 56 is shown in FIG.
As shown in FIG. 2, the parasitic capacitances 60 and 61 are connected in series between the electrode A and the ground. Parasitic capacitance 60 and parasitic capacitance 6
The electrode B is connected to the first connection portion. Here, the parasitic capacitance 6
0 has a fixed value determined by the dielectric constant and thickness of the insulating film 52 and the area of the boundary. On the other hand, the parasitic capacitance 61
Is determined by the thickness and area of the depletion layer on the surface in contact with the diffusion layer.Since the thickness of the depletion layer varies depending on the value of the voltage applied to both sides of this depletion layer, the value of the parasitic capacitance is also the value of that voltage. Fluctuates according to.

In FIG. 13, the horizontal axis shows the time elapsed from the time when the voltage was applied to the electrode A of FIG. 12, and the vertical axis shows the fluctuation of the voltage of the electrodes A and B of FIG. . Waveform A
10 shows the waveform of the electrode A in FIG.
Shows the waveform of the resistor 37 made of a polysilicon layer. The waveform B shows the waveform of the electrode B in FIG. 12, but in FIG. 10 shows the waveform of the layer corresponding to the electrode B in the lower structure of the resistor 37.
The waveform of FIG. 13 will be described below based on the configuration of FIG.

In FIG. 10, the bonding pad 63
Is applied with a voltage from a voltage source, a circuit connected to the bonding pad 63 operates, and the voltage determined by the series of circuits is applied to the resistor 37. The waveform A shows the voltage waveform applied to the resistor 37. This voltage shifts to a steady voltage value in a time of 0.01 seconds or less, and at the same time, about 13M generated by the crystal oscillator 31.
It shows how the oscillation waveform of Hz continues. The waveform B reaches a predetermined voltage in a time of 0.01 seconds or less,
After that, it shows a gradual decrease. As the voltage of the waveform B decreases, the parasitic capacitance 6 shown in FIG.
The value of 1 fluctuates. As the value of the parasitic capacitance 61 changes, the capacitance value between the electrode A and the ground also changes.

The voltage fluctuation of the waveform B will be described more specifically below with reference to FIG. When a voltage is applied to the electrode A of FIG. 12, the parasitic capacitance 60 and the parasitic capacitance 61 are rapidly charged, and the voltage between the electrode A and the ground is divided by the electrode B according to the values of the parasitic capacitances 60 and 61. The compressed voltage is output. However, a small amount of diffusion current according to the concentration of the junction flows out from the electrode B toward the ground from the junction of the parasitic capacitance 61, and the potential of the electrode B decreases with the flow of this charge. It usually takes at least 10 seconds or more for the potential of the electrode B to drop to the ground.

As described above, in FIG. 12, when the potential of the electrode B is lowered, the capacitance value of the parasitic capacitance 61 is changed, so that the capacitance value between the electrode A and the ground is changed and parasitically added to the resistor 37 of FIG. The capacitance value changed also changes. The oscillation frequency of the crystal oscillator 31 changes as the capacitance value added to the resistor 37 changes. The variation of the parasitic capacitance value and the oscillation frequency will be described.

When the parasitic capacitance value is calculated from the area occupied by each structure of the semiconductor integrated circuit and an example of the material, the value of the parasitic capacitance 60 of FIG. 12 is 1.18 pF, and the value of the parasitic capacitance 61 is the power-on. The value immediately after is 4 pF, while the value 10 seconds after the power is turned on changes to 5 pF. In this case, when the capacitance value between the electrode A and the ground is obtained, what is 0.9112 pF immediately after the power is turned on is 0.95 ps after 10 seconds.
Change to 47 pF. The rate of change of this capacitance value is 4.6.
%. On the other hand, when the frequency of the oscillation waveform of the bonding pad 34 of FIG. 10 was measured, the frequency value fluctuated by 0.3 ppm 10 seconds after the power was turned on. This is because, for example, the fluctuation range of the frequency allowed in the oscillator that outputs the reference signal in the mobile phone is plus or minus 0.3.
ppm, which is the value at the standard boundary.

[0016]

Conventionally, in a mobile telephone, an oscillation circuit is constituted by a semiconductor integrated circuit 30, a crystal oscillator 31, and a variable capacitance diode 32 as shown in FIG. Semiconductor integrated circuit 30 and crystal oscillator 3
In order to connect 1 or the like, it is necessary to connect via a bonding pad in the semiconductor integrated circuit 30, but as shown in FIG. 12, a parasitic capacitance is added to each capacitor and resistor, and moreover, the charge The value of the parasitic capacitance fluctuated with the discharge. Such variation in the parasitic capacitance value varies over 10 seconds or more after the power is turned on, and during this period, the oscillation frequency gradually changes according to the variation in the parasitic capacitance value. The rate of this change was 0.1 Hz to 10 Hz, but these values sometimes reached the allowable value of 0.3 ppm of frequency fluctuation required for the mobile phone 10 seconds after the power was turned on.

The present invention solves the above-mentioned conventional problems, and when used in an oscillation circuit of a mobile phone or the like, which requires a highly accurate oscillation frequency stability, a stable oscillation frequency can be obtained. An object is to provide a semiconductor device having a structure of capacitance and resistance.

[0018]

A semiconductor device according to claim 1, wherein a first conductivity type first semiconductor layer and a second conductivity type different from the first conductivity type formed on the first semiconductor layer. A second semiconductor layer and a first semiconductor layer formed on the first semiconductor layer and around the second semiconductor layer to electrically isolate the second semiconductor layer.
Conductivity and conductivity type isolation layer comprising a semiconductor region, a third semiconductor layer of the first conductivity type in contact with the second semiconductor layer is formed by diffusion in the upper surface isolation layer, formed on the third semiconductor layer First
Insulating film, a polysilicon layer formed on the first insulating film and serving as one electrode of the capacitor, a capacitor insulating film formed on the polysilicon layer, and another electrode of the capacitor formed on the capacitor insulating film. And a metal layer.

[0019]

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect.
In the semiconductor device described above, a second insulating film is provided between the first insulating film and the polysilicon layer, and a surface obtained by projecting the second insulating film onto the second semiconductor layer is the polysilicon layer. It is characterized in that it is formed so as to include a surface projected onto the second semiconductor layer.

The semiconductor device according to claim 3 includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the second conductivity type different from the first conductivity type formed on the first semiconductor layer An element isolation layer, which is formed on the first semiconductor layer and around the second semiconductor layer and electrically isolates the second semiconductor layer, and includes an element isolation layer, and a second semiconductor layer A third semiconductor layer of the first conductivity type formed on the upper surface by diffusion and in contact with the element isolation layer, a first insulating film formed on the third semiconductor layer, and a resistor formed on the first insulating film. And a polysilicon layer.

[0022]

The semiconductor device according to claim 4 is the semiconductor device according to claim 3.
In the semiconductor device described above, a second insulating film is provided between the first insulating film and the polysilicon layer, and a surface obtained by projecting the second insulating film onto the second semiconductor layer is the polysilicon layer. It is characterized in that it is formed so as to include a surface projected onto the second semiconductor layer.

The semiconductor device according to claim 1 or 2 is configured to use a polysilicon layer as a lower electrode of a capacitor,
The semiconductor device according to the third and fourth aspects is configured to use a polysilicon layer as a resistor.

[0025] Claim 1, according to the configuration of claim 3, since the first semiconductor layer and the element isolation layer and the third semiconductor layer is made of the same first conductivity type region, the first semiconductor layer Is set to the ground potential, the third semiconductor layer is set to the ground potential from the first semiconductor layer through the element isolation layer, and the lower surface potential of the first insulating film in contact with the third semiconductor layer is set to the ground potential. Therefore, even if a voltage is applied to the polysilicon layer, charges due to the voltage are not induced in the second semiconductor layer of the second conductivity type, so that it is possible to suppress the time change of the parasitic capacitance added to the polysilicon layer. . In particular, the capacity to form an oscillation circuit such as a mobile phone device, a resistor, claim 1, claim 3
When the above configuration is applied, it is possible to suppress the fluctuation of the oscillation frequency and realize an oscillation circuit satisfying a tolerance of 0.3 ppm, for example.

[0026]

Further, according to the structures of claims 2 and 4 , the second insulating film formed in the region including the polysilicon layer is provided between the first insulating film and the polysilicon layer. As a result, the thickness of the insulating film (first and second insulating films) directly under the polysilicon layer can be increased to about 350 nm, and the second semiconductor layer under the polysilicon layer is generated. The amount of charge can be further reduced.
By reducing this amount of charge, the change in the parasitic capacitance added to the polysilicon layer over time is further suppressed,
When applied to an oscillator circuit, the amount of fluctuation of the oscillation frequency can be further reduced. Note that the second insulating film is formed of a silicon oxide film, a silicon nitride film, or a resin.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment; Corresponding to Claim 1] FIG. 1 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device according to a first embodiment of the present invention.
In FIG. 1, 56 is a P-type semiconductor substrate (first semiconductor layer), 57 is an N-type buried diffusion layer, and 54 is an N-type semiconductor layer (second semiconductor layer) epitaxially grown on the P-type semiconductor substrate 56. , 55 is an element isolation layer formed of a P-type diffusion layer diffused from both upper and lower surfaces of the N-type semiconductor layer 54 to electrically isolate the N-type semiconductor layer 54, and 73 is a P-type semiconductor layer (third semiconductor layer). ), 52 is an insulating film (first insulating film), 70 is a polysilicon layer provided above the insulating film 52 to form a lower electrode of the capacitor, and 76 is formed on the polysilicon layer 70. A capacitor insulating film, 77 a wiring made of a metal layer connected to the polysilicon layer 70 through a through hole, 78 a metal layer serving as a capacitor upper electrode formed on the capacitor insulating film 76, and 79 an interlayer insulating film. It is a film. The insulating film 52 is formed of, for example, a silicon nitride film having a dielectric constant of 3.9 and a thickness of about 15 nm here, but may be formed of a silicon oxide film.

In the semiconductor device of this embodiment, the polysilicon layer 70 is formed as the lower electrode of the capacitor,
The capacitance insulating film 76 and the interlayer insulating film 79 are connected to the wiring 77 through through holes provided in the opening. The insulating film 52 and the P-type semiconductor layer 7 are formed below the polysilicon layer 70.
3, the epitaxially grown N-type semiconductor layer 54, the N-type buried diffusion layer 57, and the P-type semiconductor substrate 56 are present. The main difference from FIG. 11 of the conventional example is that a P-type semiconductor layer 73 is provided. The N-type semiconductor layer 54 is electrically separated from other N-type semiconductor layers by the element isolation layer 55. A P-type semiconductor layer 73, which is in contact with the lower surface of the insulating film 52 and extends over the N-type semiconductor layer 54 and the element isolation layer 55, is formed by diffusion. Since the element isolation layer 55 in contact with the grounded P-type semiconductor substrate 56 is formed of the P-type diffusion layer, the P-type semiconductor layer 73 also has the ground potential. Therefore, the N-type semiconductor layer 54 and the N-type buried diffusion layer 57.
Is a P-type semiconductor layer (56, 5
5, 73).

FIG. 2 is an equivalent circuit diagram showing the connection of the parasitic capacitance added to the polysilicon layer 70 of FIG. still,
Similarly to the conventional example, for the sake of description, the electrode A is added to the polysilicon layer 70, and the electrode B is added to the N-type semiconductor layer 54 under the polysilicon layer 70 which is separated by the element isolation layer 55.

With the structure shown in FIG. 1, a parasitic capacitance 80 due to the insulating film 52 is added between the P-type semiconductor layer 73 and the electrode A, and a parasitic capacitance 8 due to the insulating film 52 is provided between the electrode A and the ground.
0 and the parasitic capacitance 61 are added in series. The parasitic capacitance 61 is similar to the conventional parasitic capacitance 61 shown in FIG. P
Since the type semiconductor layer 73 is grounded, even if a voltage is applied to the electrode A (polysilicon layer 70), the voltage N
The charge is not induced in the type semiconductor layer 54, and the electrode A
The value of the parasitic capacitance added to (i.e., the parasitic capacitance added to the polysilicon layer 70) does not change. When the configuration of FIG. 1 is used for the capacitors 22 and 24 of the crystal oscillation circuit of FIG.
A power supply voltage is applied to the polysilicon layer 70 and the capacitors 22, 2
4, the parasitic capacitances of the capacitors 22 and 24 are stabilized even after the appearance of the oscillation waveform, and the fluctuation of the frequency of the oscillation waveform can be suppressed. Specifically, when the power supply voltage is applied to the polysilicon layer 70, 1 after the oscillation waveform appears in the silicon layer 70
The fluctuation of the frequency after 1 second can be suppressed to 0.1 ppm or less.

Second Embodiment: Corresponding to Claim 2 FIG. 3 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device according to a second embodiment of the present invention. In FIG. 3, reference numeral 71 is an insulating film (second insulating film), and this insulating film 71 is formed of a silicon oxide film, a silicon nitride film, or a resin having a temperature expansion coefficient value substantially equal to that of silicon. In addition, the same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In the second embodiment, the insulating film 71 is formed between the polysilicon layer 70 and the insulating film 52, and the other structure is the same as that of the first embodiment.
The surface of the insulating film 71 whose main surface is projected onto the N-type semiconductor layer 54 includes the surface of the polysilicon layer 70 which is projected onto the N-type semiconductor layer 54, and the projected surface of the insulating film 71 is a device isolation surface. It exists in the region where the N-type semiconductor layer 54 is separated by the layer 55. That is, the insulating film 71 is the isolation layer 5
In the upper region of the N-type semiconductor layer 54 surrounded by 5,
It is formed in a region including the formation region of the polysilicon layer 70. With this structure, the insulating film 52 and the insulating film 71 are present immediately below the polysilicon layer 70, and therefore the insulating films 52 and 71 are provided between the polysilicon layer 70 and the P-type semiconductor layer 73. The parasitic capacitance created by is connected in series.

FIG. 4 is an equivalent circuit diagram showing the connection of the parasitic capacitance added to the polysilicon layer 70 of FIG. Note that the electrodes A and B were added for the sake of explanation, as in the first embodiment. Further, in FIG. 4, reference numeral 81 is a parasitic capacitance due to the insulating film 71, and the other parts that are the same as those in FIG.

According to the configuration of FIG. 3, since the insulating film 71 is added to the configuration of FIG. 1, in FIG. 4, the parasitic capacitance of the insulating film 52 and the parasitic capacitance of the insulating film 71 are different from those of FIG. 81 is added in series. In this way, since the parasitic capacitances 80 and 81 are added in series between the electrode A and the electrode B, compared with the case where only the parasitic capacitance 80 of FIG.
The capacitance value added between B and B can be further reduced. By reducing the parasitic capacitance value between the electrodes A and B, it is possible to relatively reduce the amount of charge generated in the electrode B when a voltage is applied to the electrode A, and the amount of charge generated in the electrode A by the discharge of the charge It is possible to suppress variation in the added parasitic capacitance value. In other words, the insulating film 71 is added to the configuration of FIG.
The thickness of the insulating film (52, 71) directly under the polysilicon layer 70 can be increased to about 350 nm by adding the above, and charges generated in the N-type semiconductor layer 54 immediately under the polysilicon layer 70 can be increased. The amount can be further reduced. By reducing the charge amount, it is possible to further suppress the change in the parasitic capacitance added to the polysilicon layer 70 over time, and it is possible to further reduce the variation amount of the oscillation frequency when applied to the oscillation circuit.

The insulating film 52 formed of a silicon nitride film or a silicon oxide film has a film thickness of, for example, about 15 nm as described in the first embodiment in order to reduce the step difference of the contact portion (not shown). If the film thickness of the insulating film 52 is increased, the step difference of the contact portion (not shown) becomes large, and the disconnection of the wiring in the contact portion due to the difference becomes a problem.

First Reference Example FIG. 5 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device of a first reference example . In FIG. 5, 75 is an N-type semiconductor layer having a high impurity concentration formed on a partial surface of the N-type semiconductor layer 54, 83 is a wiring connected to the N-type semiconductor layer 75, and the other parts are the same as those in FIG. Are denoted by the same reference numerals, and the description thereof will be omitted.

In the first reference example , the P-type semiconductor layer 73 in the first embodiment is not provided, and the N-type semiconductor layer 75 is formed on a part of the surface of the N-type semiconductor layer 54.
The wiring 83 is connected to the N-type semiconductor layer 75 to connect the N-type semiconductor layer 54.
Is configured to be fixed to a predetermined potential. In addition,
Since the P-type semiconductor layer 73 (FIG. 1) is not provided, the contact with the lower surface of the insulating film 52 is N as in the conventional example of FIG.
The type semiconductor layer 54.

FIG. 6 is a circuit diagram equivalently showing the connection of the parasitic capacitance added to the polysilicon layer 70 of FIG.
Note that the electrodes A and B were added for the sake of explanation, as in the first embodiment. Further, in FIG. 6, reference numeral 82 is a power supply that indicates that a constant potential is applied to the N-type semiconductor layer 75 and the N-type semiconductor layer 54 through the wiring 83, and other parts that are the same as those in FIG. However, the description is omitted.

With the structure shown in FIG. 5, a parasitic capacitance 80 due to the insulating film 52 is added between the N-type semiconductor layer 54 and the electrode A. Since the potential of the electrode A does not affect the electrode B because the potential of the N-type semiconductor layer 54 is fixed, the parasitic capacitance added to the electrode A (that is, added to the polysilicon layer 70). The value of (parasitic capacitance) does not change. When the configuration of FIG. 5 is used for the capacitors 22 and 24 of the crystal oscillation circuit of FIG. 10, even after the power supply voltage is applied to the polysilicon layer 70 and the oscillation waveform appears in the capacitors 22 and 24,
The parasitic capacitance of 24 is stabilized, fluctuations in the frequency of the oscillation waveform can be suppressed, and an oscillation circuit satisfying a tolerance of 0.3 ppm, for example, can be realized.

Further, similarly to the structure shown in FIG. 1 in which the insulating film 71 is added to the structure shown in FIG. 3 (second embodiment), the same insulating film 71 is added to the structure shown in FIG. by increasing the thickness of the insulating film immediately under the polysilicon layer 70, Ru same effect as the second embodiment can be obtained.

In the first and second embodiments provided with the P-type semiconductor layer 73, the element isolation layer 55 needs to be formed of a P-type diffusion layer having the same conductivity type as the semiconductor substrate 56. In the first reference example , the element isolation layer 55 may be formed of a P-type diffusion layer, or the N-type semiconductor layer 54 may be formed of an electrically insulating insulating film such as an oxide film.

[ Third and Fourth Embodiments (Claim 3,
4)) and the second reference example ] FIGS. 7, 8 and 9 show the third and fourth embodiments of the present invention, respectively.
It is a figure which shows the cross-section of the polysilicon layer and its vicinity in the semiconductor device of embodiment and a 2nd reference example . 7, FIG. 8 and FIG. 9, 85 and 86 are wirings connected to both ends of the polysilicon layer 70, and other parts corresponding to those in FIGS. The description is omitted.

First and Second Embodiments and First Reference
In Reference Example describes the configuration using the polysilicon layer 70 as the lower electrode of the capacitor, the third, the form of the fourth embodiment
The state and the second reference example show a configuration in which the polysilicon layer 70 is used as a resistor. As shown in FIGS. 7, 8 and 9, the wirings 85 and 86 are connected to both ends of the polysilicon layer 70 through the through holes of the interlayer insulating film 79, and the polysilicon layer between the wirings 85 and 86 is formed. 70 acts as a resistance. 7 is the same as FIG. 1, FIG. 8 is the same as FIG. 3, and FIG. 9 is the same as FIG. 5, except for the configuration other than the upper portion of the polysilicon layer 70. Detailed description is omitted.

The first to fourth embodiments described above
In the first and second reference examples , all conductivity types (P
Type and N type) may be reversed. Also, the first to the fourth
The polysilicon layer 70 in the embodiment and the first and second reference examples is not particularly limited in conductivity type and may be either P-type or N-type, but currently, it is easy to control accuracy. From the viewpoints of (management by PCM) and ease of fabrication, when used as the lower electrode of the capacitor as in the first and second embodiments and the first reference example , it is N-type, and third,
When it is used as a resistor as in the fourth embodiment and the second reference example , it is a P type.

[0047]

As described above, claims 1 and 2 of the present invention
According to the third configuration, the first semiconductor layer and the element isolation layer and the third
Of the same conductivity type region as the semiconductor layer of
By setting the first semiconductor layer to the ground potential, the third semiconductor layer becomes the ground potential from the first semiconductor layer through the element isolation layer, and the potential of the lower surface of the first insulating film which is in contact with the third semiconductor layer becomes It can be set to the ground potential, and even if a voltage is applied to the polysilicon layer, charges due to the voltage are not induced in the second semiconductor layer of the second conductivity type, so that the parasitic capacitance added to the polysilicon layer changes with time. Can be suppressed. In particular, when applied to the configuration of capacitance and resistance of an oscillation circuit of a mobile phone device or the like that requires highly accurate oscillation frequency stability, an oscillation waveform having high frequency stability can be obtained.

[0048]

[0049] Further, Claim 2 of the present invention, according to the configuration of claim 4, the thickness of the insulating film immediately under the polysilicon layer is provided a second insulating film (the first and second insulating films) The amount of charges generated in the second semiconductor layer directly below the polysilicon layer can be further reduced, and the parasitic capacitance value added to the polysilicon layer can be prevented from changing with the passage of time. Can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device according to a first embodiment of the present invention.

2 is an equivalent circuit diagram showing a connection of a parasitic capacitance added to a polysilicon layer 70 of FIG.

FIG. 3 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device according to a second embodiment of the present invention.

4 is an equivalent circuit diagram showing a connection of a parasitic capacitance added to the polysilicon layer 70 of FIG.

FIG. 5 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in the semiconductor device of the first reference example .

6 is an equivalent circuit diagram showing a connection of a parasitic capacitance added to the polysilicon layer 70 of FIG.

FIG. 7 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a semiconductor device of a second reference example .

FIG. 10 is a diagram showing a configuration of a crystal oscillation circuit.

FIG. 11 is a diagram showing a cross-sectional structure of a polysilicon layer and its vicinity in a conventional semiconductor device.

12 is an equivalent circuit diagram showing a connection of a parasitic capacitance added to the polysilicon layer 70 of FIG.

13 is a diagram showing a change in voltage of electrodes A and B in FIG.

[Explanation of symbols]

52 Insulating film (first insulating film) 54 N-type semiconductor layer (second semiconductor layer) 55 Element isolation layer 56 P-type semiconductor substrate (first semiconductor layer) 57 N-type buried diffusion layer 70 Polysilicon layer 71 insulating film (second insulating film) 73 P-type semiconductor layer (third semiconductor layer) 75 N-type semiconductor layer 76 Capacitance insulating film 77,83,85,86 wiring 78 Metal layer 79 Interlayer insulation film

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-283055 (JP, A) JP-A-9-121021 (JP, A) JP-A-8-330524 (JP, A) JP-A-10- 223842 (JP, A) JP 62-18749 (JP, A) JP 5-121664 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 27 / 04

Claims (4)

(57) [Claims] 1. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type formed on the first semiconductor layer, and the first semiconductor layer. A first semiconductor layer formed on the semiconductor layer and around the second semiconductor layer to electrically isolate the second semiconductor layer;
An element isolation layer formed of a conductive type semiconductor region, a third semiconductor layer of a first conductivity type formed in diffusion on the upper surface of the second semiconductor layer and in contact with the element isolation layer, and on the third semiconductor layer A formed first insulating film, a polysilicon layer formed on the first insulating film and serving as one electrode of a capacitor, a capacitor insulating film formed on the polysilicon layer, and formed on the capacitor insulating film And a metal layer serving as the other electrode of the capacitor. 2. A second insulating film is provided between the first insulating film and the polysilicon layer, and the second insulating film is used as the second insulating film.
The projected surface in the semiconductor layer, the semiconductor device according to claim 1, characterized in that said polysilicon layer is formed to include a surface which is projected on the second semiconductor layer. 3. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type formed on the first semiconductor layer, and the first semiconductor layer. A first semiconductor layer formed on the semiconductor layer and around the second semiconductor layer to electrically isolate the second semiconductor layer;
An element isolation layer formed of a conductive type semiconductor region, a third semiconductor layer of a first conductivity type formed in diffusion on the upper surface of the second semiconductor layer and in contact with the element isolation layer, and on the third semiconductor layer A semiconductor device comprising: a formed first insulating film; and a polysilicon layer formed on the first insulating film and serving as a resistor. 4. A second insulating film is provided between the first insulating film and the polysilicon layer, and the second insulating film is used as the second insulating film.
4. The semiconductor device according to claim 3 , wherein the surface projected onto the semiconductor layer of is formed so as to include the surface projected onto the second semiconductor layer of the polysilicon layer.