JPH0936306A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely control a junction capacitance inside an LSI, by forming a circuit which performs the comparing with a reference capacitor of high absolute precision which is connected with the outside of a semiconductor integrated circuit, and applies a control voltage to a control terminal of an internal capacitor. SOLUTION: An input terminal V1 is connected with a switch SW1, passes a reference capacitor Cr, outputted from a switch SW2, inputted in the minus terminal of an operational amplifire E1, connected with a switch SW3, passes an irnternal capacitor Cs, and connected with the output of the operational amplifier E1 from a switch SW4. The output is connected with the minus terminal of an operational amplifier E2, whose output is fed back to the control terminal of the internal capacitor Cs via a high resistance R. By controlling the capacitance value of the internal capacitor Cs, the dispersion of the internal capacitance which is caused by the manufacturing process or the like can be restrained in a circuital manner, so that the internal capacitor Cs of high absolute precision can be easily obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an internal capacitance, and more particularly to a semiconductor integrated circuit in which the internal capacitance requires absolute accuracy.

[0002]

2. Description of the Related Art Conventionally, when absolute accuracy is required for a capacitance element formed in or on a semiconductor substrate,
The layout is designed so that there is no variation in the electrode area for forming the capacitive element, that is, the contact area between the upper and lower electrodes and the capacitive insulating film on the layout. This is because the capacitance value C generally depends on the area S and the dielectric film thickness Tox as shown by the following equation. C = (S / Tox) (ε ₀ · ε) [F] where ε ₀ is the dielectric constant of vacuum 8.854E-12 [F /
m], ε is the relative dielectric constant of the dielectric.

As a countermeasure against such a variation in the contact area, an MIM (Met) in which a capacitive element is formed on a semiconductor substrate is used.
al Insulator Metal) or MIS (Metal Insulator Silco)
n) In the case of the capacitance, measures such as increasing the etching accuracy of polycrystalline silicon for forming both side or one side electrodes of polycrystalline silicon or the like are taken. For example, in order to prevent polycrystalline silicon from being over-etched, measures have been taken such as providing a dummy pattern around an electrode to prevent excessive sneak of an etching gas.

In the case of a PN junction capacitor for forming a capacitive element in a semiconductor substrate, the above measures cannot be taken because the diffusion layer is used as an electrode. Therefore, a mask material for forming the diffusion layer is required. The concentration, temperature, time, etc. are adjusted to increase the processing accuracy of the resist film and the like, and to prevent variations in the impurity concentration and indentation amount. However, in any case, a remarkable effect cannot be expected in preventing variation in manufacturing.

For this reason, in recent years, for a junction capacitance utilizing a PN junction of an element, a control electrode is provided on the junction capacitance, and a capacitance value is controlled by externally applying a voltage to the control electrode. Proposed. FIG. 7 shows an example, and FIG. 7A is a sectional view of a PN junction capacitor. An N-type diffusion layer 400 is formed in the P-type silicon substrate 1 to form a junction capacitance, and a P-type diffusion layer 300 is formed in the N-type diffusion layer 400 to form a control electrode. FIGS. 7 (b) and 7 (c) are equivalent circuits thereof,
This is a circuit in which a high resistance R100 is connected to a diode, and the cathode side of the diode is a signal terminal TA100 and a voltage control terminal TC100.

With such a junction capacitance, the signal terminal TA1
The PN junction capacitance Cd100 between 00 and the ground can be controlled by the voltage applied to the voltage control terminal TC100.
Therefore, by applying this control voltage from outside the LSI, the variation in capacitance is corrected, and the accuracy of the junction capacitance is increased. If necessary, after forming the element, characteristics may be measured and trimming may be performed to obtain a required capacitance value.

[0007]

By controlling the voltage applied to the control terminal as described above, it is possible to improve the accuracy of the capacitance. However, since the control voltage is applied from outside the LSI, It is necessary to configure a circuit for the applied voltage outside the LSI, which complicates the configuration of the entire LSI. Also,
Since there is also a manufacturing variation in the junction capacitance, it is necessary to cope with this variation from outside the LSI, and there is a problem that the voltage control therefor is complicated and it is difficult to control it with high accuracy. . An object of the present invention is to provide a semiconductor integrated circuit in which a circuit for applying a control voltage is built in an LSI, and in which the junction capacitance can be controlled with high precision inside the LSI.

[0008]

According to the semiconductor integrated circuit of the present invention, when controlling the capacitance of an internal capacitance composed of a voltage-controlled variable capacitance element, a semiconductor integrated circuit is connected to a highly accurate reference capacitance connected outside the semiconductor integrated circuit. A circuit is provided for applying a control voltage to the control terminal of the internal capacitance to make a comparison and bring the characteristic of the internal capacitance close to the characteristic of the reference capacitance.

This circuit comprises a switched-capacitor type amplifier circuit having a capacitance in an input stage of an operational amplifier and a feedback portion, and one of the input stage capacitance and the feedback portion capacitance of the switched-capacitor type amplifier circuit has an internal capacitance. And a reference capacitor for the other, and using the output of the switched-capacitor-type amplifier circuit obtained by dividing the charge between the internal capacitor and the reference capacitor as a control voltage for the internal capacitor.

For example, a first operational amplifier having a reference capacitance connected to the input stage and an internal capacitance connected to the feedback section, and an output of the first operational amplifier connected to the input stage;
A second operational amplifier that connects the output to the control terminal of the internal capacitance via the high resistance is provided. Alternatively, a first operational amplifier in which a reference capacitance is connected to the input stage and an internal capacitance is connected to the feedback unit, and an output of the first operational amplifier is connected to the input stage, and the output is internally connected via the capacitance. And a second operational amplifier connected to the control terminal of the capacitor.

[0011]

Next, an example of an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an internal capacitance including a junction capacitance formed in a semiconductor integrated circuit of the present invention;
FIG. 3 is a circuit diagram of a reference circuit for controlling the capacitance value of the internal capacitance with high accuracy. In this circuit, the internal capacitance C
This makes it possible to control the voltage applied to the control terminal s with high accuracy inside the LSI by using a reference capacitor Cr externally attached to the LSI.

FIG. 2 is a schematic sectional view of the device structure of the internal capacitance Cs, which is formed as an npn-type bipolar transistor. As shown in FIG. 2A, an N-type collector 2 is formed in a P-type silicon substrate 1 by diffusion and ion implantation, and a lower portion composed of a P-type base is similarly formed in the collector 2 by diffusion or ion implantation. The electrode 3 is formed. The concentration of this base is
It is about 1E18a / cm ³ . Further, a control electrode 4 composed of an N-type emitter is formed in the base region by diffusion and ion implantation. The concentration of this emitter is also set to about 1E19a / cm ^{3 due} to the structure of the transistor.

A 15 nm-thick silicon oxide film 5 is formed on the upper surface of the vertical bipolar transistor structure, and polycrystalline silicon is formed on the silicon oxide film 5 on the diffusion layer of the control electrode 4 composed of an emitter. Is provided. The lower electrode 2, the control electrode 4, and the upper electrode 6 are connected to respective circuits via aluminum wirings 7 via interlayer insulating films 8, respectively. When the lower electrode 3 is a terminal TA, the control electrode 4 is a terminal TB, and the upper electrode 6 is a terminal TC, FIG.
If FIG. 2A is replaced with an equivalent circuit, the circuit becomes as shown in FIGS. 2B and 2C, and the capacitance between the terminals TA to TC can be changed by the control voltage of the terminal TB.

In this embodiment, the internal capacitance Cs is designed to be 5 PF inside the LSI and is ± 15%
It is configured as a capacitor having a degree of variation. On the other hand, the reference capacitor Cr is configured as an extremely accurate chip capacitor having a capacitance value of 5 PF and a variation of about ± 1%. As shown in FIG. 1, a switch SW is connected to the input and output of the reference capacitor Cr, respectively.
1 and SW2 are connected, and these switches SW
Reference numerals 1 and 2 switch the input terminal and the output terminal of the reference capacitor to the input terminal V1, the operational amplifier E1, and the analog ground VAG, respectively. Also, the internal capacitance C
Similarly, switches SW3 and SW are provided for input and output, respectively.
4 are connected, and the respective switches SW3, SW
Reference numeral 4 denotes an operational amplifier E1, E2
And an analog ground VAG.

The input terminal V1 is connected to the switch SW1 and passes through the reference capacitor Cr to switch SW2.
, Is input to the minus terminal of the operational amplifier E1, is connected to the switch SW3, passes through the internal capacitance Cs, and is connected from the switch SW4 to the output of the operational amplifier E1. Further, this output is connected to the minus terminal of the operational amplifier E2, and the output is fed back to the control terminal of the internal capacitance Cs via the high resistance R. This high resistance R is about 10 KΩ, and is a high resistance for preventing a signal from leaking from the control terminal of the internal capacitance Cs. The reference circuit is not particularly necessary because it is constituted by DC. It is necessary to handle AC signals. The operational amplifier E2 connected to both ends of the internal capacitance Cs and the capacitance used in other circuits and the control terminal.
The high resistance R is unnecessary when the structure is such that a sufficient isolation can be obtained between the output and the output. Here, the plus terminal of the operational amplifier E1 is connected to the analog ground VAG, and the plus terminal of the operational amplifier E2 is the input terminal V of this circuit.
1 connected. Similarly, the output of the operational amplifier E2 is applied to the control terminals of the capacitors C ₀₁ and C ₀₂ used in other circuits of the same structure in the same chip, thereby making the capacitance extremely small.

FIG. 3 shows the switches SW1 to SW of FIG.
4 is a diagram showing the configuration of FIG. 4, in which the switch of FIG. 3A is configured as a MOS transfer gate, as shown in FIG. 3B. By controlling the gate input signal of the transfer gate as shown in FIG. 3C, the switches SW1 to SW4 can be switched. In this embodiment, the switches SW1 to SW4 are configured to perform a switching operation in conjunction with a contact.

The operation of controlling the capacitance of the internal capacitance Cs by the reference circuit having the above configuration will be described. As shown in FIG. 2C, the internal capacitance Cs includes the PN junction capacitance Cd of the control electrode 4 and the lower electrode 3, the control electrode 4 and the upper electrode 6
Are CIM capacitors Cm connected in series. Here, assuming that the area of the PN junction capacitance Cd (the PN junction area of the control electrode 4 and the lower electrode 3) is 100 × 50 μm ² □,
A PN junction capacitance of 15 PF is configured as a device (bias from the control electrode is 0 V), and the area of the MIM capacitance Cm (junction area between the upper electrode 6 and the silicon oxide film 5) is 100.
× 45 μm ² □, the control electrode 4 and the upper electrode 6
This constitutes the MIM capacity of the PF.

The PN junction capacitance Cd is 1 in device structure.
Although it is composed of 5PF, it is used as 10PF when the circuit is used. The characteristics of the PN junction capacitance Cd are shown in FIG. 4, and can be changed to 15 PF at a control voltage of 0 V and to 6 PF at a control voltage of 5 V. Now, at a control voltage of 1.2 V, it becomes 10 PF,
The total internal capacitance Cs is the PN junction capacitance Cd and the MIM
The combined capacitance with the capacitance Cm is 5 PF.

Next, the overall electrical operation will be described. The circuit shown in FIG. 1 has a configuration in which the power supply voltage is 5 V, the analog ground voltage VAG is 2.5 V, and the input voltage is 3 V. Considering the state of the switch, the reference capacitor Cr is charged with a voltage difference of 0.5 V between the input voltage of 3 V and VAG = 2.5 V, and the internal capacitor Cs has a voltage between both ends of VAG1 = 2.5 V. Is not charged. Next, when the switch is set to the state, the reference capacitor Cr discharges a charge of 0.5 V to the minus terminal of the operational amplifier E1, but the operational amplifier E1
Since the plus terminal is fixed at VAG = 2.5 V, the charge does not escape to the minus terminal of the imaginary short circuit, goes to the internal capacitance Cs, and enters the output of the operational amplifier E1.

By forming such a loop, the output of the operational amplifier E1 is expressed by the following equation. E1out = (Cr / Cs) (V1-VAG) + VAG [V] (1) However, in the case of positive phase (this circuit has a positive phase switch configuration) From the above equation, the reference capacitance Cr is composed of 5PF. And
Since the internal capacitance Cs, which is a combined capacitance of the PN junction capacitance 15PF and the MIM capacitance 10PF, is composed of 6PF, the output of the operational amplifier E1 is 2.92V.

Here, when the output of the operational amplifier E1 is input to the minus terminal of the operational amplifier E2, since the input 3V is applied to the plus terminal of the operational amplifier E2, the output of the operational amplifier E2 is about 1. 2V, and the PN junction capacitance Cd designed to be 15 PF in device design is 10 PF.
And the combined capacitance with the MIM capacitor Cm connected in series is stabilized at 5 PF.

Here, it will be described that the circuit of the present invention falls within the same variation (± 1%) as the reference capacitance Cr when the internal capacitance Cs varies by ± 15% due to manufacturing variations. The internal capacitance Cs is equal to the PN junction capacitance Cd and the MIM.
Since the internal capacitance Cs is composed of the capacitance Cm, the worst case variation in the internal capacitance Cs is caused by the PN junction capacitance Cd and the MIM capacitance C.
It is conceivable that m varies in the same direction. Table 1 shows PN
PN when junction capacitance Cd and MIM capacitance Cm vary
9 is a table showing correction values of the junction capacitance Cd.

[0023]

[Table 1]

(1) PN junction capacitance Cd and MIM capacitance Cm
Are varied by plus 15% (when the internal capacitance Cs is maximized). As shown in Table 1, the PN junction capacitance Cd is 1
Variation from 5PF to 17.25PF, MIM capacity Cm
Varies from 10 PF to 11.5 PF and the internal capacitance Cs
Becomes 6.9 PF. Then, the output of the operational amplifier E1 becomes 2.86 V from the equation (1), and is input to the minus terminal of the operational amplifier E2. However, since the plus terminal of the operational amplifier E2 is fixed at 3 V, a potential difference of -140 mV is generated, and the output of the operational amplifier E2 to which negative feedback is applied operates so that the minus terminal of the operational amplifier E2 is 3 V, and the internal capacitance Cs To 10 PF. That is, when the voltage of the control electrode 4 which is the output of the operational amplifier E2 becomes 2.9 V in FIG. 4, the capacitance of the PN junction capacitance Cd is 8.8 PF, and the internal capacitance Cs is 5 PF (11.5 // 8.8
= 5PF).

(2) PN junction capacitance Cd and MIM capacitance Cm
Are both minus 15% (when the internal capacitance Cs becomes the smallest). As shown in Table 1, the PN junction capacitance Cd is 1
Variation from 5PF to 12.75PF, MIM capacity Cm
Is the internal capacitance Cs when it varies from 10PF to 8.5PF.
Becomes 5.1 PF. Then, the output of the operational amplifier E1 becomes 2.99 V from the equation (1) and is input to the minus terminal of the operational amplifier E2. However, since the plus terminal of the operational amplifier E2 is fixed at 3 V, a potential difference of -10 mV is generated, and the output of the operational amplifier E2 to which the negative feedback is applied becomes the operational amplifier E2.
Of the internal capacitance C
s is set to 10 PF. That is, the voltage of the control electrode 4, which is the output of the operational amplifier E2, becomes 0.1 V as shown in FIG. 4 so that the capacitance of the PN junction capacitance Cd is 12 PF, and the total internal capacitance Cs is 5 PF (8.5 // 12 = 5PF).

As described above, by comparing the manufacturing variation of the internal capacitance of the semiconductor integrated circuit with the externally provided reference capacitor having high absolute accuracy, it is possible to suppress the variation to the same level as the external capacitance.

Next, a second embodiment of the present invention will be described. FIG. 5A shows a modification of the internal capacitance Cs. The upper electrode 41 is composed of an N-type emitter of a normal npn bipolar transistor separated by a trench 9.
And two PN junction capacitances composed of diodes of the lower electrode 31 composed of a P-type base and two PN junction capacitances connected in series. Further, the PN junction capacitance is separated by the trench 9, and terminals contacted from the respective upper electrodes 41 are connected to TB 10, T
B11, and terminals contacted from the lower electrode 31 are TA10 and TA11. This equivalent circuit is shown in FIG.
(B) and (c), and the respective PN junction capacitances are Cd10 and Cd11.

FIG. 6 shows a circuit diagram using the internal capacitance Cs composed of the PN junction capacitance. Each PN junction capacitance Cd10
And switches SW10, SW11, S at both ends of Cd11.
W15 and SW16 are provided. Further, a capacitor CR is used instead of the high resistance R in FIG. 1, and switches SW13 and SW14 are provided at both ends of the capacitor CR. This capacity C
R is composed of a normal capacitance formed inside the LSI, and the capacitance value varies depending on the frequency in actual use, but is composed of a small value, and the output voltage of the operational amplifier E2 is transmitted when the switches at both ends are turned on and off. . Also, the PN junction capacitance Cd1
A switch SW12 is provided between the connection point of 0 and Cd11 and the switch SW13 of the capacitance CR. Other circuit operations are the same as those of the circuit of FIG.

Also in this embodiment, the PN junction capacitance C
The reference capacitance C having high absolute accuracy provided with the manufacturing variation of the internal capacitance Cs constituted by d10 and Cd11 provided outside.
By comparing with r, the variation can be suppressed to the same level as the external capacitance. Also, in the circuit of FIG. 1, a low-frequency and DC component leaked to some extent because the internal capacitance Cs and the high resistance R constituted a high-band filter, but in the circuit of FIG. By using the switch and the switch, although the high-pass filter is formed, the capacitance value can be reduced, so that there is an advantage that the DC component can be cut with a smaller area than the high resistance R.

[0030]

As described above, in the semiconductor integrated circuit of the present invention, a very accurate reference capacitance is externally provided, and the internal capacitance provided inside the semiconductor integrated circuit is fed back using a switched capacitor circuit or the like. By controlling the capacitance value of the internal capacitance by applying the above, variation in the internal capacitance due to a manufacturing process or the like can be suppressed in a circuit. Accordingly, it is not necessary to control the capacitance value of the internal capacitance from outside the semiconductor integrated circuit, so that the scale of the external circuit can be reduced, and the internal capacitance with absolute accuracy can be easily obtained. This eliminates the necessity of taking a margin in circuit design, and is effective in, for example, realizing low power consumption in designing a bias circuit, a margin of a cutoff frequency of a filter, and the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a sectional view of an internal capacitor according to the first embodiment and an equivalent circuit diagram thereof.

FIG. 3 is a circuit diagram of a switch and a drive signal waveform diagram thereof.

FIG. 4 is a voltage-capacity characteristic diagram of an internal capacitance.

FIG. 5 is a sectional view of an embodiment 2 of the present invention and an equivalent circuit diagram thereof.

FIG. 6 is a circuit diagram of a second embodiment.

FIG. 7 is a cross-sectional view of an internal capacitance of a conventional technique and its equivalent circuit diagram.

[Explanation of symbols]

 Cs Internal capacitance Cr Reference capacitance E1, E2 Operational amplifier SW1 to SW4 Switch R High resistance

Claims (6)

[Claims] 1. A semiconductor integrated circuit having an internal capacitance formed of a voltage-controlled variable capacitance element formed in a semiconductor integrated circuit and having a control terminal for variably controlling a capacitance value, the semiconductor integrated circuit being connected to the outside of the semiconductor integrated circuit. And a circuit for applying a control voltage to the control terminal of the internal capacitance to make the characteristic of the internal capacitance close to the characteristic of the reference capacitance. Semiconductor integrated circuit. 2. The internal capacitance is formed by serially connecting a PN junction capacitance composed of a base and an emitter of a vertical bipolar transistor structure formed on a semiconductor substrate, and a dielectric capacitance including an insulating film and an upper electrode formed on the emitter. 2. The semiconductor integrated circuit according to claim 1, wherein the emitter is a control electrode. 3. The semiconductor integrated circuit according to claim 1, wherein the internal capacitance has a structure in which a PN junction capacitance comprising a base and an emitter of a vertical bipolar transistor structure formed on a semiconductor substrate is connected in series, and the emitter serves as a control electrode. . 4. An input stage of an operational amplifier and a switched capacitor type amplifier circuit having a capacitance in a feedback section, wherein one of the input stage capacitance and the feedback section capacitance of the switched capacitor type amplifier circuit has the internal capacitance. 4. An output of the switched-capacitor type amplifier circuit obtained by using the reference capacitor as the other and using the internal capacitor and the reference capacitor to divide electric charge, as a control voltage of the internal capacitor. Semiconductor integrated circuit. 5. A reference capacitor is connected to the input stage,
A first operational amplifier having an internal capacitance connected to the feedback section, and a second operational amplifier having an output connected to the input stage and having an output connected to a control terminal of the internal capacitance via a high resistance.
5. The semiconductor integrated circuit according to claim 4, further comprising: an operational amplifier. 6. A reference capacitor is connected to an input stage,
A first operational amplifier having an internal capacitance connected to the feedback section, and a second operational amplifier having an output connected to the input stage and connecting the output to a control terminal of the internal capacitance via the capacitance. 5. The semiconductor integrated circuit according to claim 4, further comprising an amplifier.