JP3327169B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a bonding pad provided in a semiconductor device for connecting a circuit inside the semiconductor device and a circuit outside the semiconductor device.

[0002]

2. Description of the Related Art Conventionally, the structure of a bonding pad provided in a semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 61-53756.
And Japanese Patent Application Laid-Open No. 9-82746.

FIG. 7 is a diagram showing a cross-sectional structure near a bonding pad disclosed in Japanese Patent Application Laid-Open No. Sho 61-53756. FIG. 8 is an equivalent circuit diagram showing the connection of the parasitic capacitance attached to the bonding pad of FIG.

1 is a P-type silicon substrate, 2 is an N-type silicon layer epitaxially grown on the substrate 1, 7 is an isolation U-shaped groove, an SiO ₂ film 4 is formed on the inner surface of the groove, and poly is Silicon 9 is filled. Reference numeral 5 denotes an aluminum film serving as a bonding pad, and reference numeral 8 denotes a P-type diffusion layer formed on the surface of the N-type silicon layer 2 immediately below the bonding pad. In this configuration, each capacitance formed between the bonding pad and the P-type substrate is
, The capacitance value at the junction between the N-type silicon layer 2 and the P-type substrate 1 is C2, and the capacitance value at the junction between the P-type diffusion layer 8 and the N-type silicon layer 2 is C3. When the capacitance value C4 between the bonding pad and the ground is obtained, the reciprocal of C4 is given as the sum of the reciprocals of the values of C1, C2, and C3. The presence of the capacitance value C3 suppresses the value of the capacitance value C4 which is parasitic on and adheres to the bonding pad. In addition, the provision of the P-type diffusion layer allows a through-hole to be generated in the insulating film, and at the same time, the N-type layer and the bonding pad are insulated by the P-type layer even when a signal of a ground potential or less is applied to the bonding pad. This prevents the occurrence of abnormal current.

FIG. 9 is a diagram showing a cross-sectional structure disclosed in Japanese Patent Application Laid-Open No. 9-82746. As an example, an N-type semiconductor layer 12 is formed on a P-type semiconductor substrate 11.
An insulating film 13 made of silicon oxide is formed on the semiconductor layer 12.
Is formed. The insulating film 13 is formed of, for example, LOCO
S (Local Oxidation of Sili)
(con) method and an element isolation oxide film 14 and a field oxide film 15. On the insulating film 13,
For example, the pad 16 is formed of an aluminum-based metal.
Further, an N-type impurity diffusion layer 17 connected to the semiconductor substrate 11 is formed in the semiconductor layer 12 on the side of the pad 16. A connection hole 18 is formed in the insulating film 13 on the N-type impurity diffusion layer 17, and a pad 16 is formed in the connection hole 18.
And an electrode 19 which is electrically independent from the impurity diffusion layer 17 is formed. An element isolation diffusion layer 20 is formed surrounding the semiconductor layer 12 below the pad 16 and the impurity diffusion layer 17 located near the pad 16. Thus, by forming a PN junction under the pad 16, the pad 1
The capacitance that is parasitically attached between the semiconductor substrate 6 and the semiconductor substrate 11 is reduced. Further, by applying a reverse electric field between the semiconductor layer 12 and the semiconductor substrate 11 via the electrode 19, the width of the depletion layer is widened and the PN junction capacitance is reduced.

FIG. 10 is a diagram showing a configuration of a conventional crystal oscillation circuit. In FIG. 10, the crystal oscillation circuit includes a semiconductor integrated circuit 30, a crystal oscillator 31, and a variable capacitance diode 32 acting on the crystal oscillator 31 to vary the oscillation frequency. Here, 33, 34 and 63, 6
Reference numeral 4 denotes a bonding pad in the semiconductor integrated circuit 30 for connection to the outside. Both ends of the crystal oscillator 31 are connected to bonding pads 33 and 34. The bonding pad 33 is connected to an internal circuit via a resistor 35. In addition, the bonding pad 34
Is connected to an internal circuit through a common connection of the resistors 36, 37, and 38. A parasitic capacitance is added to these elements in a distributed manner between the element and the bonding pad 63. For example, the parasitic capacitance 43 adheres to the bonding pad 33, and the parasitic capacitance 4
4, the parasitic capacitance 45 in the resistor 35 and the parasitic capacitance 4 in the resistor 36
6. Parasitic capacitance 47 in the resistor 37 and parasitic capacitance 48 in the resistor 38
Adheres. Hereinafter, these parasitic capacitances will be described.

FIG. 11 is a view showing a cross-sectional structure near the bonding pad. In FIG. 11, reference numeral 50 denotes a metal layer containing aluminum as a main component and formed in the shape of a bonding pad in this figure. Reference numeral 51 also denotes a metal layer having aluminum as a main component, partially overlapping the shape of the metal layer 50, and having a further extended shape. In a semiconductor integrated circuit, a wiring structure of a plurality of layers is adopted, and wirings formed by the metal layer 50 and wirings formed by the metal layer 51 are formed in various shapes even in portions not shown in the figure and used as a wiring medium. . 5
Reference numeral 2 denotes an insulating film for insulating the metal layer 50 from the metal layer 51. Reference numeral 53 denotes an insulating film for insulating the metal layer 51 from the semiconductor diffusion layer. As an example, the insulating film 52
Is formed of a silicon nitride film having a thickness of 900 to 1000 nanometers, and the insulating film 53 is formed of a silicon oxide film having a thickness of 400 to 500 nanometers. 54 is
An N-type epitaxially grown semiconductor layer;
Is a P-type diffusion layer, which is a separation layer diffused from both upper and lower surfaces of the semiconductor layer 54 to electrically separate the semiconductor layer 54. Reference numeral 56 denotes a P-type semiconductor substrate in contact with one end of the separation layer 55. One end of the semiconductor substrate is connected to the ground. Reference numeral 57 denotes a high-concentration N-type diffusion layer buried to enhance the insulation at the boundary between the semiconductor layer 54 and the semiconductor substrate 56.

In FIG. 11, a metal layer 51 is extended toward the front left side, and its end is connected to high-concentration N-type diffusion layers 58 and 59, and further connected to an N-type diffusion layer 57. By providing this N-type diffusion structure near the bonding pad, when a potential lower than the ground potential due to a surge or the like is applied to the metal layer 50, the N-type diffusion layers 57, 59, 58 and the metal The charge flows through the layer 51 to prevent the bonding pad and the diffusion layer connected to the bonding pad from being destroyed.

In order to show a potential in the above structure, the virtual electrode A was connected to the metal layer 50, and the virtual electrode B was connected to the semiconductor layer 54.

FIG. 12 is an equivalent circuit diagram showing the connection of parasitic capacitance generated parasitically between the layers in FIG.

Reference numeral 60 denotes a parasitic capacitance formed between the metal layer 51 and the semiconductor layer 54 in contact with both surfaces of the oxide film 53, and 61 denotes an N-type diffusion layer 57 and the semiconductor layer 54 and the semiconductor substrate 56. And 62 indicates the parasitic capacitance formed between the N-type diffusion layers 57 to 59 and the semiconductor substrate 56 and the isolation layer 55. Here, the parasitic capacitance 60 has a fixed value determined by the dielectric constant and thickness of the oxide film and the area of the boundary. On the other hand, the parasitic capacitances 61 and 62 are determined by the thickness and the area of the depletion layer on the surface in contact with the diffusion layer, and the thickness of the depletion layer varies depending on the value of the voltage applied to both surfaces of the depletion layer. Also fluctuates according to the value of the voltage.

As described above, the parasitic capacitance 60 between the electrode A and the ground
And 61 are connected in series, and parasitic capacitances 60 and 6
1 is connected in parallel with the parasitic capacitance 62. The electrode B is connected to the connection between the parasitic capacitance 60 and the parasitic capacitance 61.

FIG. 13 shows the lapse of time from the time when the voltage is applied to the electrode A in FIG. 12 on the horizontal axis, and shows the fluctuation of the voltage on the electrodes A and B in FIG. 12 on the vertical axis. . Waveform A
FIG. 10 shows the waveform of the electrode A in FIG.
3 shows the waveform of the bonding pad 34. Waveform B shows the waveform of the electrode B in FIG. 12, but FIG. 10 shows the waveform of the layer corresponding to the electrode B in the lower structure of the bonding pad. Hereinafter, the waveform of FIG. 13 will be described based on the configuration of FIG.

Referring to FIG. 10, a bonding pad 63 is provided.
, A circuit connected to the bonding pad 63 operates, and a voltage determined by a series of circuits is applied to the bonding pad. Waveform A shows a voltage waveform applied to the bonding pad 34. The voltage shifts to a steady voltage value in 0.01 seconds or less, and at the same time, the crystal oscillator 3
1 shows a state in which an oscillation waveform of about 13 MHz generated by No. 1 is maintained. Waveform B shows a state in which the voltage reaches a predetermined voltage in 0.01 seconds or less and then gradually decreases. As the voltage of the waveform B decreases, the value of the parasitic capacitance 61 shown in FIG. 12 changes. The capacitance value between the electrode A and the ground also changes with the change in the value of the parasitic capacitance 61.

The voltage fluctuation of the waveform B will be described more specifically with reference to FIG. When a voltage is applied to the electrode A in FIG. 12, charges are rapidly charged in the parasitic capacitance 60 and the parasitic capacitance 61, and the voltage between the electrode A and the ground is distributed to the electrode B according to the values of the parasitic capacitances 60 and 61. The compressed voltage is output. However, from the junction of the parasitic capacitance 61, a small amount of diffusion current corresponding to the junction concentration flows from the electrode B toward the ground, and the potential of the electrode B decreases with the flow of the electric charge. It usually takes at least 10 seconds or more for the potential of the electrode B to fall to the ground.

As described above, when the potential of the electrode B decreases in FIG. 12, the capacitance value of the parasitic capacitance 61 changes, so that the capacitance value between the electrode A and the ground fluctuates, and parasitically on the bonding pad 34 of FIG. The added capacitance value also changes. The oscillation frequency of the crystal oscillator 31 changes with the change of the capacitance value added to the bonding pad 34. The value of the parasitic capacitance and the fluctuation of the oscillation frequency will be described.

When the parasitic capacitance value is calculated from an example of the area and material of each structure of the semiconductor integrated circuit, the value of the parasitic capacitance 60 is 1.18 pf and the value of the parasitic capacitance 62 is 1 in FIG.
The value of the parasitic capacitance 61 is 4 pf immediately after the power is turned on, whereas the value 10 seconds after the power is turned on changes to 5 pf. In this case, when the capacitance value between the electrode A and the ground is obtained, it is 10.0912 pf immediately after the power is turned on.
Changes to 10.9547 pf after 10 seconds. The ratio of the change in the capacitance value is 0.3987%.
On the other hand, when the frequency of the oscillation waveform of the bonding pad 34 in FIG. 10 was measured, the frequency value changed 0.3 ppm 10 seconds after the power was turned on. The variation range of the frequency allowed in the oscillator that outputs the reference signal in the mobile phone is ± 0.3 ppm, which is the value of the standard boundary.

[0018]

Conventionally, in a portable telephone, an oscillation circuit is constituted by a semiconductor integrated circuit 30, a crystal oscillator 31, and a variable capacitance diode 32 as shown in FIG. Semiconductor integrated circuit 30 and crystal oscillator 3
1 and the like must be connected via a bonding pad in the semiconductor integrated circuit 30. However, as shown in FIG. 12, a parasitic capacitance is added to each bonding pad, At the same time, the value of the parasitic capacitance fluctuated. Such a variation in the parasitic capacitance value fluctuates over a period of 10 seconds or more after the power is turned on, and during this period, the oscillation frequency gradually changes in accordance with the variation in the parasitic capacitance value. The rate of this change was 0.1 Hz to 10 Hz, but these values sometimes reached 0.3 ppm, which is the allowable value of the frequency fluctuation required for the mobile phone 10 seconds after the power was turned on.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor device having a structure of a bonding pad and a resistor which can be used in a portable telephone to obtain a stable oscillation frequency. I do.

[0020]

In order to achieve this object, means taken in the semiconductor device according to claim 1 of the present invention is to contact a semiconductor layer of a first conductivity type with the semiconductor layer of the first conductivity type. A second conductivity type semiconductor layer having a conductivity type opposite to the first conductivity type semiconductor layer; a first insulating film in contact with the second conductivity type semiconductor layer; and a second conductivity type semiconductor layer An element isolation layer for electrically isolating the first insulating film, a second insulating film formed above the first insulating film, and an electrical connection in contact with the first insulating film and the second insulating film. A bonding pad formed by the second metal layer in a semiconductor device having a first metal layer for performing the above and a second metal layer for making an electrical connection in contact with the second insulating film. And
An outer edge of a surface projected onto the semiconductor layer from the main surface of the bonding pad at right angles to the surface is surrounded by an outer edge of a second conductivity type semiconductor layer separated by the element isolation layer. It is assumed that.

With this configuration, when a voltage is applied to the second metal layer, the amount of electric charge generated in the second conductive type semiconductor layer immediately below the bonding pad is reduced by the thickness of the insulating film immediately below the bonding pad. It can be reduced by increasing the height. By reducing the amount of charge, the amount of the capacitance parasitically added to the bonding pad, which fluctuates over time, can be reduced. In particular, when used for a bonding pad connected to an oscillation circuit used in a cellular phone device or the like, a variation in the oscillation frequency is suppressed, and an oscillation circuit that satisfies a tolerance of, for example, 0.3 ppm is formed using a semiconductor device. Can be.

According to a second aspect of the present invention, there is provided a semiconductor device comprising a first insulating film and a third insulating film in contact with the second insulating film, and a main surface of the third insulating film. The outer edge of the surface projected onto the semiconductor layer at right angles to this surface is the outer edge of the surface projected onto the semiconductor layer at right angles to the surface from the main surface of the bonding pad of the second metal layer. And being surrounded by an outer edge of a second conductivity type semiconductor layer separated by the element isolation layer.

With this configuration, the thickness of the insulating film immediately below the bonding pad can be increased, and the amount of charge generated in the second conductive type semiconductor layer immediately below the bonding pad can be further reduced. it can. By reducing the amount of charge, the amount of the capacitance parasitically added to the bonding pad, which fluctuates over time, can be reduced. This film is formed of a silicon oxide film, a silicon nitride film, or a resin.

According to a third aspect of the present invention, there is provided a semiconductor device, wherein the element isolation layer is formed of a semiconductor layer of a second conductivity type, and the element isolation layer is formed on the semiconductor layer at right angles to the main surface of the bonding pad. A semiconductor layer of the first conductivity type is formed on the semiconductor layer of the second conductivity type so as to have a surface surrounding the surface projected on the substrate.

With this configuration, the potential of the surface of the first insulating film which is in contact with the semiconductor layer can be set to the ground potential, and the second potential is applied to the bonding pad even when a voltage is applied to the bonding pad.
Since the electric charge is not induced in the conductive semiconductor layer by the voltage, it is possible to eliminate the time change of the parasitic capacitance added to the bonding pad.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the semiconductor device of the present invention will be described below.

FIG. 1 is a diagram showing a cross-sectional structure of a bonding pad according to an embodiment of the present invention and its vicinity. In FIG. 1, reference numeral 56 denotes a P-type semiconductor layer;
7 is an N-type buried diffusion layer, 54 is a P-type semiconductor layer 5
6, an N-type semiconductor layer epitaxially grown on
Reference numeral 5 denotes a separation layer which is a P-type semiconductor layer or an oxide film layer for electrically separating the N-type semiconductor layer 54, 53 denotes an insulating film formed in contact with the semiconductor layer, and 52 denotes an upper part of the insulating film 53. An insulating film for insulating a wiring layer having a two-layer structure,
Reference numeral 51 denotes a metal layer of an aluminum alloy provided between the insulating films 52 and 53 for wiring, and reference numeral 50 denotes a metal layer of an aluminum alloy provided on the insulating film 52 for wiring. Here, the insulating film 52 is formed of a silicon nitride film having a dielectric constant of 7.5 and a thickness of about 1000 nanometers, and the insulating film 53 is formed of a silicon nitride having a dielectric constant of 3.9 and a thickness of about 500 nanometers. It is formed of an oxide film. The silicon nitride film has a harder film structure than the silicon oxide film, and has strong durability against mechanical stress on the bonding pad. Here, a bonding pad 70 is formed of the metal layer 50. Under the bonding pad 70, insulating films 52 and 53, an N-type semiconductor layer 54 epitaxially grown, an N-type buried diffusion layer 57, and a P-type Is formed. The N-type semiconductor layer 54 is electrically separated from other N-type semiconductor layers by the separation layer 55. A plane obtained by projecting the main surface of the bonding pad 70 at right angles to this plane is included in a region surrounded by the separation layer 55. From a part of the bonding pad 70, the metal layer 50 extends to the outside of the bonding pad 70 across the separation layer 55, is connected to the metal layer 51 at the point, and is connected to the N-type diffusion layer at the point. Is done.

FIG. 2 is an equivalent circuit diagram showing the connection of the parasitic capacitance added to the bonding pad 70 of FIG.
For the sake of explanation, the electrode A and the separation layer 5
The electrode B was added to the N-type semiconductor layer separated by 5 and below the bonding pad 70. As viewed from the electrode A, a parasitic capacitance 80 due to the insulating film 52 is added in series to the parasitic capacitance 60. Other capacitances between the electrode A and the ground are the same as the conventional parasitic capacitance shown in FIG. With this configuration, the parasitic capacitance 80 and the parasitic capacitance 60 are connected in series between the electrode A and the electrode B of the semiconductor layer 54. The generated parasitic capacitance value can be reduced. By reducing the parasitic capacitance value, the amount of charge generated in the electrode B when a voltage is applied to the electrode A can be relatively reduced, and the variation in the parasitic capacitance value of the electrode A due to the discharge of the charge can be suppressed. Can be. Specifically, when the bonding pad of FIG. 1 is used in the conventional crystal oscillation circuit of FIG. 10, the amount of charge charged to the electrode B can be halved, and the power supply voltage is applied to the bonding pad 63. Frequency fluctuation 10 seconds after the oscillation waveform appears on the bonding pad 34 by 0.15 p.
pm or less.

FIG. 3 is a view showing a cross-sectional structure of a bonding pad and its vicinity according to an embodiment of the present invention. Note that, in FIG. 2 and subsequent figures, the same reference numerals as those in FIG. 1 denote the same as those in FIG. 1, and a description thereof will be omitted.

In FIG. 3, an insulating film 71 is formed between the insulating film 52 and the insulating film 53 below the bonding pad 70, and the main surface of the insulating film 71 is projected onto the semiconductor layer 54, The bonding pad 70 is connected to the semiconductor layer 54.
The projection surface of the insulating film 71 is present in a region where the semiconductor layer 54 is separated by the separation layer 55. With this configuration, the insulating film 52, the insulating film 71, and the insulating film 53 exist directly below the bonding pad 70, and therefore, a parasitic capacitance formed by these layers is connected in series with the semiconductor layer. You. here,
As the insulating film 71, a silicon oxide film, a silicon nitride film, or a resin having substantially the same temperature expansion coefficient as silicon can be used.

FIG. 4 is an equivalent circuit diagram showing the connection of the parasitic capacitance added to the bonding pad 70 of FIG.
It should be noted that, in FIG. 4 and subsequent drawings, those denoted by the same reference numerals as those in FIG. 2 mean the same as those in FIG. 2, and description thereof will be omitted.

In FIG. 4, the parasitic capacitance 80 and the parasitic capacitance 6
A parasitic capacitance 81 due to the insulating film 71 is added between 0 and 0. Thus, the parasitic capacitance 8 between the electrode A and the electrode B
Since 0, 81 and 60 are added in series, the parasitic capacitance 8
The capacitance value added between the electrodes A and B can be further reduced as compared with the case where 0 and the parasitic capacitance 60 are added.

FIG. 5 is a view showing a cross-sectional structure of a bonding pad and the vicinity thereof according to an embodiment of the present invention.

In FIG. 5, a P-type semiconductor layer 73 is in contact with the insulating film 53 and straddles the N-type semiconductor layer 54 and the separation layer 55.
Are formed by diffusion. Here, since the separation layer 55 is formed of a P-type semiconductor layer, the semiconductor layer 73 is connected to the ground potential. The N-type semiconductor layer 54 below the bonding pad 70 is covered with a P-type semiconductor layer whose periphery is grounded.

FIG. 6 is a circuit diagram equivalently showing the connection of the parasitic capacitance added to the bonding pad 70 of FIG.

In FIG. 6, a parasitic capacitance 80 formed by the insulating film 52 and a parasitic capacitance 60 formed by the insulating film 53 are added in series between the P-type semiconductor layer 73 and the electrode A. No capacity 61 is added. N-type semiconductor layer 54
Even if the electric charge moves from the P-type layer to the grounded P-type layer, it does not affect the electrode A, so that the value of the parasitic capacitance added to the electrode A does not change. When the bonding pads of FIGS. 6A and 6B are used as the bonding pads 33 and 34 of the crystal oscillation circuit of FIG. Since it is stable, the fluctuation of the frequency of the oscillation waveform can be suppressed.

[0037]

As described above, when the present invention is used in an oscillation circuit that requires high-precision oscillation frequency stability, the present invention can be applied to a semiconductor layer via first and second insulating films or further. 3
By forming a bonding pad via the insulating film of the above, the accumulation of electric charges in the semiconductor layer immediately below the bonding pad can be reduced, and the parasitic capacitance value added to the bonding pad over time can be suppressed. can do.

Further, by providing a diffusion layer connected to the ground to the semiconductor layer immediately below the bonding pad, it is possible to eliminate the variation with time of the parasitic capacitance value added to the bonding pad, which is used for the crystal oscillation circuit. In this case, an oscillation waveform having high frequency stability can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a bonding pad according to an embodiment of the present invention and a cross-sectional structure in the vicinity thereof;

FIG. 2 is an equivalent circuit diagram showing a connection of a parasitic capacitance added to the bonding pad 70 of FIG. 1;

FIG. 3 is a view showing a cross-sectional structure of a bonding pad and its vicinity according to an embodiment of the present invention;

FIG. 4 is an equivalent circuit diagram showing connection of a parasitic capacitance added to the bonding pad 70 of FIG. 1;

FIG. 5 is a view showing a cross-sectional structure of a bonding pad and its vicinity according to an embodiment of the present invention.

6 is an equivalent circuit diagram showing connection of a parasitic capacitance added to the bonding pad 70 of FIG.

FIG. 7 is a diagram showing a cross-sectional structure near a conventional bonding pad.

FIG. 8 is an equivalent circuit diagram showing connection of a parasitic capacitance attached to the bonding pad of FIG. 7;

FIG. 9 is a diagram showing a cross-sectional structure near a conventional bonding pad.

FIG. 10 is a diagram showing a configuration of a conventional crystal oscillation circuit.

FIG. 11 is a diagram showing a cross-sectional structure near a conventional bonding pad.

FIG. 12 is an equivalent circuit diagram showing the connection of the parasitic capacitance in FIG. 11;

FIG. 13 is a diagram showing a change in voltage of electrodes A and B in FIG.

[Explanation of symbols]

1 P-type silicon substrate 2 N type silicon layer 4 SiO ₂ film 5 aluminum film 7 isolation U-shaped groove 8 P-type diffusion layer 9 of polysilicon 11 semiconductor substrate 12 semiconductor layer 13 insulating film 14 element isolation oxide film 15 field oxide film 16 Pad 17 Impurity diffusion layer 18 Connection hole 19 Electrode 20 Element isolation diffusion layer 30 Semiconductor integrated circuit 31 Crystal oscillator 32 Variable capacitance diode 33, 34 Bonding pad 35-38 Resistance 43-48 Parasitic capacitance 50, 51 Metal layer 52, 53 Insulation Film 54 Semiconductor layer 55 Separation layer 56 Semiconductor substrate 57, 58, 59 N-type diffusion layer 60 to 62 Parasitic capacitance 63, 64 Bonding pad 70 Bonding pad 80 to 82 Parasitic capacitance

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/60 H01L 21/822 H01L 27/04

Claims (3)

(57) [Claims] A first conductivity type semiconductor layer; a second conductivity type semiconductor layer which is in contact with the first conductivity type semiconductor layer and has a conductivity type opposite to the first conductivity type semiconductor layer; A first insulating film that is in contact with the two-conductivity-type semiconductor layer; an element isolation layer that electrically separates the second-conductivity-type semiconductor layer; and a second insulating film that is formed above the first insulating film. An insulating film, a first metal layer that is in contact with the first insulating film and the second insulating film to make an electrical connection, and is in contact with an upper part of the second insulating film to make an electrical connection. A semiconductor device comprising: a second metal layer; a bonding pad formed by the second metal layer; and an outer edge of a surface projected onto the semiconductor layer at right angles to the surface from a main surface of the bonding pad. Is defined by the outer edge of the semiconductor layer of the second conductivity type separated by the element isolation layer. Wherein a Mareta. 2. A semiconductor device, comprising: a third insulating film that is in contact with the first insulating film and the second insulating film, and is projected onto the semiconductor layer at right angles to the main surface of the third insulating film. The outer edge of the surface includes the outer edge of the surface projected onto the semiconductor layer at right angles to the main surface of the bonding pad of the second metal layer, and is separated by the element isolation layer. 2
2. The semiconductor device according to claim 1, wherein the semiconductor device is surrounded by an outer edge of the conductive semiconductor layer. 3. The semiconductor device according to claim 1, wherein the element isolation layer is formed of a semiconductor layer of a second conductivity type, and has a surface surrounding a surface projected onto the semiconductor layer at right angles to the main surface of the bonding pad. 3. The semiconductor device according to claim 1, wherein the one conductivity type semiconductor layer is formed on the second conductivity type semiconductor layer.