JPS58110072A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58110072A
JPS58110072A JP20863581A JP20863581A JPS58110072A JP S58110072 A JPS58110072 A JP S58110072A JP 20863581 A JP20863581 A JP 20863581A JP 20863581 A JP20863581 A JP 20863581A JP S58110072 A JPS58110072 A JP S58110072A
Authority
JP
Japan
Prior art keywords
emitter
diode
base
transistor
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20863581A
Other languages
Japanese (ja)
Inventor
Toshio Shigekane
重兼 寿夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP20863581A priority Critical patent/JPS58110072A/en
Publication of JPS58110072A publication Critical patent/JPS58110072A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755Vertical bipolar transistor in combination with diodes, or capacitors, or resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent an increase in total inverse recovery time for the antiparallel diode and the resistor-connected transistor of the titled semiconductor device by a method wherein the diode, which is in series with a resistor and in parallel to a base-emitter junction and having the barrier layer voltage lower than that which exists between a base and an emitter, is connected inbetween the base and the emitter of the transistor. CONSTITUTION:A resistor 3 and a diode 6, which will be in forward direction toward the base and the emitter, are connected in series inbetween the base and the emitter of the transistor, and a diode 2 is connected in parallel inbetween the emitter and the collector. According to this constitution, as the diode 6, a Schottky barrier diode having the forward voltage lower than that of the base- emitter saturation voltage of the transistor 1 is used, and when a base current runs to an emitter terminal E from a base terminal B, a resistor 3 functions as an inserted resistor. Also, when the voltage, wherein positive elecricity is on the terminal E and negative electricity is on the terminal C, the current running from the terminal E to B is interrupted by the diode 6.

Description

【発明の詳細な説明】 本発明はトランジスタのエミッタとコレクター間にエミ
ッタ接合に逆並列に高速ダイオードを接続し、ベース、
エミッタ間に抵抗を接続してなる半導体装置に関する。
[Detailed description of the invention] The present invention connects a high-speed diode in antiparallel to the emitter junction between the emitter and collector of a transistor, and
The present invention relates to a semiconductor device having a resistor connected between emitters.

トランジスタを例えばパルス暢変gl (PWM)  
方式によるモータ制御に用いる場合、負荷に誘導性のあ
ることや回生動作の関係から第1図に示すようにNPN
トランジスタlのエミッタからコレクタからコレクタへ
逆並列にダイオード2が接続される。第2図に示すPW
M方式のトランジスタインバータにおいて、例えばトラ
ンジスタ4がPWM動作を行うときには、そのターンオ
ン時にダイオード5の逆方向回復電流がコレクタ電流に
型費されるため、トランジスタ4のターンオン損失が増
加する。このターンオン損失を減するためにはダイオー
ド5には高速ダイオードが必要で、同様に他のダイオー
ドも高速ダイオードが望ましい。一方、高耐圧トランジ
スタでは耐電圧特性ならびにその安定性の向上のために
、第1図に示すように0ベース、エミッタ間に抵抗3が
接続される。ところが、この抵抗3の接続は全体として
の逆回復時間trrを増加させる働きをもつ。今、第3
図でエミッタ端子Eを正、コレクタ端子Cを負とするト
ランジスタlのエミッタ接合に対するf′WL圧が印加
されると、電流はEからダイオード2を通じてCへ流れ
るばかりでなく、Eから抵抗3を通じてトランジスタl
のベース層へ、さらすこ唄バイアスのベース、コレクタ
間接合を経てCに流れるため、トランジスタの逆方向′
dL流増幅作用によってトランジスタ内部を通じてもE
からCへ電流が流れる。
For example, a transistor can be used as a pulse width variable GL (PWM)
When used for motor control using the NPN method, as shown in Figure 1 due to the inductive nature of the load and the relationship
A diode 2 is connected in antiparallel from the emitter to the collector of the transistor l. PW shown in Figure 2
In the M-type transistor inverter, for example, when the transistor 4 performs PWM operation, the reverse recovery current of the diode 5 is used as a collector current when it is turned on, so that the turn-on loss of the transistor 4 increases. In order to reduce this turn-on loss, a high-speed diode is required as the diode 5, and similarly, high-speed diodes are also desirable for the other diodes. On the other hand, in a high voltage transistor, a resistor 3 is connected between the 0 base and the emitter, as shown in FIG. 1, in order to improve voltage resistance characteristics and stability. However, the connection of this resistor 3 has the effect of increasing the overall reverse recovery time trr. Now, the third
In the figure, when f'WL pressure is applied to the emitter junction of transistor l, with emitter terminal E being positive and collector terminal C being negative, current not only flows from E through diode 2 to C, but also from E through resistor 3. transistor l
The reverse direction of the transistor '
Due to the dL current amplification effect, E
Current flows from C to C.

つづいてCが正、Eが負の電圧が印加された場合には、
たとえダイオード2のtrrがきわめて短いとしてもト
ランジスタlのベースの蓄積キャリヤによってトランジ
スタlを通じてCからEへ電流が流れ、結果として全体
のtrrが長くなる。すなわちトランジスタの寄生効果
がtrrの増大をもたらす。この寄生効果を防止するた
め、Cを正、Eを負にした場合に同時にBと8間に逆ノ
(イアスすることが知られているが、逆バイアス用の別
電源が必要となり、ベース駆動回路も複雑になる欠点が
ある。
Next, when a voltage is applied where C is positive and E is negative,
Even if the trr of diode 2 is very short, the accumulated carriers at the base of transistor l will cause current to flow from C to E through transistor l, resulting in a longer overall trr. That is, the parasitic effect of the transistor causes an increase in trr. In order to prevent this parasitic effect, it is known that when C is made positive and E is made negative, a reverse voltage is applied between B and 8 at the same time, but a separate power supply for reverse bias is required, and the base drive The disadvantage is that the circuit becomes complicated.

本発明はこの欠点を除き、より簡単なやり方で逆並列ダ
イオードおよび抵抗接続のトランジスタの全体の逆回復
時間の増大を防止した半導体装置を提供することを目的
とする。
It is an object of the present invention to eliminate this drawback and provide a semiconductor device in which an increase in the overall reverse recovery time of anti-parallel diodes and resistor-connected transistors is prevented in a simpler manner.

この目的はトランジスタのベース、エミッタ間に抵抗と
、その抵抗に直列でベース、エミッタ接合に並列であり
、ベース、エミッタ間のえんmt圧より低いえん層電圧
を有するダイオードとを接続することによって達成され
る。そのようなダイオードとしては例えばショットキー
ノ(リヤダイオードを用いることが望ましい。
This purpose is achieved by connecting a resistor between the base and emitter of the transistor and a diode in series with the resistor and parallel to the base-emitter junction and having an emitter layer voltage lower than the base-emitter emitter pressure. be done. As such a diode, it is desirable to use, for example, a Schottchino diode (rear diode).

以下図を引用して本発明の実施例について説明する。第
4図においては、トランジスタlのベース、エミッタ間
に抵抗3のほかにベースからエミッタに向けて順方向の
ダイオード6が接続されている。ダイオード4には、例
えはショットキーノ(リヤダイオードを用いるので、そ
の臓電圧がトランジスタlのベース、エミッタ飽和電圧
V B B (s&t )より低いため、ベース端子B
からエミッタ端子Eヘベース電流が流れるとき、抵抗3
がベース、エミッタ間のそう大抵抗としてmき、Eを正
、Cを負とする電圧が印加されたときにはダイオード6
は抵抗3を通じてEからBへ流れる4冗を阻止するため
、トランジスタ寄生効果は起こらず、従ってtrrの増
大を防止できる。
Embodiments of the present invention will be described below with reference to the drawings. In FIG. 4, in addition to a resistor 3, a forward diode 6 is connected between the base and emitter of the transistor l from the base to the emitter. For diode 4, for example, a Schottkyno (rear diode) is used, so its internal voltage is lower than the base and emitter saturation voltage V B B (s&t) of transistor l, so that the base terminal B
When base current flows from emitter terminal E to emitter terminal E, resistor 3
is a very large resistance between the base and emitter, and when a voltage with E as positive and C as negative is applied, the diode 6
Since this blocks the current flowing from E to B through the resistor 3, transistor parasitic effects do not occur, and therefore an increase in trr can be prevented.

第5図はダーリントントランジスタに′!6ける実施例
で、この場合は少なくとも最終出力段トランジスタ11
のベース、エミッタ間抵抗31に直列lこショットキー
バリヤダイオード6を接続して、出力段トランジスタ1
10)trrの増大を防止する。
Figure 5 shows the Darlington transistor'! In this embodiment, at least the final output stage transistor 11
A Schottky barrier diode 6 is connected in series to the base-emitter resistor 31 of the output stage transistor 1.
10) Prevent increase in trr.

第4図、第5図の例でベース、エミッタ間に接続される
ダイオード6は必ずしもショットキーノくリヤダイオー
ドに限定されず、例えばシリコントランジスタlまたは
11に対してそのベース、エミッタ問えん層電圧より低
いえん層電圧を有するダイオード、例えばゲルマニウム
ダイオードも用いることができる。またトランジスタ1
がPNP トランジスタの場合にも実施でき、その場合
はダイオード2はコレクタからエミッタに向けて、ダイ
オード6はエミッタからベースに向けて順方向に接続さ
れる。
In the examples of FIGS. 4 and 5, the diode 6 connected between the base and the emitter is not necessarily limited to a Schottky-type rear diode. For example, the diode 6 connected between the base and the emitter is Diodes with low layer voltages, such as germanium diodes, can also be used. Also transistor 1
can also be implemented in the case of a PNP transistor, in which case diode 2 is connected in the forward direction from collector to emitter and diode 6 from emitter to base.

以上述べたように本発明はトランジスタのエミッタから
コレクター逆並列に高速ダイオードを接続シ、ベース、
エミッタ間に抵抗を接続する場合に、抵抗を通ずる′#
Itff、によって増大するベース電流に基づくトラン
ジスタ寄生効果により高速ダイ 5− オードを含めて全体としての逆回含時間が増加すること
を防止するため、ベース、エミッタ間の抵抗に直列にえ
ん層電圧の低いダイオードを接続してベース電流の増大
を防ぐもので、簡単な回路構成からなる半導体装置でP
WM方式によるモータ制御などに極めて有効に用いるこ
と−ができる。
As described above, the present invention connects a high-speed diode in antiparallel from the emitter to the collector of the transistor.
When connecting a resistor between emitters, pass through the resistor'#
In order to prevent the overall reverse recapture time including the fast diode from increasing due to transistor parasitic effects due to the base current increasing due to This is a semiconductor device with a simple circuit configuration that connects a low-voltage diode to prevent an increase in base current.
It can be used extremely effectively for motor control using the WM method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はトランジスタに付属のダイオードおよび抵抗が
接続された半導体装置の回路図、第2図はそのような半
導体装置を用いるトランジスタインバータの回路図、第
3図は第1図の半導体装置におけるトランジスタ寄生効
果の説明図、第4図は本発明に基づく半導体装置の一実
施例の回路図、第5図は別の実施例の回路図である。 ll1l・ トランジスタ、3,31 抵抗、6・・・
ダイオード。 υ、 イ(現(fI埋十山口 巖5.。 1、 6−
Fig. 1 is a circuit diagram of a semiconductor device in which a diode and a resistor attached to a transistor are connected, Fig. 2 is a circuit diagram of a transistor inverter using such a semiconductor device, and Fig. 3 is a circuit diagram of a transistor in the semiconductor device of Fig. 1. An explanatory diagram of parasitic effects, FIG. 4 is a circuit diagram of one embodiment of a semiconductor device based on the present invention, and FIG. 5 is a circuit diagram of another embodiment. ll1l Transistor, 3, 31 Resistor, 6...
diode. υ, I (currently fI 1, 6-

Claims (1)

【特許請求の範囲】 1)トランジスタのコレクタ、エミッタ間にエミッタ接
合に逆並列の高速度ダイオードを接続し−44−ス、エ
ミッタ間に抵抗と、該抵抗に直列でベース、エミッタ接
合に並列であり、ベース、エミッタ、間のえん層電圧よ
り低いえん層電圧を有するダイオードとを接続してなる
ことを特徴とする半導体装置。 2、特許請求の範囲第1項記載の装置に2いて、ダイオ
ードがショットキーバリヤダイオードであることを特徴
とする半導体装置。
[Claims] 1) A high-speed diode is connected in antiparallel to the emitter junction between the collector and emitter of the transistor, a resistor is connected between the emitter, and a resistor is connected in series with the resistor and the base is connected in parallel to the emitter junction. 1. A semiconductor device comprising: a base, an emitter, and a diode having an end layer voltage lower than the end layer voltage between the base and the emitter. 2. A semiconductor device according to claim 1, wherein the diode is a Schottky barrier diode.
JP20863581A 1981-12-23 1981-12-23 Semiconductor device Pending JPS58110072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20863581A JPS58110072A (en) 1981-12-23 1981-12-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20863581A JPS58110072A (en) 1981-12-23 1981-12-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58110072A true JPS58110072A (en) 1983-06-30

Family

ID=16559493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20863581A Pending JPS58110072A (en) 1981-12-23 1981-12-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58110072A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221261A (en) * 1985-07-16 1987-01-29 エツセ・ジ・エツセ・ミクロエレツトロニ−カ・エツセ・ピ・ア Driving element
US4965657A (en) * 1987-08-03 1990-10-23 Hitachi Ltd. Resin encapsulated semiconductor device
JP2010034312A (en) * 2008-07-29 2010-02-12 Rohm Co Ltd Semiconductor device and manufacturing method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221261A (en) * 1985-07-16 1987-01-29 エツセ・ジ・エツセ・ミクロエレツトロニ−カ・エツセ・ピ・ア Driving element
US4965657A (en) * 1987-08-03 1990-10-23 Hitachi Ltd. Resin encapsulated semiconductor device
JP2010034312A (en) * 2008-07-29 2010-02-12 Rohm Co Ltd Semiconductor device and manufacturing method therefor

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