CN113299732A - Semiconductor device, chip, apparatus and manufacturing method - Google Patents

Semiconductor device, chip, apparatus and manufacturing method Download PDF

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Publication number
CN113299732A
CN113299732A CN202010111560.XA CN202010111560A CN113299732A CN 113299732 A CN113299732 A CN 113299732A CN 202010111560 A CN202010111560 A CN 202010111560A CN 113299732 A CN113299732 A CN 113299732A
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doped region
silicon carbide
layer
doping
metal layer
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陈道坤
史波
曾丹
敖利波
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Priority to CN202010111560.XA priority Critical patent/CN113299732A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The disclosure provides a semiconductor device, a chip, equipment and a manufacturing method, and relates to the technical field of semiconductors. The semiconductor device includes: a silicon carbide substrate; a silicon carbide drift layer on the silicon carbide substrate, the silicon carbide drift layer including a first doped region having a first conductivity type, and a second doped region and a third doped region having a second conductivity type in the first doped region, wherein the second conductivity type is opposite to the first conductivity type, the third doped region is adjacent to the second doped region, and a doping concentration of the third doped region is less than a doping concentration of the second doped region; the first metal layer is connected with the second doping region; a first electrode connected to the first metal layer; and a second electrode on a side of the silicon carbide substrate remote from the silicon carbide drift layer. The semiconductor device has lower conduction voltage drop and stronger surge current resistance.

Description

Semiconductor device, chip, apparatus and manufacturing method
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a chip, a device, and a method of manufacturing the same.
Background
Silicon carbide (SiC) is one of the third generation wide bandgap semiconductors, and has excellent physical properties such as wide bandgap, high breakdown electric field, high thermal conductivity, high temperature resistance, high voltage resistance, and radiation resistance. Therefore, the SiC power device is very suitable for power electronic application systems with high temperature, high voltage, high power and the like, and has wide application prospect in the application fields of electric automobiles, photovoltaic inversion, rail transit, wind power generation, motor drive and the like.
A Silicon Carbide hybrid PiN/Schottky Diode (SiC MPS) is a known Silicon Carbide power Diode, which combines the advantages of a Schottky Barrier Diode (SBD) and a PiN Diode, and has the characteristics of low turn-on voltage, low reverse leakage, high switching frequency, strong surge resistance, and the like. Here, the Pin structure means a P +/N-/N + structure, and i means an N-layer with a low doping concentration.
Disclosure of Invention
The technical problem that this disclosure solved is: a semiconductor device is provided for use as a silicon carbide power diode.
According to an aspect of the present disclosure, there is provided a semiconductor device including: a silicon carbide substrate; a silicon carbide drift layer on the silicon carbide substrate, the silicon carbide drift layer including a first doped region having a first conductivity type, and a second doped region and a third doped region in the first doped region having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type, the third doped region is contiguous with the second doped region, and a doping concentration of the third doped region is less than a doping concentration of the second doped region; the first metal layer is connected with the second doping region; a first electrode connected to the first metal layer; and a second electrode on a side of the silicon carbide substrate remote from the silicon carbide drift layer.
In some embodiments, the third doped region surrounds the second doped region, the third doped region being contiguous with the first doped region.
In some embodiments, the silicon carbide drift layer has a recess exposing at least a portion of the second doped region, the first metal layer being located within the recess.
In some embodiments, the silicon carbide drift layer further comprises: a fourth doped region in the first doped region, wherein the fourth doped region surrounds the second doped region and the third doped region on a plane parallel to an upper surface of the silicon carbide drift layer, the fourth doped region is spaced apart from the second doped region and the third doped region, and the fourth doped region has a same conductivity type as the third doped region.
In some embodiments, the doping concentration of the fourth doping region is the same as the doping concentration of the third doping region.
In some embodiments, the semiconductor device further comprises: a second metal layer between the silicon carbide substrate and the second electrode.
In some embodiments, the semiconductor device further comprises: a first passivation layer on the silicon carbide drift layer and the first electrode; and a second passivation layer covering the first passivation layer, the second passivation layer having an opening exposing at least a portion of the first electrode.
In some embodiments, the first electrode comprises: a third metal layer on the silicon carbide drift layer, wherein the third metal layer is connected to the first metal layer; and a fourth metal layer on the third metal layer.
In some embodiments, the first doped region has a doping concentration less than a doping concentration of the third doped region.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type.
According to another aspect of the present disclosure, there is provided a chip including: a semiconductor device as described hereinbefore.
According to another aspect of the present disclosure, there is provided an apparatus comprising: a chip as described hereinbefore.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a silicon carbide drift layer on a silicon carbide substrate, wherein the silicon carbide drift layer includes a first doped region having a first conductivity type; performing a first doping of the silicon carbide drift layer to form a second doped region having a second conductivity type in the first doped region, wherein the second conductivity type is opposite the first conductivity type; performing a second doping of the silicon carbide drift layer to form a third doped region having the second conductivity type, wherein the third doped region is adjacent to the second doped region, and wherein a doping concentration of the third doped region is less than a doping concentration of the second doped region; forming a first metal layer connected with the second doped region; and forming a second electrode on one side of the silicon carbide substrate far away from the silicon carbide drift layer, and forming a first electrode connected with the first metal layer.
In some embodiments, the step of performing a first doping of the silicon carbide drift layer comprises: forming a patterned mask layer on the silicon carbide drift layer, the mask layer having a first opening exposing a portion of the first doped region; and performing first doping on the exposed portion of the first doped region through the first opening to form the second doped region.
In some embodiments, before performing the second doping, the manufacturing method further includes: and etching the silicon carbide drift layer through the first opening to form a groove, wherein the first metal layer is formed in the groove.
In some embodiments, performing a second doping of the silicon carbide drift layer comprises: etching the mask layer to enlarge the first opening; and performing second doping on the silicon carbide drift layer through the enlarged first opening to form a third doped region, wherein the third doped region surrounds the second doped region, and the third doped region is adjacent to the first doped region; after forming the third doped region, the manufacturing method further includes: and removing the mask layer.
In some embodiments, during the etching of the mask layer, a second opening exposing another portion of the first doped region is further formed, wherein the second opening surrounds the first opening on a plane parallel to the upper surface of the silicon carbide drift layer and is spaced apart from the first opening; the manufacturing method further includes: performing a third doping of the exposed other portion of the first doped region through the second opening to form a fourth doped region, wherein the fourth doped region surrounds the second doped region and the third doped region on a plane parallel to an upper surface of the silicon carbide drift layer, the fourth doped region is spaced apart from the second doped region and the third doped region, and a conductivity type of the fourth doped region is the same as a conductivity type of the third doped region.
In some embodiments, the second doping and the third doping are the same doping process.
In some embodiments, the first doping is a first ion implantation; wherein the conditions of the first ion implantation include: the impurity ions to be implanted include at least one of aluminum ions and boron ions, the implantation energy is 30keV to 400keV, and the total dose of implantation is 5 x 1014cm-2To 5X 1015cm-2(ii) a The first ion implantation is a single-step ion implantation process or a multi-step ion implantation process; the second doping is a second ion implantation process; the conditions of the second ion implantation process include: the impurity ions to be implanted include at least one of aluminum ions and boron ions, the implantation energy is 30keV to 550keV, and the total implantation dose is 1 x 1013cm-2To 5X 1014cm-2(ii) a The second ion implantation process is a single-step ion implantation process or a multi-step ion implantation process.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type.
In some embodiments, after removing the mask layer and before forming the first metal layer, the method of manufacturing further comprises: forming a protective layer on the silicon carbide drift layer; and performing an activation process on the dopants of the second, third and fourth doped regions at a temperature range of 1500 ℃ to 1900 ℃; and removing the protective layer after performing the activation process.
In some embodiments, the step of forming the first metal layer comprises: depositing a first metal layer on one side of the silicon carbide drift layer far away from the silicon carbide substrate, wherein the first metal layer fills the groove; performing at least one of etching and chemical mechanical planarization on the first metal layer to remove a portion of the first metal layer outside the groove and to retain a portion of the first metal layer inside the groove; and performing a first anneal on the first metal layer.
In some embodiments, the step of forming the second electrode comprises: forming a second metal layer on the back surface of the silicon carbide substrate; performing a second anneal on the second metal layer; and forming a second electrode on the side of the second metal layer far away from the silicon carbide substrate after the second annealing is carried out.
In some embodiments, the first anneal and the second anneal are the same anneal process.
In some embodiments, the method of manufacturing further comprises: forming a first passivation layer on the silicon carbide drift layer and the first electrode; patterning the first passivation layer to form a third opening exposing at least a portion of the first electrode; forming a second passivation layer on the first passivation layer and the exposed portion of the first electrode, the second passivation layer covering the third opening; and patterning the second passivation layer to form a fourth opening exposing at least a portion of the first electrode, wherein the fourth opening is inside the third opening.
In the above embodiments, there is provided a semiconductor device used as a silicon carbide power diode. The semiconductor device includes a silicon carbide substrate and a silicon carbide drift layer on the silicon carbide substrate. The silicon carbide drift layer includes a first doped region having a first conductivity type, and second and third doped regions having a second conductivity type in the first doped region. The second conductivity type is opposite to the first conductivity type. The third doped region is adjacent to the second doped region. The doping concentration of the third doping area is less than that of the second doping area. The semiconductor device further includes: the first metal layer is connected with the second doping region; a first electrode connected to the first metal layer; and a second electrode on a side of the silicon carbide substrate remote from the silicon carbide drift layer. The semiconductor device has lower conduction voltage drop and stronger surge current resistance.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a cross-sectional schematic view illustrating a semiconductor device according to some embodiments of the present disclosure;
FIG. 2 is a cross-sectional schematic view illustrating semiconductor devices according to further embodiments of the present disclosure;
fig. 3 is a top view illustrating various doped regions of a semiconductor device according to some embodiments of the present disclosure;
fig. 4 is a flow chart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;
fig. 5-16 are cross-sectional schematic diagrams illustrating structures at several stages in the fabrication of semiconductor devices according to further embodiments of the present disclosure.
It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be intervening devices between the specific device and the first device or the second device. When a particular device is described as being coupled to other devices, that particular device may be directly coupled to the other devices without intervening devices or may be directly coupled to the other devices with intervening devices.
All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
One of the main parameters of SiC MPS is the forward conduction voltage drop (Vf). This forward conduction voltage drop affects the operating losses of the device. The low conduction voltage drop is beneficial to reducing the working loss, reducing the heating and reducing the heat dissipation requirement of the power system. The inventors of the present disclosure found that this forward on-state voltage drop is mainly related to the P-type implant concentration in the SiC MPS active region, the P/N ratio, the schottky barrier, the drift region doping concentration and thickness, the substrate thickness.
In addition, the inventors of the present disclosure have also found that the maximum surge current that SiC MPS can withstand is related to the P-type implant concentration in the active region and the ohmic contact formed thereon, the higher the P-type implant concentration, the easier it is to form the ohmic contact, and the stronger the surge resistance. However, an excessively high P-type implant concentration decreases the forward conduction capability, increases the forward conduction voltage drop, and decreases the reverse breakdown voltage. This is because the higher the P-type injection concentration is, the wider the space charge region is, so that the forward conduction path is narrower, and therefore the forward voltage drop increases; the higher the P-type implantation concentration, the larger the built-in electric field is formed, so that the reverse breakdown voltage is reduced.
In view of this, the present disclosure provides a semiconductor device used as a silicon carbide power diode, so that the semiconductor device achieves low turn-on voltage drop and strong surge current resistance as much as possible.
Fig. 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. For example, the semiconductor device may be a silicon carbide power diode. The structure of a semiconductor device according to some embodiments of the present disclosure is described in detail below in conjunction with fig. 1.
As shown in fig. 1, the semiconductor device includes: a silicon carbide substrate 101, and a silicon carbide drift layer 102 on the silicon carbide substrate 101. For example, the silicon carbide drift layer may have a thickness of 5 μm to 100 μm.
The silicon carbide drift layer 102 may include a first doped region 111 having a first conductivity type, and a second doped region 112 and a third doped region 113 having a second conductivity type in the first doped region 111. Here, the second conductivity type is opposite to the first conductivity type. The third doped region 113 is adjacent to the second doped region 112. The doping concentration of the third doping region 113 is less than the doping concentration of the second doping region 112.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. For example, the first doped region 111 may be an N-doped region with a low doping concentration, the second doped region 111 is a heavily doped P + doped region, and the third doped region 113 is a P-doped region with a medium doping concentration. For example, a portion of the first doped region 111, the second doped region 112, and the third doped region 113 may together serve as an active region.
In some embodiments, the doping concentration of the first doping region 111 is less than the doping concentration of the third doping region 113.
In some embodiments, the doping concentration of the first doping region 111 may be 1 × 1015cm-3To 5X 1016cm-3. For example, the doping concentration of the first doping region 111 may be 2 × 1015cm-3、5×1015cm-3Or 1X 1016cm-3And the like. In some embodiments, the doping concentration of the second doping region 112 may be 5 × 1018cm-3To 1X 1020cm-3. In some embodiments, the doping concentration of the third doped region 113 may be 1 × 1017cm-3To 5X 1018cm-3。
In some embodiments, the silicon carbide substrate may have a first conductivity type. For example, the silicon carbide substrate is an N-type silicon carbide substrate. In some embodiments, the silicon carbide substrate may have a doping concentration of 1 × 1018cm-3To 5X 1019cm-3。
As shown in fig. 1, the semiconductor device further includes: a first metal layer 121 connected to the second doped region 112. For example, the first metal layer 121 may serve as an ohmic contact metal layer for the second doping region (e.g., P + doping region).
In some embodiments, the material of the first metal layer 121 may include at least one of titanium (Ti), nickel (Ni), and aluminum (Al). For example, the first metal layer may be a Ti layer, a Ni layer, a Ti/Al layer (a titanium layer and an aluminum layer), a Ni/Al layer (a nickel layer and an aluminum layer), or a Ti/Ni/Al layer (a titanium layer, a nickel layer and an aluminum layer), etc. In some embodiments, the thickness of the first metal layer 121 may be 10nm to 500 nm.
As shown in fig. 1, the semiconductor device further includes: and a first electrode 131 connected to the first metal layer 121. For example, the first electrode 131 may be an anode.
In some embodiments, the material of the first electrode may include at least one of titanium, nickel, aluminum, tungsten (W), and molybdenum (Mo). For example, the first electrode may be a Ti/Al layer, a Ni/Al layer, or a Ti/Ni/Al layer. In some embodiments, the thickness of the first electrode may be 2 μm to 5 μm.
As shown in fig. 1, the semiconductor device further includes: a second electrode 132 on a side of the silicon carbide substrate 101 remote from the silicon carbide drift layer 102. The second electrode 132 is on the back surface of the silicon carbide substrate 101. For example, the second electrode may be a cathode.
In some embodiments, the material of the second electrode may include at least one of titanium, nickel, silver (Ag), and aluminum. For example, the second electrode may be a Ti/Ni/Ag layer (titanium, nickel and silver) or a Ti/Al/Ni/Ag layer (titanium, aluminum, nickel and silver). In some embodiments, the thickness of the second electrode may be 0.5 μm to 4 μm.
Thus, a semiconductor device according to some embodiments of the present disclosure is provided. The semiconductor device includes a silicon carbide substrate and a silicon carbide drift layer on the silicon carbide substrate. The silicon carbide drift layer includes a first doped region having a first conductivity type, and second and third doped regions having a second conductivity type in the first doped region. The second conductivity type is opposite to the first conductivity type. The third doped region is adjacent to the second doped region. The doping concentration of the third doping area is less than that of the second doping area. The semiconductor device further includes: the first metal layer is connected with the second doping region; a first electrode connected to the first metal layer; and a second electrode on a side of the silicon carbide substrate remote from the silicon carbide drift layer. In the silicon carbide drift layer of the semiconductor device, the third doping region with medium doping concentration is adjacent to the second doping region with heavy doping concentration, and the first metal layer is used as an ohmic contact metal layer to be connected with the second doping region, so that the semiconductor device can realize low conduction voltage drop and strong surge current resistance.
The inventors of the present disclosure have found that in a silicon carbide device (e.g., a silicon carbide power diode), if the active region in contact with the anode is only a P-type doped region of moderate doping concentration, the on-voltage drop of such a silicon carbide device is relatively low, the reverse withstand voltage is relatively high, but the surge current resistance is relatively weak; if the active region is only a P-type doped region with high doping concentration (i.e., a heavily doped P + doped region), the on-state voltage drop of such a silicon carbide device is relatively high, the reverse withstand voltage is relatively low, but the surge current resistance is relatively strong. In the semiconductor device (i.e., the silicon carbide device) of the present disclosure, the active region in contact with the anode (i.e., the first electrode) includes the adjacent P-type doped region (i.e., the third doped region) with the medium doping concentration and the heavily doped P + doped region (i.e., the second doped region), so that the low on-state voltage drop and the high reverse withstand voltage can be ensured as much as possible, and the strong surge current resistance can be ensured as much as possible.
In some embodiments, as shown in fig. 1, the third doped region 113 surrounds the second doped region 112, and the third doped region 113 is adjacent to the first doped region 111. In this embodiment, the third doped region with the medium doping concentration is located at the periphery of the heavily doped second doped region, so that the third doped region is adjacent to the first doped region of the silicon carbide drift layer, the silicon carbide device can have the capability of low on-state voltage drop and high reverse withstand voltage as much as possible, and the heavily doped second doped region is connected with the first metal layer serving as the ohmic contact metal layer, so that the silicon carbide device can have the stronger surge current resistance as much as possible.
In some embodiments, as shown in fig. 1, the silicon carbide drift layer 102 has a recess 120 that exposes at least a portion of the second doped region 112. The first metal layer 121 is located in the recess 120. For example, the silicon carbide drift layer 102 may have a plurality of recesses 120, with one first metal layer 121 within each recess 120. Here, the first metal layer is formed in the groove, and the first metal layer can be formed in a self-aligned etching mode without performing a photoetching process, so that the photoetching steps can be reduced, and the process complexity can be reduced.
Fig. 2 is a schematic cross-sectional view illustrating semiconductor devices according to further embodiments of the present disclosure. Fig. 3 is a top view illustrating various doped regions of a semiconductor device according to some embodiments of the present disclosure. The structure of semiconductor devices according to further embodiments of the present disclosure is described in detail below in conjunction with fig. 2 and 3. The semiconductor device is, for example, a silicon carbide power diode.
The semiconductor device shown in fig. 2 includes a silicon carbide substrate 101 and a silicon carbide drift layer 102, similarly to the semiconductor device shown in fig. 1. The silicon carbide drift layer 102 includes a first doped region 111, a second doped region 112, and a third doped region 113. As shown in fig. 2, the semiconductor device further includes a first metal layer 121, a first electrode 131, and a second electrode 132.
In some embodiments, as shown in fig. 2 and 3, the silicon carbide drift layer 102 may further include: a fourth doped region (which may also be referred to as a field limiting ring termination doped region) 214 in the first doped region 111. The fourth doped region 214 surrounds the second and third doped regions 112, 113 in a plane parallel to the upper surface of the silicon carbide drift layer 102 (i.e., the surface in contact with the first electrode 131). The fourth doped region 214 is spaced apart from the second doped region 112 and the third doped region 113. In some embodiments, the conductivity type of the fourth doped region 214 is the same as the conductivity type of the third doped region 113. For example, the fourth doped region 214 is a P-type doped region.
In some embodiments, as shown in fig. 2 and 3, the silicon carbide drift layer 102 may include a plurality of fourth doped regions 214. As shown in fig. 3, the fourth doped region has a ring shape, and surrounds the second doped region 112 and the third doped region 113. The fourth doped region can prevent an electric field at the periphery of the semiconductor device from being too concentrated, so that the breakdown voltage of the semiconductor device can be improved.
It should be noted that the "ring" described herein may be square, rectangular, circular, etc. The scope of the present disclosure is not limited to the particular shape of the rings disclosed herein.
In some embodiments, the doping concentration of the fourth doping region 214 is the same as the doping concentration of the third doping region 113. Therefore, the third doped region and the fourth doped region can be simultaneously formed in one doping process in the manufacturing process, so that the doping process steps are reduced, and the manufacturing is convenient.
In some embodiments, as shown in fig. 2, the semiconductor device may further include: a second metal layer 222 between the silicon carbide substrate 101 and the second electrode 132. The second metal layer can be used as an ohmic contact metal layer on the back surface of the substrate, so that the contact resistance is reduced.
In some embodiments, the material of the second metal layer 222 may include at least one of titanium, nickel, and aluminum. For example, the second metal layer may be a Ni layer, a Ti/Al layer, a Ti/Ni/Al layer, or the like. In some embodiments, the thickness of the second metal layer 222 may be 10nm to 500 nm.
In some embodiments, as shown in fig. 2, the semiconductor device may further include: a first passivation layer 241 on the silicon carbide drift layer 102 and the first electrode 131. For example, the first passivation layer 241 has an opening 253 (hereinafter may be referred to as a third opening) exposing at least a portion of the first electrode 131.
For example, the material of the first passivation layer 241 may include an oxide of silicon (e.g., SiO or SiO)2) Silicon nitride (SiN), and silicon oxynitride (SiON). For example, the thickness of the first passivation layer 241 may be 50nm to 2000 nm.
In some embodiments, as shown in fig. 2, the semiconductor device may further include: and a second passivation layer 242 covering the first passivation layer 241. The second passivation layer 242 has an opening 254 (hereinafter may be referred to as a fourth opening) exposing at least a portion of the first electrode 131. The opening 254 is interior to the opening 253. The second passivation layer can prevent the semiconductor device from being influenced by external environment, and the reliability of the semiconductor device is improved.
In some embodiments, the second passivation layer 242 may be a polyimide (abbreviated as PI) passivation layer. In some embodiments, the thickness of the second passivation layer 242 may be 1 μm to 5 μm.
In some embodiments, as shown in fig. 2, the first electrode 131 may include a third metal layer 223 on the silicon carbide drift layer 102. The third metal layer 223 is connected to the first metal layer 121. The third metal layer may serve as a schottky contact metal layer. The Schottky contact metal layer can enable the silicon carbide power diode to form a Schottky junction, and therefore the turn-on voltage of the device can be reduced. The first electrode 131 may further include a fourth metal layer 224 on the third metal layer 223. The fourth metal layer may serve as a thickened metal layer.
In some embodiments, the material of the third metal layer 223 includes: at least one of Ti, Ni, W, Mo and the like. The thickness of the third metal layer 223 ranges from 10nm to 500 nm.
In some embodiments, the material of the fourth metal layer 224 includes: al, Ti/Al, Ni/Al or Ti/Ni/Al, etc. The total thickness of the fourth metal layer 224 ranges from 2 μm to 5 μm.
Thus, semiconductor devices according to further embodiments of the present disclosure are provided. The semiconductor device is, for example, a silicon carbide power diode. The semiconductor device includes a silicon carbide substrate, a silicon carbide drift layer, a first electrode, a second electrode, and first and second passivation layers, and the like. The silicon carbide drift layer includes a first doped region, a second doped region, a third doped region, and a fourth doped region. A portion of the first doped region, the second doped region, and the third doped region may together serve as an active region. In addition, the silicon carbide epitaxial layer is formed with a recess. And filling metal in the groove, wherein the metal and the third doped region form ohmic contact. This can reduce contact resistance and provide device performance. In the semiconductor device, the doping concentration distribution of the active region is optimized, so that the semiconductor device can realize low conduction voltage drop and stronger surge current resistance.
In some embodiments of the present disclosure, a chip is also provided. The chip may include a semiconductor device as previously described (e.g., the semiconductor device shown in fig. 1 or fig. 2).
In some embodiments of the present disclosure, an apparatus is also provided. The device may comprise a chip as described previously. For example, the device may be an electric car device, a photovoltaic inverter device, a rail transit device, a wind power generation device, a motor drive device, or the like.
Fig. 4 is a flow chart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For example, the semiconductor device may be a silicon carbide power diode. As shown in fig. 4, the manufacturing method may include steps S402 to S410.
In step S402, a silicon carbide drift layer is formed on a silicon carbide substrate, wherein the silicon carbide drift layer includes a first doped region having a first conductivity type. For example, a silicon carbide drift layer is formed on a silicon carbide substrate by an epitaxial process.
In step S404, a first doping is performed on the silicon carbide drift layer to form a second doped region having a second conductivity type in the first doped region, wherein the second conductivity type is opposite to the first conductivity type. For example, the first conductivity type is N-type and the second conductivity type is P-type. For example, the first doping is an ion implantation process.
In step S406, a second doping is performed on the silicon carbide drift layer to form a third doped region having the second conductivity type, wherein the third doped region is adjacent to the second doped region, and the doping concentration of the third doped region is less than the doping concentration of the second doped region. For example, the second doping is an ion implantation process.
In step S408, a first metal layer connected to the second doped region is formed.
In step S410, a second electrode is formed on a side of the silicon carbide substrate away from the silicon carbide drift layer, and a first electrode connected to the first metal layer is formed.
Thus, methods of fabricating semiconductor devices according to some embodiments of the present disclosure are provided. The manufacturing method comprises the following steps: forming a silicon carbide drift layer on a silicon carbide substrate, wherein the silicon carbide drift layer includes a first doped region having a first conductivity type; performing a first doping of the silicon carbide drift layer to form a second doped region having a second conductivity type in the first doped region, wherein the second conductivity type is opposite to the first conductivity type; performing second doping on the silicon carbide drift layer to form a third doped region with the second conductivity type, wherein the third doped region is adjacent to the second doped region, and the doping concentration of the third doped region is smaller than that of the second doped region; forming a first metal layer connected with the second doped region; and forming a second electrode on the side of the silicon carbide substrate far away from the silicon carbide drift layer, and forming a first electrode connected with the first metal layer. The manufacturing method can enable the formed semiconductor device to achieve low conduction voltage drop and strong surge current resistance.
In some embodiments, the step of performing a first doping of the silicon carbide drift layer may comprise: forming a patterned mask layer on the silicon carbide drift layer, the mask layer having a first opening exposing a portion of the first doped region; and performing first doping on the exposed portion of the first doped region through the first opening to form a second doped region.
In some embodiments, before performing the second doping, the manufacturing method may further include: etching is performed on the silicon carbide drift layer through the first opening to form a groove. In the subsequent process of forming the first metal layer, the first metal layer is formed in the groove.
In some embodiments, performing the second doping of the silicon carbide drift layer may include: etching the mask layer to enlarge the first opening; and performing second doping on the silicon carbide drift layer through the enlarged first opening to form a third doped region. For example, the third doped region surrounds the second doped region, and the third doped region is adjacent to the first doped region.
In some embodiments, after forming the third doped region, the manufacturing method may further include: and removing the mask layer.
Fig. 5-16 and 2 are cross-sectional schematic diagrams illustrating structures at several stages in the fabrication of semiconductor devices according to further embodiments of the present disclosure. The following describes in detail the manufacturing process of the semiconductor device according to other embodiments of the present disclosure with reference to fig. 5 to 16 and fig. 2. The semiconductor device is, for example, a silicon carbide power diode.
First, as shown in fig. 5, a silicon carbide drift layer 102 is formed on a silicon carbide substrate 101, for example, by an epitaxial process. For example, the silicon carbide drift layer 102 may include a first doped region 111 of N-type. For example, in this step, the silicon carbide drift layer 102 may be formed, in which a part of the region is the first doped region 111; the entire area of the silicon carbide drift layer 102 may be the first doped region 111.
Next, as shown in fig. 6, a mask layer 610 is formed on the silicon carbide drift layer 102, for example, by a deposition process. The masking layer 610 is then etched using, for example, a dry etch process to form a patterned masking layer. The patterned mask layer 601 has a first opening 611 exposing a portion of the first doped region 111. For example, the mask layer 610 may have one or more first openings 611.
In some embodiments, the material of mask layer 610 may include SiO2And polycrystalline silicon. In some embodiments, the thickness of the mask layer may be 0.2 μm to 4 μm. For example, the thickness of the mask layer may be 1 μm or 3 μm.
Next, as shown in fig. 6, for example, a first doping 601 is performed on the exposed portion of the first doping region 111 through the first opening 611 using an ion implantation process (which may be referred to as a first ion implantation) to form a heavily doped P + second doping region. Here, the P + second doped region may be formed by ion implantation of a high dose P-type dopant.
In some embodiments, the first ion implantation may be a single-step ion implantation process or a multi-step ion implantation process.
In some embodiments, the conditions of the first ion implantation include: the impurity ions to be implanted include at least one of aluminum (Al) ions and boron (B) ions, the implantation energy may be 30keV to 400keV, and the total dose of implantation may be 5 x 1014cm-2To 5X 1015cm-2。
In some embodiments, when the first ion implantation is performed using a multi-step ion implantation process, the multi-step ion implantation may include: the method comprises a first step of ion implantation, a second step of ion implantation and a third step of ion implantation. For example, the implantation energy of the first step ion implantation may be 360keV and the implantation dose may be 5.0 × 1014cm-2(ii) a The implantation energy of the second step ion implantation may be 240keV and the implantation dose is 1.2 × 1015cm-2(ii) a The third step of ion implantation has an implantation energy of 80keV and an implantation dose of 4.6 × 1014cm-2。
Next, as shown in fig. 7, etching is performed on the silicon carbide drift layer 102 through the first opening 611 of the mask layer 610 to form a groove 120.
Next, as shown in fig. 8, etching is performed on the mask layer 610 to enlarge the first opening 611. Then, second doping 602 is performed on the silicon carbide drift layer 102 through the enlarged first opening 611, for example, using an ion implantation process (which may be referred to as second ion implantation) to form a P-type third doped region 113 of medium doping concentration. The third doped region 113 surrounds the second doped region 112. The third doped region 113 is adjacent to the first doped region 111. In some embodiments, the second doped region 112 is spaced apart from the first doped region 111 by the third doped region 113.
In the above embodiment, the second doping is a second ion implantation process. In some embodiments, the conditions of the second ion implantation process include: the implanted impurity ions include at least one of aluminum ions and boron ions, the implantation energy may be 30keV to 550keV, and the total implantation dose is 1 × 1013cm-2To 5X 1014cm-2. For example, the second ion implantation process is a single-step ion implantation process or a multi-step ion implantation process.
In some embodiments, as shown in fig. 8, during the etching of the mask layer 610, a second opening 612 exposing another portion of the first doping region 111 is also formed. The second opening 612 surrounds the first opening 611 in a plane parallel to the upper surface of the silicon carbide drift layer 102, and the second opening 612 is spaced apart from the first opening 611. For example, one or more second openings 612, each of which is ring-shaped surrounding the first opening, may be formed by etching.
In some embodiments, the method of manufacturing further comprises: as shown in fig. 8, third doping is performed on the exposed another portion of the first doped region 111 through the second opening 612, for example, by using an ion implantation process to form a fourth doped region 214. The fourth doped region 214 surrounds the second doped region 112 and the third doped region 113 in a plane parallel to the upper surface of the silicon carbide drift layer 102. The fourth doped region 214 is spaced apart from the second doped region 112 and the third doped region 113. The conductivity type of the fourth doped region 214 is the same as the conductivity type of the third doped region 113. For example, the first doped region 214 is a P-type doped region.
In some embodiments, the second doping and the third doping are the same doping process. For example, the second doping and the third doping may be performed by the same ion implantation 602. Therefore, the ion implantation times can be reduced, and the process is simplified.
For example, in the above step, the implanted ions include at least one of Al (aluminum) and B (boron).
Next, the mask layer 610 is removed.
Next, as shown in fig. 9, after removing the mask layer 610, the manufacturing method may further include: a protective layer 910 is formed on the silicon carbide drift layer 102. For example, the protective layer may be a carbon film.
In some embodiments, the carbon film may be prepared by photoresist carbonization or radio frequency sputtering. In some embodiments, the protective layer may have a thickness of 0.05 μm to 2 μm.
Next, an activation process is performed on the dopants of the second, third and fourth doped regions 112, 113 and 214. For example, the activation process may be performed on the dopants (e.g., P-type dopants) of the second, third, and fourth doped regions at a temperature range of 1500 ℃ to 1900 ℃. Because the protective layer is formed on the silicon carbide drift layer, silicon elements in the silicon carbide drift layer are not easy to volatilize in the process of activating the dopant at high temperature. The protective layer serves to protect the silicon carbide drift layer.
Next, as shown in fig. 10, after the activation process is performed, the protective layer 910 is removed.
Next, a first metal layer connected to the second doped region 112 is formed. The process of forming the first metal layer is described in detail below in conjunction with fig. 11 and 12.
As shown in fig. 11, a first metal layer 121 is deposited on the side of the silicon carbide drift layer 102 remote from the silicon carbide substrate 101. The first metal layer 121 fills the recess 120. For example, the first metal layer may be a Ti layer, a Ni layer, a Ti/Al layer, a Ni/Al layer, a Ti/Ni/Al layer, or the like.
Next, as shown in fig. 12, at least one of etching (e.g., an etching back process) and Chemical Mechanical Planarization (CMP) is performed on the first metal layer 121 to remove a portion of the first metal layer 121 outside the groove 120 and leave a portion of the first metal layer 121 inside the groove 120. In this step, since the first metal layer is etched in self-alignment through the groove, a photolithography step may not be performed, thereby reducing process complexity.
Next, a first annealing is performed on the first metal layer 121. Through the first annealing, the first metal layer may be formed into an ohmic contact metal layer. This can reduce contact resistance.
Thus, the first metal layer 121 is formed.
Next, a second electrode is formed on the side of the silicon carbide substrate 101 remote from the silicon carbide drift layer 102. The process of forming the second electrode is described in detail below in conjunction with fig. 13 and 14.
As shown in fig. 13, a second metal layer 222 is formed on the back surface of the silicon carbide substrate 101, for example, by a deposition process.
Next, a second anneal is performed on the second metal layer 222. Through the second annealing, the second metal layer may be formed into an ohmic contact metal layer. This can reduce contact resistance.
In some embodiments, the first anneal and the second anneal are the same anneal process. For example, the first metal layer and the second metal layer may be formed together as an ohmic contact metal layer through the same annealing process after forming the first metal layer located in the groove and the second metal layer on the back surface of the silicon carbide substrate. This can reduce the number of annealing processes, thereby simplifying the manufacturing process.
In some embodiments, the first anneal and the second anneal are both at a temperature in a range of 500 ℃ to 1100 ℃.
Next, as shown in fig. 14, after the second annealing is performed, a second electrode (e.g., cathode) 132 is formed on the side of the second metal layer 222 away from the silicon carbide substrate 101, for example, by a deposition process.
Thus, the second electrode 132 is formed.
Next, as shown in fig. 15, a first electrode 131 connected to the first metal layer 121 is formed. For example, the first electrode 131 may include: a third metal layer 223 on the silicon carbide drift layer 102 in contact with the first metal layer 121, and a fourth metal layer 224 on the third metal layer 223. The third metal layer 223 may serve as a schottky contact metal layer, for example.
In some embodiments, the third metal layer 223 may be formed on the silicon carbide drift layer 102 by a deposition process; then, a fourth metal layer 224 is formed on the third metal layer 223 through a deposition process; next, patterning is performed on the fourth metal layer 224 and the third metal layer 223 through photolithography and etching processes, thereby forming the first electrode 131 as shown in fig. 15.
In some embodiments, an annealing process may be performed on the third metal layer, thereby forming the third metal layer as a schottky contact metal layer. For example, the temperature of the annealing process may range from 300 ℃ to 600 ℃.
Next, as shown in fig. 16, a first passivation layer 241 is formed on the silicon carbide drift layer 102 and the first electrode 131, for example, by a deposition process. For example, the Deposition process includes, but is not limited to, PECVD (Plasma Enhanced Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), ALD (Atomic Layer Deposition), or the like.
Next, as shown in fig. 16, the first passivation layer 241 is patterned, for example, by photolithography and etching processes to form a third opening 253 exposing at least a portion of the first electrode 131.
Next, as shown in fig. 2, a second passivation layer 242 is formed on the first passivation layer 241 and the exposed portion of the first electrode 131, for example, by a deposition process. The second passivation layer 242 covers the third opening 253.
Next, as shown in fig. 2, the second passivation layer 242 is patterned, for example, by photolithography and etching processes to form a fourth opening 254 exposing at least a portion of the first electrode 131. The fourth opening 254 is inside the third opening 253.
Thus, methods of fabricating semiconductor devices according to other embodiments of the present disclosure are provided. In the manufacturing method, the concentration distribution of the dopant of the active region of the semiconductor device is optimized through two doping processes (first doping and second doping), so that the second doping region with high doping concentration is positioned in the middle of the third doping region with medium doping concentration, the forward conduction voltage drop of the formed semiconductor device can be reduced, and the surge current resistance of the semiconductor device is improved. In addition, in the manufacturing method, the first metal layer as the ohmic contact metal is formed in a self-aligned manner, so that the process complexity can be reduced.
Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (25)

1. A semiconductor device, comprising:
a silicon carbide substrate;
a silicon carbide drift layer on the silicon carbide substrate, the silicon carbide drift layer including a first doped region having a first conductivity type, and a second doped region and a third doped region in the first doped region having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type, the third doped region is contiguous with the second doped region, and a doping concentration of the third doped region is less than a doping concentration of the second doped region;
the first metal layer is connected with the second doping region;
a first electrode connected to the first metal layer; and
a second electrode on a side of the silicon carbide substrate away from the silicon carbide drift layer.
2. The semiconductor device of claim 1,
the third doped region surrounds the second doped region, and the third doped region is adjacent to the first doped region.
3. The semiconductor device of claim 1,
the silicon carbide drift layer has a recess exposing at least a portion of the second doped region, the first metal layer being located within the recess.
4. The semiconductor device of claim 1, wherein the silicon carbide drift layer further comprises:
a fourth doped region in the first doped region, wherein the fourth doped region surrounds the second doped region and the third doped region on a plane parallel to an upper surface of the silicon carbide drift layer, the fourth doped region is spaced apart from the second doped region and the third doped region, and the fourth doped region has a same conductivity type as the third doped region.
5. The semiconductor device of claim 4,
the doping concentration of the fourth doping area is the same as that of the third doping area.
6. The semiconductor device of claim 1, further comprising:
a second metal layer between the silicon carbide substrate and the second electrode.
7. The semiconductor device of claim 1, further comprising:
a first passivation layer on the silicon carbide drift layer and the first electrode; and
a second passivation layer covering the first passivation layer, the second passivation layer having an opening exposing at least a portion of the first electrode.
8. The semiconductor device of claim 1, wherein the first electrode comprises:
a third metal layer on the silicon carbide drift layer, wherein the third metal layer is connected to the first metal layer; and
a fourth metal layer on the third metal layer.
9. The semiconductor device of claim 1,
the doping concentration of the first doping area is smaller than that of the third doping area.
10. The semiconductor device according to any one of claims 1 to 9,
the first conductive type is an N type, and the second conductive type is a P type.
11. A chip, comprising: a semiconductor device as claimed in any one of claims 1 to 10.
12. An apparatus, comprising: the chip of claim 11.
13. A method of manufacturing a semiconductor device, comprising:
forming a silicon carbide drift layer on a silicon carbide substrate, wherein the silicon carbide drift layer includes a first doped region having a first conductivity type;
performing a first doping of the silicon carbide drift layer to form a second doped region having a second conductivity type in the first doped region, wherein the second conductivity type is opposite the first conductivity type;
performing a second doping of the silicon carbide drift layer to form a third doped region having the second conductivity type, wherein the third doped region is adjacent to the second doped region, and wherein a doping concentration of the third doped region is less than a doping concentration of the second doped region;
forming a first metal layer connected with the second doped region; and
and forming a second electrode on one side of the silicon carbide substrate far away from the silicon carbide drift layer, and forming a first electrode connected with the first metal layer.
14. The manufacturing method of claim 13, wherein performing a first doping of the silicon carbide drift layer comprises:
forming a patterned mask layer on the silicon carbide drift layer, the mask layer having a first opening exposing a portion of the first doped region; and
performing a first doping on the exposed portion of the first doped region through the first opening to form the second doped region.
15. The manufacturing method according to claim 14, wherein before the second doping is performed, the manufacturing method further comprises:
and etching the silicon carbide drift layer through the first opening to form a groove, wherein the first metal layer is formed in the groove.
16. The manufacturing method according to claim 15,
the step of performing a second doping of the silicon carbide drift layer comprises: etching the mask layer to enlarge the first opening; and performing second doping on the silicon carbide drift layer through the enlarged first opening to form a third doped region, wherein the third doped region surrounds the second doped region, and the third doped region is adjacent to the first doped region;
after forming the third doped region, the manufacturing method further includes: and removing the mask layer.
17. The manufacturing method according to claim 16,
in the process of etching the mask layer, forming a second opening exposing another part of the first doping region, wherein the second opening surrounds the first opening on a plane parallel to the upper surface of the silicon carbide drift layer, and the second opening is spaced from the first opening;
the manufacturing method further includes: performing a third doping of the exposed other portion of the first doped region through the second opening to form a fourth doped region, wherein the fourth doped region surrounds the second doped region and the third doped region on a plane parallel to an upper surface of the silicon carbide drift layer, the fourth doped region is spaced apart from the second doped region and the third doped region, and a conductivity type of the fourth doped region is the same as a conductivity type of the third doped region.
18. The manufacturing method according to claim 17,
the second doping and the third doping are the same doping process.
19. The manufacturing method according to claim 13,
the first doping is first ion implantation; wherein the conditions of the first ion implantation include: the impurity ions to be implanted include at least one of aluminum ions and boron ions, the implantation energy is 30keV to 400keV, and the total dose of implantation is 5 x 1014cm-2To 5X 1015cm-2(ii) a The first ion implantation is a single-step ion implantation process or a multi-step ion implantation process;
the second doping is a second ion implantation process; the conditions of the second ion implantation process include: the impurity ions to be implanted include at least one of aluminum ions and boron ions, the implantation energy is 30keV to 550keV, and the total implantation dose is 1 x 1013cm-2To 5X 1014cm-2(ii) a The second ion implantation process is a single-step ion implantation process or a multi-step ion implantation process.
20. The manufacturing method according to any one of claims 13 to 19,
the first conductive type is an N type, and the second conductive type is a P type.
21. The manufacturing method of claim 17, wherein after removing the mask layer and before forming the first metal layer, the manufacturing method further comprises:
forming a protective layer on the silicon carbide drift layer; and
performing an activation process on dopants of the second, third, and fourth doped regions at a temperature range of 1500 ℃ to 1900 ℃; and
after the activation process is performed, the protective layer is removed.
22. The manufacturing method of claim 15, wherein the step of forming the first metal layer comprises:
depositing a first metal layer on one side of the silicon carbide drift layer far away from the silicon carbide substrate, wherein the first metal layer fills the groove;
performing at least one of etching and chemical mechanical planarization on the first metal layer to remove a portion of the first metal layer outside the groove and to retain a portion of the first metal layer inside the groove; and
a first anneal is performed on the first metal layer.
23. The manufacturing method according to claim 22, wherein the step of forming the second electrode includes:
forming a second metal layer on the back surface of the silicon carbide substrate;
performing a second anneal on the second metal layer; and
and forming a second electrode on the side of the second metal layer far away from the silicon carbide substrate after the second annealing is carried out.
24. The manufacturing method according to claim 23,
the first annealing and the second annealing are the same annealing process.
25. The manufacturing method according to claim 13, further comprising:
forming a first passivation layer on the silicon carbide drift layer and the first electrode;
patterning the first passivation layer to form a third opening exposing at least a portion of the first electrode;
forming a second passivation layer on the first passivation layer and the exposed portion of the first electrode, the second passivation layer covering the third opening; and
performing patterning on the second passivation layer to form a fourth opening exposing at least a portion of the first electrode, wherein the fourth opening is inside the third opening.
CN202010111560.XA 2020-02-24 2020-02-24 Semiconductor device, chip, apparatus and manufacturing method Pending CN113299732A (en)

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Application publication date: 20210824