JP2006196775A - Jbs, its manufacturing method, and schottky barrier diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance a soft recovery characteristic by reducing the possibility of generation of a defect in a Schottky junction interface. <P>SOLUTION: In a JBS where a Schottky junction and a pn junction coexist, a plurality of p layers 104 are arranged to be spaced from each other by a predetermined distance in an n-layer 103 inside of a guard ring 105, heavy metal is diffused from part of the surface of the guard ring 105 and from part of the surfaces of the plurality of p layers 104, and heavy metal is not diffused from the surface of the n-layer 103. More specifically, as an example, heavy metal is diffused from the surface of the guard ring 105 and is not diffused from the surfaces of the p layers 104 inside the guard ring 105. Or, as another example, heavy metal is diffused from part of the surfaces of the p layers 104 arranged inside the guard ring 105, and is not diffused from the surface of the guard ring 105. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a JBS (Junction Barrier Controlled Schottky) in which a Schottky junction and a PN junction coexist, and a method for manufacturing the same. In particular, the possibility of causing a defect at a Schottky junction interface can be reduced and soft recovery can be performed. The present invention relates to a JBS capable of improving characteristics and a manufacturing method thereof.

  Furthermore, the present invention relates to a Schottky barrier diode having a Schottky junction, and in particular, the Schottky barrier that can reduce the risk of defects at the Schottky junction interface and can improve soft recovery characteristics. It relates to a diode.

  Specifically, the present invention relates to a JBS and a manufacturing method thereof, and a Schottky barrier diode capable of increasing a switching speed and improving performance. More particularly, the present invention provides a device that does not adversely affect the SBD (Schottky Barrier Diode) interface characteristics when introducing a heavy metal such as Pt or Au as a lifetime killer into the device. The present invention relates to a JBS, a manufacturing method thereof, and a Schottky barrier diode that can reduce the reverse recovery time trr of the overall characteristics, maintain soft recovery, and do not impair forward voltage drop VF characteristics.

  The description of the basic structure of JBS has been around for a long time. For example, in Non-Patent Document 1 (BJ Baliga's book “Modern Power Devices”), Chapter 8, Section 4 (8.4 JBS Rectifiers), Almost all of them are put together. More specifically, reference 26 (BJ Baliga, “The pinch rectifier: A low forward drop, high speed power diode,” “IEEE Electron Device Letter 5, EDL-LET. 196 (1984)) (hereinafter referred to as “Non-Patent Document 2”) and Document 27 (BJ Baliga, “Analysis of junction controlled Schottky rectifier charactoristics, 109-Solid Stol. (1985)) (hereinafter referred to as “Non-Patent Document 3”).

  FIG. 38 is shown in FIG. 8.26. FIG. FIG. 38A shows a forward bias state mode, and FIG. 38B shows a reverse bias state mode. Baliga describes the features of the JBS rectifier in Non-Patent Document 1 and Non-Patent Document 2.

  The JBS rectifier is called “pinch rectifier” (pinch rectifier) in Non-Patent Document 2, and has a low VF (Forward Voltage Drop) characteristic SBD (Schottky barrier diode) and a (grid-like) PN junction. It is defined as being integrated in the drift region of the JBS rectifier.

  Baliga further noted that SBDs fabricated with a barrier height of 0.7 eV or less exhibit extreme soft breakdown characteristics that can lead to device failure, so that the depletion layer never pinches off at zero volt forward bias conditions. If a PN junction grid is designed with care and is installed in the JBS structure, a plurality of (multiple) conduction channels are included under the SBD interface, and the forward direction in the forward bias state is passed through these channels. It is mentioned that a current path is secured.

  Baliga explained that when a positive bias is applied to the N + substrate side, that is, when a reverse bias is applied to the JBS element, the PN junction and the SB surface are reverse biased. If the PN junction grid structure of the JBS rectifier is well designed so that the depletion layer closes under the SB interface, it can be spread between the depletion layers even with a reverse bias of only 2 to 3 (V). It mentions that it can cause a pinch-off. Furthermore, Baliga said that after the pinch-off is achieved, the depletion layer forms a potential barrier in the channel, and the depletion layer further extends to the N + substrate side even when a further reverse bias voltage is applied, It is said that it will support higher applied reverse voltage.

  Furthermore, Baliga said that due to the shielding effect of the potential barrier, the JBS rectifier has a problem of a decrease in SBD barrier height ΦB, which has been a problem in the conventional JBS, and an increase in leakage current (during high temperature and high reverse bias). It is said that it will be possible to operate to a normal avalanche breakdown voltage without causing thermal runaway (thermal runaway).

  Furthermore, Baliga notes that as a result, barrier materials with lower ΦB (greater leakage current than equol), which could not be used before, will also be usable.

  Even in Japan, the JBS structure has attracted attention for a long time, and the contents thereof are disclosed in, for example, Patent Document 1 (Japanese Patent Publication No. 59-35183). Patent Document 1 also aims to provide an SBD that can reduce the reverse current and increase the maximum voltage in the reverse direction. The claim of Patent Document 1 describes that a PN junction region is arranged so as to suppress a reverse current flowing through the SB interface and the PN junction when the PN junction is reverse biased by a depletion layer generated on the PN junction surface. Therefore, the JBS rectifier described in Patent Document 1 is considered to have the same or similar structure as the JBS rectifier described in Non-Patent Document 1 and Non-Patent Document 2.

  39 is a diagram corresponding to FIG. 1 of Patent Document 1, and FIG. 40 is a diagram corresponding to FIG. 2 of Patent Document 1. 39 and 40, 1 is an N + type silicon layer, 2 is an N type silicon region, 3 is a silicon substrate, 4 is a P + type silicon region, 4a is a belt-like portion, 4b and 4c are coupling portions, 5 is an oxide film, 6 is an opening, 7 is a metal layer, and 8 is a metal electrode.

  Furthermore, as another example of the prior art of JBS, for example, there is one described in Patent Document 2 (Japanese Patent Publication No. 59-49714). FIG. 41 is a view corresponding to FIG. In FIG. 41, 11 is an n-type region, 12 is an n-type semiconductor region, 12 'is a region immediately below, 13 is a p-type region, 14 and 15 are electrodes, and 16 is an insulating layer. Patent Document 2 describes a structure for realizing a rectifying element having a gentle reverse recovery characteristic (a rectifying element having a so-called soft recovery characteristic). In the device described in Patent Document 2, a plurality of P-type layers are arranged with an interval within twice the diffusion length of holes (minority carriers) in the N-layer. Specifically, as shown in FIG. 41, the region (N− region) 12 ′ immediately below the insulating layer 16 is operated as a carrier accumulation region through which the main current does not pass. That is, since this portion contributes to the gentle recovery of the reverse current, soft recovery characteristics are obtained.

  As described above, in the device having the JBS structure, the SBD region that is the unipolar device portion and the PN junction that is the bipolar device portion are mixed. Originally, an SBD having no minority carrier accumulation time is an ultrahigh-speed device, and should have both low loss (low VF) and ultrahigh speed (short trr) characteristics.

  However, in order to obtain an SBD with a higher breakdown voltage, it is necessary to use a thicker N-layer at a lower concentration, and an SBD having such an N-layer has a higher ΦB. In addition to the necessity of using a barrier material, it is known that minority carrier injection accompanied by bipolar operation is further increased from the SBD interface itself.

  Above all, such a JBS structure inevitably involves the injection of minority carriers from the P-type layer that forms the PN junction, so that the SBD region and the PN junction region into the N− layer. The lifetime value of injected minority carriers will have to be optimized (during forward bias).

  In other words, this optimization means the time trr from the moment when the polarity of the rectifier (diode) is switched from the on mode to the off mode until it completely turns off, and the rectifier (diode) remains after being injected into the N− layer. It means the optimization that the holes injected into the N-layer have to be controlled so that the soft recovery characteristics are maintained with a shorter lifetime value of the holes. .

  For example, Non-Patent Document 4 ("NI (Nippon Inter) NEWS" Vol. 26, No. 2 pp. 10-11 (February 20, 2000) is known as a conventional technique for this high-speed and soft recovery operation. Published by Nippon Inter Co., Ltd.)) is known. By referring to this Non-Patent Document 4, the needs required for devices including peripheral circuit elements can be better understood.

  FIG. 42 is a diagram corresponding to FIG. FIG. 42 shows an example of analyzing the carrier state inside the diode in the reverse recovery operation. In FIG. 42, the horizontal axis indicates the depth (relative value), and the vertical axis indicates the concentration (relative value).

  In Chapter 2 Section 3 Section 3 of Non-Patent Document 1 mentioned above, in order to obtain the best device for optimizing the recombination level, the optimum position at the deep level and its capture cross section are selected. It describes the need to develop standards for.

In Formula 2.68 of Non-Patent Document 1,
Isc (leakage current in the space charge layer) = q (elementary charge) × A (area) × Wi (depletion layer width) / τsc (lifetime)
In the case of a unipolar device, in order to reduce the leakage current Isc in the space charge layer, the lifetime τsc of space charge generation (that is, inside the depletion layer) needs to be large. It can be said that there is. This is believed to be achieved by maintaining to prevent deep levels of impurities being introduced into the active region of the device. In other words, it is better not to introduce a lifetime killer.

  In the case of bipolar devices, on the other hand, in devices where some low level minority carrier injection occurs, it is necessary to introduce deep levels of recombination centers to speed up or control the device. It becomes. In order to achieve a high switching speed, a lifetime at a small, low level (ie, when there are only a few residual holes on the verge of toff) is highly desirable. Further, in order to achieve a high switching speed, it is considered that the recombination level should be located near the middle of the gap (energy gap, hand gap). In other words, it is considered essential to introduce a lifetime killer.

  In addition, the requirements in the case of unipolar devices and the requirements in the case of bipolar devices are conflicting demands on the recombination characteristics. Therefore, in order to resolve these contradictions, the theoretical for various lifetimes is required. Non-patent document 1 describes that consideration and examination are necessary.

  In other words, (1) In order to obtain a higher-performance SBD, it can be said that it is better not to use a lifetime killer in this area. (2) In order to obtain a higher-performance PN junction rectifier, a lifetime killer (to achieve high-speed switching) is present in this region, particularly when holes (minority carriers) remain at a low level just before toff. It can be said that the use of is indispensable. (3) When the inside of the device is viewed in the vertical direction, the existence of holes at t = t1 shown by the broken line in FIG. 42 is indispensable, and it can be said that this greatly contributes to soft recovery. (4) It can be said that the lifetime of residual holes (minority carriers) needs to be appropriately controlled as switching is completed more quickly.

  Non-Patent Document 1 discloses that a lifetime control method used for a power device includes a first method including thermal diffusion of impurities that show a deep level in a silicon energy gap, and collision between high-energy particles and a silicon wafer. It is described that there are two basic processes, a second method based on creating lattice defects in the form of vacancies or interstitial atoms.

  The first method is a method using heavy metals such as Au and Pt. In power devices, killer other than Au and Pt is unlikely to be used. Non-Patent Document 1 describes that the best overall properties of Au (low VF and faster switching time) can be obtained. For details, see FIG. According to 2.36, the ratio of space charge generation life time / high level life time (Hi-level Life-time ratio) is 2 to 3 orders of magnitude lower than Pt (platinum). Is described. In other words, Au always has a large leakage current during normal temperature to high temperature use (over the entire range of 240 to 500 ° K), that is, Au has a larger leakage current than Pt by two to three digits at room temperature and one digit or more at high temperatures. . For this reason, it is considered that Au is no longer used particularly when a high leak current is involved as in a device including SBD.

  Therefore, it is considered that only Pt is used when high leakage current is involved. As a conventional technique using Pt for a power device, for example, Non-Patent Document 5 (Electrical Society of Japan Material EDD-00-128 (SPC-00-107) PP. 53-57, Fuji Electric Nemoto et al.), Patent Document 3 (Japanese Patent Laid-Open No. 8-46221) and the like. Before describing these prior arts, the “U-type distribution of Pt thermally diffused in silicon” which is the basis for using Pt will be described.

  Regarding the U-type distribution of Pt, see, for example, Non-Patent Document 6 (YK Kwon, T. Ishikawa, and H. Kuwano, “Properties of Platinum-associated silicon in Silicon” J. Appl. Phys, 61, Phys. pp. 1055-1058, 1987).

  43 is shown in FIG. FIG. Specifically, FIG. 43 is a diagram showing a U-shaped distribution of Pt. More specifically, FIG. 43 shows the U-shaped distribution of Pt after 200 Ｐ of Pt is deposited only on the back side and diffused at 900 ° C. for 1 hour.

  44 is shown in FIG. FIG. Specifically, FIG. 44 is a diagram showing the distribution after long-time diffusion. More specifically, in FIG. 43 described above, it is a diagram showing a distribution after 1 hour, 5 hours, and 50 hours after Pt 900 ° C. diffusion at the Ec−0.23 (eV) level.

  FIG. 45 is shown in FIG. It is the figure which added the result of FIG. 43 to 2.34. In Non-Patent Document 1, as shown in FIG. 45, the levels of Pt are Ec−0.19 (eV) / PtI, Ec−0.32 (eV) / PtIII, Ev + 0.42 (eV) / PtII, Ev + 0.26 (eV) / PtI. On the other hand, Non-Patent Document 6 describes three recombination levels of Ec−0.23 (eV), Ec−0.52 (eV), and Ev + 0.36 (eV) as shown in FIG. Has been. In other words, regarding the recombination center level (deep level), the judgment of which is the correct value differs among researchers, and the results differ depending on the measurement method and so on. Conceivable.

  In any document, it is considered that Pt has a recombination center at a level of 0.2 to 0.5 (eV) deep from the bunt end.

  In Non-Patent Document 5 and Patent Document 3, it is not described which level of these is effectively used, and only the result indicated by the U-type distribution is used.

  The dominant level Ev + 0.42 (eV) of Pt in Non-Patent Document 1 is considered to be close to Ev + 0.36 (eV) in Non-Patent Document 6, and according to Non-Patent Document 6, it is an acceptor level. This is considered to be a deep level level obtained when N-type Si is used. On the other hand, in Non-Patent Document 6, it is predicted that this Ev + 0.36 (eV) will be an interstitial type.

  Diffusion of Pt (and heavy metal of Au) is low in the interstitial type but has a low concentration, the substitution type has a low diffusion rate but a high concentration diffusion, and Pt introduced as the interstitial type is There is a common theory that it becomes a substitution type, that is, it becomes a position exchange type in the process of annealing or the like, and only when it becomes a substitution type can be the center of recombination, that is, it can be effective for lifetime control. There are points that are not well understood.

  However, in Patent Document 3, since a bottom-bottom (U-type) distribution is actively used, as a conclusion, a lattice that functions as an acceptor level at a level of Ev + 0.36 to 0.42 (eV). It is considered that interstitial Pt atoms are introduced into the diffusion diffusion and eventually become a substitution type, and a recombination center effective for shortening the lifetime is formed in the device.

  Although there are still many unclear points in the method using Pt diffusion and including the thermal diffusion of the (Pt) impurity that shows a deep level in the energy gap of Si, in Non-Patent Document 5 and Patent Document 3, devices are actually prototyped. Since it has been experimentally demonstrated that good results have been obtained, there is no doubt that the use of Pt is still effective in actual device design and policy.

  In Non-Patent Document 5, soft recovery and high-speed, low-loss FWD, 1200V / 50A type MPS diode (Merged PiN / Schottky diode) is diffused with platinum, and soft recovery and low-loss characteristics are compared with conventional products. There are reports that trade-offs have improved.

  According to the report, in order to obtain soft recovery characteristics, (1) it is necessary that high-concentration carriers (holes) remain on the cathode side of the drift layer (N− layer) during the reverse recovery operation. In order to reduce the reverse recovery peak current (Irp), it is necessary to reduce the number of accumulated carriers on the anode side. (3) Actively utilizing the segregation effect on the wafer surface in platinum diffusion (see Non-Patent Document 6). In addition, it is described that the carrier distribution as shown in FIG. 46 was obtained as a result of intensively distributing platinum only on the anode side.

  FIG. 46 is a diagram corresponding to FIG. Specifically, FIG. 46 is a diagram showing the carrier distribution of the MPS diode in the forward state.

  Although the basic structure of the MPS diode and the basic structure of the JBS diode are similar, the MPS diode is used for high withstand voltage and high current, whereas the JBS diode is considered to be mainly used for medium withstand voltage and medium current.

  Table 6 is a table showing the surface pattern of the MPS diode described in Non-Patent Document 1. As shown in Table 6, a relatively large surface pattern is used in the MPS diode.

  FIG. 47 is a diagram corresponding to FIG. Specifically, FIG. 47 is a diagram showing a reverse recovery measurement waveform of the MPS diode. As shown in FIG. 47, the trr time in the trr waveform is on the order of about 500 (ns), and is considered to be a medium speed diode rather than a high speed. 46 and 47, for comparison with Pt, a comparison of carrier distribution with an electron beam (EI) is shown, and a comparison of trr waveforms is shown.

  Non-Patent Document 5 describes that the injection efficiency is lower when Pt is used than when EI is used, and the accumulated carrier concentration on the cathode side is also higher. It is described that the tail current is increased, the soft recovery is performed, and the trade-off is further improved.

  However, Non-Patent Document 5 does not describe in detail the process conditions of Pt, and the category of the device differs from that of the present invention described later, and therefore the category of trr differs from that of the present invention.

  FIG. 48 is a diagram corresponding to FIG. Specifically, FIG. 48A shows a first conductivity type first semiconductor region 21 having a low impurity concentration and a first conductivity type second semiconductor having a high impurity concentration adjacent to the first semiconductor region 21. A first conductivity type semiconductor layer composed of the semiconductor region 22, and a second conductivity type semiconductor layer 23 having a high impurity concentration formed by implanting a large amount of P conductivity type impurities into the first semiconductor region 21; The diode chip | tip provided with the pn junction 24 formed between the semiconductor region 21 and the semiconductor layer 23 is shown. FIG. 48B is a diagram for explaining the reverse recovery current of the diode having the diode chip as shown in FIG. 48A, and shows the time until the peak value of the reverse recovery current Ir is reached. Let t1 be the time from the time until the reverse recovery current Ir becomes zero. Further, the minority carrier amount at time t1 is Q1, and the minority carrier amount at time t2 is Q2. FIG. 48C is a diagram for explaining the doping of platinum. In FIG. 48, 25 is a cathode electrode, and 26 is an anode electrode.

  In Patent Document 3, in a high-speed recovery semiconductor device doped with Pt, the impurity concentration distribution (U-type or pan-bottom type distribution) of Pt in the depth direction as shown in FIG. As a result of the use, it is described that the lifetime near the PN junction is shorter than the lifetime inside the N-layer, and soft recovery characteristics are obtained.

  Further, Patent Document 3 describes that the depth of the PN junction should be about 1 to 15 μm in the range where the Pt concentration is higher.

  Further, in claim 4 of Patent Document 4 (Patent No. 3072753) related to Patent Document 3, Pt is doped from a partial surface area of the semiconductor region of the (P +) layer having a high impurity concentration. Is described.

  However, Patent Document 3 and Patent Document 4 describe that Pt thermal diffusion is performed at a temperature of about 850 ° C. to 900 ° C. with respect to the Pt diffusion treatment process, but details thereof are described. Absent.

  Next, consider the second method described above, that is, the second method based on the creation of lattice defects in the form of vacancies or interstitial atoms by collision of high-energy particles with a silicon wafer.

  Non-Patent Document 7 cited in Non-Patent Document 5 (N. Kaminski, N. Gaslster, S. Linder, C. Ng, and R. Francis, “1200V Merged PIN Schottky Diode with Soft Recovery and Positive” Proceedings of EPE'99 Lausanne, 1999) describes a technique related to a combination of MPS structure and He irradiation. In this regard, in Non-Patent Document 5, such a light ion irradiation technique is described as heat of Pt or the like. It is described that the manufacturing cost is still higher than that of the diffusion method.

In Patent Document 5 (Japanese Patent Laid-Open No. 5-102161), ³ He ²⁺ ions are accelerated at an energy of 1 MeV to 40 MeV and an irradiation amount of 1 × 10 ⁹ (1 / cm ² ) to 5 × 10 ¹³ (1 / cm ² ). After irradiation, heat treatment is performed at 300 to 400 ° C. to localize a low lifetime layer having a narrower half-value width, so that the irradiation dose can be reduced as compared with conventional proton ( ¹ H ⁺ ) irradiation. It is described that the problem of withstand voltage deterioration that has been a problem can be reduced, and that the effect of reducing the annealing temperature after irradiation is also obtained.

  However, basically, in the case of irradiation with such light ions, as described above, the device becomes more expensive than the heavy metal, and the manufacturing cost increases. In addition, there are many problems in controlling device characteristics due to variations in wafer (thickness) when localized (at a desired depth of the wafer) and variations in acceleration energy control. It is done.

  For the reasons described above, in a JBS diode having an SBD region and a PiN diode region in one device, diffusion of Pt is indispensable for switching speed control (shortening and soft recovery). Conceivable.

  Conventionally, in the heavy metal diffusion of a semiconductor device, in order to reduce the manufacturing process and suppress variation in characteristics, only the P + type anode region is selectively etched using, for example, a photoresist film. A method is known in which Pt is vapor-deposited on the entire surface, the photoresist film other than the opening is removed, and Pt remaining in the opening is thermally diffused into a semiconductor N-type semiconductor substrate. An example of this type of method is described in, for example, Japanese Patent Application Laid-Open No. 6-342799.

  FIG. 49 is a diagram corresponding to FIG. Specifically, FIG. 49 is a diagram for explaining the platinum diffusion process in Patent Document 6 in detail. In FIG. 49, 31 is an N-type semiconductor substrate, 32 is an N + type semiconductor region, 36 is a P + type anode region, 43 is a silicon oxide film, 45 is a photoresist film, and 46 is platinum.

  In Patent Document 6, the process as shown in FIG. 49 can be used to reduce the number of times of heat treatment, which is a Pt sintering process, which has been conventionally performed to one, resulting in process variations. Further, it is described that the problem that Pt and the silicon oxide film react on the silicon oxide film 43 can be avoided.

  However, in the technique described in Patent Document 6 and the technique described in Patent Document 3, the target device is a PiN diode, and the method of introducing Pt is to open a solid anode region, and from this opening, Pt is introduced. Therefore, the techniques described in Patent Document 6 and Patent Document 3 cannot be applied as they are to the JBS structure having the SBD region.

  When a heavy metal such as Pt or Au is introduced into an N-type substrate such as JBS having the surface of the SBD region, the temperature for forming a PN junction (1000 to 1200 ° C.), the diffusion temperature of heavy metal such as Pt (800 ˜950 ° C.) and the process temperature difference between the SBD junction formation temperatures (300 to 500 ° C.), there is a problem that an SBD junction must be formed after heavy metal diffusion. It is described in paragraph [0007] of Patent Document 7 (Japanese Patent Laid-Open No. 2004-55586) that it is difficult to ensure the cleanness of the surface of the N-type substrate at this time.

  As described above, originally, it is better not to use heavy metal diffusion such as Pt on the surface of the SBD region, while heavy metal diffusion is considered essential to the PN junction rectifier region. Nevertheless, due to the problems described in Patent Document 7, the use of Pt has been withheld on the SBD surface in JBS devices.

  In order to solve such a problem, it is considered necessary to provide a portion where Pt is introduced and a portion where Pt is not introduced in a part of the surface element. In that case, it is considered that a mask material for blocking Pt as described in Patent Document 6 is required. As this mask material, a silicon thermal oxide film is generally considered to be used.

  In the case of using a silicon thermal oxide film, it is considered necessary to confirm whether or not the silicon thermal oxide film has a mask (block) effect with respect to a desired Pt diffusion temperature. In addition, in the technologies in Non-Patent Document 5 and Patent Document 3, the application has been made on the assumption that the technical results in Non-Patent Document 6 are correct, but it is necessary to confirm the details of the U-shaped distribution of Pt. It is believed that there is.

  About these, the present inventors tried the following confirmation.

FIG. 50 is a diagram showing diffusion coefficients in silicon and SiO ₂ film, and FIG. 51 is a diagram showing U-type distribution of Pt into silicon. Table 7 is a table showing diffusion coefficients of heavy metals (Au, Pt) in Si and SiO ₂ , and Table 8 is a table showing the U-type distribution of Pt in silicon. Values of Do and E such as boron are described in, for example, Table 4 of the Japanese version of Non-Patent Document 8 (SM Sze, VLSI Technology, International Student Edition).

Table 9 is a table corresponding to Table 4 of the Japanese version of Non-Patent Document 8. Specifically, Table 9 shows a diffusion coefficient in SiO ₂ . Table 10 is a table corresponding to Table 5 of the Japanese version of Non-Patent Document 8. Specifically, Table 10 shows the diffusion coefficient, solid solubility, and distribution coefficient at the melting point of fast diffusing impurities in silicon.

  That is, Table 9 describes the values of Do and E for boron, gold 1, gold 2, and platinum, and Table 10 lists Do and E for Au, (Au) i, (Au) s, and Pt. The value of is described. In Table 7 and FIG. 50, these values were obtained in the range of the diffusion temperature (700 to 1000 ° C., that is, a general temperature range in which heavy metal diffusion is performed). It is known that the diffusion coefficient is given as D = Do · exp (−E · q / kT).

No. in Table 7 1-No. 6 is a diffusion coefficient in silicon. In Table 7, No. 7-No. 10 is a diffusion coefficient in the SiO ₂ film. No. related to Pt. 4 and no. 5, since E of Pt is in the range of 2.22 (eV) to 2.15 (eV), the range of min to max was obtained.

In FIG. 50, among Au in silicon, (Au) i means an interstitial type, (Au) s means a substitutional type, and Au means the whole Au. No. 7 (Au1) SiO ₂ and No. 7 For 8 (Au2) SiO _2, because of the slightly different values various reports, he had been given two values.

As shown in FIG. 50, at a temperature near the heavy metal diffusion temperature in silicon, the diffusion coefficient of (Au) i is fast, the diffusion coefficient of (Au) s is slow, and the diffusion coefficient of Au (whole) is as follows: It can be said that it is a value close to the diffusion coefficient of Pt. It can be said that the diffusion coefficient of boron (B) has almost the same value in silicon and SiO ₂ film. In other words, the diffusion coefficient (speed) when forming the P + layer region in silicon and when diffusing in the SiO ₂ film, that is, when the SiO ₂ film has a required film thickness for blocking boron. It can be said that the speed is almost the same.

As further shown in FIG. 50, in the silicon oxide film, (Au1) diffusion coefficient of SiO ₂ is in the value of the relatively large (faster) but, (Au2) diffusion coefficient of SiO ₂ is (Pt) It can be said that the value is almost the same as the diffusion coefficient of SiO ₂ . Moreover, it can be said that the value of the diffusion coefficient of (Pt) SiO ₂ is at least smaller than the value of the diffusion coefficient of (B) SiO ₂ . In other words, if there is a thickness of the SiO ₂ film that can block boron (B) as a familiar P-type impurity source, (Pt) SiO ₂ in the SiO ₂ film having a smaller diffusion coefficient than that, That is, it can be said that Pt can always be blocked.

Next, consider the U-type distribution of Pt in silicon. Table 8 shows the coordinates of each of the two types of data (circle point (Ec−0.23 eV (acceptor level / N type Si)) and Δ point (Ev + 0.36 eV (donor level / P type Si)) in FIG. X axis: depth (μm), Y axis: Log axis contention (1 / cm ³ )) are read and input.

Subsequently, an experimental formula (approximate formula) passing through points P1, P2, P3, P4, P5, and P6 in Table 8 was obtained. As a result, by using the diffusion coefficients of Pt in Table 7 and FIG. 50, the diffusion equation of the usual impurities (erfc; complementary error function (for deposition) or gauss function (-x ² square of e) (for drive-in )), It is impossible to approximate at all because, as shown in Fig. 52, these functions are always displayed when displayed as X-axis (linear) and Y-axis (Log axis). This is because the U-shaped distribution (pan-bottom distribution) of Pt in silicon is always convex downward as shown in FIGS. 43 and 51. 52 is a diagram for studying an approximate expression.

That is, in order to approximate the points P1, P2, P3, P4, P5, and P6 in Table 8, it is necessary to define a completely different function type (from the function type used in the diffusion equation). It is believed that there is. Study result, as shown in FIG. 51, is bent significantly at around 30 [mu] m, 0 <close to the range of x ≦ 30 [mu] m is substantially linear, for a base of y = ^b-ax α type, further slightly lower therewith In order to give a dent, it was set as y = b-ax ^α + c type. Here, a is the surface temperature, α is the degree of bending of the dent, and c is the amount corresponding to the rising of the pan bottom, corresponding to the broken line curve in the range of 0 <x ≦ 30 μm in FIG. As a result, within the range of 0 <x ≦ 30 μm,
^{F1 (x) ≒ 2.91E14- (4.51E13} ) · x 0.52 + (3E9) (150-x) 2 ··· Formula 1
I was able to define.

On the other hand, in the range of x> 30 μm, it can be approximated by y = a (150−x) ² + b type, ie, a graph of a quadratic function having a min point at x = 150 μm. As a result of examining the coefficients a and b in the range of x> 30 μm, in the range of x> 30 μm,
F2 (x) ≈ (2E9) (150−x) ² + (3.8E13) Equation 2
I was able to define.

  The value of F (x) corresponding to each x point was obtained from Equation 1 and Equation 2, shown in Table 8, and plotted with ◇ points in FIG. Since the number of source data in FIG. 43 is small, the deviation between the data and F (x) is large in the vicinity of x = 30 μm, but the U-type (pan bottom type) distribution can be approximated by Equations 1 and 2. it is conceivable that.

Specific resistance P type wafers 13 to 15 (Ω · cm) → 14 (Ω · cm) /9.34E14 (1 / cm ² ), N type wafers 1 to ² (Ω · cm) → 1 (Ω · cm) shown in FIG. cm) /4.8E15, 2 (Ω · cm) → 2.35E15 (1 / cm ² ), the following was found. (1) On the silicon surface, the Pt concentration is about an order of magnitude less than that of the N-substrate. (2) About two orders of magnitude less in the deep part from the surface of the pan bottom. (3) The portion where the Pt concentration is high is approximately 30 μm (at the time of 900 ° C./1 h diffusion) from the surface.

  Next, the U-type distribution concentration shown in FIG. 51 and the contents described in Section 2.3.3 of Non-Patent Document 1 will be collated, compared, and confirmed. Section 2.3.3 of Non-Patent Document 1 describes the compensation effect that becomes a problem when deep level impurities (Pt) approach the N-concentration of the material wafer. It is described that this effect causes a change in the free electron concentration in the conductor, resulting in an increase in the resistivity of the N-layer, which has a serious breakdown voltage and current conduction impact. . However, Section 2.3.3 of Non-Patent Document 1 describes only the value close to the N-concentration (background resistance) of the material wafer, and does not describe what value / ratio it will be. .

  Therefore, as a precaution, the changes in concentration and VBO in the N-type 1-2 (Ω · cm) experimental wafer used in Non-Patent Document 6 were confirmed. Table 11 shows the change in VBO according to the N-layer concentration of N-type 1 to 2 (Ω · cm) in Non-Patent Document 6. FIG. 53 is a view showing the relationship between ρ (Ω · cm) and VBO (V) in Table 11.

  As shown in FIG. 53, when the value of ρ is about 1.0 (Ω · cm), when the value of ρ is changed by 20%, the value of VBO is changed by about 15%, and the value of ρ is about In the case of about 2.0 (Ω · cm), when the value of ρ changes by 10%, the value of VBO changes by a little less than 10%. Overall, it can be said that when the value of ρ changes by 10%, the value of VBO changes by about 10%.

  From the above, it is considered that the “serious effect” described in Non-Patent Document 1 is a case where there is a change of at least about 10% in the value of ρ. In this case, it is considered that there is a change of about 10% in the value of VBO.

As shown in FIGS. 43 and 51, deep level impurities with respect to the N-layer substrate concentration of 4.80 × 10 ¹⁵ (1 / cm ³ ) to 2.35 × 10 ¹⁵ (1 / cm ³ ). The effect of the compensation effect of (Pt) is at least at a concentration of 4.80 × 10 ¹⁴ (1 / cm ³ ) to 2.35 × 10 ¹⁴ (1 / cm ³ ), which is about 10% of the concentration. Become. Therefore, it is considered that the depth at which the effect of the impurity (Pt) compensation effect appears corresponds to a range of about 10 μm from the silicon surface.

  In Non-Patent Document 6, for example, the trap concentration of U-type distribution as shown in FIG. 51 is DLTS and (Schottky barrier contact formation, N-type / Au, P-type / Al are formed by vapor deposition. In other words, it was determined by CV measurement (obtained from a relationship of C (capacitance) -V (voltage) by applying a reverse bias between both electrodes).

  Although not clearly described in Non-Patent Document 5 and Patent Document 3, according to the above consideration, the U-type distribution of Pt affects the characteristics of the device, that is, it gives an effective lifetime killer. The depth from the surface is at most in the range of 10 μm, the concentration of deep impurities at that time (concentration concentration) is about 10% or more of the N− type substrate, and the depth from the surface is outside the range of 10 μm. In other words, the pan-bottom portion of the U-shaped distribution has a density difference of about two orders of magnitude from the N-substrate density.

  That is, as the carrier distribution during the reverse recovery operation described in Non-Patent Document 5 and Patent Document 3, there are few accumulated carriers on the anode side, and more accumulated carriers need to remain on the cathode side of the N-drift layer. It is thought that the distribution of “There is” is obtained.

  FIG. 54 is a diagram assuming an impurity concentration distribution and a Pt distribution. As shown in FIG. 54, the depth (Xjp) of the P + layer on the anode side is considered to be about Xjp = 1 to 20 (μm). On the other hand, the thickness of the N + substrate on the cathode side is considered to be about 50 to 400 (μm). Therefore, it is considered that the U-type distribution of Pt does not significantly affect the cathode side even though it affects the anode side as a result.

  The effective influence depth Xpt of Pt is deeper than the P + layer, that is, Xpt> Xjp, or the effective influence depth Xpt of Pt is shallower than the P + layer, that is, Xpt <Xjp. Therefore, it is determined whether the position of the PN junction is ahead of or before Xpt, and the life of accumulated carriers (holes) in the N-layer near the PN junction on the anode side is determined. The time will be very different.

  For example, in paragraph [0022] of Patent Document 3, as shown in FIG. 54, the depth at which the bottom of the U-shaped distribution starts is about 50 (μm), and the PN junction depth Xpj is about 15 μm. It is described that a change appears in the concentration difference between the vicinity of the P + layer and the internal carrier in the deep portion, and it is described that soft recovery characteristics can be obtained when Xjp <15 μm.

  As described above, Patent Document 7 describes that there is an inconvenience when Pt diffusion is performed on the N-layer surface. Therefore, in the invention described in Patent Document 7, the use of Pt is abandoned, and the electron beam is used to increase the speed of JBS. Further, FIG. 30 of Patent Document 7 shows a comparison of SW waveforms of three devices of 200V FRD (≈G2FRD), 180V JBS, and 180V SBD.

  FIG. 55 is a diagram schematically showing three devices of 200V FRD, 180V JBS, and 180V SBD. As the trr characteristics indicating the high speed of the three devices as shown in FIG. 55, the result is that the order of trr-FRD, trr-JBS, trr-SBD is fast (trr is short) at Tj = 25 ° C. and 100 ° C. This is described in Patent Document 7. As a method for further shortening trr of 180V JBS, it is considered that there is a method of using Pt together with consideration of inconvenience, but as the best choice in the past, trr−FRD≈28 (ns) On the other hand, it is considered that trr-JBS is about 48 (ns) (room temperature).

  The SBD element is originally a unipolar element (for example, VR ≦ 60 (V)) that operates at an extremely high speed. However, Non-Patent Document 9 (Y. Yamamoto and H. Miyanaga: “An Analysis of positive and Negative resistance in the High Density of Electricity. , Pp. 1364-1372 (1990)), in particular, in the high current conductive region, minority carriers (holes) are actively injected from the SB interface toward the N-epi layer. It is described that conductivity modulation in the layer (that is, N− → N, N + conversion) occurs and exhibits a current-voltage characteristic that is strange.

  In other words, although it is originally SBD, if it is a 180V system, a considerably low concentration N-epi layer is used, so the lifetime of minority carriers (holes) in the N-epi layer is considerably long. In addition to showing the value, the injection of minority carriers (holes) from the SBD interface as shown in FIG. 56 is added (even if it does not have a P + layer region), so it is no longer a pure SBD device. It will not be said. FIG. 56 is a diagram schematically showing how minority carriers (holes) are injected from the SBD interface.

  Therefore, trr-SBD without killer processing is considered to be longer than trr-FRD, trr-JBS (with killer processing).

  As described in FIG. 30 of Patent Document 7, although the value of trr-SBD is relatively large, in terms of soft recoverability, the software is applied in the order of trr-SBD waveform, trr-JBS waveform, trr-FRD waveform. The property is excellent.

  As a result, the JBS device accompanied by the electron beam irradiation process described in Patent Document 7 is considered to be a device having an intermediate characteristic that takes the good point of the FRD device and the good point of the SBD device. It is done. However, according to the study by the present inventors, trr-JBS was never shorter than trr-FRD.

  The waveform at the time of switching from ON to OFF of the diode is described in FIG. 18 of Patent Document 8 (Japanese Patent Laid-Open No. 2003-84029), for example. FIG. 57 is a diagram corresponding to FIG. It is known that the diode exhibits a waveform as shown in FIG. 57 when switching from ON to OFF. In actual diodes, most high-speed diodes repeat the damped oscillation until the ON → OFF switching is completed, and then the ON → OFF switching is completed.

  FIG. 19 of Patent Document 8 defines each element of the trr waveform on the assumption that the SW waveform of the diode converges to the IF = 0 (A) line (see FIG. 57) without overshooting. Are listed. FIG. 58 is a view corresponding to FIG.

  FIG. 59 is a diagram showing the inside of a general (JBS) device when switching from ON to OFF. Specifically, FIG. 59A shows the inside of the device during the ON period, FIG. 59B shows the inside of the device at the start of switching from ON to OFF, and FIG. 59C is ON. → Indicates the inside of the device at the completion of OFF switching.

  As shown in FIG. 59A, it is considered that electrons (-) flow from the entire surface of the substrate (N +) to the exposed SBD interface on the N- surface during the ON period. On the other hand, it is considered that holes (+) flow from each part of the P layer toward the entire surface on the substrate (N +) side. It is thought that the depletion layer is spreading slightly.

  As shown in FIG. 59 (B), at the start of switching from ON to OFF, the depletion layer begins to expand, electrons (-) are drawn to the positive potential on the cathode side, and holes (+) are drawn to the negative potential on the anode. , Sucked into each electrode and disappeared. At this time, strictly speaking, since there is a difference in the depth of Xjp, it is considered that the hole (+) that has been swept out of the depletion layer and has lost its place is in the charge peak in FIG. .

  At the completion of the ON → OFF switching, the remaining electrons (−) and holes (+) are considered to be in the positions shown in FIG. 59C, and the holes ( Since the mobility of (+) is slow, it is considered that the last remaining hole (+) settles to complete OFF while determining the recovery waveform of trr2 (see FIG. 58) with the speed of returning to the anode.

  FIG. 60 is a diagram for explaining a normal guard ring. Usually, the guard ring region indicates a concentric ring surrounding the periphery of the main joint as shown in FIG. Since the guard ring requires a large area on the chip, the guard ring is often omitted in a low breakdown voltage (VR ≦ 200 V) element. When the guard ring is omitted, deeper Xjp (see FIG. 60) is required, and the end region (hatched portion in FIG. 60) of the main joint plays a role as the guard ring.

  In the example shown in FIG. 59, the guard ring region is formed inside the chip size, and the cathode electrode on the substrate side is formed over the entire chip surface. Therefore, during the ON period shown in FIG. 59A, the flow of holes (+) tends to concentrate near the outer corner of the guard ring. On the other hand, when the ON → OFF switching shown in FIG. 59C is completed, the concentration of the equal electric field lines is likely to occur near the outer corner of the guard ring (the hatched portion in FIG. 59C). That is, the electric field strength is increased.

  This state is described in FIG. 12 of Patent Document 7, for example. FIG. 61 is a diagram corresponding to FIG. Specifically, FIG. 61 (a) shows the SBD structure, and FIG. 61 (b) shows the JBS structure. It is considered that the guard ring region around the active region of the device is exposed to severe operating conditions with ON / OFF switching.

  Another example in which the movement of the internal carrier at the time of switching from ON to OFF is described in detail is, for example, described in Patent Document 9 (Japanese Patent Laid-Open No. 2000-312011). Patent Document 9 describes that by appropriately arranging the arrangement shape of a large number of P + type semiconductor regions, it is possible to obtain a high SW speed only by introducing fewer heavy metals (Au) than conventional ones. .

  FIG. 62 is a diagram corresponding to FIG. In FIG. 62, 52 is an n− type semiconductor layer, and 56 is a p + type semiconductor region. Patent Document 9 states that when the operation is turned off, the electrons are gathered in the SBD and stopped still, and then the electrons are injected from the PN junction and immediately flow to the hole side that has lost its place at the time of OFF to be coupled and trapped. Are listed.

  However, Patent Document 9 does not fully explain the reason why the conditions are actually required in order to start the OFF mode in a state where the electrons are concentrated in the SBD (part). Even after the P + type semiconductor region is ideally arranged, it is not considered that the use of heavy metal (Au) is completely eliminated. Furthermore, when a prototype device is actually manufactured, unless the heavy metal such as Pt is doped into the Si bulk (N-layer) with some high-temperature treatment, the trr characteristics of the device can be reduced. It is considered impossible.

63 is a diagram corresponding to FIG. 3 of Patent Document 7, and FIG. 64 is a diagram corresponding to FIG. 4 of Patent Document 7. 63 and 64, 61 is an N + type semiconductor substrate, 62 is an N− type semiconductor layer, 63 is an N− type region, 64 is a P type active region, 65 is a P type guard ring, and 66 is an N + type semiconductor substrate. Alternatively, a P + type channel stop region, 67 is a barrier metal, 68 is a semiconductor oxide film, 69 is a first electrode metal, 70 is a second electrode metal, 71 is an equipotential ring electrode metal, 81a is a semiconductor oxide film (SiO ₂ film) , 81b is an oxide film mask pattern, 81c is a semiconductor oxide film, 81d is a semiconductor oxide film, and 82 is a semiconductor oxide film. 83a is a PSG film, 83b is a PSG film, and 84 is a final insulating protective film.

  In the JBS manufacturing process described in Patent Document 7, first, as shown in FIG. 63 (1), a wafer having an N− type semiconductor layer 62 epitaxially grown on an N + type semiconductor substrate 61 is oxidized. The semiconductor oxide films 81a and 82 are formed on the front and back sides. For example, silicon is used for the semiconductor substrate 61 and the semiconductor layer 62. In that case, for example, a silicon oxide film of about 0.5 μm is formed as the semiconductor oxide films 81a and 82 by a wet oxidation method at 1000 ° C. for 90 minutes.

  In the JBS manufacturing process described in Patent Document 7, next, as shown in FIG. 63 (2), the semiconductor oxide film 81a on the surface of the semiconductor layer 62 is opened using a well-known lithography / etching technique. A film mask pattern 81b is formed. Further, P-type impurities are introduced into the semiconductor layer 62 using the oxide film mask pattern 81b as a mask. This is done, for example, by implanting boron ions. After introducing the P-type impurity, thermal diffusion is performed, and the P-type impurity is activated. As a result, a P-type active region 64 and a guard ring 65 are formed.

  In the JBS manufacturing process described in Patent Document 7, as shown in FIG. 63 (3), the wafer surface including the opening of the semiconductor oxide film 81b is oxidized in the thermal diffusion process after the introduction of the P-type impurity, A new semiconductor oxide film 81c is formed. The peripheral portions of the semiconductor oxide film 81b and the semiconductor oxide film 81c are etched and opened using a well-known photolithography technique. As a result, N + type impurities are introduced through the opening, and an N + type channel stop layer 66 is formed. This is done, for example, by ion implantation of phosphorus. The depth Xjn + is, for example, 1.2 to 1.3 μm. After the introduction of the N + type impurity, the N + type impurity is activated by thermal diffusion.

  In the manufacturing process of JBS described in Patent Document 7, next, as shown in FIG. 64 (4), a PSG (phosphorus / silicate / glass) film 83a is formed. Next, the PSG film 83a and the semiconductor oxide film 81d are opened using a well-known lithography / etching / metal film forming technique to form the PSG film 83b and the semiconductor oxide film 68 as shown in FIG. . A barrier metal 67 is formed on the guard ring 65, the P-type active region 64, and the N − -type region 63 therebetween as shown in FIG. 64 (5) through the openings of the PSG film 83 b and the semiconductor oxide film 68.

  In the JBS manufacturing process described in Patent Document 7, the first electrode metal 69 and the equipotential ring electrode metal 71 are further formed by using a well-known lithography / etching / metal film forming technique. As shown in FIG. 64 (5), the barrier metal 67 is completely covered by the first electrode metal 69. A PSG film 83 b is formed on the semiconductor oxide film 68. On the other hand, the back surface of the wafer is ground. Thereby, the semiconductor oxide film 82 on the back surface is removed.

  In the JBS manufacturing process described in Patent Document 7, the second electrode metal 70 is then formed on the back surface of the wafer as shown in FIG. Further, as shown in FIG. 64 (6), a final insulating protective film 84 is formed in the peripheral region. The central first electrode metal 69 is exposed.

  According to the study by the present inventors, it is considered that (at least) one Pt mask treatment and Pt deposition / heat treatment steps must be added to the processes of FIGS. 63 (3) to 64 (4). .

  As described above, there are many forms of the JBS structure itself, but as a result, it is still considered that there is no one on the market that has faster trr characteristics and satisfies low VF device characteristics. . In addition, a lifetime killer using Pt, or an electron beam or light ion irradiation has been proposed. However, when this is applied to JBS, the problem that Pt damages the SBD interface still remains. It has not been solved, and the problem that trr shortening is not sufficient with the use of an electron beam has not been solved, and the problem of cost and local controllability have not been solved even in light ion irradiation, and the market It is considered that a system that can supply devices that can be mass-produced commercially is not established.

Japanese Patent Publication No.59-35183 Japanese Patent Publication No.59-49714 JP-A-8-46221 Japanese Patent No. 3072753 Japanese Patent Laid-Open No. 5-102161 JP-A-6-342799 JP 2004-55586 A JP 2003-84029 A JP 2000-312011 A B. J. et al. Baliga, “Modern Power Devices” B. J. et al. Baliga, “The pinch rectifier: A low forward drop, high speed power diode,” IEEE Electron Device Lett. EDL-5, 194-196 (1984) B. J. et al. Baliga, “Analysis of junction barrier controlled Schottky rectifier charactaristics,” Solid State Electron. , 28, 1089-1093 (1985) NI (Japan Inter) NEWS Vol. 26, no. 2 pp. 10-11 (issued by Nihon Inter Corporation on February 20, 2000) IEEJ Technical Committee Materials EDD-00-128 (SPC-00-107) PP. 53-57, Fuji Electric Nemoto etc. Y. K. Kwon, T .; Ishikawa, and H.I. Kuwano, “Properties of Platinum-associated deep Levels in Silicon”, J. Am. Appl. Phys, 61, 3, pp. 1055-1058, 1987 N. Kaminski, N .; Gaslster, S .; Linder, C.M. Ng, and R.A. Francis, "1200V Merged PIN Schottky Diode with Soft Recovery and Positive Temperature Coefficient," Proceedings of EPE'99 Lausanne, 1999. S. M.M. Sze, VLSI Technology, International Student Edition Y. Yamamoto and H.K. Miyanaga: “An Analysis of positive & negative resistance charactaristics in the high-Current-Density region of Schottky E ED.” ED-37, no. 5, May, pp. 1364-1372 (1990)

  In view of the above problems, the present invention provides a semiconductor device that solves the problems of the prior art and can be applied not only to JBS structures that can meet market needs, but also to other FRDs and SBDs. Objective.

  More specifically, the present invention aims to provide a semiconductor device that can be introduced and applied to an ultrahigh-speed power device and that is subjected to heavy metal (Pt) processing as a lifetime killer. .

  Furthermore, an object of the present invention is to provide a semiconductor device having a trade-off characteristic of high speed and low loss (trr-VF) exceeding that of a conventional JBS.

  In other words, it is an object of the present invention to provide a JBS that can reduce the risk of defects at the Schottky junction interface and can improve soft recovery characteristics, and a method for manufacturing the same.

  Furthermore, an object of the present invention is to provide a Schottky barrier diode that can reduce the risk of defects occurring at the Schottky junction interface and can improve soft recovery characteristics.

  According to the invention described in claim 1, in the JBS in which the Schottky junction and the PN junction coexist, a plurality of P layers are arranged at predetermined intervals in the N-layer inside the guard ring portion, There is provided a JBS characterized in that heavy metal is diffused from a part of the surface of the guard ring part and the surface of the plurality of P layers, and heavy metal is not diffused from the surface of the N− layer.

  According to a second aspect of the present invention, heavy metal is diffused from the surface of the guard ring portion, and heavy metal is not diffused from the surface of the P layer inside the guard ring portion. The described JBS is provided.

  According to a third aspect of the present invention, heavy metal is diffused from a part of the surface of the P layer arranged inside the guard ring part, and heavy metal is not diffused from the surface of the guard ring part. The JBS according to claim 1 is provided.

  According to the invention described in claim 4, heavy metal is diffused from the surface of the guard ring portion according to the required reverse recovery time trr characteristic or forward voltage drop VF characteristic of the JBS, or the P layer The method for producing a JBS according to any one of claims 1 to 3, wherein whether to diffuse heavy metal from the surface is selected.

  According to a fifth aspect of the present invention, the method of manufacturing a JBS according to the fourth aspect, wherein the shape of each P layer arranged inside the guard ring portion is a stripe shape or a dot shape. Is provided.

  According to the sixth aspect of the present invention, a plurality of P layer groups each including a plurality of P layers are provided, and the plurality of P layer groups are connected to each other via the connecting portion and arranged inside the guard ring portion. The JBS according to any one of claims 1 to 3 is provided.

  According to the seventh aspect of the present invention, a P ++ layer that is shallower than the P layer and thicker than the P layer is formed in the P layer, and heavy metal is diffused from the surface of the P ++ layer. A JBS according to claim 1 or 3 is provided.

  According to the invention described in claim 8, platinum is diffused at a diffusion temperature of 930 to 950 ° C. from a part of the surface of the guard ring portion and the surfaces of the plurality of P layers. 1 is provided.

  According to the invention described in claim 9, the wafer specific resistance of JBS is set to 3.5 to 4.85 Ω · cm, and the thickness of the N− layer is set to about 15 μm. 1 is provided.

  According to the tenth aspect of the present invention, when the reduction of the reverse recovery time trr is required, the area of the surface of the P layer where the heavy metal is diffused is increased, and the reduction of the forward voltage drop VF is required. 5. The method of manufacturing a JBS according to claim 4, wherein an area of the surface of the P layer in which heavy metal is diffused is reduced.

  According to the invention described in claim 11, heavy metal is diffused from a plurality of locations among the surfaces of a plurality of P layers arranged inside the guard ring portion. A manufacturing method is provided.

  According to a twelfth aspect of the present invention, the plurality of P layers are arranged at intervals inside the guard ring portion, and heavy metals are diffused from the surfaces of the plurality of P layers. The described JBS is provided.

  According to the thirteenth aspect of the present invention, there is provided the JBS according to the third aspect, wherein the outer edge portion of the opening of the heavy metal diffusion mask pattern is arranged inside the outer edge portion of the P layer. The

  According to the invention of claim 14, a P ++ layer shallower than the depth of the P layer and thicker than the concentration of the P layer is formed in the P layer, and an outer edge portion of the P ++ layer and the heavy metal The size of the surface of the P ++ layer and the size of the opening of the heavy metal diffusion mask pattern are set so that the outer edge of the opening of the diffusion mask pattern substantially coincides, and heavy metal is diffused from the surface of the P ++ layer. A JBS according to claim 13 is provided.

  According to the invention described in claim 15, heavy metal is diffused so that the lifetime of the peripheral portion of the inner region is shorter than the lifetime of the central portion of the inner region of the guard ring portion. A JBS according to claim 1 is provided.

  According to the invention described in claim 16, heavy metal is diffused from the surface of two or more P layers among a plurality of P layers arranged at intervals in the N-layer inside the guard ring portion. A JBS according to claim 1 is provided.

  According to the invention described in claim 17, the two P layers in which heavy metals can be diffused from the surface are arranged inside the guard ring portion so as to sandwich the P layer in which heavy metals cannot be diffused from the surface. A JBS according to claim 1 is provided.

  According to the invention described in claim 18, between the two P layers from which heavy metals are diffused from the surface, a P layer from which heavy metals are not diffused from the surface is disposed, and the surface of the P layer from which heavy metals are diffused is disposed. 18. The JBS according to claim 17, wherein the area of the surface of the P layer where heavy metals cannot diffuse is set smaller than the area.

  According to the nineteenth aspect of the present invention, in the Schottky barrier diode having a Schottky junction, heavy metal is diffused from the surface of the guard ring portion, and from the surface of the N-layer disposed inside the guard ring portion. A Schottky barrier diode is provided that does not diffuse heavy metal.

  In the JBS according to claim 1, heavy metal is diffused from a part of the surface of the guard ring part and the surface of the plurality of P layers arranged at intervals inside the guard ring part. Heavy metals cannot be diffused from the surface of the N-layer disposed inside. That is, heavy metal cannot be diffused from the Schottky junction interface disposed inside the guard ring portion. Therefore, the risk of defects occurring at the Schottky junction interface can be reduced. Furthermore, the lifetime in the vicinity of the PN junction can be made shorter than the lifetime in the N− layer, and soft recovery characteristics can be obtained. As a result, soft recovery characteristics can be improved as compared with JBS described in JP-A-2004-55586. That is, the maximum reverse recovery current value IRM can be made smaller than the JBS described in Japanese Patent Application Laid-Open No. 2004-55586.

  In the JBS according to the second aspect, heavy metal is diffused from the surface of the guard ring portion, and heavy metal is not diffused from the surface of the P layer inside the guard ring portion. That is, heavy metal is diffused only from the surface of the guard ring portion among the surface of the guard ring portion, the surface of the P layer, and the surface of the N− layer. Therefore, the reverse recovery time trr can be shortened compared to the case where heavy metal is diffused from the surface of the portion other than the guard ring portion. That is, the reverse recovery time trr can be made shorter than when heavy metal is diffused from the surface of the P layer arranged inside the guard ring portion. This is probably because the concentration of holes in the outer corners of the guard ring when the JBS is switched from ON to OFF can be suppressed, and the concentration of equipotential lines can be suppressed.

  In other words, in the JBS according to the second aspect, heavy metals are diffused from the surface of the guard ring portion far from the N− layer, and heavy metals are not diffused from the surface of the P layer near the N− layer. Therefore, the possibility that the diffused heavy metal may reach the surface of the N− layer can be reduced. That is, the risk that the diffused heavy metal reaches the Schottky junction interface can be reduced.

  In the JBS according to the third aspect, heavy metal is diffused from a part of the surface of the P layer arranged inside the guard ring part, and heavy metal is not diffused from the surface of the guard ring part. That is, heavy metal is not diffused from the surface of the guard ring part, and heavy metal is not diffused from the surface of the N-layer disposed inside the guard ring part, and the P layer arranged inside the guard ring part. Heavy metal is diffused from only a part of the surface of the metal. Therefore, the forward voltage drop VF can be suppressed lower than when heavy metal is diffused from the surface of the guard ring portion.

  In the method of manufacturing a JBS according to claim 4, for example, heavy metal is diffused from the surface of the guard ring portion according to the reverse recovery time trr characteristic or the forward voltage drop VF characteristic of the JBS requested by the user, or the guard Whether to diffuse heavy metal from the surface of the P layer arranged inside the ring portion is selected. In detail, for example, a trr-VF trade-off curve of JBS is created in advance by experiment, and then a reverse recovery time trr characteristic or a forward voltage drop VF characteristic to be obtained is selected from the trr-VF trade-off curve, and then obtained. Whether heavy metal is diffused from the surface of the guard ring part or heavy metal is diffused from the surface of the P layer arranged inside the guard ring part so that the reverse recovery time trr characteristic or the forward voltage drop VF characteristic is obtained. Then, heavy metal is diffused from the surface of the guard ring portion or the surface of the P layer. Therefore, a JBS having a desired reverse recovery time trr characteristic or forward voltage drop VF characteristic can be manufactured.

  In other words, if heavy metal is diffused from the surface of the N-layer arranged inside the guard ring portion, the reverse recovery time trr characteristic and the forward voltage drop VF characteristic of the JBS are the trr-VF trade-off curve described above. Since it becomes difficult to manufacture a JBS having a desired reverse recovery time trr characteristic or a forward voltage drop VF characteristic, the JBS manufacturing method according to claim 4, Heavy metals cannot be diffused from the surface of the N-layer disposed inside.

  In the method of manufacturing a JBS according to the fifth aspect, the shape of each P layer arranged inside the guard ring portion is a stripe shape or a dot shape. Therefore, it is possible to reduce the load for creating the JBS trr-VF trade-off curve, compared to the case where the shape of each P layer arranged inside the guard ring portion is a complicated shape.

  In the JBS according to the sixth aspect, a plurality of P layer groups each including a plurality of P layers are provided, and the plurality of P layer groups are connected via the connecting portion, and are arranged inside the guard ring portion. Therefore, the soft recovery characteristics of a large JBS can be improved.

  In the JBS according to claim 7, a P ++ layer that is shallower than the depth of the P layer and higher than the concentration of the P layer is formed in the P layer, and heavy metals are diffused from the surface of the P ++ layer. Therefore, ohmic resistance can be reduced as compared with the case where the P ++ layer is not formed, and the amount of holes injected from the PIN region (P layer) can be suppressed. Specifically, the P ++ layer is formed in the P layer such that the surface area of the P ++ layer is smaller than the surface area of the P layer before the P ++ layer is formed.

  In the JBS according to claim 8 and 9, platinum diffuses at a diffusion temperature of 930 to 950 ° C. from a part of the surface of the guard ring part and the surface of the plurality of P layers arranged inside the guard ring part. It is done. Specifically, the wafer specific resistance of JBS is set to 3.5 to 4.85 Ω · cm, and the thickness of the N− layer disposed inside the guard ring portion is set to about 15 μm. Therefore, soft recovery characteristics can be improved as compared with the conventional JBS.

  In the method of manufacturing a JBS according to claim 10, when the reduction of the reverse recovery time trr is required, the surface area of the P layer where the heavy metal is diffused is increased, and the forward voltage drop VF is required to be reduced. Sometimes the surface area of the P layer where heavy metals are diffused is reduced. Therefore, the reverse recovery time trr characteristic or the forward voltage drop VF characteristic of the manufactured JBS can be brought close to the desired reverse recovery time trr characteristic or the forward voltage drop VF characteristic without having to significantly change the design of the JBS manufacturing apparatus. .

  In the manufacturing method of JBS of Claim 11, a heavy metal is diffused from several places among the surfaces of several P layer arranged inside the guard ring part. Therefore, the reverse recovery time trr can be reduced as compared with the conventional case in which heavy metal is diffused from only one place on the surface of the P layer arranged inside the guard ring portion.

  In the JBS of the twelfth aspect, a plurality of P layers are arranged at intervals inside the guard ring portion, and heavy metals are diffused from the surfaces of the plurality of P layers. In other words, heavy metal is not diffused from the surface of a single P layer disposed inside the guard ring portion, but heavy metal is diffused from the surfaces of a plurality of P layers arranged at intervals inside the guard ring portion. Can be diffused. Thereby, the reverse recovery time trr of 20 to 40 ns, which is shorter than the case where heavy metal is diffused from the surface of a single P layer disposed inside the guard ring portion, can be achieved.

  In the JBS according to the thirteenth aspect, the outer edge portion of the opening of the heavy metal diffusion mask pattern is arranged inside the outer edge portion of the P layer. That is, the opening of the heavy metal diffusion mask pattern is set smaller than the surface of the P layer. That is, a gap is provided between the boundary line between the P layer and the N− layer and the outer edge portion of the heavy metal diffusion mask pattern. Therefore, the possibility that the heavy metal diffused from the surface of the P layer reaches the Schottky junction interface adjacent to the P layer can be reduced. That is, the possibility that the heavy metal diffused from the surface of the P layer reaches the surface of the N− layer adjacent to the surface of the P layer can be reduced.

  In the JBS according to claim 14, a P ++ layer shallower than the depth of the P layer and thicker than the concentration of the P layer is formed in the P layer, and the outer edge of the P ++ layer and the opening of the heavy metal diffusion mask pattern are formed. The size of the surface of the P ++ layer and the size of the opening of the heavy metal diffusion mask pattern are set so that the outer edge portion substantially matches, and heavy metal is diffused from the surface of the P ++ layer. Specifically, the P ++ layer is formed in the P layer such that the surface area of the P ++ layer is smaller than the surface area of the P layer before the P ++ layer is formed. Therefore, ohmic resistance can be reduced as compared with the case where the P ++ layer is not formed, and the amount of holes injected from the PIN region (P layer) can be suppressed. Furthermore, the possibility that the heavy metal diffused from the surface of the P ++ layer reaches the Schottky junction interface adjacent to the P layer outside the P ++ layer can be reduced. That is, the possibility that the heavy metal diffused from the surface of the P ++ layer reaches the surface of the N− layer adjacent to the P layer outside the P ++ layer can be reduced.

  In the JBS of the fifteenth aspect, the heavy metal is diffused so that the lifetime of the peripheral portion of the inner region is shorter than the lifetime of the central portion of the inner region of the guard ring portion. Therefore, the central part of the inner area of the guard ring part can contribute to the soft recovery characteristics.

  In the JBS according to the sixteenth aspect, heavy metals are diffused from the surface of two or more P layers among a plurality of P layers arranged at intervals in the N-layer inside the guard ring portion. That is, heavy metals are diffused from the surfaces of two or more P layers arranged at intervals. That is, a predetermined gap is provided between two P layers in which heavy metals are diffused from the surface. Therefore, as the heavy metal concentration in the N-layer between the two P layers becomes higher than in the case where heavy metals are diffused from the surfaces of the two P layers arranged in close proximity, the N- The risk of defects occurring on the surface of the layer (Schottky junction interface) can be reduced.

  In the JBS of the seventeenth aspect, two P layers in which heavy metals are diffused from the surface are arranged inside the guard ring portion so as to sandwich a P layer in which heavy metals are not diffused from the surface. Therefore, it is possible to arrange the two P layers closer to each other than when heavy metal is diffused from the surfaces of the two adjacent P layers, thereby increasing the pinch-off effect. That is, the P layer in which heavy metal cannot be diffused from the surface and the P layer in which heavy metal is diffused from the surface are arranged close to each other, thereby increasing the pinch-off effect.

  In the JBS according to claim 18, a P layer in which heavy metal cannot be diffused from the surface is disposed between two P layers in which heavy metal is diffused from the surface, and the surface area of the P layer from which heavy metal is diffused is determined. However, the area of the surface of the P layer where heavy metals cannot be diffused is set small. Therefore, the area of the surface of the P layer in which heavy metal is diffused and the area of the surface of the P layer in which heavy metal is not diffused are set to be equal to each other between two P layers in which heavy metal is diffused from the surface. The area of the surface of the N-layer can be increased, thereby reducing the forward voltage drop VF. For example, in the case where the surface of the P layer is configured in a stripe shape, the P layer in which heavy metal cannot be diffused from the surface disposed between the two P layers than the width of two P layers from which heavy metal is diffused from the surface. The width of is set small. In addition, for example, when the surface of the P layer is configured in a dot shape such as a circle or a rectangle, the diameter of the two P layers from which heavy metal is diffused from the surface is larger than the surface disposed between them. The diameter of the P layer where the heavy metal cannot be diffused is set small.

  The guard ring part of the Schottky barrier diode is considered to be exposed to the same effect as that produced in the guard ring part of the JBS as shown in FIGS. That is, it is considered that holes are likely to gather in the guard ring portion in both forward and reverse (ON / OFF) biases in the Schottky barrier diode. In view of this point, in the Schottky barrier diode according to claim 19, heavy metal is diffused from the surface of the guard ring portion, and heavy metal is diffused from the surface of the N− layer disposed inside the guard ring portion. Absent. That is, heavy metal cannot be diffused from the Schottky junction interface disposed inside the guard ring portion. For this reason, the risk of defects occurring at the Schottky junction interface can be reduced, and soft recovery characteristics can be improved as compared with the case where heavy metals cannot be diffused from the surface of the guard ring portion. Specifically, the lifetime of holes around the guard ring portion is shortened, and as a result, a high-speed Schottky barrier diode can be obtained.

  Hereinafter, a first embodiment of a JBS (Junction Barrier Controlled Schottky) of the present invention will be described. 1 to 3 are views showing a manufacturing process of the JBS of the first embodiment. In the manufacturing process of the JBS of the first embodiment, first, as shown in FIG. 1A, a wafer having an N− layer 102 epitaxially grown on an N + type semiconductor substrate 101 is oxidized, and the wafer A semiconductor oxide film 121a is formed on the front surface (upper surface in FIG. 1A), and a semiconductor oxide film 122 is formed on the back surface of the wafer (lower surface in FIG. 1A). In the JBS of the first embodiment, silicon is used as the semiconductor substrate 101 and the N− layer 102. In that case, a silicon oxide film of about 0.5 μm is formed as the semiconductor oxide films 121a and 122 by, for example, a wet oxidation method at 1000 ° C. for 90 minutes. That is, in the JBS of the present invention, “semiconductor oxide film” means “silicon oxide film”.

  Next, the semiconductor oxide film 121a on the surface of the N− layer 102 (upper surface in FIG. 1A) is opened using a lithography / etching technique, and the oxide film mask pattern 121b is formed as shown in FIG. 1B. It is formed. Next, P-type impurities are introduced into the N − layer 102 using the oxide film mask pattern 121b as a mask. This is done, for example, by implanting boron ions. After introducing the P-type impurity, thermal diffusion is performed, and the P-type impurity is activated. As a result, as shown in FIG. 1B, a plurality of P layers (P-type active regions) 104 and guard ring portions 105 are formed. That is, a portion of the N− layer 102 excluding the P layer 104 and the guard ring portion 105 becomes the N− layer 103.

  Next, in the thermal diffusion step after the introduction of the P-type impurity, the surface of the wafer (upper surface of FIG. 1B) including the opening of the semiconductor oxide film 121b is oxidized, and as shown in FIG. A semiconductor oxide film 121c is formed. Next, the peripheral portions of the semiconductor oxide film 121b and the semiconductor oxide film 121c (the left edge portion and the right edge portion in FIG. 1C) are etched and opened using a photolithography technique. As a result, N + type impurities are introduced through the opening, and an N + type channel stop layer 106 is formed as shown in FIG. This is done, for example, by ion implantation of phosphorus. In the JBS of the first embodiment, the N + type channel stop layer 106 is provided. However, in the JBS of the second embodiment, the N + type channel stop layer may not be provided.

  Next, as shown in FIG. 2A, openings 130 are formed in the semiconductor oxide films 121b and 121c, and high-concentration P-type impurities pass through the openings 130 in the plurality of P layers 104 and guard rings. Part 105 is introduced. After introducing the P-type impurity, thermal diffusion is performed, and the P-type impurity is activated. As a result, as shown in FIG. 2A, a P ++ layer 104 ′ (see FIG. 2B) is formed in the P layer 104, and a P ++ layer 105 ′ is formed in the guard ring portion 105.

  The area of the surface of the P ++ layer 104 'is made smaller than the area of the surface of the P layer 104 (see FIG. 1C) before the P ++ layer 104' is formed. Specifically, as shown in FIG. 2 (A), the outer edge portion of the surface of the P ++ layer 104 ′ is disposed inside the outer edge portion of the surface of the P layer 104 before the P ++ layer 104 ′ is formed. . Further, the depth Xjp ′ of the P ++ layer 104 ′ is made shallower than the depth Xjp of the P layer 104. The concentration of the P ++ layer 104 ′ is set higher than the concentration of the P layer 104. Thereby, the ohmic improvement of the P layer (PIN region) 104 can be achieved, and the amount of holes injected from the P layer (PIN region) 104 can be suppressed. As a result, it is possible to suppress the reverse recovery time trr from becoming long.

  In the JBS of the first embodiment, the P ++ layers 104 ′ and 105 ′ are formed. In the JBS of the third embodiment, both the P ++ layers 104 ′ and 105 ′ or one of them is provided. It is also possible not to. When the P ++ layer 105 ′ is provided in the guard ring part 105 as in the JBS of the first embodiment, the ohmic property of the guard ring part 105 can be emphasized, while the JBS of the third embodiment Thus, when the P ++ layer 105 ′ is not provided in the guard ring portion 105, the hole injection amount can be emphasized.

  Next, as shown in FIG. 2B, the semiconductor oxide films 121b and 121c inside the guard ring part 105 are removed by etching, leaving the semiconductor oxide films 121b and 121c outside the guard ring part 105. Next, a heavy metal diffusion mask pattern 140 having an opening 141 is formed using a photoresist film. Next, in the photoresist lift-off process, the heavy metal adhering to the surface of the heavy metal diffusion mask pattern 140 (the upper surface in FIG. 2B) is removed together with the heavy metal diffusion mask pattern 140.

  Next, heavy metal that has not been removed in the photoresist lift-off process because it was located in the opening 141 is exposed from the surface of the guard ring portion 105, specifically, the surface of the P ++ layer 105 ′ in the guard ring portion 105 ( It is diffused from the upper surface of FIG. In the JBS of the first embodiment, platinum is diffused as a heavy metal, but in the JBS of the fourth embodiment, a heavy metal such as Au can be diffused instead.

  Next, as shown in FIG. 3A, a PSG (phosphorus / silicate / glass) film 123a is formed. Note that the semiconductor oxide films 121b and 121c shown in FIG. 1C are collectively shown as a semiconductor oxide film 121d in FIG.

  Next, the PSG film 123a and the semiconductor oxide film 121d are opened by using lithography, etching, and metal film formation techniques to form the PSG film 123b and the semiconductor oxide film 108 as shown in FIG. Next, a barrier metal 107 is formed on the guard ring portion 105, the P layer (P-type active region) 104, and the N− layer 103 therebetween.

  Next, the first electrode metal 109 and the equipotential ring electrode metal 111 are formed by using lithography / etching / metal film forming technique. The barrier metal 107 is completely covered by the first electrode metal 109. Next, the back surface of the wafer (the lower surface in FIG. 3B) is ground. Thereby, the semiconductor oxide film 122 on the back surface is removed. In the JBS of the first embodiment, the equipotential ring electrode metal 111 is provided. However, in the JBS of the fifth embodiment, it is possible not to provide the equipotential ring electrode metal.

  Next, as shown in FIG. 3C, the second electrode metal 110 is formed on the back surface of the wafer (the lower surface of FIG. 3C). Next, a final insulating protective film 124 is formed in the peripheral region.

  4 is a view of the N-layer 103, the P layer 104, and the guard ring portion 105 shown in FIGS. 1 to 3 as viewed from the upper side of FIGS. As shown in FIG. 4, in the JBS of the first embodiment, an N− layer 103 is arranged inside the guard ring portion 105, and a plurality of stripe-shaped Ps are arranged in the N− layer 103 with a predetermined interval. Layers 104 are arranged. That is, in the JBS of the first embodiment, a Schottky junction interface is formed on the surface of the N-layer 103 shown in FIG. 4, and a PN junction interface is formed on the boundary surface between the P layer 104 and the N-layer 103 around it. Is formed.

  FIG. 5 is a view of the heavy metal diffusion mask pattern 140 and its opening 141 shown in FIG. 2B as viewed from the upper side of FIG. As shown in FIGS. 2B, 4, and 5, in the JBS of the first embodiment, from the surface of the guard ring part 105, in detail, the P ++ layer 105 ′ in the guard ring part 105 The opening 141 of the heavy metal diffusion mask pattern 140 is formed so that heavy metal is diffused from the surface.

  That is, in the JBS of the first embodiment, as shown in FIGS. 2B, 4, and 5, the N− layer 103 disposed on the surface of the guard ring portion 105 and on the inner side of the guard ring portion 105. Heavy metal diffuses only from the surface of the guard ring portion 105 (specifically, the surface of the P ++ layer 105 ′) among the surface and the surfaces of the plurality of P layers 104 arranged at intervals in the N− layer 103. Thus, heavy metal cannot be diffused from the surface of the N− layer 103 disposed inside the guard ring portion 105. That is, heavy metal cannot be diffused from the Schottky junction interface disposed inside the guard ring portion 105. Therefore, the risk of defects occurring at the Schottky junction interface can be reduced. Furthermore, the lifetime in the vicinity of the PN junction can be made shorter than the lifetime in the N-layer 103, whereby soft recovery characteristics can be obtained as will be described later together with experimental data. As a result, the soft recovery characteristic can be improved as compared with the conventional JBS configured like the JBS described in JP-A-2004-55586. That is, the maximum reverse recovery current value IRM can be made smaller than the conventional JBS configured like the JBS described in JP-A-2004-55586.

  Specifically, in the JBS of the first embodiment, as shown in FIGS. 2B, 4, and 5, heavy metal is applied from the surface of the guard ring portion 105 (specifically, the surface of the P ++ layer 105 ′). Is diffused, and heavy metals cannot be diffused from the surface of the P layer 104 and the surface of the P ++ layer 104 ′ inside the guard ring portion 105. That is, among the surface of the guard ring portion 105 (and the surface of the P ++ layer 105 ′), the surface of the P layer 104 (and the surface of the P ++ layer 104 ′), and the surface of the N− layer 103, the surface of the guard ring portion 105. Heavy metal is diffused only from (specifically, the surface of the P ++ layer 105 ′). Therefore, as will be described later along with experimental data, the reverse recovery time trr can be made shorter than when heavy metal is diffused from the surface of the portion other than the guard ring portion 105. That is, the reverse recovery time trr can be made shorter than when heavy metal is diffused from the surface of the P layer 104 (and the surface of the P ++ layer 104 ′) arranged inside the guard ring portion 105. The reason for this is considered to be that the concentration of holes in the outer corners of the guard ring portion 105 when the JBS is switched from ON to OFF can be suppressed, and the concentration of equipotential lines can be suppressed.

  In other words, in the JBS of the first embodiment, as shown in FIGS. 2B, 4, and 5, the surface of the guard ring portion 105 far from the N− layer 103 (specifically, the P ++ layer 105 The heavy metal is diffused from the surface of 'and the heavy metal is not diffused from the surface of the P layer 104 close to the N-layer 103. Therefore, the risk that the diffused heavy metal reaches the surface of the N− layer 103 can be reduced. That is, the risk that the diffused heavy metal reaches the Schottky junction interface can be reduced.

  In the JBS of the first embodiment, platinum as a heavy metal is diffused at a diffusion temperature of 930 to 950 ° C. from the surface of the guard ring portion 105 (specifically, the surface of the P ++ layer 105 ′). In the JBS of the sixth embodiment, heavy metal can be diffused at a diffusion temperature other than the above-described temperature instead.

  Furthermore, in the JBS of the first embodiment, the wafer specific resistance of the JBS is set to, for example, 3.5 to 4.85 Ω · cm, and the thickness of the N− layer 103 disposed inside the guard ring portion 105 is, for example, It is set to about 15 μm.

  The seventh embodiment of the JBS of the present invention will be described below. The JBS of the seventh embodiment is manufactured by the same manufacturing process as the manufacturing process of the JBS of the first to sixth embodiments described above, except as described below.

  FIG. 6 is a diagram showing a part of the manufacturing process of the JBS of the seventh embodiment. As described above, in the manufacturing process of the JBS of the first embodiment, as shown in FIG. 2B, the heavy metal diffusion mask pattern 140 having the opening 141 is formed using the photoresist film, Next, heavy metal is diffused from the surface of the guard ring portion 105 (specifically, the surface of the P ++ layer 105 ′) through the opening 141. In the JBS manufacturing process of the seventh embodiment, FIG. As described above, a heavy metal diffusion mask pattern 240 having an opening 241 is formed using a photoresist film, and then the surface of a part of the P layer 104 (specifically, a P ++ layer 104 ′ is formed through the opening 241. Heavy metal diffuses from the surface.

  In the JBS of the seventh embodiment, as shown in FIG. 6, the P ++ layer 104 ′ is formed. However, in the JBS of the eighth embodiment, the P ++ layer 104 ′ may not be provided. In the JBS of the eighth embodiment, the outer edge portion of the opening 241 (see FIG. 6) of the heavy metal diffusion mask pattern 240 is formed rather than the outer edge portion of the P layer 104 (see FIG. 6) where heavy metal is diffused from the surface. Arranged inside. That is, the opening 241 (see FIG. 6) of the heavy metal diffusion mask pattern 240 is set to be smaller than the surface of the P layer 104 (see FIG. 6). That is, a gap is provided between the boundary line between the P layer 104 and the N− layer 103 and the outer edge portion of the opening 241 of the heavy metal diffusion mask pattern 240. Therefore, the possibility that the heavy metal diffused from the surface of the P layer 104 reaches the Schottky junction interface adjacent to the P layer 104 can be reduced. That is, it is possible to reduce the possibility that the heavy metal diffused from the surface of the P layer 104 reaches the surface of the N− layer 103 adjacent to the surface of the P layer 104.

  Returning to the description of the JBS of the seventh embodiment, FIG. 7 shows the N-layer 103, the P layer 104, and the guard ring portion 105 shown in FIGS. It is the figure seen from the upper side. As shown in FIG. 7, a plurality of striped P layers 104 arranged at predetermined intervals in the N− layer 103 inside the guard ring portion 105 are included in the first region 104-1. The one included in the second region 104-2, the one included in the third region 104-3, the one included in the fourth region 104-4, and the fifth region 104-. 5, those included in the sixth region 104-6, and those included in the seventh region 104-7.

  FIG. 8 is a view of the JBS heavy metal diffusion mask pattern 240 and its opening 241 of the seventh embodiment shown in FIG. 6 as viewed from the upper side of FIG. As shown in FIGS. 6 to 8, in the JBS of the seventh embodiment, a plurality of P layers 104 included in the second region 104-2, the fourth region 104-4, and the sixth region 104-6 are provided. Specifically, the opening 241 of the heavy metal diffusion mask pattern 240 has the second region 241-2 and the fourth region so that the heavy metal is diffused from the surface of the P ++ layer 104 ′ in the P layer 104. 241-4 and the sixth region 241-6.

  That is, in the JBS of the seventh embodiment, as shown in FIGS. 6 to 8, the surface of the guard ring portion 105, the surface of the N− layer 103 disposed inside the guard ring portion 105, and the N− Among the surfaces of the plurality of P layers 104 arranged at intervals in the layer 103, heavy metals are diffused only from the surface of a part of the P layer 104 (specifically, the surface of the P ++ layer 104 ′), and the guard Heavy metal cannot be diffused from the surface of the N− layer 103 disposed inside the ring portion 105. That is, heavy metal cannot be diffused from the Schottky junction interface disposed inside the guard ring portion 105. Therefore, the risk of defects occurring at the Schottky junction interface can be reduced.

  In the JBS of the seventh embodiment, as shown in FIG. 7, one P layer group including seven regions (104-1 to 104-7) is provided in the guard ring portion 105. In the ninth embodiment, instead of providing a large guard ring portion, it is possible to provide, for example, four P layer groups composed of seven regions. Specifically, in the JBS of the ninth embodiment, four P layer groups each including seven regions are provided, and the four P layer groups are connected via the connecting portion, and are arranged inside the large guard ring portion. Has been. Therefore, the soft recovery characteristics of a large JBS can be improved.

  Furthermore, in the JBS of the seventh embodiment, as shown in FIG. 6, a P ++ layer 104 ′ that is shallower than the depth of the P layer 104 and higher than the concentration of the P layer 104 is formed in the P layer 104. Heavy metals are diffused from the surface of the P ++ layer 104 ′. Therefore, ohmic resistance can be reduced and the amount of holes injected from the PIN region (P layer) can be suppressed as compared with the case where the P ++ layer 104 ′ is not formed.

  Specifically, in the JBS of the seventh embodiment, as shown in FIG. 6, the P ++ layer 104 is larger than the surface area of the P layer 104 (see FIG. 1C) before the P ++ layer 104 ′ is formed. A P ++ layer 104 ′ is formed in the P layer 104 so that the surface area of “′ becomes small.

  In the JBS of the seventh embodiment, platinum as a heavy metal is diffused from the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) at a diffusion temperature of 930 to 950 ° C. In the JBS of the tenth embodiment, heavy metal can be diffused at a diffusion temperature other than the above-described temperature instead.

  Further, in the JBS of the seventh embodiment, the wafer specific resistance of the JBS is set to, for example, 3.5 to 4.85 Ω · cm, and the thickness of the N− layer 103 disposed inside the guard ring portion 105 is, for example, It is set to about 15 μm.

  Further, in the JBS of the seventh embodiment, as shown in FIG. 7, in detail, from a plurality of locations on the surfaces of the plurality of P layers 104 arranged inside the guard ring portion 105, in detail, the second region 104. −2, heavy metal is diffused from the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) included in the fourth region 104-4 and the sixth region 104-6. Therefore, the reverse recovery time trr can be reduced, as will be described later together with experimental data, as compared to the case where heavy metal is diffused from only one place on the surface of the P layer arranged inside the guard ring portion.

  In other words, in the JBS of the seventh embodiment, as shown in FIG. 7, a plurality of the second region 104-2, the fourth region 104-4, and the sixth region 104-6 inside the guard ring portion 105 are provided. The P layers 104 are arranged at intervals, and heavy metals are diffused from the surfaces of the P layers 104 (specifically, the surfaces of the P ++ layers 104 ′). That is, heavy metal is not diffused from the surface of a single P layer disposed inside the guard ring part, but the surfaces of a plurality of P layers 104 arranged at intervals inside the guard ring part 105 ( Specifically, heavy metal is diffused from the surface of the P ++ layer 104 ′. Thereby, as will be described later together with experimental data, a reverse recovery time trr of 20 to 40 ns is achieved, which is shorter than the case where heavy metal is diffused from the surface of a single P layer disposed inside the guard ring portion. be able to.

  In the JBS of the seventh embodiment, as shown in FIG. 6, the outer edge portion of the opening 241 of the heavy metal diffusion mask pattern 240 is arranged on the inner side than the outer edge portion of the P ++ layer 104 ′. In the JBS of the embodiment, instead, the P ++ layer is formed so that the outer edge of the P ++ layer 104 ′ (see FIG. 6) and the outer edge of the opening 241 (see FIG. 6) of the heavy metal diffusion mask pattern 240 substantially coincide with each other. It is also possible to set the dimension of the surface 104 ′ and the dimension of the opening 241 of the heavy metal diffusion mask pattern 240.

  Specifically, in the JBS of the eleventh embodiment, the P ++ layer 104 ′ (see FIG. 6) is shallower than the depth of the P layer 104 (see FIG. 6) and higher than the concentration of the P layer 104 (see FIG. 6). ) Is formed in the P layer 104, and the size of the surface of the P ++ layer 104 ′ and the heavy metal diffusion layer are such that the outer edge portion of the P ++ layer 104 ′ and the outer edge portion of the opening 241 of the heavy metal diffusion mask pattern 240 substantially coincide with each other. The size of the opening 241 of the mask pattern 240 is set, and heavy metal is diffused from the surface of the P ++ layer 104 ′. That is, in the JBS of the eleventh embodiment, as in the JBS of the seventh embodiment shown in FIG. 6, the area of the P ++ layer 104 ′ is larger than the area of the surface of the P layer 104 before the P ++ layer 104 ′ is formed. A P ++ layer 104 ′ is formed in the P layer 104 so as to reduce the surface area. Therefore, ohmic resistance can be reduced and the amount of holes injected from the PIN region (P layer) can be suppressed as compared with the case where the P ++ layer 104 ′ is not formed. Further, it is possible to reduce the possibility that the heavy metal diffused from the surface of the P ++ layer 104 ′ reaches the Schottky junction interface adjacent to the P layer 104 outside the P ++ layer 104 ′. That is, the possibility that the heavy metal diffused from the surface of the P ++ layer 104 ′ reaches the surface of the N− layer 103 adjacent to the P layer 104 outside the P ++ layer 104 ′ can be reduced.

  Returning to the description of the JBS of the seventh embodiment, in the JBS of the seventh embodiment, the lifetime of the peripheral portion of the inner region is shorter than the lifetime of the central portion of the inner region of the guard ring portion 105. In addition, heavy metals are diffused. Therefore, the central portion of the inner region of the guard ring portion 105 can contribute to the soft recovery characteristics.

  Further, in the JBS of the seventh embodiment, as shown in FIGS. 6 to 8, two of the plurality of P layers 104 arranged at intervals in the N− layer 103 inside the guard ring portion 105. Heavy metal is diffused from the surface of one or more P layers 104 (specifically, the surface of the P ++ layer 104 ′). That is, heavy metals are diffused from the surface of two or more P layers 104 arranged in spaced relation (specifically, the surface of the P ++ layer 104 ′). That is, as shown in FIG. 7, a gap wider than the width of the P layer 104 is provided between two adjacent P layers 104 where heavy metal is diffused from the surface. Therefore, as the heavy metal concentration in the N-layer between the two P layers becomes higher than in the case where heavy metals are diffused from the surfaces of the two P layers arranged in close proximity, the N- The risk of defects occurring on the surface of the layer (Schottky junction interface) can be reduced.

  In the JBS of the seventh embodiment, as shown in FIGS. 6 to 8, for example, the P layer 104 in the third region 104-3 where the heavy metal cannot be diffused from the surface is sandwiched from the surface. The P layer 104 in the second region 104-2 and the P layer 104 in the fourth region 104-4 where the heavy metal is diffused are arranged inside the guard ring portion 105. Therefore, compared with the case where heavy metal is diffused from the surfaces of two adjacent P layers, for example, the P layer 104 in the second region 104-2 closest to the third region 104-3 and the second region 104-2. The P layer 104 in the nearest third region 104-3 can be arranged close to each other, thereby increasing the pinch-off effect. That is, for example, the P layer 104 in the third region 104-3 in which heavy metal cannot be diffused from the surface and the P layer 104 in the second region 104-2 in which heavy metal is diffused from the surface are arranged close to each other. Thus, the pinch-off effect can be increased.

  In the JBS of the twelfth embodiment, a P layer in which heavy metals cannot be diffused from the surface is disposed between two P layers in which heavy metals are diffused from the surface, and the surface area of the P layer from which heavy metals are diffused is determined. However, it is also possible to set the surface area of the P layer where heavy metals cannot be diffused small. According to the JBS of the twelfth embodiment, the heavy metal is removed from the surface as compared with the case where the surface area of the P layer where the heavy metal is diffused and the surface area of the P layer where the heavy metal is not diffused are set equal. The area of the surface of the N− layer between the two P layers to be diffused can be increased, thereby reducing the forward voltage drop VF. For example, in the case where the surface of the P layer is configured in a stripe shape, the P layer in which heavy metal cannot be diffused from the surface disposed between the two P layers than the width of two P layers from which heavy metal is diffused from the surface. The width of is set small. In addition, for example, when the surface of the P layer is configured in a dot shape such as a circle or a rectangle, the diameter of the two P layers from which heavy metal is diffused from the surface is larger than the surface disposed between them. The diameter of the P layer where the heavy metal cannot be diffused is set small.

  The thirteenth embodiment of the JBS of the present invention will be described below. The JBS of the thirteenth embodiment is manufactured by the same manufacturing process as the manufacturing process of the JBS of the first to twelfth embodiments described above, except as described below.

  FIG. 9 is a diagram showing a part of the manufacturing process of the JBS of the thirteenth embodiment. As described above, in the manufacturing process of the JBS of the first embodiment, as shown in FIG. 2B, the heavy metal diffusion mask pattern 140 having the opening 141 is formed using the photoresist film, Next, heavy metal is diffused from the surface of the guard ring portion 105 (specifically, the surface of the P ++ layer 105 ′) through the opening 141. In the JBS manufacturing process of the thirteenth embodiment, as shown in FIG. As described above, a heavy metal diffusion mask pattern 340 having an opening 341 is formed using a photoresist film, and then the surface of a part of the P layer 104 (specifically, a P ++ layer 104 ′ is formed through the opening 341). Heavy metal diffuses from the surface.

  FIG. 10 is a view of the JBS heavy metal diffusion mask pattern 340 and its opening 341 of the thirteenth embodiment shown in FIG. 9 as viewed from the upper side of FIG. As shown in FIGS. 9 and 10, in the JBS of the thirteenth embodiment, from the surfaces of the plurality of P layers 104 included in the second region 104-2 and the sixth region 104-6 (see FIG. 7). Specifically, the opening 341 of the heavy metal diffusion mask pattern 340 includes the second region 341-2 and the sixth region 341-1 so that the heavy metal is diffused from the surface of the P ++ layer 104 ′ in the P layer 104. 6 is formed.

  That is, in the JBS of the thirteenth embodiment, as shown in FIGS. 9 and 10, the surface of the guard ring portion 105, the surface of the N− layer 103 disposed inside the guard ring portion 105, and the N− Among the surfaces of the plurality of P layers 104 arranged at intervals in the layer 103, heavy metals are diffused only from the surface of a part of the P layer 104 (specifically, the surface of the P ++ layer 104 ′), and the guard Heavy metal cannot be diffused from the surface of the N− layer 103 disposed inside the ring portion 105. That is, heavy metal cannot be diffused from the Schottky junction interface disposed inside the guard ring portion 105. Therefore, the risk of defects occurring at the Schottky junction interface can be reduced.

  Further, in the JBS of the thirteenth embodiment, as shown in FIGS. 7 and 9, in detail, from a plurality of locations on the surfaces of the plurality of P layers 104 arranged inside the guard ring portion 105, Heavy metal is diffused from the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) included in the second region 104-2 and the sixth region 104-6 (see FIG. 7). Therefore, the reverse recovery time trr can be reduced, as will be described later together with experimental data, as compared to the case where heavy metal is diffused from only one place on the surface of the P layer arranged inside the guard ring portion.

  In other words, in the JBS of the thirteenth embodiment, as shown in FIGS. 7 and 9, a plurality of P layers 104 are provided in the second region 104-2 and the sixth region 104-6 inside the guard ring portion 105. Are arranged at intervals, and heavy metals are diffused from the surface of the plurality of P layers 104 (specifically, the surface of the P ++ layer 104 ′). That is, heavy metal is not diffused from the surface of a single P layer disposed inside the guard ring part, but the surfaces of a plurality of P layers 104 arranged at intervals inside the guard ring part 105 ( Specifically, heavy metal is diffused from the surface of the P ++ layer 104 ′. Thereby, as will be described later together with experimental data, a reverse recovery time trr of 20 to 40 ns is achieved, which is shorter than the case where heavy metal is diffused from the surface of a single P layer disposed inside the guard ring portion. be able to.

  In the JBS of the thirteenth embodiment, as in the JBS of the seventh embodiment, the lifetime of the peripheral portion of the inner region is shorter than the lifetime of the central portion of the inner region of the guard ring portion 105. , Heavy metals are diffused. Therefore, the central portion of the inner region of the guard ring portion 105 can contribute to the soft recovery characteristics.

  Furthermore, in the JBS of the thirteenth embodiment, as shown in FIGS. 9 and 10, two of the plurality of P layers 104 arranged at intervals in the N− layer 103 inside the guard ring portion 105. Heavy metal is diffused from the surface of one or more P layers 104 (specifically, the surface of the P ++ layer 104 ′). That is, heavy metals are diffused from the surface of two or more P layers 104 arranged in spaced relation (specifically, the surface of the P ++ layer 104 ′). That is, as shown in FIG. 7, a gap wider than the width of the P layer 104 is provided between two adjacent P layers 104 where heavy metal is diffused from the surface. Therefore, as the heavy metal concentration in the N-layer between the two P layers becomes higher than in the case where heavy metals are diffused from the surfaces of the two P layers arranged in close proximity, the N- The risk of defects occurring on the surface of the layer (Schottky junction interface) can be reduced.

  Hereinafter, a fourteenth embodiment of the JBS of the present invention will be described. The JBS of the fourteenth embodiment is manufactured by the same manufacturing process as the manufacturing process of the JBS of the first to thirteenth embodiments described above, except as described below.

  FIG. 11 is a diagram showing a part of the manufacturing process of the JBS of the fourteenth embodiment. As described above, in the manufacturing process of the JBS of the first embodiment, as shown in FIG. 2B, the heavy metal diffusion mask pattern 140 having the opening 141 is formed using the photoresist film, Next, heavy metal is diffused from the surface of the guard ring portion 105 (specifically, the surface of the P ++ layer 105 ′) through the opening 141. In the manufacturing process of the JBS of the fourteenth embodiment, as shown in FIG. As described above, a heavy metal diffusion mask pattern 440 having an opening 441 is formed using a photoresist film, and then the surface of a part of the P layer 104 (specifically, a P ++ layer 104 ′ is formed through the opening 441). Heavy metal diffuses from the surface.

  FIG. 12 is a view of the JBS heavy metal diffusion mask pattern 440 and its opening 441 of the fourteenth embodiment shown in FIG. 11 as viewed from the upper side of FIG. As shown in FIGS. 11 and 12, in the JBS of the fourteenth embodiment, the P ++ layer in the P layer 104 is described in detail from the surface of the plurality of P layers 104 included in the fourth region 104-4. An opening 441 of the heavy metal diffusion mask pattern 440 is formed in the fourth region 441-4 so that heavy metal is diffused from the surface 104 ′.

  That is, in the JBS of the fourteenth embodiment, as shown in FIGS. 11 and 12, the surface of the guard ring part 105, the surface of the N− layer 103 disposed inside the guard ring part 105, and the N− Among the surfaces of the plurality of P layers 104 arranged at intervals in the layer 103, heavy metals are diffused only from the surface of a part of the P layer 104 (specifically, the surface of the P ++ layer 104 ′), and the guard Heavy metal cannot be diffused from the surface of the N− layer 103 disposed inside the ring portion 105. That is, heavy metal cannot be diffused from the Schottky junction interface disposed inside the guard ring portion 105. Therefore, the risk of defects occurring at the Schottky junction interface can be reduced.

  Furthermore, in the JBS of the fourteenth embodiment, as shown in FIGS. 11 and 12, one surface of the P layer 104 (in detail, the surface of the P ++ layer 104 ′) arranged inside the guard ring portion 105 is used. Heavy metal is diffused from the portion, and heavy metal is not diffused from the surface of the guard ring portion 105. That is, heavy metal is not diffused from the surface of the guard ring part 105, and heavy metal is not diffused from the surface of the N− layer 103 arranged inside the guard ring part 105, and is arranged inside the guard ring part 105. Heavy metal is diffused from only a part of the surface of the formed P layer 104 (specifically, the surface of the P ++ layer 104 ′). Therefore, as will be described later along with experimental data, the forward voltage drop VF can be kept lower than when heavy metal is diffused from the surface of the guard ring portion 105.

  In the JBS of the fourteenth embodiment, as in the JBS of the seventh embodiment, the lifetime of the peripheral portion of the inner region is shorter than the lifetime of the central portion of the inner region of the guard ring portion 105. , Heavy metals are diffused. Therefore, the central portion of the inner region of the guard ring portion 105 can contribute to the soft recovery characteristics.

  Furthermore, in the JBS of the fourteenth embodiment, as shown in FIGS. 11 and 12, two of the plurality of P layers 104 arranged at intervals in the N-layer 103 inside the guard ring portion 105 are used. Heavy metal is diffused from the surface of one or more P layers 104 (specifically, the surface of the P ++ layer 104 ′). That is, heavy metal is diffused from the surface of two or more P layers 104 arranged in the fourth region 104-4 (see FIG. 7) at intervals (specifically, the surface of the P ++ layer 104 '). That is, as shown in FIG. 7, a gap wider than the width of the P layer 104 is provided between two adjacent P layers 104 where heavy metal is diffused from the surface. Therefore, as the heavy metal concentration in the N-layer between the two P layers becomes higher than in the case where heavy metals are diffused from the surfaces of the two P layers arranged in close proximity, the N- The risk of defects occurring on the surface of the layer (Schottky junction interface) can be reduced.

  In the JBS of the fifteenth embodiment, the JBSs of the first to fourteenth embodiments described above can be appropriately combined.

  In the method of manufacturing the JBS of the present invention, for example, depending on the reverse recovery time trr characteristic or the forward voltage drop VF characteristic of the JBS requested by the user, the heavy metal is applied from the surface of the guard ring portion 105 like the JBS of the first embodiment. Or diffuse heavy metal from a part of the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) arranged inside the guard ring portion 105 as in the JBS of the seventh embodiment. Diffusion or heavy metal is diffused from a part of the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) arranged inside the guard ring portion 105 like the JBS of the thirteenth embodiment Or the surface of the P layer 104 (in detail, the surface of the P ++ layer 104 ′) arranged inside the guard ring portion 105 as in the JBS of the fourteenth embodiment. Or diffusing is selected heavy metals from parts. Specifically, a JBS trr-VF trade-off curve, which will be described in detail later, is preliminarily created by experiment, for example, and then the reverse recovery time trr characteristic or forward voltage drop VF characteristic requested by the user is determined by the trr-VF. From the surface of the guard ring unit 105 as in the JBS of the first embodiment so that the reverse recovery time trr characteristic or the forward voltage drop VF characteristic required by the user is obtained, for example, from the trade-off curve. Heavy metal is diffused, or heavy metal from a part of the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) arranged inside the guard ring portion 105 as in the JBS of the seventh embodiment Or the P layer 10 arranged inside the guard ring portion 105 as in the JBS of the thirteenth embodiment. The heavy metal is diffused from a part of the surface (specifically, the surface of the P ++ layer 104 ′), or the P layer 104 arranged inside the guard ring portion 105 like the JBS of the fourteenth embodiment. It is selected whether heavy metal is diffused from a part of the surface (specifically, the surface of the P ++ layer 104 ′), and then the surface of the guard ring part 105 or the surface of the P layer 104 (specifically, the P ++ layer 104 ′). Heavy metal diffuses from a part of the surface. Thereby, for example, a JBS having a reverse recovery time trr characteristic or a forward voltage drop VF characteristic required by a user can be manufactured.

  In other words, if heavy metal is diffused from the surface of the N-layer disposed inside the guard ring portion 105, the reverse recovery time trr characteristic and the forward voltage drop VF characteristic of the JBS have the trr-VF tradeoff described above. Since it is difficult to manufacture a JBS having a desired reverse recovery time trr characteristic or forward voltage drop VF characteristic because it deviates from the curve, the JBS manufacturing method according to the present invention has an inner side of the guard ring portion 105. Heavy metal cannot be diffused from the surface of the N-layer 103 disposed on the surface.

  Furthermore, in the method of manufacturing a JBS according to the present invention, the shape of each P layer 104 arranged inside the guard ring portion 105 is a stripe shape as shown in FIG. And so on. Therefore, the load for creating the above-described JBS trr-VF tradeoff curve can be reduced as compared with the case where the shape of each P layer 104 arranged inside the guard ring portion 105 is a complicated shape. .

  Specifically, in the method of manufacturing a JBS of the present invention, when the reduction of the reverse recovery time trr is required, the area of the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) on which heavy metal is diffused is reduced. When it is increased and the reduction of the forward voltage drop VF is required, the area of the surface of the P layer 104 (specifically, the surface of the P ++ layer 104 ′) into which the heavy metal is diffused is decreased. Therefore, the reverse recovery time trr characteristic or the forward voltage drop VF characteristic of the manufactured JBS can be brought close to the desired reverse recovery time trr characteristic or the forward voltage drop VF characteristic without having to significantly change the design of the JBS manufacturing apparatus. .

  Hereinafter, a first embodiment of the Schottky barrier diode of the present invention will be described. The Schottky barrier diode of the first embodiment is configured in substantially the same manner as the JBS of the first embodiment described above, except that the P layer and the P ++ layer are not provided inside the guard ring portion.

  Specifically, it is considered that the guard ring portion of the Schottky barrier diode is exposed to the same effect as that produced in the guard ring portion of JBS as shown in FIGS. That is, it is considered that holes are likely to gather in the guard ring portion in both forward and reverse (ON / OFF) biases in the Schottky barrier diode. In view of this point, in the Schottky barrier diode of the first embodiment, heavy metal is diffused from the surface of the guard ring portion, and heavy metal is diffused from the surface of the N− layer disposed inside the guard ring portion. Absent. That is, heavy metal cannot be diffused from the Schottky junction interface disposed inside the guard ring portion. For this reason, the risk of defects occurring at the Schottky junction interface can be reduced, and soft recovery characteristics can be improved as compared with the case where heavy metals cannot be diffused from the surface of the guard ring portion. Specifically, the lifetime of holes around the guard ring portion is shortened, and as a result, a high-speed Schottky barrier diode can be obtained. In other words, the lifetime of the holes under the Schottky junction interface is not shortened by the diffusion of Pt, so that the part remains long and contributes to (maintains) the soft recovery property (Schottky). On the other hand, the lifetime of the holes under the guard ring is shortened by the diffusion of Pt, which is shortened. As a result, the lifetime distribution inside the device has been completed, and as a result, the device as a whole has a higher-speed Schottky barrier while maintaining soft recovery than a conventional Schottky barrier diode without Pt diffusion. It seems that a diode has been obtained.

  Experiments were performed using the JBS of the above-described embodiment. In the experiment, a square JBS of 2.66 mm × 2.66 mm was used. That is, for example, the length of one side of the square JBS shown in FIG. 4 is 2.66 mm.

  The JBS of the present invention is also referred to as “MPS (Merged PIN with SBD). Specifically, the JBS of the present invention is obtained by incorporating the SBD into the PIN structure device G2 FRD manufactured by Nihon Inter Corporation. The JBS of the present invention has advantageous characteristics such as soft recovery of SBD without losing the high speed of the PIN structure device G2 FRD manufactured by Nihon Inter Corporation.

  In the experiment, the reverse recovery time trr was changed by changing the number of P layers 104 in each of the regions 101-1 to 101-7 shown in FIG. 7 and the area ratio of the P layer 104 to the N-layer 103 around it. The forward voltage drop VF and the like were measured. In addition to the stripe shape as shown in FIG. 7, the shape of the P layer 104 may be a dot shape such as a circle or a rectangle. In the experiment, a stripe shape is used as the shape of the P layer 104. . The width of the surface of the N− layer 103 between two adjacent P layers 104 was set to 10.05 μm after boron diffusion. The depth Xjp of the P layer 104 was set to 3 μm. In the step shown in FIG. 1B, when boron diffuses from the outer edge portion of the semiconductor oxide film 121a laterally by 0.7 times (= 2.1 μm) the depth of the guard ring portion 105 and the P layer 104. Assumed.

  13 and 14 are diagrams showing switching waveforms of the JBS of the first embodiment. Specifically, the JBS used for obtaining the switching data shown in FIGS. 13 and 14 is configured in the same manner as the JBS of the first embodiment described above. That is, in the JBS used for acquiring the switching data shown in FIGS. 13 and 14, heavy metal is diffused only from the surface of the guard ring portion 105, and from the surfaces of the P layer 104 and the N− layer 103. Is not diffused by heavy metals. Further, in the JBS used for acquiring the switching data shown in FIGS. 13 and 14, the surface of the guard ring part 105 and the surface of the P layer 104 occupying the area of the region inside the outer edge part of the guard ring part 105. The area ratio K is set to 50%. 13 and 14, “G2 FRD” indicates the switching waveform of the PIN structure device G2 FRD manufactured by Nihon Inter Co., Ltd., and “Conventional JBS” is the JBS described in JP-A-2004-55586. The switching waveform of the conventional JBS configured as described above is shown. FIG. 13 shows a switching waveform at Tj = 25 ° C., and FIG. 14 shows a switching waveform at Tj = 100 ° C.

  As shown in FIG. 13 and FIG. 14, the maximum reverse recovery current value IRM could be made smaller in the JBS of the first embodiment than in the PIN structure device G2 FRD manufactured by Nihon Inter Corporation and the conventional JBS. . That is, the soft recovery characteristics could be improved as compared with the PIN structure device G2 FRD manufactured by Nihon Inter Corporation and the conventional JBS. Further, as shown in FIG. 14, at Tj = 100 ° C., the convergence of the reverse recovery current of the JBS of the first embodiment is the same as the reverse recovery current of the PIN structure device G2 FRD manufactured by Nihon Inter Corporation and the conventional JBS. It was faster than convergence. That is, it was considered that the JBS of the first embodiment was excellent in high temperature characteristics.

  By comparing the switching waveform of the JBS of the first embodiment shown in FIGS. 13 and 14 with the switching waveform of the conventional JBS described in FIG. 30 of Japanese Patent Application Laid-Open No. 2004-55586, the first embodiment of the present invention is compared. It was confirmed that the epoch-making soft recovery characteristic could be obtained by the JBS of one embodiment. That is, the conventional JBS described in FIG. 30 of Japanese Patent Application Laid-Open No. 2004-55586 cannot obtain a reverse recovery time trr characteristic shorter than that of the PIN structure device G2 FRD manufactured by Nihon Inter Corporation. Although the maximum reverse recovery current value IRM was larger than that of the PIN structure device G2 FRD made by the company, as shown in FIG. 14, the JBS of the first embodiment is more than the PIN structure device G2 FRD made by Nihon Inter Corporation. In addition, a short reverse recovery time trr characteristic could be obtained, and the maximum reverse recovery current value IRM could be made smaller than that of the PIN structure device G2 FRD manufactured by Nihon Inter Corporation.

  Table 1 is a table showing VF-trr trade-off characteristics in each Pt diffusion pattern, and FIG. 15 is a diagram showing VF-trr trade-off characteristics in each Pt diffusion pattern shown in Table 1. In Table 1 and FIG. 15, “K = 50” means that the ratio K of the surface area of the guard ring portion 105 and the P layer 104 occupying the area inside the outer edge portion of the guard ring portion 105 is 50%. “K = 65” indicates that the ratio K is set to 65%. The “GR portion only” means that the heavy metal is diffused only from the surface of the guard ring portion 105, and the heavy metal is not diffused from the surfaces of the P layer 104 and the N− layer 103. The data of JBS is shown.

  “Three P layers” means that heavy metal is not diffused from the surfaces of the guard ring portion 105 and the N− layer 103, and the second region 104-2 and the fourth region 104 among the plurality of P layers 104. 4 shows the JBS data of the seventh embodiment in which heavy metal is diffused from the surface of the P layer 104 in the three regions of -4 and the sixth region 104-6. “Two P layers” means that heavy metals are not diffused from the surfaces of the guard ring portion 105 and the N− layer 103, and the second region 104-2 and the sixth region 104 out of the plurality of P layers 104. The JBS data of the thirteenth embodiment in which heavy metals are diffused from the surface of the P layer 104 in the two regions of −6 are shown. “One P layer” means that heavy metal is not diffused from the surfaces of the guard ring portion 105 and the N− layer 103, and the P layer 104 in the fourth region 104-4 among the plurality of P layers 104. 14 shows JBS data of a fourteenth embodiment in which heavy metals are diffused from the surface of the steel.

  As shown in FIG. 15, in the JBS of the present invention, each Pt pattern at K = 65% shows excellent trr-VF trade-off characteristics on the normal temperature (Tj = 25 ° C.) side, and high temperature (Tj = 100 ° C) also showed a good value. On the high temperature side, the reverse recovery time trr increased as the number of P layers 104 in which heavy metal was diffused from the surface decreased. In the case where heavy metal is diffused only from the surface of the guard ring part 105, and K = 50%, the forward voltage drop VF is a PIN structure device G2 manufactured by Nippon Inter Corp. at room temperature (Tj = 25 ° C.). Although it was as high as the forward voltage drop VF of FRD, a very short reverse recovery time trr could be obtained. In addition, when heavy metal was diffused only from the surface of the guard ring portion 105, and K = 50%, a very short reverse recovery time trr could be obtained even at high temperatures (Tj = 100 ° C.). The switching waveforms shown in FIGS. 13 and 14 show the switching waveforms of this sample, that is, the sample in which heavy metal is diffused only from the surface of the guard ring portion 105 at K = 50%. A heavy metal is diffused only from the surface of the guard ring part 105, and a sample at room temperature (Tj = 25 ° C.) out of K = 50% is shown in the experimental factor table (Tables 2 to 4) described later. Corresponds to “Serial No. 103”, and the high-temperature (Tj = 100 ° C.) sample corresponds to “Serial No. 104” in the experimental factor table described later.

  Further, as shown in FIG. 15, according to the JBS of the present invention, a favorable trr− in which the reverse recovery time trr is shorter and the forward voltage drop VF is lower than the PIN structure device G2 FRD manufactured by Nihon Inter Corporation. A VF trade-off curve was obtained.

  Further, as shown in FIG. 15, four samples of “GR portion only”, “3 P layers”, “2 P layers” and “1 P layer” were located on the same trade-off curve. In other words, when the user requests a high-speed reverse recovery time trr, “GR section only” may be selected. When the reverse recovery time trr is somewhat low, a low forward voltage drop VF is required. It was confirmed that any one of “3 P layers”, “2 P layers”, and “1 P layer” may be selected.

  In addition, the surface of the N-layer 103 and Pt must be in contact with each of the four samples of “GR portion only”, “3 P layers”, “2 P layers”, and “1 P layer”. 15 can be avoided, so that a combination of four samples of “GR part only”, “3 P layers”, “2 P layers” and “1 P layer” is also shown in FIG. It is considered to be located on the off curve.

  Tables 2 to 4 are experimental factor tables showing samples used in the experiment. Among the columns indicating “Pt diffusion region” in Tables 2 to 4, “GR part only” corresponds to the JBS of the first embodiment described above, and “three P layers” represents the above-described first item. 7 corresponds to the JBS of the thirteenth embodiment described above, and “one P layer” corresponds to the JBS of the fourteenth embodiment described above. It corresponds to. On the other hand, “the entire P layer” and “only the SBD portion” do not correspond to the embodiment of the present invention, and correspond to a comparative example in which the configuration of the present invention is not adopted.

  Table 5 shows the relationship between the K value and the forward voltage drop VF characteristics, and FIG. 16 shows the relationship between the forward voltage drop VF characteristics shown in Table 5. In FIG. 16, the horizontal axis indicates the value of the ratio K described above, and the vertical axis indicates the forward voltage drop VF. The sample used is equivalent to the JBS of the first embodiment (“GR part only”), a specific resistance of 3.5 Ω · cm is selected, and a thickness of the N− layer 103 of 15 μm is selected. , 950 ° C. was selected as the Pt diffusion temperature, and the measured temperatures were compared between Tj = 25 ° C. and Tj = 100 ° C. As a comparative example, a PIN structure device G2 FRD manufactured by Nippon Inter Corp. and a JBS sample of Pt 930 ° C. (K = 65%) were used.

  As shown in FIG. 16, in a slightly small current region (IF = 1 (A)), the forward voltage drop VF characteristic of SBD generally shows a lower rise than that of the PIN diode. However, both Tj = 25 ° C. and 100 ° C. tended to be lower VF, and the forward voltage drop VF increased as the K value increased. In the vicinity of the rated current (IF = 10 (A)), the VF value on the K = 50% side is large, and the VF value tends to decrease toward K = 80% (both Tj = 25 ° C. and 100 ° C.). The value of the forward voltage drop VF (IF = 10 (A) only) of the PIN structure device G2 FRD manufactured by Nihon Inter Corporation is K = 50% JBS at Tj = 25 ° C., and K = 50 at Tj = 100 ° C. % Of JBS became closest. The JBS of the Pt930 ° C. diffusion product had a lower VF value than the JBS having the same K value (K = 65%).

  FIG. 17 shows the VF-IF characteristic at Tj = 25 ° C., and FIG. 18 shows the VF-IF characteristic at Tj = 100 ° C. As shown in FIGS. 17 and 18, on the relatively low current region side (VF ≦ 0.6 (hot) to 0.7 (cold) V), the rise at the lower VF is seen as the K value is lower. On the relatively high current region side (VF ≧ 0.6 (hot) to 0.7 (cold) V), the reverse rotation is performed so that the K value becomes the low VF in the descending order, and the reverse point is Tj = 25. At ℃, VF≈0.74 (V), and at Tj = 100 ° C., VF≈0.6 (V).

  FIG. 19 is a diagram showing the relationship between the K value and the reverse recovery time trr characteristic. As shown in FIG. 19, the reverse recovery time trr has a tendency to increase as the value of the ratio K increases. That is, an increase in K value means an increase in minority carriers (holes). The reverse recovery time trr of the PIN structure device G2 FRD manufactured by Nihon Inter Corporation was close to the reverse recovery time trr of the JBS of the present invention with K = 50%. The reverse recovery time trr of the Pt 930 ° C. diffusion was longer.

  FIG. 20 is a diagram showing the relationship between the K value and -di / dt. As shown in FIG. 20, the shorter reverse recovery time trr (K = 50%) is considered to be closer to SBD and soft recovery, and the longer reverse recovery time trr is closer to PIN. It is considered hard recovery.

  FIG. 21 is a diagram showing SOF (softness factor) at each K value. As shown in FIG. 21, an element closer to the SBD that has a shorter reverse recovery time trr (K = 50%) gives a larger softness factor, ie, soft recovery, while longer It has been found that elements closer to the PIN that are of the reverse recovery time trr give a smaller softness factor, ie hard recovery.

  FIG. 22 is a diagram showing Qrr (reverse recovery charge) at each K value, and FIG. 23 is a diagram showing an integrated value of Qrr (reverse recovery charge) at each K value.

  FIG. 24 is a diagram showing the relationship between the difference in the Pt diffusion region pattern and the reverse recovery time trr characteristic. 24 and FIGS. 25 to 28 described later, “GR portion only” corresponds to the JBS of the first embodiment described above, and “three P layers” corresponds to the JBS of the seventh embodiment described above. The “two P layers” correspond to the JBS of the thirteenth embodiment described above, and the “one P layer” corresponds to the JBS of the fourteenth embodiment described above. In the sample in which Pt is diffused from the entire surface of the P layer and the sample in which Pt is diffused from the SBD surface, the surface of the N-layer 103 that becomes the SBD surface is doped and diffused with Pt. The breakdown voltage VR characteristics could not be obtained normally.

  As shown in FIG. 24, the reverse recovery time trr is Tj = 25 ° C. and 100 ° C. in the order of “GR part only”, “P layer 3”, “P layer 2”, “P layer 1”. In any case, it became longer. Due to the difference in the amount of Pt (heavy metal killer) incorporated into the N-layer 103, there is a difference between the "P layer 3" sample, the "P layer 2" sample, and the "P layer 1" sample. It is thought that occurred.

  FIG. 25 is a diagram showing the relationship between the Pt diffusion pattern region difference and the dir / dt characteristic, FIG. 26 is a diagram showing the relationship between the Pt diffusion region pattern difference and the Qrr property, and FIG. 27 is a diagram of the Pt diffusion region pattern. FIG. 28 shows the relationship between the difference and the maximum reverse recovery current value IRM characteristic, and FIG. 28 shows the relationship between the difference in the Pt diffusion pattern region and the SOF characteristic.

  FIG. 29 and FIG. 30 are diagrams showing the relationship between the difference in Pt diffusion region pattern at normal temperature (Tj = 25 ° C.) and the forward voltage drop VF. 29 and 30, “GR part only” corresponds to the JBS of the first embodiment described above, and “three P layers” corresponds to the JBS of the seventh embodiment described above. “Two P layers” corresponds to the JBS of the thirteenth embodiment described above, and “one P layer” corresponds to the JBS of the fourteenth embodiment described above. On the other hand, “the entire P layer” and “only the SBD portion” do not correspond to the embodiment of the present invention, and correspond to a comparative example in which the configuration of the present invention is not adopted.

  As shown in FIG. 29, in the case of “only GR part”, the leakage current did not flow until the forward voltage drop VF = about 0.3V. Although not shown in FIG. 29, in the sample having two guard ring portions, a result almost coincident with the curve of “GR portion only” was obtained. In the sample of “GR part only”, the current in the low voltage region was difficult to flow. When the forward voltage drop VF ≧ 0.6 V, the current flowed easily in the order of “GR portion only”> “P layer entire surface” ≈ “SBD portion only”. The cause is considered to be that the lifetime of holes becomes longer in the order of “only GR part”, “entire P layer”, and “only SBD part”.

  In addition, as shown in FIG. 30, there was almost no difference when the forward voltage drop VF ≦ 0.8V. When the forward voltage drop VF> 0.8V, the current flowed easily in the order of “one P layer”> “two P layers”> “three P layers”.

  FIG. 31 and FIG. 32 are diagrams showing the relationship between the difference in the Pt diffusion region pattern at high temperature (Tj = 100 ° C.) and the forward voltage drop VF. In FIG. 31 and FIG. 32, “GR part only” corresponds to the JBS of the first embodiment described above, and “three P layers” correspond to the JBS of the seventh embodiment described above. “Two P layers” corresponds to the JBS of the thirteenth embodiment described above, and “one P layer” corresponds to the JBS of the fourteenth embodiment described above. On the other hand, “the entire P layer” and “only the SBD portion” do not correspond to the embodiment of the present invention, and correspond to a comparative example in which the configuration of the present invention is not adopted.

  As shown in FIG. 31, a reactive current region was generated in the low voltage portion even at a high temperature (Tj = 100 ° C.). On the high current region side, there was a tendency that current tends to flow in the order of “GR part only”> “SBD part only”> “P layer entire surface”. Further, as shown in FIG. 32, in the high current region (forward voltage drop VF> 0.8 V) side, as in the case of room temperature (Tj = 25 ° C.) shown in FIG. 30, “one P layer”> There was a tendency that current tends to flow in the order of “two P layers”> “three P layers”.

  FIG. 33 shows the relationship between the Pt diffusion pattern and the forward voltage drop VF characteristic in the small current region (0.01 A), and FIG. 34 shows the relationship between the Pt diffusion pattern and the forward voltage drop VF property in the medium current region (1A). FIG. 35 is a diagram showing the relationship, and FIG. 35 is a diagram showing the relationship between the Pt diffusion pattern and the forward voltage drop VF characteristic in the rated current region (10A). 33 to 35, “GR portion only” corresponds to the above-described JBS of the first embodiment, and “three P layers” corresponds to the above-described JBS of the seventh embodiment. “Two P layers” corresponds to the JBS of the thirteenth embodiment described above, and “one P layer” corresponds to the JBS of the fourteenth embodiment described above. On the other hand, “the entire P layer” and “only the SBD portion” do not correspond to the embodiment of the present invention, and correspond to a comparative example in which the configuration of the present invention is not adopted.

  As shown in FIG. 33, in the small current region (0.01 A), the two forward voltage drops VF of “the entire P layer” and “only the SBD portion” were extremely low. As shown in FIG. 34, in the middle current region (1A), the two forward voltage drops VF of “the entire surface of the P layer” and “only the SBD portion” were slightly higher. As shown in FIG. 35, in the rated current region (10 A), from about 0.33 (“P layer entire surface”) to 0.60 (“SBD part only”) V, “GR part only” (881.4 mV) However, the forward voltage drop VF increased. It is considered that a “normal SBD interface (or PN junction interface)” is not obtained for “the entire surface of the P layer” and “only the SBD part” compared to the other four.

  As shown in FIGS. 29 and 31, for the two patterns “entire surface of P layer” and “only SBD part”, the forward voltage drop VF in the low current region is extremely low, and Tj = 25 ° C. → Tj = 100 At 0 ° C., the rising voltage was almost 0 V, and the forward voltage drop VF was very low compared to the other four patterns.

  Regarding the two patterns of “P-layer entire surface” and “SBD part only”, a low forward voltage drop VF itself should be welcomed, but considering that the breakdown voltage is NG, a normal SBD interface is obtained. It is thought that it is not. Therefore, these are considered to be consumed as reactive current (or short-circuit current).

  In order to shorten the reverse recovery time trr, a higher Pt processing temperature (930 to 950 ° C.) is required. In this temperature region, the surface of the N− layer 103 is in direct contact with Pt atoms. It is considered that not only the barrier height peculiar to a normal barrier metal can be obtained but also an intermetallic compound that seems to be Pt—Pd—Mo—Silicide is formed at the interface.

  Of course, there is also a method in which an unnecessary part on the surface of this intermetallic compound (Silicide) is removed and an SBD is formed using the Silicide part remaining in the Si bulk. However, it is believed that the method is not suitable for stably supplying products to the market on a commercial basis.

  FIG. 36 is a diagram showing the VF-trr trade-off characteristic at each K value. In FIG. 36, “K = 50” means that the ratio K of the surface area of the guard ring part 105 and the P layer 104 occupying the area inside the outer edge part of the guard ring part 105 is set to 50%. “K = 65” indicates that the ratio K is set to 65%, and “K = 80” indicates that the ratio K is set to 80%. Is shown. The “GR portion only” means that the heavy metal is diffused only from the surface of the guard ring portion 105, and the heavy metal is not diffused from the surfaces of the P layer 104 and the N− layer 103. The data of JBS is shown. That is, all the data of the JBS of the present invention in FIG. 36 is “GR part only” data. In the JBS of the present invention in FIG. 36, the wafer specific resistance ρ is set to 3.5 Ω · cm, and the thickness of the N− layer 103 is set to 15 μm.

  As shown in FIG. 36, in the JBS of the present invention, the forward voltage drop VF is lower than the PIN structure device G2 FRD manufactured by Nihon Inter Corporation at both normal temperature (Tj = 25 ° C.) and high temperature (Tj = 100 ° C.). was gotten. In particular, at a high temperature (Tj = 100 ° C.), a forward voltage drop VF considerably lower than that of the PIN structure device G2 FRD manufactured by Nihon Inter Corporation was obtained.

  FIG. 37 is a diagram showing the VF-trr trade-off characteristic at each K value. In FIG. 37, “K = 50” means that the ratio K of the surface area of the guard ring part 105 and the P layer 104 occupying the area inside the outer edge part of the guard ring part 105 is set to 50%. “K = 65” indicates that the ratio K is set to 65%, and “K = 80” indicates that the ratio K is set to 80%. Is shown. The “GR portion only” means that the heavy metal is diffused only from the surface of the guard ring portion 105, and the heavy metal is not diffused from the surfaces of the P layer 104 and the N− layer 103. The data of JBS is shown. That is, all the data of the JBS of the present invention in FIG. 37 is “GR section only” data. In the JBS of the present invention in FIG. 37, the wafer specific resistance ρ is set to 4.85 Ω · cm. In FIG. 37, among the JBS data of the present invention, “♦” and small “■” indicate that Pt was diffused at 950 ° C., and “◯” indicates that Pt was diffused at 930 ° C. Shows things.

  As shown in FIG. 37, in the JBS of the present invention, the forward voltage drop VF is lower than the PIN structure device G2 FRD manufactured by Nihon Inter Corporation at both normal temperature (Tj = 25 ° C.) and high temperature (Tj = 100 ° C.). was gotten. A lower forward voltage drop VF was obtained in the case where Pt was diffused at 930 ° C. than in the case where Pt was diffused at 950 ° C. That is, a lower forward voltage drop VF was obtained when the diffusion temperature of heavy metal was lowered.

It is the figure which showed the manufacturing process of JBS of 1st Embodiment. It is the figure which showed the manufacturing process of JBS of 1st Embodiment. It is the figure which showed the manufacturing process of JBS of 1st Embodiment. It is the figure which looked at the N-layer 103, P layer 104, and guard ring part 105 which were shown in FIGS. 1-3 from the upper side of FIGS. 1-3. It is the figure which looked at the heavy metal diffusion mask pattern 140 and its opening 141 shown in FIG. 2B from the upper side of FIG. It is the figure which showed a part of manufacturing process of JBS of 7th Embodiment. It is the figure which looked at the N-layer 103, P layer 104, and guard ring part 105 which were shown in FIGS. 1-3 and FIG. 6 from the upper side of FIGS. 1-3, and FIG. It is the figure which looked at the heavy metal diffusion mask pattern 240 and its opening 241 of JBS of 7th Embodiment shown in FIG. 6 from the upper side of FIG. It is the figure which showed a part of manufacturing process of JBS of 13th Embodiment. It is the figure which looked at the heavy metal diffusion mask pattern 340 and its opening part 341 of JBS of 13th Embodiment shown in FIG. 9 from the upper side of FIG. It is the figure which showed a part of manufacturing process of JBS of 14th Embodiment. It is the figure which looked at the heavy metal diffusion mask pattern 440 and its opening 441 of JBS of 14th Embodiment shown in FIG. 11 from the upper side of FIG. It is the figure which showed the switching waveform of JBS of 1st Embodiment. It is the figure which showed the switching waveform of JBS of 1st Embodiment. FIG. 3 is a diagram showing VF-trr trade-off characteristics in each Pt diffusion pattern shown in Table 1. 6 is a diagram illustrating a relationship with a forward voltage drop VF characteristic shown in Table 5. FIG. It is the figure which showed the VF-IF characteristic in Tj = 25 degreeC. It is the figure which showed the VF-IF characteristic in Tj = 100 degreeC. It is the figure which showed the relationship between K value and reverse recovery time trr characteristic. It is the figure which showed the relationship between K value and -di / dt. It is the figure which showed SOF (softness factor) in each K value. It is the figure which showed Qrr (reverse recovery electric charge) in each K value. It is the figure which showed the integrated value of Qrr (reverse recovery electric charge) in each K value. It is the figure which showed the relationship between the difference of Pt diffusion area | region pattern, and reverse recovery time trr characteristic. It is the figure which showed the relationship between the difference of Pt diffusion pattern area | region, and dir / dt characteristic. It is the figure which showed the relationship between the difference of Pt diffusion area | region pattern, and a Qrr characteristic. It is the figure which showed the relationship between the difference of a Pt diffusion area | region pattern, and the maximum reverse recovery current value IRM characteristic. It is the figure which showed the relationship between the difference of a Pt diffusion pattern area | region, and a SOF characteristic. It is the figure which showed the relationship between the difference of the Pt diffusion area | region pattern in normal temperature (Tj = 25 degreeC), and the forward voltage drop VF. It is the figure which showed the relationship between the difference of the Pt diffusion area | region pattern in normal temperature (Tj = 25 degreeC), and the forward voltage drop VF. It is the figure which showed the relationship between the difference of the Pt diffusion area | region pattern in high temperature (Tj = 100 degreeC), and the forward voltage drop VF. It is the figure which showed the relationship between the difference of the Pt diffusion area | region pattern in high temperature (Tj = 100 degreeC), and the forward voltage drop VF. It is the figure which showed the relationship between the Pt diffusion pattern and the forward voltage drop VF characteristic in a small electric current area (0.01A). It is the figure which showed the relationship between the Pt diffusion pattern and the forward voltage drop VF characteristic in a middle current region (1A). It is the figure which showed the relationship between the Pt diffusion pattern in a rated current area (10A), and a forward voltage drop VF characteristic. It is the figure which showed the VF-trr trade-off characteristic in each K value. It is the figure which showed the VF-trr trade-off characteristic in each K value. FIG. 8.26. FIG. It is a figure corresponded to FIG. 1 of patent document 1. FIG. It is a figure equivalent to FIG. 2 of patent document 1. FIG. It is a figure equivalent to FIG. 4 of patent document 2. FIG. FIG. 4 is a diagram corresponding to FIG. 3 of Non-Patent Document 4. FIG. FIG. FIG. FIG. FIG. It is the figure which added the result of FIG. 43 to 2.34. FIG. 3 is a diagram corresponding to FIG. 2 of Non-Patent Document 5. 6 is a diagram corresponding to FIG. 5 of Non-Patent Document 5. FIG. It is a figure equivalent to FIG. It is a figure equivalent to FIG. 3 of patent document 6. FIG. It is a diagram showing the diffusion coefficient in silicon and SiO ₂ film. It is the figure which showed U type distribution of Pt in silicon. It is a figure for examining an approximate expression. It is the figure which showed the relationship between (rho) (ohm * cm) in Table 11, and VBO (V). It is the figure which assumed impurity concentration distribution and Pt distribution. It is the figure which showed roughly the three devices of 200V type FRD, 180V type JBS, and 180V type SBD. It is the figure which showed roughly the mode of injection | pouring of the minority carrier (hole) from a SBD interface. FIG. 19 is a diagram corresponding to FIG. 18 of Patent Document 8. FIG. 20 is a diagram corresponding to FIG. 19 of Patent Document 8. It is the figure which showed the inside of the general (JBS) device at the time of ON-> OFF switching. It is a figure for demonstrating a normal guard ring. FIG. 13 is a diagram corresponding to FIG. 12 of Patent Document 7. FIG. 6 is a diagram corresponding to FIG. 5 of Patent Document 9. It is a figure equivalent to FIG. 3 of patent document 7. FIG. FIG. 5 is a diagram corresponding to FIG. 4 of Patent Document 7.

Explanation of symbols

103 N-layer 104 P layer 105 Guard ring part 140 Heavy metal diffusion mask pattern 141 Opening part

Claims (19)

  In a JBS in which a Schottky junction and a PN junction coexist, a plurality of P layers are arranged at predetermined intervals in an N-layer inside the guard ring portion, and the surface of the guard ring portion and the plurality of P layers are arranged. A heavy metal is diffused from a part of the surface of the NBS, and a heavy metal is not diffused from the surface of the N-layer.   2. The JBS according to claim 1, wherein heavy metal is diffused from a surface of the guard ring part, and heavy metal is not diffused from a surface of the P layer inside the guard ring part. 3.   2. The JBS according to claim 1, wherein heavy metal is diffused from a part of the surface of the P layer arranged inside the guard ring part, and heavy metal is not diffused from the surface of the guard ring part. 3.   According to the required reverse recovery time trr characteristic or forward voltage drop VF characteristic of JBS, it is selected whether heavy metal is diffused from the surface of the guard ring part or heavy metal is diffused from the surface of the P layer. The manufacturing method of JBS as described in any one of Claims 1-3 characterized by these.   The method of manufacturing a JBS according to claim 4, wherein the shape of each P layer arranged inside the guard ring portion is a stripe shape or a dot shape.   4. A plurality of P layer groups comprising a plurality of P layers are provided, and a plurality of P layer groups are connected via a connecting portion and arranged inside the guard ring portion. JBS according to item.   4. A P ++ layer that is shallower than the P layer and deeper than the P layer is formed in the P layer, and heavy metals are diffused from the surface of the P ++ layer. JBS as described in.   2. The JBS according to claim 1, wherein platinum is diffused at a diffusion temperature of 930 to 950 ° C. from a part of the surface of the guard ring part and the surfaces of the plurality of P layers.   2. The JBS according to claim 1, wherein a wafer specific resistance of the JBS is set to 3.5 to 4.85 Ω · cm, and a thickness of the N− layer is set to about 15 μm.   When the reduction of the reverse recovery time trr is required, the surface area of the P layer where the heavy metal is diffused is increased, and when the reduction of the forward voltage drop VF is required, the surface of the P layer where the heavy metal is diffused The method of manufacturing a JBS according to claim 4, wherein an area of the JBS is reduced.   11. The method of manufacturing a JBS according to claim 10, wherein heavy metal is diffused from a plurality of locations among the surfaces of a plurality of P layers arranged inside the guard ring portion.   4. The JBS according to claim 3, wherein a plurality of P layers are arranged inside the guard ring portion at intervals, and heavy metals are diffused from the surfaces of the plurality of P layers.   4. The JBS according to claim 3, wherein the outer edge of the opening of the heavy metal diffusion mask pattern is arranged on the inner side than the outer edge of the P layer.   A P ++ layer having a depth shallower than the depth of the P layer and higher than the concentration of the P layer is formed in the P layer, and an outer edge portion of the P ++ layer and an outer edge portion of the opening of the heavy metal diffusion mask pattern are formed. 14. The JBS according to claim 13, wherein the size of the surface of the P ++ layer and the size of the opening of the heavy metal diffusion mask pattern are set so as to substantially match, and heavy metal is diffused from the surface of the P ++ layer. .   2. The JBS according to claim 1, wherein heavy metal is diffused so that a lifetime of a peripheral portion of the inner region is shorter than a lifetime of a central portion of the inner region of the guard ring portion.   The heavy metal is diffused from the surface of two or more P layers among a plurality of P layers arranged at intervals in the N-layer inside the guard ring portion. JBS.   2. The JBS according to claim 1, wherein two P layers in which heavy metals are diffused from the surface are arranged inside the guard ring portion so as to sandwich a P layer in which heavy metals are not diffused from the surface. .   A P layer in which heavy metal cannot be diffused from the surface is disposed between two P layers in which heavy metal is diffused from the surface, and P in which heavy metal cannot be diffused more than the surface area of the P layer from which heavy metal is diffused. The JBS according to claim 17, wherein the area of the surface of the layer is set small.   A Schottky barrier diode having a Schottky junction, characterized in that heavy metal is diffused from the surface of the guard ring part, and heavy metal is not diffused from the surface of the N-layer disposed inside the guard ring part. Barrier diode.

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