US20200295178A1 - Semiconductor device and manufacturing method for semiconductor device - Google Patents
Semiconductor device and manufacturing method for semiconductor device Download PDFInfo
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- US20200295178A1 US20200295178A1 US16/702,404 US201916702404A US2020295178A1 US 20200295178 A1 US20200295178 A1 US 20200295178A1 US 201916702404 A US201916702404 A US 201916702404A US 2020295178 A1 US2020295178 A1 US 2020295178A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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Definitions
- the present invention relates to a semiconductor device, and a manufacturing method for a semiconductor device.
- a configuration including, between a cell region and a termination region, an impurity layer having impurity concentration lower than that of a portion of the cell region on the termination region side has been proposed (for example, Japanese Patent Application Laid-Open No. 2000-150859 and Japanese Patent Application Laid-Open No. 2013-125928).
- a positive voltage can be less liable to be applied to a portion between an anode and a cathode in the semiconductor device during recovery. Therefore, current concentration, as well as heat generation, caused at the portion of the cell region on the termination region side during recovery can be reduced.
- the present invention has been made in view of the problems as described above, and has an object to provide a technology that can reduce manufacturing costs of a semiconductor device.
- the present invention is intended for a semiconductor device.
- the semiconductor device includes a semiconductor substrate of a first conductivity type, and an insulation film. In the semiconductor substrate, a cell region, an interface region surrounding the cell region, and a termination region surrounding the interface region are defined.
- the insulation film is disposed on a surface of the semiconductor substrate.
- the insulation film includes a first opening portion in at least one of the cell region and the termination region, and a second opening portion in the interface region.
- the second opening portion has an opening ratio lower than an opening ratio of the first opening portion.
- the semiconductor device further includes a first impurity layer of a second conductivity type, and a second impurity layer of the second conductivity type.
- the first impurity layer is disposed on the surface of the semiconductor substrate below the first opening portion.
- the second impurity layer has impurity concentration lower than impurity concentration of the first impurity layer, and is disposed on the surface of the semiconductor substrate below the second opening portion.
- Manufacturing costs of the semiconductor device can be reduced.
- FIG. 1 is a plan view illustrating a configuration of a related semiconductor device.
- FIG. 2 is a cross-sectional diagram illustrating a configuration of the related semiconductor device.
- FIG. 3 is a circuit diagram illustrating an equivalent circuit of the related semiconductor device at the time of recovery operation.
- FIG. 4 is a graph showing various waveforms of the related semiconductor device at the time of recovery operation.
- FIG. 5 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 6 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 7 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 8 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 9 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 10 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 11 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 12 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 13 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 14 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 15 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- FIG. 16 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a first embodiment.
- FIG. 17 is a plan view illustrating a configuration of a first opening portion and second opening portions according to the first embodiment.
- FIG. 18 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment.
- FIG. 19 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment.
- FIG. 20 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment.
- FIG. 21 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment.
- FIG. 22 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment.
- FIG. 23 is a plan view illustrating a configuration of a first opening portion and second opening portions according to a first modification.
- FIG. 24 is a plan view illustrating a configuration of first opening portions and second opening portions according to the first modification.
- FIG. 25 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second modification.
- FIG. 26 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second embodiment.
- FIG. 27 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a third embodiment.
- a semiconductor device related thereto (hereinafter referred to as a “related semiconductor device”) will be described.
- description will be given by taking an example of a configuration in which a first conductivity type is an N type, and a second conductivity type is a P type.
- the first conductivity type may be a P type
- the second conductivity type may be an N type.
- FIG. 1 is a plan view illustrating a configuration of a related semiconductor device.
- the related semiconductor device includes an N-type semiconductor substrate 51 .
- the semiconductor substrate 51 may be made of a general semiconductor wafer, or may be made of an epitaxial growth layer.
- a cell portion 1 being a cell region, an interface portion 2 being an interface region, and a termination portion 3 being a termination region are defined.
- the interface portion 2 is adjacent to and surrounds the cell portion 1
- the termination portion 3 is adjacent to and surrounds the interface portion 2 .
- the cell portion 1 for example, at least one of a semiconductor switching element with an embedded diode (not shown) and a diode is disposed.
- a semiconductor switching element with an embedded diode not shown
- description will be given by taking an example of a configuration in which a semiconductor switching element with an embedded diode is disposed in the cell portion 1 . In such a configuration, the cell portion 1 conducts electricity when the semiconductor switching element is turned on, and the termination portion 3 holds a breakdown voltage when the semiconductor switching element is turned off.
- FIG. 2 is a cross-sectional diagram taken along the line A-A′ of FIG. 1 .
- the related semiconductor device includes a drift layer 6 , an anode layer 7 , guard ring layers 8 , a ballast resistance layer 9 , an insulation film 10 , a front surface electrode 11 , a termination conductive film 12 , a semi-insulation film 13 , a buffer layer 14 , an N+ layer 15 , and a back surface electrode 16 .
- the drift layer 6 is a portion of the N-type semiconductor substrate 51 , except the anode layer 7 , the guard ring layers 8 , the ballast resistance layer 9 , the buffer layer 14 , and the N+ layer 15 .
- the insulation film 10 is an oxide film, for example, and is disposed on a surface of the semiconductor substrate 51 .
- the insulation film 10 includes a first opening portion in at least one of the cell portion 1 and the termination portion 3 , and a P+-type first impurity layer is disposed in a surface of the semiconductor substrate 51 below the first opening portion.
- the first opening portions are disposed in both of the cell portion 1 and the termination portion 3
- the P+-type first impurity layer is each of the anode layer 7 disposed below a first opening portion 10 a 1 of the cell portion 1 and the guard ring layers 8 disposed below first opening portions 10 a 2 of the termination portion 3
- a plurality of guard ring layers 8 are disposed below a plurality of first opening portions 10 a 2 of the termination portion 3
- the front surface electrode 11 being a conductive film is disposed on the insulation film 10 , and is connected to the anode layer 7 through the first opening portion 10 a 1 .
- the termination conductive film 12 being a conductive film is disposed on the insulation film 10 , and is connected to the guard ring layers 8 through the first opening portions 10 a 2 .
- the semi-insulation film 13 is disposed on a portion of the front surface electrode 11 on the termination portion 3 side, the termination conductive film 12 , and the insulation film 10 .
- the semi-insulation film 13 is a compound film containing a compound of elements of the semiconductor substrate 51 and an insulator, or an organic semiconductor film.
- the buffer layer 14 is an N-type impurity layer having impurity concentration higher than that of the drift layer 6 (semiconductor substrate 51 ), and is disposed on the semiconductor substrate 51 on a back surface side.
- the N+ layer 15 is an N+-type impurity layer having impurity concentration higher than that of the drift layer 6 and the buffer layer 14 , and is disposed further on the back surface side of the semiconductor substrate 51 than the buffer layer 14 .
- the back surface electrode 16 is disposed on a back surface of the N+ layer 15 .
- FIG. 3 is a circuit diagram illustrating an equivalent circuit of the related semiconductor device at the time of recovery operation.
- a semiconductor switching element 61 is a semiconductor switching element disposed in the cell portion 1
- a diode 62 is a diode disposed in the cell portion 1 .
- An anode of the diode 62 corresponds to the front surface electrode 11
- a cathode of the diode 62 corresponds to the back surface electrode 16 .
- a circuit parasitic inductance L s is connected between the diode 62 and the semiconductor switching element 61
- a load inductance L m is connected in parallel with the diode 62 .
- a gate resistor R g is connected between the semiconductor switching element 61 and an AC power supply 63 .
- Vcc is 1800 V, for example.
- Temperature is 423 K, for example.
- a gate voltage is ⁇ 15 V to 15 V, for example.
- the circuit parasitic inductance L s is 2.47 ⁇ H
- the semiconductor switching element 61 of the cell portion 1 when the semiconductor switching element 61 of the cell portion 1 is turned on, carriers are stored in the cell portion 1 and the termination portion 3 . Further, when the semiconductor switching element 61 is in a recovery state, a positive voltage is applied between the front surface electrode 11 functioning as an anode and the back surface electrode 16 functioning as a cathode.
- FIG. 4 is a graph showing a current waveform (Jf: solid line) and a voltage waveform (Vka: one-dot chain line) of the related semiconductor device at the time of recovery operation.
- Jf solid line
- Vka voltage waveform
- the diode 62 is in a state of a high reverse current, a high voltage, and a high dI/dt.
- internal currents flow toward the anode side.
- internal currents from the termination portion 3 concentrate on a contact portion of the cell portion 1 on the termination side (a portion indicated by the dotted circle of FIG. 2 ), and thus heat is generated in this portion.
- the ballast resistance layer 9 for reducing this heat generation is disposed.
- the ballast resistance layer 9 is a P-type impurity layer that has impurity concentration lower than that of the anode layer 7 and the guard ring layers 8 and that is disposed in the interface portion 2 .
- the entire upper surface of the ballast resistance layer 9 is covered by the insulation film 10 .
- the ballast resistance layer 9 is connected to and located between the anode layer 7 and the guard ring layer 8 , and a lower end of the ballast resistance layer 9 is located above lower ends of the anode layer 7 and the guard ring layer 8 .
- the ballast resistance layer 9 configured as described above functions as a resistor (ballast resistor) for internal currents during recovery. Therefore, the internal currents as well as heat generation can be reduced.
- the lower the concentration of the ballast resistance layer 9 the higher the resistance value of the ballast resistor. As a result, recovery interruption capability of reducing the internal currents can be enhanced without increasing a chip size.
- FIG. 5 to FIG. 15 are each a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device.
- the semiconductor substrate 51 is prepared. Then, as illustrated in FIG. 6 , an insulation film 21 is formed on a surface of the semiconductor substrate 51 .
- a formation method for the insulation film 21 for example, heating of the semiconductor substrate 51 , deposition or coating on the semiconductor substrate 51 , or the like is used.
- the injected impurities 22 are activated.
- the anode layer 7 is formed below the first opening portion 10 a 1
- the guard ring layers 8 are formed below the first opening portions 10 a 2 .
- bottom portions of the first opening portions 10 a 1 and 10 a 2 are oxidized, and an insulation film 23 is formed on the bottom portions.
- photolithography and etching are performed on the insulation film 21 , thereby forming an opening portion 24 exposing the semiconductor substrate 51 in the insulation film 21 of the interface portion 2 .
- P-type impurities 25 are injected into the semiconductor substrate 51 with concentration lower than the injection concentration of FIG. 8 , through the opening portion 24 .
- the injected impurities 25 are activated.
- the ballast resistance layer 9 is formed below the opening portion 24 . Note that, due to the temperature during this activation, a bottom portion of the opening portion 24 is oxidized, and an insulation film 26 is formed on the bottom portion.
- the insulation film 23 on the bottom portions of the first opening portions 10 a 1 and 10 a 2 is removed, by using a mask used in the process of FIG. 7 .
- the insulation film 10 of FIG. 2 is formed.
- the front surface electrode 11 and the termination conductive film 12 are selectively formed on the anode layer 7 and the guard ring layers 8 , respectively, and as illustrated in FIG. 15 , the semi-insulation film 13 is selectively formed.
- the buffer layer 14 , the N+ layer 15 , and the back surface electrode 16 are formed on the back surface of the semiconductor substrate 51 . Consequently, the related semiconductor device of FIG. 2 is completed.
- FIG. 16 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention.
- the cross-sectional diagram of FIG. 16 corresponds to the cross-sectional diagram of FIG. 2 .
- components according to the first embodiment components that are the same as or similar to the components described above are denoted by the same or similar reference signs, and different components will be mainly described.
- the insulation film 10 not only includes the first opening portions 10 a 1 and 10 a 2 , but also includes a plurality of second opening portions 10 b in the interface portion 2 , each of which has an opening ratio lower than each of the first opening portions 10 a 1 and 10 a 2 .
- the opening ratio refers to a ratio of an opening portion (the first opening portion or the second opening portion) per unit area, and is a value obtained by dividing the total area of an opening portion by the total area of the insulation film 10 and the opening portion.
- FIG. 17 is a plan view illustrating the first opening portion 10 a 1 and the second opening portions 10 b .
- the first opening portion 10 a 2 is substantially the same as the first opening portion 10 a 1 , and hereinafter the same holds true.
- the first opening portion 10 a 1 does not particularly have a pattern
- the second opening portions 10 b have a stripe pattern.
- each of the plurality of second opening portions 10 b has an opening ratio lower than each of the first opening portions 10 a 1 and 10 a 2 .
- the ballast resistance layer 9 is a P-type second impurity layer having impurity concentration lower than that of the anode layer 7 and the guard ring layers 8 , as with the ballast resistance layer 9 of the related semiconductor device.
- concentration of the anode layer 7 on a surface of the semiconductor substrate 51 is 10 16 to 10 18 cm 3
- concentration of the ballast resistance layer 9 on a surface of the semiconductor substrate 51 is 10 14 to 10 16 cm ⁇ 3 .
- the concentration of the ballast resistance layer 9 on a surface of the semiconductor substrate 51 be 0.001 times higher than and 0.5 times lower than the concentration of the anode layer 7 on a surface of the semiconductor substrate 51 .
- the ballast resistance layer 9 according to the first embodiment is disposed in a surface of the semiconductor substrate 51 throughout positions below each of the plurality of second opening portions 10 b . Further, the semi-insulation film 13 is connected to the front surface electrode 11 and the termination conductive film 12 , and is connected to the ballast resistance layer 9 through the second opening portions 10 b.
- FIG. 18 to FIG. 22 are each a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment.
- the semiconductor substrate 51 is prepared ( FIG. 5 ), and the insulation film 21 is formed on a surface of the semiconductor substrate 51 ( FIG. 6 ). Then, as illustrated in FIG. 18 , photolithography and etching are performed, thereby forming the first opening portions 10 a 1 and 10 a 2 exposing the semiconductor substrate 51 in the insulation film 21 of the cell portion 1 and the termination portion 3 , and forming the second opening portions 10 b exposing the semiconductor substrate 51 in the insulation film 21 of the interface portion 2 . In this manner, the insulation film 10 of FIG. 16 is substantially formed.
- P-type impurities 32 are injected into the semiconductor substrate 51 with relatively high concentration, through the first opening portions 10 a 1 and 10 a 2 .
- the second opening portions 10 b have an opening ratio lower than that of the first opening portions 10 a 1 and 10 a 2 , the impurities 32 less easily reach the semiconductor substrate below the second opening portions 10 b . Therefore, when an injection device uniformly applies the P-type impurities 32 , the P-type impurities 32 are injected into the semiconductor substrate 51 below the first opening portions 10 a 1 and 10 a 2 with relatively high concentration, whereas the P-type impurities 32 are injected into the semiconductor substrate 51 below the second opening portions 10 b with concentration lower than the above concentration.
- the injected impurities 32 are activated.
- the anode layer 7 is formed below the first opening portion 10 a 1
- the guard ring layers 8 are formed below the first opening portions 10 a 2
- the ballast resistance layer 9 is formed below the second opening portions 10 b .
- an insulation film (not shown) formed on bottom portions of the first opening portions 10 a 1 and 10 a 2 and the second opening portions 10 b due to the temperature during the activation is removed, by using a mask used in the process of FIG. 18 .
- the front surface electrode 11 and the termination conductive film 12 are selectively formed on the anode layer 7 and the guard ring layers 8 , respectively, and as illustrated in FIG. 22 , the semi-insulation film 13 is selectively formed. Then, the buffer layer 14 , the N+ layer 15 , and the back surface electrode 16 are formed on the back surface of the semiconductor substrate 51 . Consequently, the semiconductor device of FIG. 16 is completed.
- ballast resistance layer 9 which are required in the manufacture of the related semiconductor device, are not required. Therefore, manufacturing costs of the semiconductor device can be reduced.
- the second opening portions 10 b are covered by the semi-insulation film 13 . Therefore, deterioration in characteristics of the device due to contaminants can be less liable to be caused.
- the semi-insulation film 13 has characteristics of hopping conduction of electric charge, and therefore electric charge induced by external influence flows due to the hopping conduction. As a result, local potential distribution abnormality due to external influence can be less liable to be caused, and thus long-term reliability can be enhanced.
- first opening portion 10 a 1 and the second opening portions 10 b is illustrated in FIG. 17 .
- the shapes of the second opening portions 10 b and the first opening portions 10 a 1 and 10 a 2 are not limited to those illustrated in FIG. 17 , as long as the opening ratio of the second opening portions 10 b is lower than the opening ratio of each of the first opening portions 10 a 1 and 10 a 2 .
- the first opening portion 10 a 1 may not particularly have a pattern, whereas the second opening portions 10 b may have a dotted pattern.
- first opening portions 10 a 1 may have a stripe pattern, and the second opening portions 10 b may have a dotted pattern.
- first opening portions 10 a 1 may have a stripe pattern
- the second opening portions 10 b may have a stripe pattern having a different size from the stripe pattern of the first opening portions 10 a 1
- first opening portions 10 a 1 may have a honeycomb pattern
- the second opening portions 10 b may have a honeycomb pattern having a different size and density from the honeycomb pattern of the first opening portions 10 a 1 .
- each of the first opening portions 10 a 1 and the second opening portions 10 b are uniformly disposed in the insulation film 10 , but may be locally non-uniform.
- the semiconductor device according the first embodiment includes the termination conductive film 12 ( FIG. 16 ). However, as illustrated in FIG. 25 , the semiconductor device may not include the termination conductive film 12 .
- the semi-insulation film 13 is connected to the front surface electrode 11 , and is connected to each of the guard ring layers 8 and the ballast resistance layer 9 through the first opening portions 10 a 2 and the second opening portions 10 b . Also with such a configuration, effects similar to those of the first embodiment can be obtained. Note that the above second modification can also be similarly applied to various configurations other than the first embodiment.
- FIG. 26 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second embodiment of the present invention.
- the cross-sectional diagram of FIG. 26 corresponds to the cross-sectional diagram of FIG. 16 .
- components according to the second embodiment components that are the same as or similar to the components described above are denoted by the same or similar reference signs, and different components will be mainly described.
- the semiconductor device according to the second embodiment has a configuration that a P+ layer 17 is added to the configuration ( FIG. 16 ) of the semiconductor device according to the first embodiment.
- the N+ layer 15 is an N+-type third impurity layer having impurity concentration higher than that of the semiconductor substrate 51 .
- the N+ layer 15 is disposed on the back surface of the semiconductor substrate 51 , at the interface portion 2 , the cell portion 1 and a corresponding portion which is a portion of the termination portion 3 corresponding to one guard ring layer 8 a closest to the interface portion 2 .
- the P+ layer 17 is a P+-type fourth impurity layer.
- the P+ layer 17 is disposed on the back surface of the semiconductor substrate 51 , at a position of the termination portion 3 except the above-mentioned corresponding portion.
- FIG. 27 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a third embodiment of the present invention.
- the cross-sectional diagram of FIG. 27 corresponds to the cross-sectional diagram of FIG. 16 .
- components according to the third embodiment components that are the same as or similar to the components described above are denoted by the same or similar reference signs, and different components will be mainly described.
- the semiconductor device according to the third embodiment has a configuration that a lifetime killer level 18 is added to the configuration ( FIG. 16 ) of the semiconductor device according to the first embodiment.
- the semiconductor substrate 51 includes the lifetime killer level 18 in the termination portion 3 .
- the lifetime killer level 18 is formed by electron beam irradiation, proton irradiation, heavy metal diffusion, or the like.
- carrier concentration of the termination portion 3 can be reduced owing to the lifetime killer level 18 . Therefore, reduction of currents flowing from the termination portion 3 toward the anode side during recovery, i.e., recovery interruption capability, can be further enhanced.
- each embodiment can be freely combined with each other, and each embodiment can be modified or omitted as appropriate, within the scope of the invention.
Abstract
Description
- The present invention relates to a semiconductor device, and a manufacturing method for a semiconductor device.
- Regarding a semiconductor device, a configuration including, between a cell region and a termination region, an impurity layer having impurity concentration lower than that of a portion of the cell region on the termination region side has been proposed (for example, Japanese Patent Application Laid-Open No. 2000-150859 and Japanese Patent Application Laid-Open No. 2013-125928). According to such a configuration including the impurity layer, a positive voltage can be less liable to be applied to a portion between an anode and a cathode in the semiconductor device during recovery. Therefore, current concentration, as well as heat generation, caused at the portion of the cell region on the termination region side during recovery can be reduced.
- However, when the impurity layer as above is added, there are problems that an additional mask and an additional process are required, and manufacturing costs are increased.
- The present invention has been made in view of the problems as described above, and has an object to provide a technology that can reduce manufacturing costs of a semiconductor device.
- The present invention is intended for a semiconductor device. The semiconductor device includes a semiconductor substrate of a first conductivity type, and an insulation film. In the semiconductor substrate, a cell region, an interface region surrounding the cell region, and a termination region surrounding the interface region are defined. The insulation film is disposed on a surface of the semiconductor substrate. The insulation film includes a first opening portion in at least one of the cell region and the termination region, and a second opening portion in the interface region. The second opening portion has an opening ratio lower than an opening ratio of the first opening portion. The semiconductor device further includes a first impurity layer of a second conductivity type, and a second impurity layer of the second conductivity type. The first impurity layer is disposed on the surface of the semiconductor substrate below the first opening portion. The second impurity layer has impurity concentration lower than impurity concentration of the first impurity layer, and is disposed on the surface of the semiconductor substrate below the second opening portion.
- Manufacturing costs of the semiconductor device can be reduced.
- These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
-
FIG. 1 is a plan view illustrating a configuration of a related semiconductor device. -
FIG. 2 is a cross-sectional diagram illustrating a configuration of the related semiconductor device. -
FIG. 3 is a circuit diagram illustrating an equivalent circuit of the related semiconductor device at the time of recovery operation. -
FIG. 4 is a graph showing various waveforms of the related semiconductor device at the time of recovery operation. -
FIG. 5 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 6 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 7 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 8 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 9 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 10 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 11 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 12 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 13 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 14 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 15 is a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. -
FIG. 16 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a first embodiment. -
FIG. 17 is a plan view illustrating a configuration of a first opening portion and second opening portions according to the first embodiment. -
FIG. 18 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment. -
FIG. 19 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment. -
FIG. 20 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment. -
FIG. 21 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment. -
FIG. 22 is a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment. -
FIG. 23 is a plan view illustrating a configuration of a first opening portion and second opening portions according to a first modification. -
FIG. 24 is a plan view illustrating a configuration of first opening portions and second opening portions according to the first modification. -
FIG. 25 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second modification. -
FIG. 26 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second embodiment. -
FIG. 27 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a third embodiment. - <Related Semiconductor Device>
- First, prior to describing a semiconductor device according to embodiments of the present invention, a semiconductor device related thereto (hereinafter referred to as a “related semiconductor device”) will be described. In the following, description will be given by taking an example of a configuration in which a first conductivity type is an N type, and a second conductivity type is a P type. However, this is not restrictive, and the first conductivity type may be a P type, and the second conductivity type may be an N type.
-
FIG. 1 is a plan view illustrating a configuration of a related semiconductor device. As illustrated inFIG. 1 , the related semiconductor device includes an N-type semiconductor substrate 51. Thesemiconductor substrate 51 may be made of a general semiconductor wafer, or may be made of an epitaxial growth layer. - In the
semiconductor substrate 51, acell portion 1 being a cell region, aninterface portion 2 being an interface region, and atermination portion 3 being a termination region are defined. In plan view, theinterface portion 2 is adjacent to and surrounds thecell portion 1, and thetermination portion 3 is adjacent to and surrounds theinterface portion 2. In thecell portion 1, for example, at least one of a semiconductor switching element with an embedded diode (not shown) and a diode is disposed. In the following, description will be given by taking an example of a configuration in which a semiconductor switching element with an embedded diode is disposed in thecell portion 1. In such a configuration, thecell portion 1 conducts electricity when the semiconductor switching element is turned on, and thetermination portion 3 holds a breakdown voltage when the semiconductor switching element is turned off. -
FIG. 2 is a cross-sectional diagram taken along the line A-A′ ofFIG. 1 . The related semiconductor device includes adrift layer 6, ananode layer 7,guard ring layers 8, aballast resistance layer 9, aninsulation film 10, afront surface electrode 11, a terminationconductive film 12, asemi-insulation film 13, abuffer layer 14, anN+ layer 15, and aback surface electrode 16. - In the example of
FIG. 2 , thedrift layer 6 is a portion of the N-type semiconductor substrate 51, except theanode layer 7, theguard ring layers 8, theballast resistance layer 9, thebuffer layer 14, and theN+ layer 15. - The
insulation film 10 is an oxide film, for example, and is disposed on a surface of thesemiconductor substrate 51. Theinsulation film 10 includes a first opening portion in at least one of thecell portion 1 and thetermination portion 3, and a P+-type first impurity layer is disposed in a surface of thesemiconductor substrate 51 below the first opening portion. - In the following, an example in which the first opening portions are disposed in both of the
cell portion 1 and thetermination portion 3 will be described. Also, an example in which the P+-type first impurity layer is each of theanode layer 7 disposed below a first opening portion 10 a 1 of thecell portion 1 and the guard ring layers 8 disposed below first opening portions 10 a 2 of thetermination portion 3, and in which a plurality of guard ring layers 8 are disposed below a plurality of first opening portions 10 a 2 of thetermination portion 3 will be described. - The
front surface electrode 11 being a conductive film is disposed on theinsulation film 10, and is connected to theanode layer 7 through the first opening portion 10 a 1. The terminationconductive film 12 being a conductive film is disposed on theinsulation film 10, and is connected to the guard ring layers 8 through the first opening portions 10 a 2. - The
semi-insulation film 13 is disposed on a portion of thefront surface electrode 11 on thetermination portion 3 side, the terminationconductive film 12, and theinsulation film 10. For example, thesemi-insulation film 13 is a compound film containing a compound of elements of thesemiconductor substrate 51 and an insulator, or an organic semiconductor film. - The
buffer layer 14 is an N-type impurity layer having impurity concentration higher than that of the drift layer 6 (semiconductor substrate 51), and is disposed on thesemiconductor substrate 51 on a back surface side. TheN+ layer 15 is an N+-type impurity layer having impurity concentration higher than that of thedrift layer 6 and thebuffer layer 14, and is disposed further on the back surface side of thesemiconductor substrate 51 than thebuffer layer 14. Theback surface electrode 16 is disposed on a back surface of theN+ layer 15. -
FIG. 3 is a circuit diagram illustrating an equivalent circuit of the related semiconductor device at the time of recovery operation. Asemiconductor switching element 61 is a semiconductor switching element disposed in thecell portion 1, and adiode 62 is a diode disposed in thecell portion 1. An anode of thediode 62 corresponds to thefront surface electrode 11, and a cathode of thediode 62 corresponds to theback surface electrode 16. A circuit parasitic inductance Ls is connected between thediode 62 and thesemiconductor switching element 61, and a load inductance Lm is connected in parallel with thediode 62. A gate resistor Rg is connected between thesemiconductor switching element 61 and anAC power supply 63. Vcc is 1800 V, for example. Temperature is 423 K, for example. A gate voltage is −15 V to 15 V, for example. The circuit parasitic inductance Ls is 2.47 μH, for example. - Here, when the
semiconductor switching element 61 of thecell portion 1 is turned on, carriers are stored in thecell portion 1 and thetermination portion 3. Further, when thesemiconductor switching element 61 is in a recovery state, a positive voltage is applied between thefront surface electrode 11 functioning as an anode and theback surface electrode 16 functioning as a cathode. -
FIG. 4 is a graph showing a current waveform (Jf: solid line) and a voltage waveform (Vka: one-dot chain line) of the related semiconductor device at the time of recovery operation. At the time of recovery operation (T1 to T2), thediode 62 is in a state of a high reverse current, a high voltage, and a high dI/dt. As a result, as indicated by the arrows ofFIG. 2 , internal currents flow toward the anode side. Particularly, internal currents from thetermination portion 3 concentrate on a contact portion of thecell portion 1 on the termination side (a portion indicated by the dotted circle ofFIG. 2 ), and thus heat is generated in this portion. - In the related semiconductor device, the
ballast resistance layer 9 for reducing this heat generation is disposed. Theballast resistance layer 9 is a P-type impurity layer that has impurity concentration lower than that of theanode layer 7 and the guard ring layers 8 and that is disposed in theinterface portion 2. Note that, as illustrated inFIG. 2 , in the related semiconductor device, the entire upper surface of theballast resistance layer 9 is covered by theinsulation film 10. Further, theballast resistance layer 9 is connected to and located between theanode layer 7 and theguard ring layer 8, and a lower end of theballast resistance layer 9 is located above lower ends of theanode layer 7 and theguard ring layer 8. - The
ballast resistance layer 9 configured as described above functions as a resistor (ballast resistor) for internal currents during recovery. Therefore, the internal currents as well as heat generation can be reduced. The lower the concentration of theballast resistance layer 9, the higher the resistance value of the ballast resistor. As a result, recovery interruption capability of reducing the internal currents can be enhanced without increasing a chip size. - <Manufacturing Method>
- Next, a manufacturing method for the related semiconductor device will be described.
FIG. 5 toFIG. 15 are each a cross-sectional diagram illustrating a manufacturing method for the related semiconductor device. - First, as illustrated in
FIG. 5 , thesemiconductor substrate 51 is prepared. Then, as illustrated inFIG. 6 , aninsulation film 21 is formed on a surface of thesemiconductor substrate 51. As a formation method for theinsulation film 21, for example, heating of thesemiconductor substrate 51, deposition or coating on thesemiconductor substrate 51, or the like is used. - Then, as illustrated in
FIG. 7 , photolithography and etching are performed on theinsulation film 21, thereby performing patterning. In this manner, the first opening portions 10 a 1 and 10 a 2 exposing thesemiconductor substrate 51 are formed in theinsulation film 21 of thecell portion 1 and thetermination portion 3. Then, as illustrated inFIG. 8 , P-type impurities 22 are injected into thesemiconductor substrate 51 with relatively high concentration, through the first opening portions 10 a 1 and 10 a 2. - Next, as illustrated in
FIG. 9 , the injectedimpurities 22 are activated. In this manner, theanode layer 7 is formed below the first opening portion 10 a 1, and the guard ring layers 8 are formed below the first opening portions 10 a 2. Note that, due to the temperature during this activation, bottom portions of the first opening portions 10 a 1 and 10 a 2 are oxidized, and aninsulation film 23 is formed on the bottom portions. - After that, as illustrated in
FIG. 10 , photolithography and etching are performed on theinsulation film 21, thereby forming anopening portion 24 exposing thesemiconductor substrate 51 in theinsulation film 21 of theinterface portion 2. Then, as illustrated inFIG. 11 , P-type impurities 25 are injected into thesemiconductor substrate 51 with concentration lower than the injection concentration ofFIG. 8 , through the openingportion 24. - Next, as illustrated in
FIG. 12 , the injectedimpurities 25 are activated. In this manner, theballast resistance layer 9 is formed below the openingportion 24. Note that, due to the temperature during this activation, a bottom portion of the openingportion 24 is oxidized, and aninsulation film 26 is formed on the bottom portion. - Then, as illustrated in
FIG. 13 , theinsulation film 23 on the bottom portions of the first opening portions 10 a 1 and 10 a 2 is removed, by using a mask used in the process ofFIG. 7 . In this manner, theinsulation film 10 ofFIG. 2 is formed. Then, as illustrated inFIG. 14 , thefront surface electrode 11 and the terminationconductive film 12 are selectively formed on theanode layer 7 and the guard ring layers 8, respectively, and as illustrated inFIG. 15 , thesemi-insulation film 13 is selectively formed. Then, thebuffer layer 14, theN+ layer 15, and theback surface electrode 16 are formed on the back surface of thesemiconductor substrate 51. Consequently, the related semiconductor device ofFIG. 2 is completed. - Incidentally, to form the
ballast resistance layer 9 in the manufacturing process of the related semiconductor device, a dedicated mask used inFIG. 10 , and dedicated processes used in the injection process of theimpurities 25 ofFIG. 11 and the activation process ofFIG. 12 are required. As a result, a problem of causing increase in manufacturing costs is present. In light of this, in the embodiments of the present invention described below, this problem can be solved. -
FIG. 16 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention. The cross-sectional diagram ofFIG. 16 corresponds to the cross-sectional diagram ofFIG. 2 . In the following, of components according to the first embodiment, components that are the same as or similar to the components described above are denoted by the same or similar reference signs, and different components will be mainly described. - As illustrated in
FIG. 16 , theinsulation film 10 according to the first embodiment not only includes the first opening portions 10 a 1 and 10 a 2, but also includes a plurality ofsecond opening portions 10 b in theinterface portion 2, each of which has an opening ratio lower than each of the first opening portions 10 a 1 and 10 a 2. Here, the opening ratio refers to a ratio of an opening portion (the first opening portion or the second opening portion) per unit area, and is a value obtained by dividing the total area of an opening portion by the total area of theinsulation film 10 and the opening portion. -
FIG. 17 is a plan view illustrating the first opening portion 10 a 1 and thesecond opening portions 10 b. Note that the first opening portion 10 a 2 is substantially the same as the first opening portion 10 a 1, and hereinafter the same holds true. In the example ofFIG. 17 , the first opening portion 10 a 1 does not particularly have a pattern, whereas thesecond opening portions 10 b have a stripe pattern. As a result, each of the plurality ofsecond opening portions 10 b has an opening ratio lower than each of the first opening portions 10 a 1 and 10 a 2. - The
ballast resistance layer 9 according to the first embodiment is a P-type second impurity layer having impurity concentration lower than that of theanode layer 7 and the guard ring layers 8, as with theballast resistance layer 9 of the related semiconductor device. In the first embodiment, concentration of theanode layer 7 on a surface of thesemiconductor substrate 51 is 1016 to 1018 cm3, and concentration of theballast resistance layer 9 on a surface of thesemiconductor substrate 51 is 1014 to 1016 cm−3. Note that it is preferable that the concentration of theballast resistance layer 9 on a surface of thesemiconductor substrate 51 be 0.001 times higher than and 0.5 times lower than the concentration of theanode layer 7 on a surface of thesemiconductor substrate 51. - Further, as illustrated in
FIG. 16 , theballast resistance layer 9 according to the first embodiment is disposed in a surface of thesemiconductor substrate 51 throughout positions below each of the plurality ofsecond opening portions 10 b. Further, thesemi-insulation film 13 is connected to thefront surface electrode 11 and the terminationconductive film 12, and is connected to theballast resistance layer 9 through thesecond opening portions 10 b. - <Manufacturing Method>
- Next, a manufacturing method for the semiconductor device according to the first embodiment will be described.
FIG. 18 toFIG. 22 are each a cross-sectional diagram illustrating a manufacturing method for the semiconductor device according to the first embodiment. - First, as with the case of the related semiconductor device, the
semiconductor substrate 51 is prepared (FIG. 5 ), and theinsulation film 21 is formed on a surface of the semiconductor substrate 51 (FIG. 6 ). Then, as illustrated inFIG. 18 , photolithography and etching are performed, thereby forming the first opening portions 10 a 1 and 10 a 2 exposing thesemiconductor substrate 51 in theinsulation film 21 of thecell portion 1 and thetermination portion 3, and forming thesecond opening portions 10 b exposing thesemiconductor substrate 51 in theinsulation film 21 of theinterface portion 2. In this manner, theinsulation film 10 ofFIG. 16 is substantially formed. - Next, as illustrated in
FIG. 19 , P-type impurities 32 are injected into thesemiconductor substrate 51 with relatively high concentration, through the first opening portions 10 a 1 and 10 a 2. Note that since thesecond opening portions 10 b have an opening ratio lower than that of the first opening portions 10 a 1 and 10 a 2, theimpurities 32 less easily reach the semiconductor substrate below thesecond opening portions 10 b. Therefore, when an injection device uniformly applies the P-type impurities 32, the P-type impurities 32 are injected into thesemiconductor substrate 51 below the first opening portions 10 a 1 and 10 a 2 with relatively high concentration, whereas the P-type impurities 32 are injected into thesemiconductor substrate 51 below thesecond opening portions 10 b with concentration lower than the above concentration. - Then, as illustrated in
FIG. 20 , the injectedimpurities 32 are activated. In this manner, theanode layer 7 is formed below the first opening portion 10 a 1, the guard ring layers 8 are formed below the first opening portions 10 a 2, and theballast resistance layer 9 is formed below thesecond opening portions 10 b. Note that an insulation film (not shown) formed on bottom portions of the first opening portions 10 a 1 and 10 a 2 and thesecond opening portions 10 b due to the temperature during the activation is removed, by using a mask used in the process ofFIG. 18 . - Next, as illustrated in
FIG. 21 , thefront surface electrode 11 and the terminationconductive film 12 are selectively formed on theanode layer 7 and the guard ring layers 8, respectively, and as illustrated inFIG. 22 , thesemi-insulation film 13 is selectively formed. Then, thebuffer layer 14, theN+ layer 15, and theback surface electrode 16 are formed on the back surface of thesemiconductor substrate 51. Consequently, the semiconductor device ofFIG. 16 is completed. - <Overview of First Embodiment>
- According to the semiconductor device according to the first embodiment as described above, dedicated mask and processes for forming the
ballast resistance layer 9, which are required in the manufacture of the related semiconductor device, are not required. Therefore, manufacturing costs of the semiconductor device can be reduced. - Note that, in the configuration in which the semiconductor substrate 51 (ballast resistance layer 9) in the
second opening portions 10 b is exposed, contaminants may enter thesemiconductor substrate 51, and characteristics of the device may be deteriorated. Further, due to the influence of external electric charge in an application environment, the surface of thesemiconductor substrate 51 may be charged up through an oxide film, and long-term reliability of the semiconductor device may be deteriorated. - In light of this, in the first embodiment, the
second opening portions 10 b are covered by thesemi-insulation film 13. Therefore, deterioration in characteristics of the device due to contaminants can be less liable to be caused. Further, thesemi-insulation film 13 has characteristics of hopping conduction of electric charge, and therefore electric charge induced by external influence flows due to the hopping conduction. As a result, local potential distribution abnormality due to external influence can be less liable to be caused, and thus long-term reliability can be enhanced. - <First Modification>
- In the first embodiment, an example of the first opening portion 10 a 1 and the
second opening portions 10 b is illustrated inFIG. 17 . However, the shapes of thesecond opening portions 10 b and the first opening portions 10 a 1 and 10 a 2 are not limited to those illustrated inFIG. 17 , as long as the opening ratio of thesecond opening portions 10 b is lower than the opening ratio of each of the first opening portions 10 a 1 and 10 a 2. For example, as illustrated inFIG. 23 , the first opening portion 10 a 1 may not particularly have a pattern, whereas thesecond opening portions 10 b may have a dotted pattern. Further, for example, as illustrated inFIG. 24 , first opening portions 10 a 1 may have a stripe pattern, and thesecond opening portions 10 b may have a dotted pattern. - Further, although illustration is omitted, first opening portions 10 a 1 may have a stripe pattern, and the
second opening portions 10 b may have a stripe pattern having a different size from the stripe pattern of the first opening portions 10 a 1. Alternatively, first opening portions 10 a 1 may have a honeycomb pattern, and thesecond opening portions 10 b may have a honeycomb pattern having a different size and density from the honeycomb pattern of the first opening portions 10 a 1. Note that, in the examples of theFIG. 17 ,FIG. 23 , andFIG. 24 , each of the first opening portions 10 a 1 and thesecond opening portions 10 b are uniformly disposed in theinsulation film 10, but may be locally non-uniform. - As described above, by controlling the opening ratio of the
second opening portions 10 b, impurity concentration of theballast resistance layer 9 can be controlled, and thus recovery interruption capability can be controlled. In this manner, a semiconductor device having appropriate recovery interruption capability can be implemented. Note that the above first modification can also be similarly applied to various configurations other than the first embodiment. - <Second Modification>
- The semiconductor device according the first embodiment includes the termination conductive film 12 (
FIG. 16 ). However, as illustrated inFIG. 25 , the semiconductor device may not include the terminationconductive film 12. In this case, thesemi-insulation film 13 is connected to thefront surface electrode 11, and is connected to each of the guard ring layers 8 and theballast resistance layer 9 through the first opening portions 10 a 2 and thesecond opening portions 10 b. Also with such a configuration, effects similar to those of the first embodiment can be obtained. Note that the above second modification can also be similarly applied to various configurations other than the first embodiment. -
FIG. 26 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second embodiment of the present invention. The cross-sectional diagram ofFIG. 26 corresponds to the cross-sectional diagram ofFIG. 16 . In the following, of components according to the second embodiment, components that are the same as or similar to the components described above are denoted by the same or similar reference signs, and different components will be mainly described. - As illustrated in
FIG. 26 , the semiconductor device according to the second embodiment has a configuration that aP+ layer 17 is added to the configuration (FIG. 16 ) of the semiconductor device according to the first embodiment. - The
N+ layer 15 is an N+-type third impurity layer having impurity concentration higher than that of thesemiconductor substrate 51. In the second embodiment, theN+ layer 15 is disposed on the back surface of thesemiconductor substrate 51, at theinterface portion 2, thecell portion 1 and a corresponding portion which is a portion of thetermination portion 3 corresponding to one guard ring layer 8 a closest to theinterface portion 2. - The
P+ layer 17 is a P+-type fourth impurity layer. TheP+ layer 17 is disposed on the back surface of thesemiconductor substrate 51, at a position of thetermination portion 3 except the above-mentioned corresponding portion. - According to the semiconductor device according to the second embodiment configured as described above, reduction of currents flowing from the
termination portion 3 toward the anode side during recovery, i.e., recovery interruption capability, can be further enhanced. -
FIG. 27 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a third embodiment of the present invention. The cross-sectional diagram ofFIG. 27 corresponds to the cross-sectional diagram ofFIG. 16 . In the following, of components according to the third embodiment, components that are the same as or similar to the components described above are denoted by the same or similar reference signs, and different components will be mainly described. - As illustrated in
FIG. 27 , the semiconductor device according to the third embodiment has a configuration that alifetime killer level 18 is added to the configuration (FIG. 16 ) of the semiconductor device according to the first embodiment. Specifically, thesemiconductor substrate 51 includes thelifetime killer level 18 in thetermination portion 3. Note that, for example, thelifetime killer level 18 is formed by electron beam irradiation, proton irradiation, heavy metal diffusion, or the like. - According to the semiconductor device according to the third embodiment configured as described above, carrier concentration of the
termination portion 3 can be reduced owing to thelifetime killer level 18. Therefore, reduction of currents flowing from thetermination portion 3 toward the anode side during recovery, i.e., recovery interruption capability, can be further enhanced. - Note that, in the present invention, each embodiment can be freely combined with each other, and each embodiment can be modified or omitted as appropriate, within the scope of the invention.
- While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
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EP4152413A1 (en) * | 2021-09-15 | 2023-03-22 | Hitachi Energy Switzerland AG | Power diode and method for producing a power diode |
WO2023051911A1 (en) * | 2021-09-29 | 2023-04-06 | Dynex Semiconductor Limited | Semiconductor device |
EP4246588A1 (en) * | 2022-03-16 | 2023-09-20 | Huawei Digital Power Technologies Co., Ltd. | Diode and power circuit |
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JP2000114550A (en) | 1998-10-06 | 2000-04-21 | Hitachi Ltd | Diode and power converter |
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JP5206541B2 (en) * | 2008-04-01 | 2013-06-12 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
US8507352B2 (en) * | 2008-12-10 | 2013-08-13 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
JP5515922B2 (en) * | 2010-03-24 | 2014-06-11 | 富士電機株式会社 | Semiconductor device |
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KR101534106B1 (en) * | 2011-07-05 | 2015-07-06 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
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JP2013187344A (en) | 2012-03-08 | 2013-09-19 | Hitachi Ltd | Semiconductor device and manufacturing method of the same |
JPWO2014054319A1 (en) | 2012-10-02 | 2016-08-25 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
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WO2023051911A1 (en) * | 2021-09-29 | 2023-04-06 | Dynex Semiconductor Limited | Semiconductor device |
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