JP2009501961A - 予測的なプロセッサコンポーネントサスペンドのためのシステム及びその方法 - Google Patents
予測的なプロセッサコンポーネントサスペンドのためのシステム及びその方法 Download PDFInfo
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- JP2009501961A JP2009501961A JP2008505345A JP2008505345A JP2009501961A JP 2009501961 A JP2009501961 A JP 2009501961A JP 2008505345 A JP2008505345 A JP 2008505345A JP 2008505345 A JP2008505345 A JP 2008505345A JP 2009501961 A JP2009501961 A JP 2009501961A
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- 238000000034 method Methods 0.000 title claims description 19
- 239000000725 suspension Substances 0.000 title 1
- 230000002093 peripheral effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 102100027556 39S ribosomal protein L17, mitochondrial Human genes 0.000 description 3
- 101000924474 Homo sapiens Annexin A2 Proteins 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 101100074851 Candida albicans (strain SC5314 / ATCC MYA-2876) LIP7 gene Proteins 0.000 description 1
- 102100023441 Centromere protein J Human genes 0.000 description 1
- 101000907924 Homo sapiens Centromere protein J Proteins 0.000 description 1
- 101000693082 Homo sapiens Serine/threonine-protein kinase 11-interacting protein Proteins 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- YAFQFNOUYXZVPZ-UHFFFAOYSA-N liproxstatin-1 Chemical compound ClC1=CC=CC(CNC=2C3(CCNCC3)NC3=CC=CC=C3N=2)=C1 YAFQFNOUYXZVPZ-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Computer Security & Cryptography (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Executing Machine-Instructions (AREA)
- Microcomputers (AREA)
- Power Sources (AREA)
- Advance Control (AREA)
Abstract
Description
Claims (10)
- 複数の命令を受け取るステップと、
前記複数の命令からの命令シーケンスの実行中に使用されないと予想される、プロセッサの1つ又は2つ以上のコンポーネントを特定するステップと、
前記プロセッサによる前記命令シーケンスの少なくとも一部の実行中に、前記プロセッサの前記1つまたは2つ以上の特定されたコンポーネントの少なくとも1つをサスペンドするステップとを含む、方法。 - 前記少なくとも1つのコンポーネントをサスペンドするステップは、前記少なくとも1つのコンポーネントを1つまたは2つ以上の電源領域から切り離すことを含む、請求項1記載の方法。
- 前記少なくとも1つのコンポーネントをサスペンドするステップは、前記少なくとも1つのコンポーネントをクロックゲーティングすることを含む、請求項1記載の方法。
- 前記少なくとも1つのコンポーネントをサスペンドするステップは、前記少なくとも1つのコンポーネントを再起動するのに消費されると予想される電力量に基づいて、前記少なくとも1つのコンポーネントをサスペンドするか否かを判断するステップを含む、請求項1記載の方法。
- プロセッサであって、
複数のコンポーネントと、
複数の命令を記憶するためのストレージ手段と、
前記プロセッサによる前記複数の命令の命令シーケンスの実行中に使用されないと予想される、前記複数のコンポーネントの1つまたは2つ以上のコンポーネントを特定するための手段と、
前記プロセッサによる前記命令シーケンスの少なくとも一部の実行中に前記1つまたは2つ以上の特定されたコンポーネントの少なくとも1つをサスペンドする手段とを備える、プロセッサ。 - 前記少なくとも1つのコンポーネントをサスペンドするための手段は、前記少なくとも1つのコンポーネントを1つまたは2つ以上の電源領域から切り離すための手段を含む、請求項5記載のプロセッサ。
- 前記命令シーケンスに含まれない命令が前記プロセッサによる実行のために要求される前の継続期間を求めるための手段をさらに備える、請求項5記載のプロセッサ。
- 前記少なくとも1つのコンポーネントをサスペンドするための手段は、前記継続期間が第1のしきい値よりも大きいときに、前記少なくとも1つのコンポーネントをクロックゲーティングするための手段を含む、請求項7記載のプロセッサ。
- 前記少なくとも1つのコンポーネントをサスペンドするための手段は、前記継続期間が第2のしきい値よりも大きいときに、前記少なくとも1つのコンポーネントを1つまたは2つ以上の電源領域から切り離すための手段を含み、ここで、前記第2のしきい値は、前記第1のしきい値よりも大きい、請求項7記載のプロセッサ。
- 前記少なくとも1つのコンポーネントをサスペンドするための手段は、前記継続期間が第1のしきい値よりも大きいときに、前記少なくとも1つのコンポーネントを1つまたは2つ以上の電源領域から切り離すための手段を含む、請求項7記載のプロセッサ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/098,321 US7441136B2 (en) | 2005-04-04 | 2005-04-04 | System for predictive processor component suspension and method thereof |
PCT/US2006/010242 WO2006107589A2 (en) | 2005-04-04 | 2006-03-21 | System for predictive processor component suspension and method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009501961A true JP2009501961A (ja) | 2009-01-22 |
Family
ID=36695060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008505345A Pending JP2009501961A (ja) | 2005-04-04 | 2006-03-21 | 予測的なプロセッサコンポーネントサスペンドのためのシステム及びその方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7441136B2 (ja) |
JP (1) | JP2009501961A (ja) |
KR (1) | KR20070116857A (ja) |
CN (1) | CN101427218A (ja) |
DE (1) | DE112006000824T5 (ja) |
GB (1) | GB2440849B (ja) |
TW (1) | TWI401564B (ja) |
WO (1) | WO2006107589A2 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100806284B1 (ko) * | 2005-12-08 | 2008-02-22 | 한국전자통신연구원 | 동적 전압 스케일링을 적용한 고효율 프로세서 |
JP5247037B2 (ja) * | 2007-01-26 | 2013-07-24 | キヤノン株式会社 | 半導体集積回路及びその制御方法 |
US8103562B2 (en) * | 2007-04-03 | 2012-01-24 | Sony Computer Entertainment America Llc | System and method for processor cycle accounting and valuation |
US8020017B2 (en) * | 2008-08-15 | 2011-09-13 | Freescale Semiconductor, Inc. | Management of power domains in an integrated circuit |
KR101197591B1 (ko) * | 2008-12-22 | 2012-11-08 | 한국전자통신연구원 | 저전력 프로세서 |
JP5674611B2 (ja) * | 2011-09-22 | 2015-02-25 | 株式会社東芝 | 制御システム、制御方法およびプログラム |
US20130262896A1 (en) * | 2012-03-29 | 2013-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Processor and electronic device |
US8954775B2 (en) * | 2012-06-20 | 2015-02-10 | Intel Corporation | Power gating functional units of a processor |
US20140157017A1 (en) * | 2012-12-05 | 2014-06-05 | Qualcomm Incorporated | Power management of communication devices |
JP6521565B2 (ja) * | 2014-01-20 | 2019-05-29 | Dmg森精機株式会社 | 省電力を考慮したncプログラム生成装置 |
US10223123B1 (en) * | 2016-04-20 | 2019-03-05 | Apple Inc. | Methods for partially saving a branch predictor state |
US9977680B2 (en) * | 2016-09-30 | 2018-05-22 | International Business Machines Corporation | Clock-gating for multicycle instructions |
Citations (1)
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JP2001236226A (ja) * | 2000-01-14 | 2001-08-31 | Texas Instr Inc <Ti> | マイクロプロセッサ |
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US5666537A (en) * | 1994-08-12 | 1997-09-09 | Intel Corporation | Power down scheme for idle processor components |
US6012125A (en) * | 1997-06-20 | 2000-01-04 | Advanced Micro Devices, Inc. | Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions |
US6457120B1 (en) * | 1999-11-01 | 2002-09-24 | International Business Machines Corporation | Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions |
US7849463B2 (en) * | 2000-06-02 | 2010-12-07 | Microsoft Corporation | Dynamically variable idle time thread scheduling |
US6839828B2 (en) * | 2001-08-14 | 2005-01-04 | International Business Machines Corporation | SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode |
US6816977B2 (en) * | 2001-12-03 | 2004-11-09 | Hewlett-Packard Development Company, L.P. | Power reduction in computing devices using micro-sleep intervals |
US6795781B2 (en) * | 2002-06-27 | 2004-09-21 | Intel Corporation | Method and apparatus for compiler assisted power management |
US7143243B2 (en) * | 2003-05-29 | 2006-11-28 | Via-Cyrix, Inc. | Tag array access reduction in a cache memory |
US7281144B2 (en) * | 2004-02-17 | 2007-10-09 | Intel Corporation | Power management in communication devices |
US20060074497A1 (en) * | 2004-09-29 | 2006-04-06 | Pollin Robert E | Methods, systems, and articles of manufacture for providing a timing apparatus with an almanac memory |
-
2005
- 2005-04-04 US US11/098,321 patent/US7441136B2/en active Active
-
2006
- 2006-03-21 DE DE112006000824T patent/DE112006000824T5/de not_active Ceased
- 2006-03-21 GB GB0718783A patent/GB2440849B/en not_active Expired - Fee Related
- 2006-03-21 KR KR1020077022720A patent/KR20070116857A/ko not_active Application Discontinuation
- 2006-03-21 CN CNA2006800106584A patent/CN101427218A/zh active Pending
- 2006-03-21 JP JP2008505345A patent/JP2009501961A/ja active Pending
- 2006-03-21 WO PCT/US2006/010242 patent/WO2006107589A2/en active Application Filing
- 2006-03-22 TW TW095109803A patent/TWI401564B/zh active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001236226A (ja) * | 2000-01-14 | 2001-08-31 | Texas Instr Inc <Ti> | マイクロプロセッサ |
Also Published As
Publication number | Publication date |
---|---|
US20060225046A1 (en) | 2006-10-05 |
GB0718783D0 (en) | 2007-11-07 |
TWI401564B (zh) | 2013-07-11 |
US7441136B2 (en) | 2008-10-21 |
WO2006107589A2 (en) | 2006-10-12 |
KR20070116857A (ko) | 2007-12-11 |
GB2440849A (en) | 2008-02-13 |
WO2006107589A3 (en) | 2007-02-08 |
DE112006000824T5 (de) | 2008-02-07 |
CN101427218A (zh) | 2009-05-06 |
TW200702979A (en) | 2007-01-16 |
GB2440849B (en) | 2008-10-29 |
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