JP2009294306A - Display device and driving method of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device of an AC drive system which facilitates temperature compensation for reduction in display quality caused by insufficient charge of pixel capacity at the front stage. <P>SOLUTION: A gate signal (G(j)) output to a gate signal line to which at least pixels other than the front stage in terms of a gate scan order in each unit can be output to the gate signal line as a waveform in the form of connecting first voltage including a voltage level gradient period (t1) in which voltage is started from a level of a gate low voltage (Vg1) and is raised to a level of gate high (Vgh) and a voltage level fixed period (t2), following the voltage level gradient period (t1), in which voltage becomes constant at a level of gate high voltage (Vgh) , and second voltage (Vg1) including gate low voltage (Vg1) other than a whole period of the first voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to AC driving of a display device.

  In the driving method of the liquid crystal module, AC driving in which the polarity of the liquid crystal applied voltage is reversed for each frame is mainly used for the purpose of suppressing deterioration of the liquid crystal. When dot inversion is performed in the frame in order to further improve the display quality, as shown in FIG. 9, for each line of the gate signal line and the source signal line, the gate start is also performed. Output to the source signal line every period of the gate signals G (1), G (2),..., G (m) output as the pulse GSP is transferred through the shift register of the gate driver. The polarity of the source signal S to be inverted is reversed. Further, the polarity of the source signal S is inverted even for each frame for the same pixel. In FIG. 9, source signals for two adjacent source signal lines are denoted by S (1) and S (2). As a result, there arises a problem that the power consumption of the source driver increases as the source signal lines are alternately charged to voltages of different polarities. In order to solve this problem, polarity inversion is performed every two lines. So-called 2H dot inversion driving has become the mainstream.

  In the 2H dot inversion drive, as shown in FIG. 10, the gate signals G (1) and G (2) and the gate signals G (3) and G (4) are connected to two continuous gate signal lines. The source signal S having the same polarity is supplied to the pixels on the same source signal line, and the polarity of the source signal S is inverted for the next two gate signal lines on the source signal line, so that adjacent source signal lines are connected to each other. The polarity is also inverted between the source signal S (1) and the source signal S (2). Further, the polarity of the source signal S is inverted even for each frame for the same pixel.

  As shown in FIG. 11, normally, the waveform is rounded at the rise and fall of the source signal S. Therefore, when 2H dot inversion driving is performed, of the two consecutive pixels having the same polarity of the source signal S on the same source signal line, the pixel connected to the previous gate signal line Since the polarity of the source signal S supplied to the source signal line is inverted from that of the source signal S for the pixel on the previous stage, the source signal S has a large rising region or falling region. In the writing period T1 of the source signal S to the pixel capacitor, the liquid crystal application time is shortened by the waveform rounding period Td. That is, the charge stored in the pixel capacitance is reduced. On the other hand, of the two consecutive pixels having the same polarity of the source signal S on the same source signal line, the source signal S is compared to the pixel on the previous stage for the pixel connected to the rear gate signal line. Therefore, there is a case where the source signal S itself is very close to the source signal S of the pixel on the preceding stage because it is not accompanied by polarity inversion and is an adjacent pixel. Therefore, the source signal S does not have a large rising region or falling region, and a sufficient liquid crystal application time can be obtained in the writing period T2 of the source signal S to the pixel capacitor.

  As a result, the ability of the liquid crystal potential to reach the lower pixel is lower than that of the rear pixel.

  In order to solve such a problem, Patent Document 1 discloses a configuration in which the writing period of the source signal S for the pixels on the preceding stage is lengthened.

  FIG. 12 shows the configuration of the display device of Patent Document 1.

In this display device, the timing controller 400 supplies the gate driver 200 with a vertical synchronization start signal STV, a gate selection signal CPV, and a gate enable signal OE. FIG. 13 shows these waveforms. The gate enable signal OE has a low period that determines an active period of the gate signal g (g1, g2,...). The timing control unit 400 controls the high period of the gate enable signal OE, for example, The length of the predetermined Low period can be made different from other Low periods. In this way, when 2H dot inversion driving is performed, the active period of the gate signal g for the pixels on the preceding stage is lengthened so that the substantial charging periods of the pixel capacitances are aligned on the preceding stage and the succeeding stage. .
JP 2003-66928 A (published March 5, 2003)

  However, the above-described insufficient charging of the pixel capacity on the front stage in the 2H dot inversion drive does not affect the display at room temperature or high temperature, and does not cause a problem. This causes a problem of deterioration of display quality.

  Therefore, in the display device of Patent Document 1, if it is attempted to solve the insufficient charge of the pixel capacitor on the front stage only at a low temperature, a temperature sensor is provided in the display device, and the timing controller is based on the temperature detection output from the temperature sensor. However, the low period of the gate enable signal OE must be controlled, and a complicated configuration is required.

  As described above, the conventional display device that performs 2H dot inversion driving has a problem in that a complicated configuration is required to perform temperature compensation for a reduction in display quality caused by insufficient charging of the pixel capacity on the front stage side. It was.

  The present invention has been made in view of the above-described conventional problems, and the object thereof is due to insufficient charging of the pixel capacity at the foremost stage among a plurality of pixels to which source signals having the same polarity are continuously supplied. An object of the present invention is to realize an alternating current drive type display device and a display device drive method capable of easily performing temperature compensation for a reduction in display quality.

  In order to solve the above-described problem, the display device of the present invention divides a plurality of pixels connected to the same source signal line into units each including N consecutive pixels (N is an integer of 2 or more). In an active matrix display device that performs alternating current driving in which the pixels within each unit have the same polarity as the source signal, and the adjacent source units have the opposite polarity with respect to the same source signal line, A voltage level in which the gate signal output to the gate signal line connected to at least the pixels other than the first stage in the above unit in the gate scanning order starts from a level higher than the gate low voltage and gradually increases to the gate high voltage level A first voltage comprising a ramp period and a voltage level constant period that is constant at the gate high voltage level following the voltage level ramp period. And a second voltage comprising a gate low voltage, as connecting combined waveform is characterized in that it is possible to output to the gate signal line.

  According to the above invention, the gate signal output to the gate signal line to which at least the pixels other than the foremost stage are connected is generated as a waveform obtained by connecting the first voltage and the second voltage. The charging of the pixel capacitor during the voltage level gradient period accompanying the rise of the signal proceeds slowly. Therefore, the reachability of the liquid crystal potential at the end of the pixel selection period can be made equal to that of the pixel at the front stage. As a result, the brightness is uniform in the foremost pixel and the other pixels, and a reduction in display quality can be avoided.

  Further, the slope of the voltage level slope period can be arbitrarily formed by utilizing the characteristics of the analog circuit, such as a time constant due to a resistor and a capacitor. Therefore, the slope of the slope can be changed as appropriate according to the configuration of the analog circuit, and the slope of the slope according to the ambient temperature is generated on the analog circuit using the temperature characteristics of the analog circuit. Can do. Therefore, it is possible to easily perform temperature compensation with respect to a decrease in display quality caused by insufficient charging of the frontmost pixel.

  As described above, temperature compensation can be easily performed for a decrease in display quality caused by insufficient charging of the pixel capacity at the front stage in a plurality of pixels to which source signals having the same polarity are continuously supplied. There is an effect that an AC drive type display device can be realized.

  In the display device of the present invention, in order to solve the above-described problem, the first voltage is a voltage level increase period in which the voltage level gradually increases, and the voltage level increase period including at least the voltage level inclination period at the end. A high level period that is a constant level of the gate high voltage following the voltage level increasing period and that first includes at least the constant voltage level period, and a voltage that decreases the voltage level following the high level period It is characterized in that it is a voltage extracted from one of the voltage waveforms included in the original signal, which is a signal generated so that a voltage waveform consisting of a level drop period is repeated continuously.

  According to the above invention, the first voltage is extracted from the original signal generated so that the voltage waveform composed of the voltage level rising period, the high level period, and the voltage level decreasing period is continuously repeated. The first voltage extracted from the original signal can be used for all of the gate signals using the first voltage that is sequentially output to the line, and the gate signal can be easily generated.

  In order to solve the above-described problem, the display device of the present invention extracts the gate signal output to the gate signal line connected to the pixels other than the first stage in each unit from the original signal. And the second voltage are connected to form a gate signal having the waveform, and the gate signal output to the gate signal line to which the pixel in the foremost stage is connected is the High of one voltage waveform. A gate signal obtained by connecting the gate high voltage extracted from a period after the voltage level constant period in the level period and the second voltage is used.

  According to the above invention, all of the gate signal output to the gate signal line connected to the pixels other than the front-stage pixel and the gate signal output to the gate signal line connected to the front-stage pixel are all. Can be generated using the same original signal. Therefore, there is an effect that all gate signals can be easily generated.

  In order to solve the above-described problem, the display device of the present invention includes the first voltage obtained by extracting the gate signal output to the gate signal line to which each pixel is connected, from the original signal, in each unit. A gate signal having the above waveform is formed by connecting the second voltage.

  According to the above invention, there is an effect that all gate signals can be easily generated using the same original signal.

  In the display device of the present invention, in order to solve the above problems, the circuit that generates the original signal includes an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. , A sixth resistor, a constant current source, a capacitor, and a switch. One end of the first resistor is connected to the non-inverting input terminal of the operational amplifier, and the other end of the first resistor is connected to the other end of the first resistor. A constant reference voltage is input, one end of the second resistor is connected to the non-inverting input terminal, the other end of the second resistor is connected to GND, and the third resistor One end is connected to the inverting input terminal of the operational amplifier, the other end of the third resistor is connected to one end of the fourth resistor and one terminal of the switch, and one end of the fourth resistor. Is connected to the output terminal of the operational amplifier. The other end of the resistor is connected to the inverting input terminal, and the other end of the fifth resistor is connected to one end of the sixth resistor and one terminal of the capacitor. The other end is connected to the output terminal of the constant current source, the other end of the capacitor and the other terminal of the switch are connected to GND, and the switch is a control signal for switching between a high level and a low level. It is characterized in that it opens and closes according to.

  According to the above invention, in response to the opening / closing operation of the switch, the subtracting unit configured using the operational amplifier generates the voltage waveform including the voltage level rising period, the high level period, and the voltage level decreasing period of the original signal. There is an effect that it can be easily generated.

  In order to solve the above problems, the display device of the present invention is characterized in that the fifth resistor is a negative thermistor.

  According to the above invention, the gradient of the slope of the voltage level rise period of the original signal can be greatly changed between the low temperature and the normal temperature / high temperature due to the temperature characteristics of the negative characteristic thermistor, so that temperature compensation for the degradation of display quality There is an effect that can be easily performed.

  In order to solve the above-described problem, the display device driving method of the present invention is configured so that a plurality of pixels connected to the same source signal line are in units of consecutive N pixels (N is an integer of 2 or more). Separately, an active matrix display device that performs AC driving in which the source signal is the same polarity among the pixels in each unit and the source signal is opposite in the units adjacent to each other in the same source signal line. In the driving method of the display device for driving the gate signal, the gate signal output to the gate signal line connected to at least the pixels other than the first stage in each unit in the gate scanning order is started from a level equal to or higher than the gate low voltage. The voltage level is gradually increased to the level of the gate high voltage, and is constant at the level of the gate high voltage following the voltage level inclination period. A first voltage comprising the pressure level a predetermined period, a second voltage comprising a gate low voltage, as connecting combined waveform is characterized by outputting to the gate signal line.

  According to the above invention, the gate signal output to the gate signal line to which at least the pixels other than the foremost stage are connected is generated as a waveform obtained by connecting the first voltage and the second voltage. The charging of the pixel capacitor during the voltage level gradient period accompanying the rise of the signal proceeds slowly. Therefore, the reachability of the liquid crystal potential at the end of the pixel selection period can be made equal to that of the pixel at the front stage. As a result, the brightness is uniform in the foremost pixel and the other pixels, and a reduction in display quality can be avoided.

  Further, the slope of the voltage level slope period can be arbitrarily formed by utilizing the characteristics of the analog circuit, such as a time constant due to a resistor and a capacitor. Therefore, the slope of the slope can be changed as appropriate according to the configuration of the analog circuit, and the slope of the slope according to the ambient temperature is generated on the analog circuit using the temperature characteristics of the analog circuit. Can do. Therefore, it is possible to easily perform temperature compensation with respect to a decrease in display quality caused by insufficient charging of the frontmost pixel.

  As described above, temperature compensation can be easily performed for a decrease in display quality caused by insufficient charging of the pixel capacity at the front stage in a plurality of pixels to which source signals having the same polarity are continuously supplied. There is an effect that it is possible to realize a driving method of an AC drive type display device.

  In order to solve the above-described problem, the display device driving method of the present invention uses the first voltage as a voltage level rising period in which the voltage level gradually increases, and at least including the voltage level inclination period at the end. A level rise period, a high level period that is a constant level of the gate high voltage following the voltage level rise period, a high level period that initially includes at least the voltage level constant period, and a voltage level that follows the high level period A voltage extracted from one of the voltage waveforms included in an original signal, which is a signal generated so that a voltage waveform composed of a voltage level decrease period that decreases is continuously repeated, is characterized.

  According to the above invention, the first voltage is extracted from the original signal generated so that the voltage waveform composed of the voltage level rising period, the high level period, and the voltage level decreasing period is continuously repeated. The first voltage extracted from the original signal can be used for all of the gate signals using the first voltage that is sequentially output to the line, and the gate signal can be easily generated.

  In order to solve the above-described problem, the display device driving method of the present invention extracts, from the original signal, the gate signal output to the gate signal line to which the pixels other than the foremost stage are connected in each unit. The first voltage and the second voltage are connected to form a gate signal having the waveform, and the gate signal output to the gate signal line to which the pixel at the front stage is connected is one voltage waveform. A gate signal obtained by connecting the gate high voltage extracted from the period after the voltage level fixed period in the high level period and the second voltage is used.

  According to the above invention, all of the gate signal output to the gate signal line connected to the pixels other than the front-stage pixel and the gate signal output to the gate signal line connected to the front-stage pixel are all. Can be generated using the same original signal. Therefore, there is an effect that all gate signals can be easily generated.

  In order to solve the above-described problem, the display device driving method of the present invention extracts the gate signal output to the gate signal line to which each pixel is connected in each unit from the original signal. And the second voltage are connected to form a gate signal having the above waveform.

  According to the above invention, there is an effect that all gate signals can be easily generated using the same original signal.

  As described above, the display device of the present invention starts the gate signal output to the gate signal line to which the pixels other than the first stage are connected in the gate scanning order in each of the above units from a level higher than the gate low voltage. A voltage level ramp period that gradually rises to the level of the gate high voltage, a voltage level constant period that is constant at the gate high voltage level following the voltage level ramp period, and a gate low voltage. The second voltage can be output to the gate signal line as a connected waveform.

  As described above, temperature compensation can be easily performed for a decrease in display quality caused by insufficient charging of the pixel capacity at the front stage in a plurality of pixels to which source signals having the same polarity are continuously supplied. There is an effect that an AC drive type display device can be realized.

  In the driving method of the display device of the present invention, as described above, the gate signal output to the gate signal line to which the pixels other than the foremost stage are connected in the above units in the gate scanning order is set to a gate low voltage or higher. A first voltage comprising a voltage level ramp period starting from a level and gradually rising to a gate high voltage level; and a voltage level constant period that is constant at the gate high voltage level following the voltage level ramp period; The second voltage composed of the voltage is output to the gate signal line as a connected waveform.

  As described above, temperature compensation can be easily performed for a decrease in display quality caused by insufficient charging of the pixel capacity at the front stage in a plurality of pixels to which source signals having the same polarity are continuously supplied. There is an effect that it is possible to realize a driving method of an AC drive type display device.

  The embodiment of the present invention will be described with reference to FIGS. 1 to 8 as follows.

  FIG. 4 shows a circuit configuration of the liquid crystal display device 1 which is the display device according to the present embodiment.

  The liquid crystal display device 1 includes a liquid crystal panel 2, a flexible printed board 3, and a control board 4.

  In the liquid crystal panel 2, a display region 2a, a plurality of gate signal lines GL, and a plurality of source signal lines SL are formed on a glass substrate using amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like. In addition, the display device is an active matrix display panel in which the gate driver 5 is mounted or built and is bonded to the counter substrate with the liquid crystal layer interposed therebetween. The display area 2a is an area in which a plurality of picture elements PIX ... are arranged in a matrix. The picture element PIX includes a TFT 11, which is a picture element selection element, a liquid crystal capacitor CL, and an auxiliary capacitor Cs. The gate of the TFT 11 is connected to the gate signal line GL, and the source of the TFT 11 is connected to the source signal line SL. The liquid crystal capacitor CL and the auxiliary capacitor Cs are connected to the drain of the TFT 11.

  The plurality of gate signal lines GL are composed of gate signal lines GL1, GL2, GL3,... GLm, and are connected to the output of the gate driver 5, respectively. The plurality of source signal lines SL are made up of source signal lines SL1, SL2, SL3,..., SLn, and are connected to the output of the source driver 6 described later. Further, although not shown, auxiliary capacitance lines for applying an auxiliary capacitance voltage to the auxiliary capacitances Cs of the picture elements PIX... Are formed.

  The gate driver 5 is provided on the display panel 2 in a region adjacent to the display region 2a on one side in the extending direction of the gate signal lines GL... And the gate signal is transmitted to each of the gate signal lines GL. In response to the gate signal, gate pulses are sequentially supplied to the gate signal lines GL.

  The flexible printed circuit board 3 includes a source driver 6. The source driver 6 supplies a source signal to each of the source signal lines SL. The control board 4 is connected to the flexible printed board 3 and supplies necessary signals and power to the gate driver 5 and the source driver 6. Signals and power supplied from the control board 4 to the gate driver 5 are supplied from the liquid crystal panel 2 to the gate driver 5 via the flexible printed board 3.

  The liquid crystal display device 1 having the above configuration will be described below as a display device capable of performing 2H dot inversion driving. However, in the present embodiment, not only 2H dot inversion driving but generally connected to the same source signal line. The divided pixels are divided into units composed of N consecutive pixels (N is an integer of 2 or more), and the pixels within each unit have the same polarity and adjacent to the same source signal line. The unit can be applied to an AC driving method that performs NH dot inversion driving in which the source signal has a reverse polarity. In the case of NH dot inversion driving, in the following description of 2H dot inversion driving, “front side” may be read as “front side” and “back side” may be read as “other than front side”.

  In the following description, it is assumed that the pixel PIX basically has no distinction between colors such as RGB. Therefore, the distinction of the pixels is equivalent to the distinction of the picture element PIX. Even if there is a distinction between colors, regardless of whether the unit of each color combination is aligned along the gate signal line GL or along the source signal line SL, the distinction between the pixels is distinguished from the distinction between the picture elements PIX. It shall be equal.

  FIG. 5 shows the configuration of the gate driver 5.

  The gate driver 5 generates a gate signal G (j) (j = 1, 2,..., Even number of m) having a waveform indicated by a solid line in FIG. 7, and this gate signal G (j) is 2H dots. In the inversion drive, the signal is output as a gate signal of a pixel on the rear stage side of two consecutive pixels that supply a source signal having the same polarity. As will be described later, the gate signal G (j) has a voltage level inclination period t1 at the rising edge. Therefore, charging of the pixel capacitor during this period has a large resistance between the source and drain of the TFT as the selection element. Proceed slowly. Therefore, the reachability of the liquid crystal potential at the end of the pixel selection period can be made equal to that of the preceding pixel. Thereby, the luminance is uniform between the pixels on the front stage and the pixels on the rear stage, and it is possible to avoid deterioration of display quality.

  In order to obtain the same effect by NH dot inversion driving, the gate signal of the pixel other than at the foremost stage should be the waveform of the gate signal G (j) in FIG.

  The same effect can be obtained by generating the gate signal G (j) having the waveform shown in FIG. 7 for all of j = 1, 2,..., M in both 2H dot inversion driving and NH dot inversion driving. It is done.

  The gate driver 5 includes a gate driver chip 21 and a plurality of switch circuits 22... For generating a gate signal G (j) having the above waveform. Although the gate driver chip 21 is COG-mounted on the liquid crystal panel 2, it may be mounted on a flexible printed board, or may be formed monolithically with the display region 2 a on the liquid crystal panel 2 instead of being formed in a chip form. The switch circuits 22 are formed monolithically on the liquid crystal panel 2 with the display area 2a. The switch circuits 22... May be provided on the flexible printed circuit board or may be formed integrally with the gate driver chip 21.

  The gate driver chip 21 includes a shift register. The shift register includes m shift register stages F1, F2,... Fm, and a gate start pulse GSP input to the first shift register stage F1 is converted into a gate clock GCK input to each shift register stage. Are sequentially shifted to the final shift register stage Fm. The gate driver chip 21 outputs an output from each shift register stage during the active period of the input gate enable signal GOE and outputs a low level voltage during the inactive period of the gate enable signal GOE. The connection switching control signal ctl of the switch circuit 22 assigned corresponding to the register stage is used.

  Each switch circuit 22 switches between connecting the gate signal line GL to the input terminal of the voltage VD1 or connecting it to the input terminal of the voltage VD2 in accordance with the control signal ctl input from the gate driver chip 21. The switch circuit 22 corresponding to the shift register stage Fj (j = 1, 2,..., M) connects the gate signal line GLj to the input terminal of the voltage VD1 when the control signal ctl is at the first level, for example, the High level. When the control signal ctl is at the second level, for example, the Low level, the waveform of the gate signal G (j) is formed by connecting the gate signal line GLj to the input terminal of the voltage VD2.

  The waveforms of the gate clock GCK and the gate enable signal GOE are shown in FIG. Although not shown, the gate start pulse GSP is a high-level vertical synchronization pulse having a pulse width corresponding to one period of the gate clock GCK, and is synchronized with the timing of the gate clock GCK. The gate clock GCK, the gate start pulse GSP, and the gate enable signal GOE are supplied from the control board 4. The voltage waveform input as the voltage VD1 corresponds to the voltage (original signal) Vout in FIG. The voltage Vout is a comb-like waveform voltage that is synchronized with the gate clock GCK and has the gate high voltage Vgh that is the high level of the gate signal G at the maximum level. The voltage input as the voltage VD2 is a gate low voltage Vgl which is the low level of the gate signal G.

  FIG. 6 shows a basic configuration of a circuit that generates the voltage Vout.

  This circuit includes an operational amplifier OP, resistors R1, R2, R3, and R4, resistors Rct1 and Rct2, a constant current source Ict, a capacitor Cct, and a switch SW1. The circuit may be provided on the control board 6 or may be mounted or formed on the liquid crystal panel 2.

  One end of the resistor (first resistor) R1 is connected to the non-inverting input terminal of the operational amplifier OP, and the voltage Vin is input to the other end of the resistor R1. The voltage Vin is a constant reference voltage, and is set equal to the gate high voltage Vgh here. One end of the resistor (second resistor) R2 is connected to the non-inverting input terminal, and the other end of the resistor R2 is connected to GND. One end of the resistor (third resistor) R3 is connected to the inverting input terminal of the operational amplifier OP, and the other end of the resistor R3 is connected to one end of the resistor Rct1 and one terminal of the switch SW1. One end of the resistor (fourth resistor) R4 is connected to the output terminal of the operational amplifier OP, and the other end of the resistor R4 is connected to the inverting input terminal.

  The other end of the resistor (fifth resistor) Rct1 is connected to one end of the resistor (sixth resistor) Rct2 and one terminal of the capacitor Cct. The other end of the resistor Rct2 is connected to the output terminal of the constant current source Ict. The other end of the capacitor Cct and the other terminal of the switch SW1 are connected to GND.

  The switch SW1 opens and closes according to the control signal GSD, and is closed when the control signal GSD is at a high level, and is open when the control signal GSD is at a low level. The control signal GSD has a waveform synchronized with the gate clock GCK in the same cycle as shown in FIG. 7, and after a predetermined period after falling from the High level to the Low level at the rising timing of the gate clock GCK. It rises to the High level again.

  In the circuit having the above configuration, the operational amplifier OP and the resistors R1, R2, R3, and R4 constitute a subtracting unit. In this subtraction unit, the following subtraction process is performed.

Vout = Vin. (R2 / (R1 + R2)). (1+ (R4 / R3))
− (R4 / R3) · Vct
Here, if R1 = R4, R2 = R3, and A = R4 / R3,
Vout = Vin-A · Vct
It becomes.

  When the control signal GSD signal becomes low level, the switch SW1 is controlled to be in an open state, and charging from the constant current source Ict to the capacitor Cct is performed via the resistor Rct2. At this time, the voltage Vct at the connection point between the resistor Rct1 and the switch SW1 gradually increases from zero. Subsequently, when the control signal GSD becomes High level, the switch SW1 is controlled to be closed, and the charge charged in the capacitor Cct is gradually discharged through the resistor Rct1. At this time, the voltage Vct gradually decreases and becomes zero after a predetermined time. As a result, the voltage Vct changes in a sawtooth waveform as shown in FIG.

  In the subtracting section, the voltage Vct multiplied by A (= R4 / R3) is subtracted from the voltage Vin. While the voltage Vct is zero, the voltage Vin is output as the voltage Vout. As a result, as shown in FIG. 7, a comb waveform wave voltage Vout composed of a continuous trapezoidal wave is output.

  In FIG. 5, when the gate start pulse GSP is shifted to the shift register stage Fj and the shift register stage Fj outputs an active pulse, while the gate enable signal GOE is at the low level, the control signal ctl is at the high level. Thus, the voltage Vout input to the gate driver 5 as the voltage VD1 is output to the gate signal line Gj. Then, during a period other than the above, the control signal ctl is set to the Low level, whereby the gate low voltage Vgl input to the gate driver 5 as the voltage VD2 is output to the gate signal line Gj.

  As a result, as shown by the solid line in FIG. 7, the gate signal G (j) has a waveform having a pulse with a rising slope during the pixel selection period. The broken line waveforms show several gate signals on the front and rear sides of the gate signal line GLj. As can be seen from FIG. 7, the rise timing of this pulse is the timing at which the gate enable signal GOE switches from High to Low, that is, the timing at which the active level is switched to the inactive level. The voltage level gradient period t1 extracted and output to the gate signal line GLj changes according to the timing. Here, the timing is set at any point in time during which the voltage level of the trapezoidal wave of the voltage Vout is rising, and at least the level at the timing of the voltage Vout is set to a level equal to or higher than the gate low voltage Vgl. ing.

  As described above, the gate signal G (j) output to the gate signal line GLj starts from a level equal to or higher than the gate low voltage Vgl and gradually increases to the level of the gate high voltage Vgh, and the voltage level described above. A first voltage composed of a voltage level constant period t2 that is constant at the level of the gate high voltage Vgh following the ramp period t1, and a second voltage composed of the gate low voltage Vgl other than the entire period of the first voltage. , Has a connected waveform. The first voltage is a voltage level rise period in which the voltage level gradually rises, and includes a voltage level rise period that lastly includes at least the voltage level ramp period t1, and a gate high voltage Vgh following the voltage level rise period. A voltage waveform comprising a high level period in which the voltage level is constant and including at least the voltage level constant period t2 first and a voltage level decrease period in which the voltage level decreases following the high level period is repeated. It is the voltage extracted from one said voltage waveform contained in the signal produced | generated so that it may continue.

  Further, the shape of the slope in the voltage level slope period t1 may be linear or curved, and is arbitrary. This inclination utilizes the characteristics of the analog circuit that can be determined by the time constant of the resistor and capacitor in the configuration of FIG. Therefore, the gradient of the inclination can be changed as appropriate according to the configuration of the analog circuit. In the present embodiment, in particular, the temperature characteristic of the analog circuit is used, and the gradient of the slope is changed on the analog circuit according to the ambient temperature, resulting in insufficient charge of the pixel capacity on the front stage side in 2H dot inversion driving. Therefore, it is possible to easily perform temperature compensation for a decrease in display quality. Next, this temperature compensation will be described.

  FIG. 8 shows a configuration of a circuit for generating the voltage Vout for performing the temperature compensation.

  This circuit uses a negative characteristic thermistor (NTC) Th1 instead of the resistor Rct1 as the fifth resistor in the configuration of FIG. The negative characteristic thermistor Th1 has a large resistance value at low temperatures and a small resistance value at high temperatures. Accordingly, as shown in FIG. 1A, the gradient of the slope of the voltage Vout during the voltage level rising period, that is, the slope of the slope of the gate signal G (j) during the voltage level slope period t1 is small at low temperatures. As shown in FIG. 1B, the slope of the slope of the voltage Vout during the voltage level rise period, and hence the slope of the slope of the gate signal G (j) during the voltage level slope period t1 is very large.

  Accordingly, it is possible to provide a rising slope in the gate signal G (j) substantially only at a low temperature, and temperature compensation for a reduction in display quality can be easily performed.

  In FIGS. 1A and 1B, the control signal GSD is synchronized with the gate clock GCK while having a period equal to two periods of the gate clock GCK, and the latter stage side of the gate clock GSD in 2H dot inversion driving. The low level is set for a predetermined period from the rising edge of the clock pulse corresponding to the pixel selection period. As a result, as a result of extracting the gate signal G (j) from the voltage Vout, the gate signal G (j) for the pixel on the front stage has a waveform having a square-wave gate pulse, and the gate signal G (j) for the pixel on the rear stage. Has a waveform having a first voltage gate pulse consisting of a voltage level ramp period t1 and a voltage level constant period t2. The waveform of the control signal GSD does not affect the shape of the square wave of the gate signal G (j) in FIG.

  FIG. 2 shows the waveforms of the gate signals G (j) and the source signal S (0) on the positive polarity side when the gate signals G (j) of FIGS. 1 (a) and 1 (b) are employed. . The gate signal G (2) corresponds to the solid line gate signal G (j) in FIG. 1A, and the period Tslope corresponds to the voltage level gradient period t1 in FIG. Since the amount of charge in the period Tslope is suppressed, the amount of charge in the period T1 in which the source signal S (0) is written to the pixel capacitor by the gate signal G (1) and the source signal S (0) by the gate signal G (2) are pixelated. The amount of charge in the period T2 (= voltage level inclination period t1 + voltage level constant period t2) in which the capacitor is written becomes equal. The situation is the same for the source signal S on the negative polarity side. In the writing of the source signal S to the pixel capacitor on the front stage side, the rising of the source signal S is already slow, so that even if the slope of the rising edge of the gate signal G (j) on the front stage is provided, the amount of charge more than this There is not much decline. Therefore, the effect that the luminance is uniform between the pixels on the front stage and the pixels on the rear stage is obtained.

  Further, as shown in FIGS. 3A and 3B, the control signal GSD is synchronized with the gate clock GSD while having a period equal to one period of the gate clock GCK as in FIG. You may make it become a Low level only for a predetermined period from the rise of a clock pulse. In this case, at the time of low temperature, all gate signals G (j) have a waveform having a gate pulse of the first voltage composed of the voltage level inclination period t1 and the voltage level constant period t2. The waveform of the control signal GSD does not affect the shape of the square wave of the gate signal G (j) in FIG.

  In the circuit of FIG. 6, the resistor Rct1 is a resistor that does not change its resistance value largely depending on the ambient temperature, like the negative characteristic thermistor Th1, but the second circuit shown in FIG. 6 is provided to change to the resistor Rct1. If the resistors having different resistance values are provided as the resistors, and the two circuits are switched according to the ambient temperature and connected to the terminal of the voltage VD1 of the gate driver 5, temperature compensation is possible. At this time, for example, if the output of the circuit having the fifth resistor having the larger resistance value is connected to the terminal of the voltage VD1 with a positive temperature coefficient thermistor, the gate signal G (j) at low temperature can be generated. If the output of the circuit having the fifth resistor having the smaller resistance value is connected to the terminal of the voltage VD1 with a negative characteristic thermistor, the gate signal G (j) at normal temperature and high temperature can be generated.

  Further, temperature compensation is possible even in a configuration in which the two resistors are connected in parallel as the fifth resistor in the same place, and the resistors that conduct at low temperature, normal temperature, and high temperature are switched. What is necessary is just to connect the said positive characteristic thermistor and a negative characteristic thermistor in series with resistance as a switch for conduction | electrical_connection.

  In addition, using the fact that the forward voltage of the diode changes with temperature, a fifth resistor is created by connecting the diode in parallel to a normal resistor, and generates a case where the diode is conductive and a case where it is not conductive depending on the temperature. In this way, the time constant can be changed. In this configuration, a fifth resistor is formed by connecting a diode in the reverse direction in parallel with a normal resistor, and a change in temperature of the breakdown voltage in the reverse characteristic of the diode can also be used.

  It is also possible to use a semiconductor layer as the fifth resistor and change the time constant using the temperature change of the resistance value of the semiconductor. Furthermore, it is possible to configure the fifth resistor by a MOS resistor, apply any one of the voltages of the diode to the gate of the MOS resistor, and change the time constant by utilizing the change in the MOS resistance due to the ambient temperature.

  In addition, the circuit for determining the time constant is not limited to the configuration shown in FIGS. 6 and 8, and an infinite number of generally known time constant circuits can be used. If the slope waveform created by this time constant circuit is processed by the subtracting unit shown in FIGS. 6 and 8, the voltage Vout can be obtained.

  Further, without using the subtracting unit, the waveform of the voltage level rising period, the high level period, and the voltage level decreasing period are sequentially transmitted from different switch outputs using the timing of the gate enable signal GOE and the control signal GSD. The voltage Vout can also be generated by outputting and connecting them. The voltage level drop period can be generated with a discharge waveform of a charged capacity, for example.

  Thus, in the case where a slope is provided at the rising edge of the gate signal G (j), a temperature compensation configuration that can be changed freely in an analog circuit is possible. In addition, temperature compensation does not need to be performed in two ways: low temperature, normal temperature and high temperature, and may be divided into any number of stages, or a continuous compensation level may be provided. The circuit is very convenient to achieve this.

  Furthermore, according to the liquid crystal display device 1 according to the present embodiment, the circuit for generating the voltage Vout and the switch circuit 22... Are configured separately from the conventional control circuit and driver circuit, and the control circuit and driver circuit. Just connect. Therefore, the existing control circuit and driver circuit, particularly those in the form of a chip, can be used as they are to generate the gate signal G (j) with a slope at the rising edge. In the configuration of Patent Document 1, in order to change the width of the gate pulse, the configuration of the control circuit and the driver circuit must be changed, and the conventional one cannot be used.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be suitably used for an active matrix display device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention, wherein (a) is a waveform diagram showing a generation process of a gate signal at a low temperature, and (b) is a waveform diagram showing a generation process of a gate signal at a normal temperature and a high temperature. It is a wave form diagram explaining the charge amount of the pixel capacity | capacitance by a source signal when performing a display drive using the gate signal of Fig.1 (a). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention, where (a) is a waveform diagram illustrating a generation process of another gate signal at a low temperature, and (b) is a waveform diagram illustrating a generation process of another gate signal at a normal temperature and a high temperature. It is. 1, showing an embodiment of the present invention, is a block diagram illustrating a configuration of a display device. FIG. FIG. 5 is a circuit block diagram illustrating a configuration of a gate driver included in the display device of FIG. 4. FIG. 6 is a circuit diagram illustrating a basic configuration of a circuit that generates a voltage input to the gate driver of FIG. 5. FIG. 6 is a waveform diagram showing a generation process of a gate signal generated by the gate driver of FIG. 5. FIG. 6 is a circuit diagram showing a configuration of a circuit capable of temperature compensation for generating a voltage input to the gate driver of FIG. 5. It is a timing chart which shows a prior art and illustrates dot inversion driving. It is a timing chart which shows a prior art and illustrates 2H dot inversion driving. It is a timing chart which shows a prior art and illustrates a problem of 2H dot inversion driving. It is a block diagram which shows a prior art and shows the structure of the display apparatus which can change the width | variety of a gate pulse. FIG. 13 is a timing chart showing a conventional technique and showing an operation of the display device of FIG. 12.

Explanation of symbols

1 Liquid crystal display device (display device)
Vgh Gate high voltage Vgl Gate low voltage (second voltage)
Vin voltage (reference voltage)
Vout voltage (original signal)
t1 Voltage level ramp period t2 Voltage level fixed period G (j) Gate signal OP Operational amplifier R1 Resistance (first resistance)
R2 resistance (second resistance)
R3 resistance (third resistance)
R4 resistance (fourth resistance)
Rct1 resistance (fifth resistance)
Rct2 resistance (sixth resistance)
Th1 negative characteristic thermistor (fifth resistor)
Ict current source Cct capacitor SW switch GSD control signal

Claims (10)

A plurality of pixels connected to the same source signal line are divided into units composed of N consecutive pixels (N is an integer of 2 or more), and the pixels within each unit have the same polarity as the source signal. In addition, in the active matrix type display device that performs AC driving with the source signal having a reverse polarity between adjacent units with respect to the same source signal line,
In each of the above units, the gate signal output to the gate signal line connected to at least the pixels other than the first stage in the gate scanning order starts from a level higher than the gate low voltage and gradually increases to the gate high voltage level A waveform in which a first voltage composed of a level ramp period, a voltage level constant period that is constant at the gate high voltage level following the voltage level ramp period, and a second voltage composed of the gate low voltage are connected. A display device capable of outputting to the gate signal line.   The first voltage is a voltage level rise period in which the voltage level gradually rises and includes at least a voltage level rise period that lastly includes the voltage level ramp period, and a constant level of the gate high voltage following the voltage level rise period. And a voltage waveform comprising a high level period that initially includes at least the voltage level constant period and a voltage level lowering period in which the voltage level decreases following the high level period is generated so as to be repeated continuously. The display device according to claim 1, wherein the display device is a voltage extracted from one of the voltage waveforms included in an original signal which is a generated signal. In each of the units, the waveform of the gate signal output to the gate signal line connected to the pixels other than the first stage is connected to the first voltage and the second voltage extracted from the original signal. A gate signal having
A gate high voltage obtained by extracting a gate signal output to the gate signal line to which the pixel at the foremost stage is connected from a period after the voltage level fixed period in the High level period of one voltage waveform; The display device according to claim 2, wherein the display device is a gate signal obtained by connecting two voltages.   In each of the above units, a gate having the above waveform by connecting the first voltage extracted from the original signal and the second voltage to the gate signal output to the gate signal line to which each pixel is connected. The display device according to claim 2, wherein the display device is a signal. The circuit for generating the original signal includes an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a constant current source, a capacitor, and a switch. With
One end of the first resistor is connected to the non-inverting input terminal of the operational amplifier, a constant reference voltage is input to the other end of the first resistor, and one end of the second resistor is the non-inverting terminal. The other end of the second resistor is connected to GND, one end of the third resistor is connected to the inverting input terminal of the operational amplifier, and the third resistor is connected to the input terminal. The other end is connected to one end of the fourth resistor and one terminal of the switch. One end of the fourth resistor is connected to the output terminal of the operational amplifier, and the other end of the fourth resistor. Is connected to the inverting input terminal, the other end of the fifth resistor is connected to one end of the sixth resistor and one terminal of the capacitor, and the other end of the sixth resistor is connected to the end of the sixth resistor. Connected to the output terminal of the constant current source. The other end of the switch and the other terminal of the switch are connected to GND, and the switch opens and closes according to a control signal that switches between a high level and a low level. The display device according to claim 1.   6. The display device according to claim 5, wherein the fifth resistor is a negative characteristic thermistor. A plurality of pixels connected to the same source signal line are divided into units composed of N consecutive pixels (N is an integer of 2 or more), and the pixels within each unit have the same polarity as the source signal. In addition, in the display device driving method for driving an active matrix display device that performs AC driving with the source signal having a reverse polarity between adjacent units with respect to the same source signal line,
In each of the above units, the gate signal output to the gate signal line to which at least the pixels other than the first stage are connected in the gate scanning order starts from a level higher than the gate low voltage and gradually increases to the gate high voltage level A waveform in which a first voltage composed of a level ramp period, a voltage level constant period that is constant at the gate high voltage level following the voltage level ramp period, and a second voltage composed of the gate low voltage are connected. A method for driving a display device, characterized by outputting to the gate signal line.   The first voltage is a voltage level rise period in which the voltage level gradually rises and includes at least the voltage level ramp period at the end, a constant level of the gate high voltage following the voltage level rise period, And a voltage waveform comprising a high level period that initially includes at least the voltage level constant period and a voltage level lowering period in which the voltage level decreases following the high level period is generated so as to be repeated continuously. 8. The method of driving a display device according to claim 7, wherein a voltage extracted from one of the voltage waveforms included in an original signal which is a generated signal is used. In each of the units, the waveform of the gate signal output to the gate signal line connected to the pixels other than the first stage is connected to the first voltage and the second voltage extracted from the original signal. A gate signal having
A gate high voltage obtained by extracting a gate signal output to the gate signal line to which the pixel at the foremost stage is connected from a period after the voltage level fixed period in the High level period of one voltage waveform; The display device driving method according to claim 8, wherein the gate signal is obtained by connecting two voltages.   In each of the above units, a gate having the above waveform by connecting the first voltage extracted from the original signal and the second voltage to the gate signal output to the gate signal line to which each pixel is connected. The display device driving method according to claim 8, wherein the display device is a signal.

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