CN110796994A - Liquid crystal display and driving circuit thereof - Google Patents
Liquid crystal display and driving circuit thereof Download PDFInfo
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- CN110796994A CN110796994A CN201911177747.3A CN201911177747A CN110796994A CN 110796994 A CN110796994 A CN 110796994A CN 201911177747 A CN201911177747 A CN 201911177747A CN 110796994 A CN110796994 A CN 110796994A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
Abstract
The invention discloses a liquid crystal display and its drive circuit, the said drive circuit includes: a timing control module for generating a first pulse signal, a second pulse signal and an enable signal; the power supply management module is used for generating a positive voltage signal and a negative voltage signal; the pulse wave modulation module is electrically connected with the time sequence control module and the power management module and generates a modulation signal according to the positive pressure signal, the first pulse wave signal and the second pulse wave signal; and the potential transfer module is electrically connected with the time sequence control module, the power management module and the pulse wave modulation module, and generates a scanning signal according to the enabling signal, the modulation signal and the negative pressure signal.
Description
Technical Field
The present invention relates to a display technology, and more particularly, to a liquid crystal display and a driving circuit thereof.
Background
The lcd has advantages of high image quality, low power consumption, and small size, for example: thin film transistor liquid crystal displays (TFT-LCDs) are becoming the mainstream of flat panel displays.
Taking TFT-LCD as an example, the parasitic capacitance on the liquid crystal panel can generate a capacitive coupling effect, which causes the scanning voltage change during the operation of the liquid crystal panel, i.e. feed through effect, and further causes the liquid crystal display to flicker.
Although some technical solutions have been developed to reduce the feed through effect, the feed through effect still cannot be completely overcome, and thus the display quality is still to be improved.
Therefore, there is a need to provide a solution to the problems of the prior art.
Disclosure of Invention
In view of the above, the present invention provides a liquid crystal display and a driving circuit thereof to solve the problem of the prior art that the liquid crystal display has a feed through effect.
To achieve the aforesaid objective, one aspect of the present invention provides a driving circuit, including: the timing control module is used for generating a first pulse wave signal, a second pulse wave signal and an enabling signal, wherein the phases of the first pulse wave signal and the second pulse wave signal are opposite, and the enabling signal has an enabling level and a de-enabling level; the power supply management module is used for generating a positive voltage signal and a negative voltage signal; the pulse wave modulation module is electrically connected with the time sequence control module and the power management module and generates a modulation signal according to the positive voltage signal, the first pulse wave signal and the second pulse wave signal, when the first pulse wave signal is at a high level, the modulation signal is the positive voltage signal, and when the first pulse wave signal is at a low level, the modulation signal is a signal generated by discharging of the positive voltage signal; and the potential transfer module is electrically connected with the time sequence control module, the power management module and the pulse wave modulation module, the potential transfer module generates a scanning signal according to the enabling signal, the modulation signal and the negative pressure signal, when the enabling signal is at the enabling level, the scanning signal is a signal generated by increasing the modulation signal according to a high potential, and when the enabling signal is at the de-enabling level, the scanning signal is the negative pressure signal.
In an embodiment of the invention, the pulse modulation module is a third-order driving circuit.
In an embodiment of the invention, the third-order driving circuit includes a first N-type transistor, a P-type transistor, a second N-type transistor, a zener diode, a first resistor, a second resistor, a third resistor, and a capacitor, the first N-type transistor is coupled to the first resistor, the P-type transistor is coupled to the first resistor, the second resistor, the third resistor, and the capacitor, the zener diode is coupled between the third resistor and the second N-type transistor, the first N-type transistor inputs the first pulse signal, the P-type transistor inputs the second pulse signal, the second N-type transistor inputs the positive voltage signal, and the capacitor outputs the modulation signal.
In an embodiment of the invention, the first N-type transistor and the second N-type transistor are NMOS transistors, respectively, and the P-type transistor is a PMOS transistor.
In an embodiment of the invention, the pulse modulation module and the power management module are integrated into a power compensation integrated circuit.
To achieve the above object, another aspect of the present invention provides a liquid crystal display, comprising: a display member; and a control unit electrically connected to the display unit, the control unit having a driving circuit, the driving circuit including: the timing control module is used for generating a first pulse wave signal, a second pulse wave signal and an enabling signal, wherein the phases of the first pulse wave signal and the second pulse wave signal are opposite, and the enabling signal has an enabling level and a de-enabling level; the power supply management module is used for generating a positive voltage signal and a negative voltage signal; the pulse wave modulation module is electrically connected with the time sequence control module and the power management module and generates a modulation signal according to the positive voltage signal, the first pulse wave signal and the second pulse wave signal, when the first pulse wave signal is at a high level, the modulation signal is the positive voltage signal, and when the first pulse wave signal is at a low level, the modulation signal is a signal generated by discharging of the positive voltage signal; and the potential transfer module is electrically connected with the time sequence control module, the power management module and the pulse wave modulation module, the potential transfer module generates a scanning signal according to the enabling signal, the modulation signal and the negative pressure signal, when the enabling signal is at the enabling level, the scanning signal is a signal generated by increasing the modulation signal according to a high potential, and when the enabling signal is at the de-enabling level, the scanning signal is the negative pressure signal.
In an embodiment of the invention, the pulse modulation module is a third-order driving circuit.
In an embodiment of the invention, the third-order driving circuit includes a first N-type transistor, a P-type transistor, a second N-type transistor, a zener diode, a first resistor, a second resistor, a third resistor, and a capacitor, the first N-type transistor is coupled to the first resistor, the P-type transistor is coupled to the first resistor, the second resistor, the third resistor, and the capacitor, the zener diode is coupled between the third resistor and the second N-type transistor, the first N-type transistor inputs the first pulse signal, the P-type transistor inputs the second pulse signal, the second N-type transistor inputs the positive voltage signal, and the capacitor outputs the modulation signal.
In an embodiment of the invention, the first N-type transistor and the second N-type transistor are NMOS transistors, respectively, and the P-type transistor is a PMOS transistor.
In an embodiment of the invention, the pulse modulation module and the power management module are integrated into a power compensation integrated circuit.
Compared with the prior art, the liquid crystal display and the driving circuit thereof can reduce the difference voltage between the opening voltage and the closing voltage by providing the scanning signal to the scanning line of the display component (such as a liquid crystal panel) so as to provide the opening voltage and the closing voltage for the grid electrode, and utilize the modulation signal as the opening voltage, thereby reducing the influence of feed-through effect on the display component, improving the flicker condition of the liquid crystal display caused by the feed-through effect and being beneficial to improving the use experience of the liquid crystal display.
Drawings
Fig. 1 is an equivalent circuit diagram showing a feed through effect at a pixel point in a liquid crystal panel.
FIG. 2 is a block diagram of a liquid crystal display and a driving circuit thereof according to the present invention.
Fig. 3 is a schematic diagram of signal waveforms in fig. 2.
Fig. 4 is a circuit diagram of the pulse modulation module in fig. 2.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. Furthermore, directional phrases used herein, such as, for example, upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, lateral, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., refer only to the orientation of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
It should be understood that the lcd has different feedback voltages due to the different manufacturing processes of the lcd, so that the flicker occurs in different degrees. As shown in fig. 1, it is an equivalent circuit of a feed through effect existing at a pixel point in a liquid crystal panel, for example: a Thin Film Transistor (TFT) at the pixel point has a gate G, a drain D and a source S, the gate G and the drain D are respectively coupled to a scan line SL and a data line DL, and a storage capacitor Cst and a liquid crystal capacitor Clc are provided between the source S and the common electrode Vcom for providing a pixel voltage Vp, such as voltages Vpon and Vpoff for different pixel states. The gate voltage Vg at the gate G has two voltages, one is a turn-on voltage Vgh provided by the scan line SL to the gate G, and the other is a turn-off voltage Vgl provided by the scan line SL to the gate G. However, since a parasitic capacitance Cgs exists between the gate G and the source S, when the gate voltage Vg of the gate G is switched from the turn-on voltage Vgh to the turn-off voltage Vgl, the charges of the parasitic capacitance Cgs, the storage capacitance Cst, and the liquid crystal capacitance Clc are considered to be conserved, as shown in the following equations (1) and (2):
(Vgh-Vpon)Cgs+(Vcom-Vpon)(Cst+Clc)＝(Vgl-Vpoff)Cgs+(Vcom-Vpoff)(Cst+Clc) (1)
as can be seen from the above equation, if the turn-on voltage Vgh becomes smaller, Δ V can be reduced to reduce the feedthrough effect. Therefore, the present invention can utilize this mechanism as an improvement basis for reducing the feed through effect.
The technical scheme of the invention can be harder than various liquid crystal displays which need to reduce the feed through effect, such as: the following description is made by taking a Gate On Array (GOA) type liquid crystal display as an example, but not limited thereto.
Referring to fig. 2, the lcd embodiment of the present invention may include a display unit a and a control unit C, where the display unit a may be, for example, a liquid crystal panel having a plurality of pixels; the control component C may be, for example, a hardware module with a GOA control function, and the control component C is electrically connected to the display component a, for example: the control unit C includes a corresponding signal generating circuit for the above-mentioned scanning lines and data lines, for controlling the display unit a to operate a display function. The following illustrates an embodiment of the control unit C, but not limited thereto.
For example, as shown in fig. 2, the control unit C may have a driving circuit for providing a scan signal for the scan line. For example: the driving circuit may include: the pulse wave modulation module 3 is electrically connected with the timing control module 1 and the power management module 2, and the potential transfer module 4 is electrically connected with the timing control module 1, the power management module 2 and the pulse wave modulation module 3. The following illustrates embodiments of the driving circuit, but not limited thereto.
For example, as shown in fig. 2, the timing control module 1 may be, for example, a timing control integrated circuit (TCONIC), and the timing control module 1 may be configured to generate a first pulse signal GVOFF, a second pulse signal GVON and an enable signal VCK _ T, as shown in fig. 3, the first pulse signal GVOFF and the second pulse signal GVON have opposite phases, it should be understood that the first pulse signal GVOFF and the second pulse signal GVON are alternately high and low signals; the enable signal VCK _ T has an enable (enable) level P1 and a disable (disable) level P2, such as: the enable level P1 may be a digital logic voltage (DVDD) of 3.3 volts (V), and the disable level P2 may be a ground voltage of 0V. Thus, the above signals can be used as the basis for the subsequent generation of the scanning signals.
As shown in fig. 2, the power management module 2 may be, for example, a Power Management Integrated Circuit (PMIC), and the power management module 2 may be configured to generate a positive voltage signal VGHP and a negative voltage signal VGL, where the positive voltage signal VGHP may be, for example, a positive voltage dc signal and the negative voltage signal VGL may be, for example, a negative voltage dc signal, such as: minus 6 to minus 10V, but not limited thereto. Thus, the above signals can be used as the basis for the subsequent generation of the scanning signals.
As shown in fig. 2 and fig. 3, the pulse modulation module 3 can be, for example, a compensation circuit having a first pulse signal with a discharge voltage waveform (it appears that a corner is cut), the pulse modulation module 3 can generate a modulation signal VGH according to the positive voltage signal VGHP, the first pulse signal GVOFF and the second pulse signal GVON, the modulation signal VGH is the positive voltage signal VGHP when the first pulse signal GVOFF is at a high level, and the modulation signal VGH is a signal generated by discharging according to the positive voltage signal VGHP when the first pulse signal GVOFF is at a low level. Therefore, the voltage difference can be reduced at the moment when the modulation signal VGH is switched from the high level to the low level, so as to improve the feed through effect of the liquid crystal panel.
For example, as shown in fig. 4, the pulse modulation module 3 can be, for example, a third-order driving circuit, the third-order driving circuit includes a first N-type transistor Q1, a P-type transistor Q2, a second N-type transistor Q3, a zener diode Z, a first resistor R1, a second resistor R2, a third resistor R3, and a capacitor C, the first N-type transistor Q1 is coupled to the first resistor R1, the P-type transistor Q2 is coupled to the first resistor R1, the second resistor R2, the third resistor R3, and the capacitor C, the zener diode Z is coupled between the third resistor R3 and the second N-type transistor Q3, the first N-type transistor Q1 can input the first pulse signal GVOFF, the P-type transistor Q2 can input the second pulse signal GVON, the second N-type transistor Q3 can input the positive voltage signal vgq 3, the capacitor C may output the modulation signal VGH, such as: one end of the capacitor C is coupled to the P-type transistor Q2 and the third resistor R3, and the other end of the capacitor C is grounded.
Specifically, as shown in fig. 4, the first N-type transistor Q1 and the second N-type transistor Q3 may be NMOS transistors, respectively, and the P-type transistor Q2 may be PMOS transistors, it being understood that the PMOS transistors and the NMOS transistors have a control terminal (e.g., a gate terminal), a first terminal (e.g., one of a drain terminal and a source terminal), and a second terminal (e.g., the other of a drain terminal and a source terminal).
For example, as shown in fig. 4, in the third-order driving circuit, the control terminal of the first N-type transistor Q1 inputs the first pulse signal GVOFF, the first terminal of the first N-type transistor Q1 is coupled to the first resistor R1, and the second terminal of the first N-type transistor Q1 is grounded; the second pulse signal GVON is input to the control terminal of the second N-type transistor Q3, the first terminal of the second N-type transistor Q3 is coupled to the zener diode Z, and the second terminal of the second N-type transistor Q3 is grounded; the control terminal of the P-type transistor Q2 is coupled to the first resistor R1 and the second resistor R2, the first terminal of the P-type transistor Q2 is coupled to the second resistor R2 and inputs the positive voltage signal VGHP, the second terminal of the P-type transistor Q2 is coupled to the third resistor R3 and the capacitor C, the third resistor R3 is connected in series with the zener diode Z, and the capacitor C outputs the modulation signal VGH.
Specifically, when the first pulse signal GVOFF is at a high level, the first N-type transistor Q1 is turned on, so that the P-type transistor Q2 is turned on; at this time, the second pulse signal GVON is low, and the second N-type transistor Q3 is turned off, so that the modulation signal VGH is the positive voltage signal VGHP, and the capacitor C is charged with the positive voltage signal VGHP. On the other hand, when the first pulse signal GVOFF is at a low level, the first N-type transistor Q1 is turned off, so that the P-type transistor Q2 is turned off, and at this time, the second pulse signal GVON is at a high level, the second N-type transistor Q3 is turned on, the capacitor C, the third resistor R3, the zener diode Z and the second N-type transistor Q3 form a discharge loop, and the charge in the capacitor C can be discharged through the zener diode Z and the second N-type transistor Q3, so that the modulation signal VGH is a signal generated by discharging according to the positive voltage signal VGHP.
Specifically, the width w and the depth d of the signal generated by discharging according to the positive voltage signal VGHP can be adjusted, for example: the resistance value of the third resistor R3 can be used to control the discharge speed (related to the width w), and the characteristic value of the zener diode Z can be used to control the lower limit value (related to the depth d) of the discharge signal, so that the modulation signal VGH can be generated according to the actual requirement.
In an embodiment, as shown in fig. 2, the pulse modulation module 3 and the power management module 3 can be further integrated into a power compensation integrated circuit, so as to further reduce the hardware size of the driving circuit.
As shown in fig. 2 and 3, the level shift module 4 can be, for example, a level shift integrated circuit (L/S IC), the level shift module 4 can generate a scan signal CK according to the enable signal VCK _ T, the modulation signal VGH and the negative voltage signal VGL, the scan signal CK is generated by raising the modulation signal VGH according to a high voltage V1 when the enable signal VCK _ T is the enable level P1, and the scan signal CK is the negative voltage signal VGL when the enable signal VCK _ T is the disable level P2, for example: the high level range of the enabling signal VCK _ T is 24 to 32V, and the low level range of the enabling signal VCK _ T is minus 6 to minus 10V. Therefore, the level conversion is realized by the level shift module 4 according to the modulating signal VGH, so as to meet the requirements of the on-voltage (e.g. above 20V) and the off-voltage (e.g. below-5V) of the thin film transistor.
Therefore, the liquid crystal display and the driving circuit thereof according to the above-mentioned embodiments of the invention provide the scan signal to the scan line of the display device (e.g. the liquid crystal panel) to provide the gate-on voltage and the gate-off voltage, and use the modulation signal as the gate-on voltage, so as to reduce the difference voltage between the gate-on voltage and the gate-off voltage, so as to reduce the influence of feed-through (feed-through) effect on the display device, improve the flicker (flicker) of the liquid crystal display caused by the feed-through effect, and contribute to improving the use experience of the liquid crystal display.
The present invention has been described in relation to the above embodiments, which are only exemplary of the implementation of the present invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the invention.
Claims (10)
1. A drive circuit, characterized by: the method comprises the following steps:
the timing control module is used for generating a first pulse wave signal, a second pulse wave signal and an enabling signal, wherein the phases of the first pulse wave signal and the second pulse wave signal are opposite, and the enabling signal has an enabling level and a de-enabling level;
the power supply management module is used for generating a positive voltage signal and a negative voltage signal;
the pulse wave modulation module is electrically connected with the time sequence control module and the power management module and generates a modulation signal according to the positive voltage signal, the first pulse wave signal and the second pulse wave signal, when the first pulse wave signal is at a high level, the modulation signal is the positive voltage signal, and when the first pulse wave signal is at a low level, the modulation signal is a signal generated by discharging of the positive voltage signal; and
the potential transfer module is electrically connected with the time sequence control module, the power management module and the pulse wave modulation module, and generates a scanning signal according to the enabling signal, the modulation signal and the negative pressure signal, when the enabling signal is at the enabling level, the scanning signal is a signal generated by increasing the modulation signal according to a high potential, and when the enabling signal is at the de-enabling level, the scanning signal is the negative pressure signal.
2. The drive circuit of claim 1, wherein: the pulse wave modulation module is a three-order drive circuit.
3. The drive circuit of claim 2, wherein: the third-order driving circuit comprises a first N-type transistor, a P-type transistor, a second N-type transistor, a zener diode, a first resistor, a second resistor, a third resistor and a capacitor, wherein the first N-type transistor is coupled to the first resistor, the P-type transistor is coupled to the first resistor, the second resistor, the third resistor and the capacitor, the zener diode is coupled between the third resistor and the second N-type transistor, the first N-type transistor inputs the first pulse signal, the P-type transistor inputs the second pulse signal, the second N-type transistor inputs the positive voltage signal, and the capacitor outputs the modulation signal.
4. A drive circuit as claimed in claim 3, wherein: the first N-type transistor and the second N-type transistor are NMOS transistors respectively, and the P-type transistor is a PMOS transistor.
5. The drive circuit of claim 1, wherein: the pulse wave modulation module and the power management module are integrated into a power compensation integrated circuit.
6. A liquid crystal display, characterized by: the method comprises the following steps:
a display member; and
a control unit electrically connected to the display unit, the control unit having a driving circuit, the driving circuit comprising:
the timing control module is used for generating a first pulse wave signal, a second pulse wave signal and an enabling signal, wherein the phases of the first pulse wave signal and the second pulse wave signal are opposite, and the enabling signal has an enabling level and a de-enabling level;
the power supply management module is used for generating a positive voltage signal and a negative voltage signal;
the pulse wave modulation module is electrically connected with the time sequence control module and the power management module and generates a modulation signal according to the positive voltage signal, the first pulse wave signal and the second pulse wave signal, when the first pulse wave signal is at a high level, the modulation signal is the positive voltage signal, and when the first pulse wave signal is at a low level, the modulation signal is a signal generated by discharging of the positive voltage signal; and
the potential transfer module is electrically connected with the time sequence control module, the power management module and the pulse wave modulation module, and generates a scanning signal according to the enabling signal, the modulation signal and the negative pressure signal, when the enabling signal is at the enabling level, the scanning signal is a signal generated by increasing the modulation signal according to a high potential, and when the enabling signal is at the de-enabling level, the scanning signal is the negative pressure signal.
7. The liquid crystal display of claim 6, wherein: the pulse wave modulation module is a three-order drive circuit.
8. The liquid crystal display of claim 7, wherein: the third-order driving circuit comprises a first N-type transistor, a P-type transistor, a second N-type transistor, a zener diode, a first resistor, a second resistor, a third resistor and a capacitor, wherein the first N-type transistor is coupled to the first resistor, the P-type transistor is coupled to the first resistor, the second resistor, the third resistor and the capacitor, the zener diode is coupled between the third resistor and the second N-type transistor, the first N-type transistor inputs the first pulse signal, the P-type transistor inputs the second pulse signal, the second N-type transistor inputs the positive voltage signal, and the capacitor outputs the modulation signal.
9. The liquid crystal display of claim 8, wherein: the first N-type transistor and the second N-type transistor are NMOS transistors respectively, and the P-type transistor is a PMOS transistor.
10. The liquid crystal display of claim 6, wherein: the pulse wave modulation module and the power management module are integrated into a power compensation integrated circuit.
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| CN201911177747.3A CN110796994A (en) | 2019-11-27 | 2019-11-27 | Liquid crystal display and driving circuit thereof |
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| CN201911177747.3A CN110796994A (en) | 2019-11-27 | 2019-11-27 | Liquid crystal display and driving circuit thereof |
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| CN114187875A (en) * | 2021-11-25 | 2022-03-15 | 绵阳惠科光电科技有限公司 | Voltage adjusting circuit and method and display device |
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Application publication date: 20200214 |