KR20200061121A - Discharging circuit and display device including the same - Google Patents

Abstract

The present invention relates to a discharge circuit for preventing an afterimage from occurring on a screen when power of a display panel is turned off, and a display device including the same. The discharge circuit of the present invention provides a first gate low signal (VGL1) and a second gate low signal (VGL2) to a gate driving unit in a first step (P1), supplies a gate high signal (VGH) to the gate driving unit in a second step (P2), and supplies a ground signal (GND) to the gate driving unit in a third step (P3).

Description

Discharge circuit and display device including same {DISCHARGING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a discharge circuit and a display device including the same, and more particularly, to a device that improves a problem that an afterimage of a screen remains in a display device including an oxide thin film transistor.

Flat panel displays such as liquid crystal displays (LCDs) and organic light emitting displays (OLEDs) are thinner than conventional cathode ray tubes (CRTs), It has the advantage of being lightweight and has low power consumption, so it is rapidly replacing the existing CRT.

The flat panel display device includes a display panel, and a plurality of gate wirings and a plurality of data wirings that define a plurality of pixel areas crossing each other may be formed. In addition, a switching thin film transistor may be formed in each pixel area, and the switching thin film transistor may display an image on each pixel by adjusting the amount of light transmitted according to a data signal applied through the data wiring.

The thin film transistor may be divided into an amorphous silicon thin film transistor (a-Si TFT), a polycrystalline silicon thin film transistor (poly TFT), and an oxide thin film transistor (Oxide TFT).

The amorphous silicon thin film transistor has an advantage in that a manufacturing process is not complicated, a low temperature process is possible, and a yield is high. In addition, since it is amorphous, the uniformity of the device is good, which is advantageous for large-sized areas. However, it has a limitation in that it cannot be used in a high-performance display device due to low electron mobility, and the device is deteriorated as it continues to operate and thus cannot maintain initial performance.

Since the polysilicon thin film transistor has a higher electron mobility than the amorphous silicon thin film transistor, it can be applied to a high performance display device. However, since performance may be different for each device, a compensation circuit must be designed for each pixel to uniformly adjust the voltage across each device. Therefore, there is a problem in that the manufacturing process is complicated and the additional cost is increased.

The oxide (oxide) thin film transistor has a higher electron mobility than the amorphous silicon thin film transistor, which is advantageous for implementing a driving circuit for controlling a switching element as well as a switching element in the display panel, and the manufacturing process is similar to that of the amorphous silicon thin film transistor. It has the advantage of utilizing existing equipment.

On the other hand, in a display device including an oxide thin film transistor, a defect in which an afterimage appears on the display panel may occur when the power of the display panel is turned off. Therefore, there is a need for a configuration and method to solve this problem.

An object of the present invention is to solve the above problems, and to provide a discharge circuit for preventing an afterimage from occurring on a screen when a power is turned off in a display device including an oxide thin film transistor and a display device including the same. .

In order to achieve the above object, the present invention provides the first gate row signal VGL1 and the second gate row signal VGL2 to the gate driver in the first step P1, and in the second step P2, A gate high signal VGH is supplied to the gate driver, and a third circuit P3 provides a discharge circuit that supplies a ground signal GND to the gate driver.

In the first step P1, the power of the display panel is on, and the second step P2 is from the time the power of the display panel is turned off to the first time T. , In the third step P3, after the first time T elapses after the power of the display panel is turned off, a discharge circuit is provided.

The discharge circuit includes a first gate low signal output terminal (VGL1_O), a second gate low signal output terminal (VGL2_O), a discharge signal input terminal (DSC_I), a second gate low signal input terminal (VGL2_I), and a first diode (D1). ), a second diode (D2), a first resistor (R1), a first node (N1), a second node (N2), and the discharge signal input terminal (DSC_I) is the first node (N1) and Connected, the second gate low signal input terminal VGL2_I is connected to the anode electrode of the second diode D2, the anode electrode of the first diode D1 is connected to the first node N1, The cathode electrode of the first diode D1 is connected to a second node N2, and the anode electrode of the second diode D2 is connected to the second gate low signal input terminal VGL2_I, and the second The cathode electrode of the diode D2 is connected to the second node N2, one end of the first resistor R1 is connected to the first node N1, and the other end of the first resistor R1. Is connected to the first gate low signal output terminal VGL1_O, the first gate low signal output terminal VGL1_O is connected to the other end of the first resistor R1, and the second gate low signal output terminal (VGL2_O) provides a discharge circuit of the display device connected to the second node N2.

In the first step P1, the first gate row signal VGL1 is output through the first gate row signal output terminal VGL1_O, and the second gate row signal VGL2 is the second gate row. Output through the signal output terminal (VGL2_O), in the second step (P2), the gate high signal (VGH) the first gate low signal output terminal (VGL1_O) and the second gate low signal output terminal (VGL2_O) ), and in the third step (P3 ), the ground signal GND is output through the first gate low signal output terminal VGL1_O and the second gate low signal output terminal VGL2_O. Provide a discharge circuit of the device.

The first gate low signal VGL1 provides a discharge circuit of a display device having a voltage lower than that of the second gate low signal VGL2.

Another embodiment of the present invention, the discharge circuit; A power IC generating a power supply voltage VCC and a first gate low signal VGL1, a second gate low signal VGL2, a gate high signal VGH, and a ground signal GND; It provides a power supply including a level shifter for generating a gate start signal (VST) and a clock signal (CLK).

In the first step (P1), the level shifter supplies the first gate low signal (VGL1) to the discharge signal input terminal (DSC_I) of the discharge circuit, and supplies the second gate low signal (VGL2). Supply to the second gate low signal input terminal (VGL2_I) of the inverting circuit, and in the second step (P2), supply the gate high signal (VGH) to the discharge signal input terminal (DSC_I) of the discharge circuit, The second gate low signal VGL2 is supplied to the second gate low signal input terminal VGL2_I of the inversion circuit, and in the third step P3, the ground signal GND is discharged from the discharge circuit. It provides a power supply for supplying the signal input terminal (DSC_I) and the second gate low signal input terminal (VGL2_I).

Another embodiment of the present invention, the power supply; A display panel including a gate line and a data line, defining a plurality of pixel areas while the gate line and the data line intersect, and including a thin film transistor positioned at a point where the gate line and the data line intersect; A gate driver including a shift register having first to mth stages and supplying a gate signal to the display panel; It provides a display device including a data driver for supplying a data signal to the display panel.

According to another embodiment of the present invention, the discharge circuit includes a first step (P1) of supplying a first gate low signal (VGL1) and a second gate low signal (VGL2) to the gate driver; A second step P2 in which the discharge circuit supplies the gate high signal VGH to the gate driver; It provides a driving method of a discharge circuit comprising a third step (P3) of the discharge circuit supplies a ground signal (GND) to the gate driver.

In the first step P1, the power of the display panel is on, and the second step P2 is from the time the power of the display panel is turned off to the first time T. The third step (P3) provides a method of driving a discharge circuit that is after the first time (T) has elapsed after the display panel is turned off.

The discharge circuit outputs the first gate low signal VGL1 to the first gate low signal output terminal VGL1_O in the first step P1, and outputs the second gate low signal VGL2 to the second gate. Output to the low signal output terminal (VGL2_O), in the second step (P2), the gate high signal (VGH) to the first gate low signal output terminal (VGL1_O) and the second gate low signal output terminal (VGL2_O) A method of driving a discharge circuit that outputs and outputs the ground signal GND to the first gate low signal output terminal VGL1_O and the second gate low signal output terminal VGL2_O in the third step P3 is provided. .

The first gate low signal VGL1 provides a method of driving a discharge circuit of a display device having a voltage lower than that of the second gate low signal VGL2.

In the first step (P1), the level shifter supplies the first gate low signal (VGL1) to the discharge signal input terminal (DSC_I) of the discharge circuit, and inverts the second gate low signal (VGL2). Supply to the second gate low signal input terminal (VGL2_I) of the circuit, and in the second step (P2), supply the gate high signal (VGH) to the discharge signal input terminal (DSC_I) of the discharge circuit, and the The second gate low signal VGL2 is supplied to the second gate low signal input terminal VGL2_I of the discharge circuit, and in the third step P3, the ground signal GND is a discharge signal of the discharge circuit. It provides a driving method of the level shifter supplied to the input terminal (DSC_I) and the second gate low signal input terminal (VGL2_I).

As described above, the discharge circuit of the present invention discharges the line to which the second gate low signal is applied together with the line to which the first gate low signal is applied to remove the DC component remaining in the display panel, and an afterimage occurs on the screen. By not doing so, it has the effect of improving the reliability of the display panel.

1 is a view showing the configuration of a display device of the present invention.
FIG. 2A is a diagram showing a gate driver in a gate-in-panel structure when one gate-low signal is used, and FIG. 2B is a diagram showing a reliability curve of a thin film transistor when one gate-low signal is used.
3A is a diagram showing a gate driver in a gate-in-panel structure when two gate low signals are used, and FIG. 3B is a diagram showing a reliability curve of a thin film transistor when two gate low signals are used.
4 is a view showing the configuration of a shift register of a power supply unit and a gate driver including a discharge circuit, a power IC, and a level shifter of the present invention.
5 is a view showing a waveform according to the driving step of the discharge circuit.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

1 is a view showing the configuration of a display device of the present invention.

The display device according to an exemplary embodiment of the present invention includes a display panel 100, a power supply unit 200, a timing control unit 300, a gate driving unit 400, and a data driving unit 500.

The display panel 100 of the present invention may be a liquid crystal panel or an organic light emitting diode panel, and may be other types of display panels that are not limited thereto and can control the amount of light transmitted by the thin film transistor.

The display panel 100 is composed of pixels in a matrix form to display an image, and a plurality of gate lines GL1 to GLm and parallel gate lines GL1 to GL1 to the first substrate of the display panel 100 are spaced apart at predetermined intervals. Data wirings DL1 to DLn defining a pixel area P crossing GLm) are provided.

At the intersection of the gate wirings GL1 to GLm and the data wirings DL1 to DLn, a thin film transistor (not shown) that controls the amount of light transmission according to the data signal and a storage capacitor (not shown) that maintains the data signal voltage until the next frame. ) Is formed, and a pixel electrode (not shown) and a common electrode (not shown) are provided in the pixel area P where the image is displayed.

Also, a black matrix (not shown), a color filter layer (not shown), or the like may be formed on the second substrate of the display panel 100.

The power supply unit 200 may generate logic driving voltages required to drive the liquid crystal display device. In particular, the gate high signal VGH and the gate low signal supplied to the gate driver 400 together with the power supply voltage VCC, the high potential voltage VDD, the common voltage VCOM, and the gamma reference voltage VCOM, VGL) and the like.

The high potential voltage (VDD) may be used as a voltage corresponding to the highest or lowest gradation of the data signal, and the gamma reference voltage (GMA) may be used as the voltage corresponding to the intermediate gradations of the data signal, and the gate high signal ( VGH) may be used as a high level of the gate signal, and the gate low signal VGL may be used as a low level of the gate signal.

As such, the power supply unit 200 includes a gate high signal VGH and a gate low signal VGL that turn on and turn off thin film transistors located in the pixel region of the display panel 100. ) Is generated and supplied to the gate driver 400.

The power supply unit 200 may be in the form of a power control integrated circuit (PMIC) using a boost converter method. In addition, the power supply unit 200 includes a power IC 210, a level shifter 220, and a discharge circuit 230, which will be described in detail later.

The timing controller 300 receives timing signals such as a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (Main Clock, MCLK) from the host system 600. After receiving and processing the input, it is transmitted to the gate driver 400 and the data driver 500. Signals for controlling the operation timing of the gate driver 400 include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The signal that controls the operation timing of the data driver 500 includes a source start pulse (SSP), a source shift clock (SSC), a source output enable signal (Source Output Enable, SOE), Polarity control signals (Polarity, POL) are included.

The gate driver 400 shifts the gate start pulse GSP transmitted from the timing controller 300 according to the gate shift clock GSC, and sequentially applies the gate-on voltage Von to the gate lines GL1 to GLm. The gate high signal (VGH) is provided. In addition, the gate low signal VGL having the gate off voltage Voff is supplied to the gate lines GL1 to GLm during the remaining period when the gate high signal VGH of the gate on voltage Von is not supplied. The gate driver 400 may be a gate in panel (GIP) structure formed on the display panel 100.

The data driver 500 generates a sampling signal by shifting a source start pulse (SSP) from the timing controller 300 according to a source shift clock (SSC). Then, the data driver 500 latches the image data RGB input according to the source shift clock SSC according to the sampling signal, changes it into a data signal, and then horizontal lines in response to the source output enable (SOE) signal. Data signals are supplied to the data lines DL1 to DLn in units. To this end, the data driver 500 may include a data sampling unit (not shown), a latch unit (not shown), a digital-to-analog conversion unit (not shown), an output buffer (not shown), and the like.

The gate driving unit 400 and the data driving unit 500 may be formed in the form of a plurality of driving integrated circuits (D-ICs), and the plurality of driving integrated circuits are formed by a chip on glass (COG) method. It may be mounted on the display panel 100.

FIG. 2A is a diagram showing a gate driver in a gate-in-panel structure when one gate-low signal is used, and FIG. 2B is a diagram showing a reliability curve of a thin film transistor when one gate-low signal is used.

When the oxide thin film transistor is operated for a long time, heat is generated due to internal resistance, and the characteristics of the thin film transistor may be changed. This change in characteristics is called bias temperature stress, and the threshold voltage of the thin film transistor can be changed.

2A, when one and the same gate row signal VGL is applied to the source electrodes of the T2 and T4 transistors, the voltage applied to the gate electrode of the T3 transistor and the voltage applied to the source electrode of the T3 transistor are gate low signals (VGL). ), the voltage Vgs between the gate and the source of the T3 transistor becomes zero. In this case, since the voltage Vgs between the gate and the source does not have a negative (-) value, the T3 transistor is subjected to a positive bias temperature stress (PBTS), so that the threshold voltage is increased as shown in FIG. 2B.

3A is a diagram showing a gate driver in a gate-in-panel structure when two gate low signals are used, and FIG. 3B is a diagram showing a reliability curve of a thin film transistor when two gate low signals are used. In FIG. 3A, the first gate low signal VGL1 is applied to the source electrode of the T2 transistor, and the second gate low signal VGL2 is applied to the source electrode of the T4 transistor. That is, a line for applying the first gate row signal VGL1 and a line for applying the second gate row signal VGL2 to each of the thin film transistors included in the gate driver of the gate-in-panel structure are respectively connected to the gate driver. Two different gate low signals can be applied. Here, it is preferable that the voltage of the first gate low signal VGL1 is lower than that of the second gate low signal VGL2.

The voltage of the first gate low signal VGL1 is applied to the gate electrode of the T3 transistor, and the voltage of the second gate low signal VGL2 is applied to the source electrode of the T3 transistor. Since the voltage of the first gate low signal VGL1 is lower than that of the second gate low signal VGL2, the voltage Vgs between the gate and the source of the T3 transistor has a negative value. Accordingly, the T3 transistor is subjected to negative bias temperature stress (NBTS), thereby improving the problem of increasing the threshold voltage by canceling the positive bias temperature stress. Therefore, in a display device including an oxide thin film transistor, it is preferable to use two gate low signals in order to cancel the positive bias temper stress.

Meanwhile, the display device has a problem that an afterimage remains when the power is turned off. This occurs because the gate low signal VGL is applied to the gate lines GL1 to GLm and charge remains in the storage capacitor even when the thin film transistor is turned off when the power supply voltage of the driving display device is cut off. . To solve this problem, a discharge circuit is provided in the gate driver to discharge the electric charge charged in the storage capacitor when the display device is turned off.

The discharge circuit outputs the gate low signal VGL when the power of the display device is on to maintain the turn-off state of the thin film transistor positioned on the display panel. As soon as the power of the display device is turned off, the gate high signal VGH is output for a certain period of time T to discharge the charge remaining in the storage capacitor located in the display panel. After a certain time T has elapsed, the ground signal GND is applied to maintain the discharge state.

When an oxide thin film transistor is used to implement a high performance display device and simplify the manufacturing process, two gate low signals (VGL1, VGL2) are used to prevent the threshold voltage of the thin film transistor from rising due to a positive bias temper stress. It is preferable to use, but when only one of the terminals outputting two gate-low signals is discharged when the display device is turned off, charge remains in the gate-in panel (GIP) by the remaining gate-low signals that are not discharged. Thereby, there is a problem that an afterimage occurs on the screen. Therefore, it is possible to solve a problem in which afterimages are generated on the screen only when both terminals are discharged from the terminals outputting the gate low signals.

Accordingly, the present invention may include a discharge circuit 230 for discharging all terminals outputting two gate low signals in the power supply unit 200.

4 is a view showing the configuration of a shift register of a power supply unit and a gate driver including a discharge circuit, a power IC, and a level shifter of the present invention.

The power IC 210 uses a power supply voltage VCC, a gate high signal VGH, a first gate low signal VGL1, a second gate low signal VGL2, and ground using an input voltage Vin supplied from the outside. The signal GND is generated and supplied to the level shifter 220, and a power supply voltage VCC is supplied to the shift register 410 of the gate driver 400.

The level shifter 220 receives the start signal ST, the first clock signal GCLK, and the second clock signal MCLK from the timing controller, and then generates the gate start signal VST and the clock signal CLK. It is supplied to the shift register 410 of the gate driver 400. The gate high signal VGH that turns on the thin film transistor of the display panel is supplied to the shift register 410 of the gate driver 400.

Also, the level shifter 220 discharges the first gate low signal VGL1 or the gate high signal VGH and the ground signal GND through the discharge signal output terminal DSC_P, and the discharge signal input terminal DSC_I of the discharge circuit 230. ), and the second gate low signal VGL2 or the gate high signal VGH and the ground signal GND through the gate low signal output terminal VGL_P, the second gate low signal input terminal of the discharge circuit 230. By supplying with (VGL2_I), the discharge circuit 230 discharges the electric charge remaining in the gate driver 400.

The discharge circuit 230 of the present invention may include a first gate low signal output terminal (VGL1_O) and a second gate low signal output terminal (VGL2_O), and a discharge signal input terminal (DSC_I) and a second gate low signal input The terminal VGL2_I may include a first diode D1, a second diode D2, a first resistor R1, a first node N1, and a second node N2.

The discharge signal input terminal DSC_I of the discharge circuit 230 may be connected to the first node N1 and the level shifter 220, and the second gate low signal input terminal VGL2_I is the anode of the second diode D2. It can be connected to the electrode and the level shifter 220.

The anode electrode of the first diode D1 may be connected to the first node N1, and the cathode electrode may be connected to the second node N2.

The anode electrode of the second diode D2 may be connected to the second gate row signal input terminal VGL2_I, and the cathode electrode may be connected to the second node N2.

One end of the first resistor R1 may be connected to the first node N1, and the other end may be connected to the first gate low signal output terminal VGL1_O.

The first gate low signal output terminal VGL1_O may be connected to the other end of the first resistor R1 and the shift register 410 included in the gate driver 400, and the second gate low signal output terminal VGL2_O The second node N2 and the shift register 410 included in the gate driver 400 may be connected. Here, the voltage of the first gate low signal VGL1 is preferably lower than the voltage of the second gate low signal VGL2.

The discharge circuit 230 outputs the first gate low signal VGL1 supplied from the level shifter 220 through the first gate low signal output terminal VGL1_O when the power of the display panel is maintained on. Then, the second gate low signal VGL2 is output through the second gate low signal output terminal VGL2_O. Accordingly, by supplying the two gate low signals to the gate driver 400, the threshold voltage of the thin film transistor rises by canceling the positive bias temperature stress (PBTS) generated in the thin film transistor included in the gate driver 400. Can be prevented.

The discharge circuit 230 receives the gate high signal VGH supplied from the level shifter 220 from the moment when the power of the display panel is turned off to a certain time T until the first gate low signal. The signal is output through the output terminal VGL1_O and the second gate low signal output terminal VGL2_O. Accordingly, the gate high signal VGH is supplied to all of the lines where the two gate low signals are supplied to the gate driver 400 to discharge the remaining charge after the power of the display panel is turned off.

The discharge circuit 230 receives the ground signal GND supplied from the level shifter 220 after the predetermined time T after the power of the display panel is turned off. By outputting through VGL1_O and the second gate low signal output terminal VGL2_O, the gate high signal or the gate low signal is not supplied to the gate driver 400.

The shift register 410 included in the gate driver 400 includes a plurality of stages ST1, ST2, ..., STm that are connected to each other, and a start pulse VST supplied from the level shifter 220. The gate signal is sequentially supplied to the gate lines according to the clock signal CLK. The gate start signal VST is supplied to the first stage ST1 of the shift register 410, and each of the second to mth stages ST2, ..., STm is transferred to the previous stages ST1, ..., STm The gate high signal (VGH) having the gate-on voltage sequentially on the gate lines (GL1, ..., GLm), or gate off (off) by receiving the output signal of -1) as the gate start signal (VST) ) A first gate row signal VGL1 having a voltage is supplied to drive the thin film transistor in the display area.

5 is a view showing a waveform according to the driving step of the discharge circuit. As an embodiment, the first gate low signal VGL1 is set to -14V, the second gate low signal VGL2 is set to -12V, the gate high signal VGH is set to 14V, and the ground signal GND is set to 0V. .

In step P1 in which the power of the display panel of FIG. 5 is maintained on, the power of the display panel VCC is on, and the first gate low signal is applied to the discharge signal input terminal DSC_I. (VGL1) is input, and the second gate low signal VGL2 is input to the second gate low signal input terminal VGL2_I.

At this time, in the discharge circuit 230 of FIG. 4, a current flows from the anode electrode to the cathode electrode, and the second node N2 has the same voltage as the voltage of the second gate low signal VGL2. do. However, the voltage of the first gate low signal VGL1, in which the voltage of the second node N2 (−12 V in the embodiment) is applied to the first node N1 through the discharge signal input terminal DSC_I (in the embodiment, − 14V), but since the current cannot flow from the cathode electrode of the first diode D1 to the anode electrode, the first diode D1 is in a state in which the current is cut off and applied to the second gate low signal input terminal VGL2_I Since the second gate low signal VGL2 is output to the second gate low signal output terminal VGL2_O as it is, the second gate low signal is output from the second gate low signal output terminal VGL2_O as in step P1 of FIG. 5. The second gate low signal VGL2 having the same waveform as the waveform applied to the input terminal VGL2_I is output. In addition, since the first diode D1 is cut off and the first gate low signal VGL1 applied through the discharge signal input terminal DSC_I is output as it is to the first gate low signal output terminal VGL1_O, the first gate low The first gate low signal VGL1 having the same waveform as the waveform applied to the discharge signal input terminal DSC_I is output from the signal output terminal VGL1_O. The power of the display panel of FIG. 5 is turned off. In step P2 from immediately until a certain time T has passed, the power supply VCC of the display device is in an off state and the gate high signal VGH is input to the discharge signal input terminal DSC_I, The second gate low signal VGL2 is input to the second gate low signal input terminal VGL2_I.

At this time, the voltage of the gate high signal VGH (14 V in the embodiment) applied to the first node N1 through the discharge signal input terminal DSC_I in the discharge circuit 230 of FIG. 4, the second gate low signal input The second gate low signal VGL2 through the terminal VGL2_I is greater than the voltage of the second gate low signal (−12 V in the embodiment). Therefore, as current flows from the anode electrode of the first diode D1 toward the cathode electrode, the second gate low signal output terminal VGL2_O outputs the gate high signal VGH. In addition, since the gate high signal VGH applied through the discharge signal input terminal DSC_I is output to the first gate low signal output terminal VGL1_O as it is, the gate high signal is output from the first gate low signal output terminal VGL1_O. The discharge circuit maintains the outputs of the first and second gate low signals VGL1 and VGL2 in step P1 in which the power of the display device is turned on, and the power of the display device is turned off. By outputting the gate high signal VGH through the first and second gate low signal output terminals VGL1_O and VGL2_O in step P2 immediately after (off), charges remaining in the gate driver 400 may be discharged. .

In step P3 after a certain time T has elapsed after the power of the display panel of FIG. 5 is turned off, the power supply VCC of the display device continues to be off, and a discharge signal The ground signal GND is input to the input terminal DSC_I and the second gate low signal input terminal VGL2_I.

At this time, the voltage of the ground signal (0V in the embodiment) applied to the first node N1 through the discharge signal input terminal DSC_I in the discharge circuit 230 of FIG. 4 is the second gate low signal input terminal VGL2_I ) Is equal to the voltage (0V in the embodiment) of the second node N2 to which the ground signal GND is applied. Accordingly, the second gate low signal output terminal VGL2_O outputs the ground signal GND. In addition, the first gate low signal output terminal VGL1_O also outputs the ground signal GND.

Thus, by discharging all the terminals outputting the two gate low signals through the steps P1 to P3, it is possible to discharge the electric charge remaining in the gate driver and to solve the problem of the residual image remaining on the screen.

As described above, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the gist of the present invention and not impairing the effect.

100: display panel 200: power supply
210: Power IC 220: Level shifter
230: discharge circuit 300: timing control
400: gate driver 410: shift register
500: data driving unit 600: host system
T1: First transistor T2: Second transistor
T3: Third transistor T4: Fourth transistor
DSC: Discharge circuit input terminal
VGL2_I: 2nd gate low signal input terminal
VGL1_O: 1st gate low signal output terminal
VGL2_O: Second gate low signal output terminal
D1: first diode D2: second diode
R1: 1st resistor N1: 1st node
N2: second node

Claims (13)

In the first step P1, the first gate row signal VGL1 and the second gate row signal VGL2 are supplied to the gate driver,
In the second step P2, the gate high signal VGH is supplied to the gate driver,
In the third step (P3), a discharge circuit that supplies a ground signal (GND) to the gate driver.
According to claim 1,
In the first step P1, the power of the display panel is on.
The second step (P2) is from the time when the power of the display panel is turned off (off) to the first time (T),
The third step (P3) is a discharge circuit after the first time (T) after the power of the display panel is turned off (off) state.
According to claim 1,
The discharge circuit includes a first gate low signal output terminal (VGL1_O), a second gate low signal output terminal (VGL2_O), a discharge signal input terminal (DSC_I), a second gate low signal input terminal (VGL2_I), and a first diode (D1). ), a second diode D2, a first resistor R1, a first node N1, and a second node N2,
The discharge signal input terminal (DSC_I) is connected to the first node (N1),
The second gate low signal input terminal VGL2_I is connected to the anode electrode of the second diode D2,
The anode electrode of the first diode D1 is connected to the first node N1, and the cathode electrode of the first diode D1 is connected to the second node N2,
The anode electrode of the second diode D2 is connected to the second gate row signal input terminal VGL2_I, and the cathode electrode of the second diode D2 is connected to the second node N2,
One end of the first resistor R1 is connected to the first node N1, and the other end of the first resistor R1 is connected to the first gate low signal output terminal VGL1_O,
The first gate low signal output terminal VGL1_O is connected to the other end of the first resistor R1,
The second gate low signal output terminal VGL2_O is a discharge circuit of the display device connected to the second node N2.
The method of claim 3,
In the first step P1, the first gate row signal VGL1 is output through the first gate row signal output terminal VGL1_O, and the second gate row signal VGL2 is the second gate row. Output through the signal output terminal (VGL2_O),
In the second step P2, the gate high signal VGH is output through the first gate low signal output terminal VGL1_O and the second gate low signal output terminal VGL2_O,
In the third step (P3), the discharge circuit of the display device for outputting the ground signal (GND) through the first gate low signal output terminal (VGL1_O) and the second gate low signal output terminal (VGL2_O).
The method according to any one of claims 1 to 4,
The first gate low signal VGL1 is a discharge circuit of a display device having a lower voltage than the second gate low signal VGL2.
The method according to any one of claims 1 to 4,
The discharge circuit;
A power IC generating a power supply voltage VCC and a first gate low signal VGL1, a second gate low signal VGL2, a gate high signal VGH, and a ground signal GND;
A power supply unit including a level shifter generating a gate start signal (VST) and a clock signal (CLK).
The method of claim 6,
The level shifter,
In the first step (P1), the first gate low signal (VGL1) is supplied to the discharge signal input terminal (DSC_I) of the discharge circuit, and the second gate low signal (VGL2) is the first of the inversion circuit. 2 It supplies to the gate low signal input terminal (VGL2_I),
In the second step (P2), the gate high signal (VGH) is supplied to the discharge signal input terminal (DSC_I) of the discharge circuit, and the second gate low signal (VGL2) is the second gate of the inversion circuit. It is supplied as a low signal input terminal (VGL2_I),
In the third step (P3), the power supply for supplying the ground signal (GND) to the discharge signal input terminal (DSC_I) and the second gate low signal input terminal (VGL2_I) of the discharge circuit.
The method of claim 6,
The power supply;
A display panel including a gate line and a data line, defining a plurality of pixel areas while the gate line and the data line intersect, and including a thin film transistor positioned at a point where the gate line and the data line intersect;
A gate driver including a shift register having first to mth stages and supplying a gate signal to the display panel;
A display device comprising a data driver supplying a data signal to the display panel.
A first step P1 in which the discharge circuit supplies the first gate low signal VGL1 and the second gate low signal VGL2 to the gate driver;
A second step P2 in which the discharge circuit supplies the gate high signal VGH to the gate driver;
And a third step (P3) in which the discharge circuit supplies a ground signal (GND) to the gate driver.
The method of claim 9,
In the first step P1, the power of the display panel is on.
The second step (P2) is from the moment the power of the display panel is turned off (off) to the first time (T),
The third step (P3) is a method of driving a discharge circuit after the first time (T) has elapsed after the power of the display panel is turned off.
The method of claim 9,
The discharge circuit,
In the first step P1, the first gate low signal VGL1 is output to a first gate low signal output terminal VGL1_O, and the second gate low signal VGL2 is a second gate low signal output terminal. Output as (VGL2_O),
In the second step P2, the gate high signal VGH is output to the first gate low signal output terminal VGL1_O and the second gate low signal output terminal VGL2_O,
In the third step (P3), the driving method of the discharge circuit that outputs the ground signal (GND) to the first gate low signal output terminal (VGL1_O) and the second gate low signal output terminal (VGL2_O).
The method according to any one of claims 9 to 11,
The first gate low signal (VGL1) is a method of driving a discharge circuit of a display device having a lower voltage than the second gate low signal (VGL2).
The method of claim 9,
The level shifter,
In the first step (P1), the first gate low signal (VGL1) is supplied to the discharge signal input terminal (DSC_I) of the discharge circuit, and the second gate low signal (VGL2) is the first of the inversion circuit. 2 It supplies to the gate low signal input terminal (VGL2_I),
In the second step P2, the gate high signal VGH is supplied to the discharge signal input terminal DSC_I of the discharge circuit, and the second gate low signal VGL2 is the second gate of the discharge circuit. It is supplied as a low signal input terminal (VGL2_I),
In the third step (P3), the level shifter driving method of supplying the ground signal (GND) to the discharge signal input terminal (DSC_I) and the second gate low signal input terminal (VGL2_I) of the discharge circuit.

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