JP2009276921A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer for outputting the storage data of the memory of a small pin type microcomputer to the outside. <P>SOLUTION: The microcomputer in which a CPU, a memory and a peripheral circuit are loaded on one semiconductor chip includes: a counter 33 for counting a clock in test to generate an address; address switches 34-1 to 34-15 for supplying an address generated by the counter 33 in test to a memory 12; and a selector 40 for dividing data read by the address from the memory in test into a plurality of blocks, and for outputting the signal of one block indicated by a mode signal to be supplied from the outside from the external terminal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a microcomputer, and more particularly to a one-chip microcomputer.

  Conventionally, there is a one-chip microcomputer in which functions such as a CPU, a memory (RAM, ROM), and a peripheral LSI are mounted on one semiconductor chip.

  The microcomputer includes a multi-pin type microcomputer in which an address bus and a data bus are led out to an external terminal, and a small pin type microcomputer in which the address bus and the data bus are not led out to an external terminal.

  FIG. 6 shows a test state of a conventional multi-pin type microcomputer. When testing the data stored in the ROM 1a of the multi-pin microcomputer 1, the external terminals of the address bus and the data bus of the microcomputer 1 are connected to the external terminals A [15: 0] of the address bus of the tester 2 and the data bus. Connect to external terminal D [15: 0].

  Then, a read address is supplied from the tester 2 to the ROM 1a of the microcomputer 1 and read data from the ROM 1a is supplied to the tester 2. The tester 2 uses the read data as standard data (original data written in the ROM 1a). Compare and detect both matches / mismatches.

  FIG. 7 shows a test state of a conventional small pin type microcomputer. When testing the data stored in the ROM 3a of the small pin type microcomputer 3, since the microcomputer 3 does not have external terminals of the address bus and the data bus, a test instruction signal is sent from the tester 4 to the CPU 3b of the microcomputer 3 through the external terminal TEST. Supply.

  As a result, the CPU 3b executes a test program stored in advance in a part of the ROM 3a, sequentially reads out the storage data to be tested from the ROM 3a, and the CPU 3b adds the 15-bit read data to obtain the sum.

  Thereafter, the CPU 3b reads the sum data stored in advance in a part of the ROM 3a, compares the sum data with the above sum, detects the coincidence / mismatch of both, and the detection result is output from one of the general-purpose external terminals GPIO0 to GPIO3. 4 is supplied.

  In addition, although the publicly known literature was investigated about the technique regarding a channel data setting circuit, the publicly known literature corresponding to this was not found.

  Although it is possible to determine whether or not there is an error in the data written in the ROM 3a by a conventional test of a small pin type microcomputer, if there is an error, it cannot recognize which address in the ROM 3a has an error. For this reason, when an error occurs in the ROMs of a plurality of microcomputers, there is a problem that it is impossible to analyze which part of the manufacturing process causes the error.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a microcomputer capable of outputting data stored in a memory of a small pin microcomputer to the outside.

A microcomputer according to an embodiment of the present invention is a microcomputer in which a CPU, a memory, and a peripheral circuit are mounted on one semiconductor chip.
A counter (33) for generating an address by counting a clock during a test;
An address switch (34-1 to 34-15) for supplying an address generated by the counter (33) during the test to the memory (12);
A selector (40) that divides the data read from the memory (12) by the address during the test into a plurality of blocks and outputs a signal of one block indicated by a mode signal supplied from the outside from an external terminal And having.

Preferably, a flip-flop (31) that divides the clock to generate a read enable signal;
A signal switch (32) for supplying a read enable signal generated by the flip-flop (31) to the memory (12) during a test.

  Preferably, the counter (33) is part of the timer (16).

  Preferably, the memory is a ROM (12).

  Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, data stored in a memory of a small pin type microcomputer can be output to the outside.

<Overall configuration of microcomputer>
FIG. 1 is a block diagram showing a microcomputer according to an embodiment of the present invention. In the figure, a microcomputer 10 includes a CPU 11, a ROM 12, a RAM 13, a serial input / output circuit (UART) 14, an 8-bit timer 15, a 16-bit timer 16, an analog input circuit 17, and a general-purpose port circuit 18. The CPU 11, ROM 12, RAM 13, serial input / output circuit 14, 8-bit timer 15, 16-bit timer 16, analog input / output circuit 17, and general-purpose port circuit 18 have an internal address bus 20 and a data bus, respectively. 21 is connected. These circuits and buses 11 to 21 are collectively formed on a one-chip semiconductor substrate.

  The external terminals RXD and TXD of the microcomputer 10 are connected to the serial input / output circuit 14 and perform serial signal input / output during normal operation, and a 2-bit mode signal is input from a tester (not shown) during testing.

  The external terminal TEST is connected to the serial input / output circuit 14, the 16-bit timer 16, and the general-purpose port circuit 18, and indicates a normal operation at a low level (or indefinite state) and a test mode that indicates a test operation at a high level. A signal is input from a tester (not shown).

  The external terminal RST is connected to each circuit such as the CPU 11, the serial input / output circuit 14, the 8-bit timer 15, the 16-bit timer 16, the general-purpose port circuit 18, and the like, and receives a reset signal.

  The external terminal SG is connected to the analog input / output circuit 17, and an analog signal is input / output.

  The external terminals GPIO0 to GPIO3 are connected to the general-purpose port circuit 18, and perform input / output of various signals during normal operation, and output 4-bit divided data during testing.

  The external terminal CLK is connected to each circuit such as the CPU 11, the serial input / output circuit 14, the 8-bit timer 15, the 16-bit timer 16, the general-purpose port circuit 18, and the like, and receives an external clock (system clock).

<Operation during ROM test>
FIG. 2 is a block diagram for explaining the operation during the ROM test. In the figure, the T-type flip-flop 31 in the 16-bit timer 16 is supplied from the external terminal CLK when the reset signal shown in FIG. The external clock shown in FIG. 3A is divided by half to obtain the signal shown in FIG.

  The counter 33 is a 16-bit counter. When the reset signal supplied from the external terminal RST goes low and the reset is released, the initial value is set to 0, and the clock supplied from the flip-flop 31 is counted. A 15-bit count value is supplied to switches (address switches) 34-1 to 34-15. FIG. 3C shows the count value of the counter 33. In the figure, “H ′” indicates a hexadecimal display. The 16-bit count value of the counter 33 is supplied to the comparison circuit 35.

  Each of the switches 32, 34-1 to 34-15 is turned on during a test operation in which the test mode signal is at a high level. As a result, the signal shown in FIG. 3E is supplied from the switch 32 to the ROM 12 as a read enable signal (read signal). Further, the lower 15-bit count value of the counter 33 shown in FIG. 3D is supplied from the switches 34-1 to 34-15 as an address to the ROM 12 through the address bus 20.

  The 16-bit timer 16 has a comparison circuit 35 and a 16-bit register 36. During normal operation, the 16-bit timer 16 compares the count value of the counter 33 with a value set in the register 36 for a predetermined time. Then, the comparison circuit 35 outputs a coincidence signal. This coincidence signal is supplied to the CPU 11.

  During the test operation, a read enable signal and an address are supplied to the ROM 12 so that data is read from the ROM 12 and supplied to the general-purpose port circuit 18 through the data bus 21 as shown in FIG.

  The general-purpose port circuit 18 has a selector 40. The selector 40 is supplied with a test mode signal from the external terminal TEST and a 2-bit mode signal from the external terminals RXD and TXD during a test operation.

  As shown in the truth table of FIG. 4, when the test mode signal is 1 (high level), the selector 40 is 4-bit data on the data bus 21 if RXD = 1 and TXD = 1. [3: 0] is output to the external terminals GPIO0 to GPIO3, and if the mode C is RXD = 1 and TXD = 0, the 4-bit data [7: 4] of the data bus 21 is output to the external terminals GPIO0 to GPIO3. To do. If RXD = 0 and TXD = 1, mode B, the 4-bit data [11: 8] of the data bus 21 is output to the external terminals GPIO0 to GPIO3, and RXD = 0 and TXD = 0 in mode A. If there is, the 4-bit data [15:12] of the data bus 21 is output to the external terminals GPIO0 to GPIO3.

  That is, if the mode is A during the test operation, as shown in FIG. 3G, the 0th (LSB) to 3rd bits of the ROM 12 output are output from the external terminals GPIO0 to GPIO3 to a tester (not shown), In mode B, as shown in FIG. 3H, the fourth to seventh bits of the ROM 12 output are output from the external terminals GPIO0 to GPIO3. In the case of mode C, as shown in FIG. 3 (I), the 8th to 11th bits of the ROM 12 output are output from the external terminals GPIO0 to GPIO3. Thus, the 12th to 15th bits of the ROM 12 output are output from the external terminals GPIO0 to GPIO3.

  FIG. 5 shows a flowchart of the ROM read process executed in the test operation. In the figure, the CPU 11 is stopped in step S1. Loop processing is performed in steps S2 to S7. In this loop processing, the modes are changed in order of A, B, C, and D.

  In step S3, the 16-bit timer 16 is started. In step S4, data is read from the ROM 11, and 4 bits corresponding to the modes A, B, C, and D are output from the external terminals GPIO0 to GPIO3.

  When reading to the final address of the ROM 12 is completed, the process proceeds from step S5 to step S6, and the 16-bit timer 16 is reset.

  In this way, reading from the ROM 12 is repeated four times, and all the data read from the ROM 12 is output.

  According to the embodiment, since all data can be read from all addresses of the ROM 12, whether or not there is an error in comparing each data with the standard data (original data written in the ROM 1a) by the tester. If there is an error, the address can be recognized. For this reason, when an error occurs in the ROMs of a plurality of microcomputers, it is possible to analyze which part of the manufacturing process caused the error.

  In addition, since the address and read enable signal of the ROM 12 are generated using the 16-bit timer 16 originally provided in the microcomputer, it is not necessary to generate the address and read enable signal by the tester, and the test is easy. Become. Further, the above test can be realized with a simple configuration in which the flip-flop 31, the switches 34-1 to 34-15, and the selector 40 are simply added.

  In the above embodiment, the ROM 12 is read four times by switching the mode. However, the mode is switched four times to A, B, C, and D while the 16-bit timer 16 generates one address, and 16 bits. The data may be sequentially output from the external terminals GPIO0 to GPIO3 by 4 bits.

It is a block block diagram of one Embodiment of the microcomputer of this invention. It is a block block diagram for demonstrating the operation | movement at the time of ROM test. It is a signal timing chart of each part of FIG. It is a figure which shows the truth table for demonstrating selector operation | movement. It is a flowchart of a ROM read process executed in a test operation. It is a figure which shows the mode of the test of the conventional multipin type | mold microcomputer. It is a figure which shows the mode of the test of the conventional small pin type | mold microcomputer.

Explanation of symbols

10 Microcomputer 11 CPU
12 ROM
13 RAM
14 serial input / output circuit 15 8-bit timer 16 16-bit timer 17 analog input circuit 18 general-purpose port circuit 20 address bus 21 data bus 31 flip-flop 32, 34-1 to 34-15 switch 33 counter 35 comparison circuit 36 register 40 selector

Claims (4)

In a microcomputer in which a CPU, memory and peripheral circuits are mounted on one semiconductor chip,
A counter that generates an address by counting the clock during testing,
An address switch that supplies the memory with an address generated by the counter during testing;
A selector that divides data read from the memory from the memory at the time of the test into a plurality of blocks, and outputs a signal of one block indicated by a mode signal supplied from the outside from an external terminal;
A microcomputer characterized by comprising: The microcomputer according to claim 1.
A flip-flop that divides the clock to generate a read enable signal;
A signal switch for supplying a read enable signal generated by the flip-flop to the memory during the test;
A microcomputer characterized by comprising: The microcomputer according to claim 2.
The microcomputer, wherein the counter is a part of a timer. The microcomputer according to claim 3.
The microcomputer is characterized in that the memory is a ROM.

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