JP2003302448A - Test circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test circuit capable of heightening the throughput and suppressing the increase of circuit area. <P>SOLUTION: Serial data SD are inputted from the outside via a serial interface circuit 10 and converted into N-bit parallel data [1]-[N] for a test by a N-bit shift register 20, and the parallel data PD [1]-[N] are circulated, to thereby generate N-bit parallel data PD [1]-[N] for a different test. Then, a signature as the serial data is generated by using a N data portion of the N-bit parallel data PDIN acquired by a user logic circuit and outputted to the outside via the serial interface circuit 10. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for testing a semiconductor circuit mounted on a semiconductor chip. 2. Description of the Related Art A semiconductor integrated circuit (LSI) is provided with a semiconductor circuit (referred to as an internal block) on a semiconductor chip. Therefore, on that semiconductor chip,
A test circuit for directly controlling and observing the operation of the internal block may be mounted. As such a test circuit, typically, a scan test circuit, a BIST (Bu
An it-In Self Test) circuit and a data input device for testing are known. The scan test circuit forms a scan chain by connecting a plurality of flip-flops constituting an internal block in series, sends test data serially to the scan chain, and gives the sent serial data to the internal block. In addition, the circuit tests the operation of the internal block by fetching output data of the internal block into a flip-flop, serially extracting the captured data to the outside, and observing the data. The BIST circuit has a test pattern generation device for generating a test pattern for testing the operation of the internal block, inputs the generated test pattern to the internal block, analyzes the output result of the internal block, and determines whether the output is good or bad. It is a circuit for determining. The test data input device is a device mounted on the semiconductor chip for controlling a test pattern input from outside the semiconductor chip. The test pattern input from the outside is controlled by the test data input device. It is controlled by the input device and input to the internal block. However, the above-described scan test circuit only tests the operation of the cells constituting the internal block, and it is therefore difficult to verify the function of the entire internal block. . Further, the BIST circuit tests the operation of the internal block using a test pattern having a fixed sequence from a test pattern generation device mounted on a semiconductor chip. It is difficult to obtain a high fault coverage. On the other hand, since the test data input device can freely input various test patterns, the problems in the scan test circuit and the BIST circuit can be avoided. When the operation of the internal block is tested with this test data input device, the number of terminals is reduced even when the internal block handles parallel data in order to reduce the size of the semiconductor integrated circuit package. The input / output terminal preferably inputs and outputs data as serial data. Here, in order to convert serial data at the input terminal into parallel data, there are a method using a shift register and a method of storing serial data in a memory and outputting it as parallel data. In a system using a shift register, for example, when serial data is converted into N-bit parallel data, the shift register requires N cycles of time. Also, converting N-bit parallel data into serial data and outputting it requires a time of N cycles or more. Therefore, there is a problem that the throughput decreases in the test. Further, the method using a memory requires an area for arranging the memory on a semiconductor chip. SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a test circuit in which the throughput is increased and the increase in the circuit area is suppressed. According to the present invention, there is provided a test circuit for testing a semiconductor circuit mounted on a semiconductor chip, the test circuit being mounted on the semiconductor chip. A shift register that inputs serial data from outside the semiconductor chip, converts the serial data into N-bit parallel data for testing, and circulates the parallel data to generate different N-bit parallel data for testing; A signature generation circuit for generating a signature as serial data using the obtained N-bit parallel data and outputting the signature to the outside of the semiconductor chip. In the test circuit of the present invention, when testing the operation of a semiconductor circuit mounted on a semiconductor chip, serial data is inputted from outside the semiconductor chip and converted into N-bit parallel data for testing by the register. In addition, by circulating the parallel data to generate different test N-bit parallel data, the value of the shift register can be changed every cycle and output to the semiconductor circuit as test parallel data. it can. Therefore, it is not necessary to input N-bit serial data into parallel data at a time interval equal to or longer than N cycles, thereby increasing the test throughput. In addition, compared to the conventional technique of outputting parallel test data using a memory, an increase in circuit area can be suppressed. Further, when converting the N-bit parallel data output from the semiconductor circuit into serial data, a signature generation circuit (MISR: Mu1t)
ip1e Input Signature Regi
s) to generate a signature of parallel data input every cycle (typically, data compression
Since RC data is generated and output to the outside of the semiconductor chip, the quality of data output from the semiconductor circuit can be determined without lowering the throughput of the semiconductor circuit. The embodiments of the present invention will be described below. FIG. 1 is a block diagram of a test circuit according to one embodiment of the present invention. A test circuit 1 shown in FIG. 1 is mounted on a semiconductor chip, and this test circuit 1 controls the operation of a user logic circuit (not shown) which is a semiconductor circuit mounted on the semiconductor chip. This is the circuit to be tested.
It is assumed that the user logic circuit has an N-bit parallel data bus and has a specification of taking in all the parallel data during the data valid assertion period. The test circuit 1 includes a serial interface circuit 10, an N-bit shift register 20,
And a MISR 30 (corresponding to a signature generation circuit according to the present invention). The serial interface circuit 10 includes:
Serial data DIN and a serial data input valid signal DIN_VALID are input from outside the semiconductor chip. The serial data DIN is captured by the serial interface circuit 10 while the serial data input valid signal DIN_VALID is at logic 1 (data valid assert period). Also, from the serial interface circuit 10, while the serial data output valid signal DOUT_VALID is at logic 1 (data valid assert period), compressed serial data DOUT from the user logic circuit to be described later is output.
Is output. The serial interface circuit 10 captures the serial data DIN while the serial data input valid signal DIN_VALID is asserted, and outputs the captured serial data DIN to the N-bit shift register 20 as serial data SD. Also, this serial interface circuit 10
A parallel data generation signal PDCNT for generating N-bit parallel data based on the serial data SD
To the N-bit shift register 20. Further, the serial interface circuit 10 outputs N-bit parallel data [1] to N-bit parallel data (described later) output from the N-bit shift register 20 to the user logic circuit.
A parallel data valid signal PD_VALID for taking [N] into the user logic circuit is generated. The N-bit shift register 20 receives the serial data SD and the parallel data generation signal PDCNT from the serial interface circuit 10 and converts them into test N-bit parallel data PD [1] to PD [N]. Parallel data PD [1] ~
By circulating [N], different test N-bit parallel data PD [1] to PD [N] are generated. The MISR 30 has N-bit parallel data PDIN and an N-bit parallel data input valid signal PDIN_VAL obtained by the user logic circuit.
An ID is input. The MISR 30 sets the N-bit parallel data input valid signal PDIN_VALID to logic 1
During the data valid assert period, the N-bit parallel data PDIN is fetched, and a signature (CRC data) as serial data is generated by using the N data of the fetched N-bit parallel data PDIN to generate a serial interface. The data is output to the circuit 10 as serial data SDOUT. Hereinafter, FIG.
The operation of the test circuit 1 shown in FIG.
This will be described with reference to FIG. FIG. 2 is a diagram showing the configuration of the N-bit shift register shown in FIG. 1, FIG. 3 is a diagram showing the configuration of the MISR shown in FIG. 1, and FIG. 4 is a timing chart of the test circuit shown in FIG. is there. The flip-flops 21_1,..., 21_N-2, 2 are provided in the N-bit shift register 20 shown in FIG.
1_N-1, 21_N and a selector 22 are provided. Here, when test data is requested from the user logic circuit, as shown in FIG. 4, while the serial data input valid signal DIN_VALID is at logic 1 (data valid assert period), the serial data DIN
Are input to the serial interface circuit 10 for N bits (serial data D1 shown in FIG. 4), and the serial data S
D and the parallel data generation signal PDCNT are output to the N-bit shift register 20. In response to this, the N-bit shift register 20 receives the flip-flops 21_1,.
_N-2, 21_N-1, 21_N, the serial data SD is converted to test N-bit parallel data PD.
Convert to [1] to [N]. Thereafter, while the serial data input valid signal VIN_VALID is at logic 0, the data R1, R2, R3,... Shown in FIG. , R (N-1), N-bit parallel data PD [1] to PD [1] are generated. As described above, in the shift register, the parallel data is automatically generated by shifting the feedback value. In this way, different parallel data can be output every cycle. Next, in order to output different parallel data, the signal VIN_VALID is set to logic 1, and the N-bit data (serial data D2 shown in FIG. 1] to [N] are generated. By doing so, it is possible to generate N-bit test data in which the first N-bit test data and the newly input test data are mixed. Thus, at D2 next to R (2N-1) shown in FIG.
All the bit shift registers 20 are replaced with the newly input test data D2, and different test data can be efficiently generated. When N = 16 bits, USB (Universal Serial)
Bus), which can be applied to the format of a data packet, and is a packet ID which is one of USB headers.
(PID) and the CRC of the generated data can be calculated in advance and added. In the test circuit 1 of the present embodiment, when testing the operation of a user logic circuit mounted on a semiconductor chip, serial data DIN is input from outside the semiconductor chip by an N-bit shift register 20 for testing. To the N-bit parallel data PD [1] to PD [1] to [N].
By circulating [N] to generate different test N-bit parallel data PD [1] to PD [N], the value of the N-bit shift register 20 is changed every cycle to obtain test parallel data. Since the data is output to the user logic circuit, it is not necessary to input N-bit parallel data at a time interval of N cycles or more when converting the parallel data of N bits into serial data, thereby increasing the test throughput. In addition, compared to the conventional technique of outputting parallel test data using a memory, an increase in circuit area can be suppressed. The user logic circuit outputs MI
N-bit parallel data PDIN and N-bit parallel data input valid signal PDIN_ toward SR30
VALID is output. Here, the user logic circuit performs an N-bit parallel data input valid signal PDI.
While N_VALID is at logic 1 (data valid assertion period), N-bit parallel data PDIN is output every cycle. Therefore, when the same clock is used, N-bit parallel data PDIN is directly converted into serial data and output. It is difficult to do. Therefore, a signature (CRC data) corresponding to the serial data is generated by the MISR 30, output to the outside via the serial interface circuit 10, and whether or not the data from the user logic circuit is correct is determined. As shown in FIG. 3, the MISR 30 includes a combination circuit 31 and an N-bit shift register 32. The combinational circuit 31 sets the N-bit parallel data input valid signal PDIN_VALID to logic 1
During the data valid assertion period, the N-bit parallel data PDIN is fetched for N bits, thereby circulating the serial data from itself and the N-bit shift register 32 and performing data compression to obtain a signature as serial data. It generates CRC data and outputs it as serial data SDOUT via the serial interface circuit 10 to the outside. In this way, the quality of data output from the user logic circuit can be determined without lowering the throughput of the user logic circuit. As described above, according to the present invention,
It is possible to provide a test circuit in which the throughput is increased and the increase in the circuit area is suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a test circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration of an N-bit shift register shown in FIG. FIG. 3 is a diagram showing a configuration of the MISR shown in FIG. 1; FIG. 4 is a timing chart of the test circuit shown in FIG. [Description of Signs] 1 Test circuit 10 Serial interface circuit 20 N-bit shift registers 21_1,..., 21_N-2, 21_N-1, 21_N
Flip-flop 22 Selector 30 MISR 31 Combination circuit 32 N-bit shift register

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Claims (1)

Claims: 1. A test circuit mounted on a semiconductor chip for testing a semiconductor circuit mounted on the semiconductor chip, wherein serial data is input from outside the semiconductor chip for testing. A shift register that generates different test N-bit parallel data by circulating the parallel data and serial data using the N-bit parallel data obtained by the semiconductor circuit. And a signature generation circuit for generating the signature of (1) and outputting the signature to the outside of the semiconductor chip.