JP4193336B2 - Microcontroller test circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcontroller test circuit incorporated for testing peripherals (peripheral circuits) having respective functions inside a microcontroller (hereinafter referred to as a microcomputer) via an external terminal without using a CPU.
[0002]
[Prior art]
In it is difficult to test each pair referrals internal high functionality of the microcomputer proceeds, it is incorporated microcontroller test circuit, through an external terminal to each peripheral itself for each pair referrals without using the CPU The MUX separation method for testing is employed. In this MUX separation method, in order to normally operate the microcontroller test circuit, the test signal from the outside to separate each pair referrals, it is necessary to output a control signal or the like. Therefore, in addition to the common bus connecting each pair referrals, for each pair referrals, lines for inputting and outputting a test signal from the external control signal lines or the like for inputting and outputting a control signal are arranged, each of these lines The external terminal was arranged in.
[0003]
[Problems to be solved by the invention]
Above the prior art, as the number of bits of the common bus is increased, or enough to become many Bae referrals number, the number of number of external terminals required for test, assigning all such external terminals to the normal function terminal The problem to be solved was left to be difficult.
[0004]
[Means for Solving the Problems]
The present invention adopts the following configuration in order to solve the above points.
<Configuration 1>
Built in the microcontroller, for testing a plurality of Bae referrals including microcontroller individually, a microcontroller test circuit for input and output from the outside of the microcontroller a predetermined signal via the external terminals, each and La Itodeta multiple parallel bits written as an expected value at a predetermined address in the peripherals, and in comparison with the reading out has been read data as the expected value of the plurality of parallel bits after write completion, the said write data read data A comparison unit that outputs a coincidence signal when they match, and a state monitoring unit that monitors the operation state of the microcontroller and detects the desired operation state, and connects the output of the comparison unit to the external terminal, the external output of the previous SL coincidence signal through a terminal to luma Lee microcontroller tests In road, comprising an address generator for generating said predetermined address and bus control signals, and sends a skip signal to the address generation unit reserved area recognition unit when the predetermined address was reserved area, the The address generation unit counts when writing of an expected value to the predetermined address is completed and when an acknowledge signal from the predetermined peripheral becomes active after completion of bus reading, or when a skip signal is received from the reserved area recognition unit The reserved area recognition unit recognizes that the predetermined address is a reserved area when the acknowledge signal from the predetermined peripheral is not active for a predetermined time and outputs the skip signal. Microcontroller test characterized by sending to address generator Road.
[0005]
[0006]
<Configuration 2 >
The microcontroller test circuit according to Configuration 1 , wherein the reserved area recognition unit includes a time setting circuit capable of arbitrarily setting the predetermined time from the outside via the external terminal. .
[0007 ]
[0008 ]
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described using specific examples.
<Specific example 1>
FIG. 1 is a block diagram of the configuration of the first specific example.
Before explaining the specific example 1 with reference to FIG. 1, in order to clarify the solution problem of the microcontroller test circuit according to the present invention, the MUX separation method will be described below using a comparative example.
[0010]
FIG. 2 is a block diagram of a comparative example.
2, the peripheral (peripheral circuit) alone having a plurality of respective functions without using the CPU, the test method for testing from the external terminal, i.e. a block diagram of a microcomputer employing the MUX isolation scheme.
As shown in the figure, the microcomputer includes a CPU 11, a first peripheral 12, a second peripheral 13, a third peripheral 14, an address decoder 15, a test circuit 16, a port control circuit 17, selectors 20 to 25, and a test control circuit 26. It consists of
[0011]
The CPU 11 is a microprocessor that controls the entire microcomputer.
First from the third pair referrals 1 2-14 are various functional blocks microcomputer built. The present invention is to test a pair referrals this from individual external terminal to output a predetermined signal. Although only three are described here as an example, an extremely large number of actual microcomputers are incorporated.
[0012]
Address decoder 15 is a part that specifies the address of the test all-out Bae referrals in portion when the test mode.
Test circuit 16 is a part for supplying the control signals necessary to the third pair referrals 1 2-14 from the first to the test mode.
[0013]
The port control circuit 17 is a part that controls input / output of the port. Here is a partial to select a test all-out Bae referrals at the time of the test mode.
The selectors 20 to 25 are input / output switchers.
The test control circuit 26 is a part that controls the common bus in the test mode.
[0014]
As an example of the operation of the microcomputer in the test mode, a case where the second peripheral 13 is tested will be described.
The second peripheral 13 is set to the test mode from the test mode terminals 81 and 82 of the test circuit 16.
[0015]
By this mode setting, the test control signals 61 and 63 become active. When the test control signal 61 becomes active, the CPU 11 releases the common bus. A common bus from this point governs selector 21 and the selector 20 and the test control circuit 26. Here, only one selector 21 is shown in the figure, but in the actual circuit, the read data 41 normally employs a 32-bit data line, so the selector 21 needs 32 bits.
[0016]
The selector 21 connects the read data 41 to a 32-bit normal function terminal (external terminal) 51 when the test control signal 61 becomes active. That is, the output of the second peripheral 13 can be read from the outside.
[0017]
The test control circuit 26 writes a 32-bit normal function terminal (external terminal) 52, a 24-bit normal function terminal (external terminal) 53, and a 2-bit normal function terminal (external terminal) 54 to a 32-bit write. Connected to the data 42, 24-bit address signal 43, and 2-bit bus control signal 44, the expected value (write data), address value, and bus control signal value from each normal function terminal 52 to 54 to the second peripheral 13 are displayed. Enable input from outside.
[0018]
Further, when the test control signal 63 becomes active, the selector 24 selects the normal function terminal (external terminal) 72 and enables input to the second peripheral 13 from the outside. Similarly, the selector 23 selects the output terminal 93 of the second peripheral 13 and enables the output signal value of the second peripheral 13 to be output to the normal function terminal (external terminal) 73.
[0019]
As a result, all signals (including the bus) of the second peripheral 13 can be controlled and tested from the normal function terminals (external terminals) of the chip.
The points to be noted here are as follows.
Here, the number of peripherals is limited to three, but in an actual circuit, the number is extremely large. Therefore, the required quantity of normal function terminals (external terminals) is enormous. It is an object of the present invention to enable testing without increasing the number of normal function terminals (external terminals). Specific examples thereof will be described below.
[0020]
Returning to FIG. 1 again, the configuration of Example 1 will be described.
The specific example 1 aims to reduce the number of normal function terminals (external terminals) 51 of the 32-bit read data 41 (FIG. 2).
In the following description, read data and write data are limited to 32 bits as an example.
[0021]
As shown in FIG. 1, the microcontroller test circuit of the first specific example includes a comparison unit 1, a state monitoring unit 2, and a selection unit 3.
Comparing section 1, Bae and referrals write data 42 to write the parallel 32-bit expected value at a predetermined address (register) Le (Fig. 2), parallel 32 bit read to read the expected value written after completion of writing data 41 (FIG. 2) is a part that outputs a coincidence signal when they coincide.
[0022]
Here, 32 bits of write data 42 (FIG. 2) and 32 bits of read data 41 (FIG. 2) are compared, and when all 32 bits match, that is, a predetermined address (register) operates normally. A coincidence signal is output when it is confirmed.
[0023]
The state monitoring unit 2 is a part that outputs the coincidence signal of the comparison unit when the operation state of the microcomputer is monitored and a desired operation state is detected.
As an example, it is constituted by a three-input AND gate 102. When the acknowledge signal 40 and the bus control signal 44 are received, the coincidence signal 111 is passed.
[0024]
Reading to a predetermined address (register) is instructed by the bus control signal 44, and when the reading is completed, the acknowledge signal 40 becomes active. This is because the match between the write data 42 (FIG. 2) and the read data 41 (FIG. 2) can be confirmed for the first time in this state.
[0025]
The selection unit 3 is a part for outputting the coincidence signal to the normal function terminal (external terminal) 121 by the test control signal 61 output from the test circuit 16 (FIG. 2).
With this configuration, the normal function terminal (external terminal) 51 required for 32 bits can be replaced with a 1-bit normal function terminal (external terminal) 121 as described in the comparative example.
[0026]
<Effect of specific example 1>
With the configuration of the specific example 1 described above, the normal function terminal (external terminal) 51 required for 32 bits can be replaced with a 1-bit normal function terminal (external terminal) 121.
[0027]
<Specific example 2>
In specific example 2, an address generation unit is provided inside for the purpose of automating the test.
FIG. 3 is a block diagram of the configuration of the second specific example.
As shown in FIG. 3, the microcontroller test circuit of the specific example 2 includes an address generation unit 130, an OR gate 140, and a reserved area recognition unit 150.
[0028]
Address generator 130, Bae when referrals acknowledge signal after completion of the writing of the expected value at a predetermined address (register) of Le is activated, or after counted up when receiving a skip signal from the reservation area recognition unit to be described This is the part that outputs the address.
[0029]
Reserved area recognition unit 150, when the acknowledge signal pair referrals or we did not activate a predetermined time, the skip signal recognizes that the address is a reserved area in the portion to be sent to the address generator 130 is there. This predetermined time is set in advance in a clock counter disposed therein. When a predetermined number of clocks are counted while the acceptance of the acknowledge signal is stopped, the reserved area recognition unit 150 overflows, outputs a skip signal, and returns to count 0 again.
[0030]
OR gate 140, an address count-up signal 141 when the acknowledge signal after completion of writing of the expected value of accepted skip signal 151 from the time it is active, or reserved area recognition unit 150 at a predetermined address in Bae referrals (register) This is a part sent to the generation unit 130.
[0031]
An address generation operation of the address generation unit 130 will be described.
FIG. 4 is an explanatory diagram of a register map example.
Normally, when expected values are written to predetermined addresses (registers) in the order of addresses, it is sufficient for the address generator 130 to count up each time an acknowledge signal becomes active. However, the reservation state shown in FIG. 4 may be set. For example, the acknowledge signal becomes active after writing to address 1 in FIG. 4 is completed, and the address generator 130 counts up and outputs address 2.
[0032]
Since this address (register) 2 is reserved, the acknowledge signal is not activated. That is, the address generation unit 130 enters an operation stop state without being counted up. In this case, the reserved area recognition unit 150 starts clock counting . When Bae referrals or we acknowledge signal does not become active a predetermined time, and sends a skip signal 151 recognizes that the address is a reserved area to said OR gate 140.
The OR gate 140 sends a count-up signal 141 to the address generation unit 130 when it receives a skip signal from the reserved area recognition unit 150. As a result, the address generation unit 130 counts up and outputs address 3.
[0033]
<Effect of specific example 2>
The following effects are acquired by providing the structure of the specific example 2 demonstrated above.
1 . Bae referrals can automate the testing of Le.
2 . It is possible to automate the test even if the address of the pair referrals there is a reservation state.
3. It is also possible to delete the normal function terminal (external terminal) 53 (FIG. 2) for inputting the 24-bit address signal 43 (FIG. 2) from the outside.
[0034]
<Specific example 3>
Specific example 3 is an extended example of specific example 2 and includes a time setting circuit for arbitrarily changing the time for the reserved area recognition unit to recognize the reserved state.
FIG. 5 is a block diagram of the configuration of the third specific example.
Only differences from the second specific example will be described.
As shown in FIG. 5, the reserved area recognition unit 200 includes a counter circuit 210 and a time setting circuit 220 as an example.
[0035]
The counter circuit 210 is a portion that overflows when a predetermined number of clocks are counted when the acknowledge signal is in an inactive state, outputs a skip signal, and returns to the count of 0 again.
The time setting circuit 220 is a part that arbitrarily sets a count number for skipping a reserved area via the bus. That is, this is a part for arbitrarily setting a grace time for skipping the reserved area from the outside.
The address generator 130 that has received the count-up signal from the OR gate 140 performs the same operation as in the second specific example.
Other constituent functions are the same as those in the second specific example.
[0036]
<Effect of specific example 3>
By providing the configuration described above, in addition to the effect of the second specific example, it is possible to arbitrarily set a grace period for skipping the reserved area from the outside, so that it is possible to reduce redundant test cycles. Become.
[0037]
<Specific Example 4>
In Example 4, the writing of an expected to Bae referrals, and also reads performed using a common bus, and an object thereof is to remove the external terminal other than the normal function terminal for the common bus (external terminals).
[0038]
FIG. 6 is a block diagram of the configuration of the fourth specific example.
6, the microcontroller test circuit of the fourth specific example includes a test register control unit 120, a first register 138, and a second register 139.
The test register control unit 120 is connected to a common bus, and is a part that enables transmission and reception of predetermined control signals and expected values from the outside of the microcomputer via the common bus.
[0039]
The first register 138 receives an expected value from the test register control unit 120, the expected value temporarily holding a part to be written in the pair referrals via specific signal line.
The second register 139 holds temporarily read an expected value over a specific signal line after completion writing expectations onto Kipe referrals, a part to be sent to the test register control unit 120.
[0040]
The microcontroller test circuit embodiment 4, and the test register control unit 120, a first register 138, a second register 139 is arranged for each pair referrals.
Figure 6 shows a state which is arranged as an example in the second pair referrals 1 3.
[0041]
Next, the operation of the microcontroller test circuit of Example 4 will be described.
The test control signal 61 to 64, the second pair referrals 1 3 is controlled in the test state.
Test register control unit 120 controls the test select signal 122, 125 by the value of the test control signal 61 to 64, the first register 138 from the common bus to the write enable state, the second register 139 second to readable state from Bae referrals 1 3.
[0042]
Test in the above state.
The expected value is written to the first register 138 via the common bus and temporarily held. The expected value is written to the second pair referrals 1 3 via the selector 24.
Expected value written in the second pair referrals 1 3 is sent through a signal line 99 to the second register 139, and is temporarily held.
[0043]
And controls the test select signal 127 by the value of the test control signal 61 to 64 in this state, reads out the second pair referrals expected value written in the LE 1 3 the second register 139 to be read from the common bus .
As a result, it is possible to test a second pair referrals 1 3 from the outside.
[0044]
<Effect of specific example 4>
With the configuration described above, it is possible to delete the normal function terminals (external terminals) connected to other than the common bus.
[0045]
<Specific example 5>
In Example 5, the writing of an expected to similarly Bae referrals as in example 4, and also reads performed using a common bus, to remove the external terminal other than the normal function terminal for the common bus (external terminals) Regarding other examples aimed at.
[0046]
FIG. 7 is a block diagram of the configuration of the fifth specific example.
7, the microcontroller test circuit of Example 5 includes a port register control circuit 50, a first test register 56, a second test register 57, a test port control unit 300, and selectors 301 and 302. .
A port register control circuit 50, a first test register 56, a second test register 57, a selector 301, 302 are disposed for each pair referrals.
Figure 7 shows a state which is arranged as an example in the second pair referrals 1 3.
[0047]
The port register control circuit 50 is connected to a common bus, and is a part that enables transmission and reception of a predetermined control signal and an expected value from the outside of the microcontroller via the common bus.
First test register 56, and a second test register 57 is arranged between the port register control circuit 50 and the pair referrals and held temporarily accept the expected value from the common bus, the expected value to Bae referrals The part to write. Furthermore, temporarily held by reading the expectation value written to Bae referrals, it is also a part sends to the common bus.
[0048]
Test port control unit 300 is a part for performing tests Bae referrals controls the microcontroller test circuit.
The selector 301 and the selector 302 are portions that form signal paths necessary for the test based on the control of the test port control unit 300.
[0049]
Next, the operation of the microcontroller test circuit of Example 5 will be described.
The second pair referrals 1 3 by the test control signal 61 to 64 is controlled in the test state.
The test port control unit 300 controls the test select signals 311 and 312 according to the values of the test control signals 61 to 64, makes the first test register 56 writable from the common bus, and sets the second test register 57 to the second test register 57. to readable state from the second pair referrals 1 3.
[0050]
Test in the above state.
An expected value is written to the first test register 56 via the common bus and temporarily held. The expected value is written to the second pair referrals 1 3 via the selector 24.
Expected value written in the second pair referrals 1 3 is sent to a second test register 57 via the signal line 99, and is temporarily held.
[0051]
The expected value held in the second test register 57 is output to the external terminal 214 via the selector 59.
As a result, it is possible to test a second pair referrals 1 3 from the outside.
The matters to be noted here are as follows.
The selectors 58 and 59, the first test register 56, the second test register 57, and the port register control circuit 50 are employed in the port control circuit 17 (FIG. 2) of the comparative example (FIG. 2) already described. And are well known components to those skilled in the art. Therefore, it is not necessary to arrange again for the microcontroller test circuit, and it can be shared with the port control circuit 17 (FIG. 2).
[0052]
<Effect of Specific Example 5>
By providing the configuration described above, it is possible to delete the normal function terminals (external terminals) connected to other than the common bus as in the fourth specific example.
Furthermore, since some components can be shared with the port control circuit, the area occupied by the microcontroller test circuit on the IC substrate can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a configuration of a specific example 1;
FIG. 2 is a block diagram of a configuration of a comparative example.
FIG. 3 is a block diagram of a configuration of specific example 2;
FIG. 4 is an explanatory diagram of a register map example;
FIG. 5 is a block diagram of a configuration of specific example 3;
FIG. 6 is a block diagram of a configuration of a specific example 4;
FIG. 7 is a block diagram of a configuration of a specific example 5;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Comparison part 2 State monitoring part 3 Selection part 41 Read data 42 Write data 112 Match signal 121 External terminal

Claims (2)

Built in the microcontroller, for testing a plurality of Bae referrals including microcontroller individually, a microcontroller test circuit for input and output from the outside of the microcontroller a predetermined signal via an external terminal,
Compared the and La Itodeta multiple parallel bits written as an expected value at a predetermined address of the peripherals, and read out by the read data as an expected value of the plurality of parallel bits after completion of writing, the write data and the read A comparator that outputs a match signal when the data matches,
A state monitoring unit that monitors the operation state of the microcontroller and detects the desired operation state, and connects the output of the comparison unit to the external terminal;
In the output to the luma Lee microcontroller test circuit before Symbol coincidence signal through the external terminal,
An address generation unit that generates the predetermined address and bus control signal; and a reserved area recognition unit that sends a skip signal to the address generation unit when the predetermined address is a reserved area;
The address generation unit
Outputs the address counted up when the write of the expected value to the predetermined address is completed and the acknowledge signal from the predetermined peripheral becomes active after completion of the bus read, or when the skip signal is received from the reserved area recognition unit And
The reserved area recognition unit
A microcontroller test characterized in that when the acknowledge signal from the predetermined peripheral is not active for a predetermined time, the predetermined address is recognized as a reserved area and the skip signal is sent to the address generator. circuit. The microcontroller test circuit of claim 1 , wherein
The reserved area recognition unit
Microcontroller test circuit, characterized in that it comprises a time setting circuit capable of setting a predetermined time from an external via the external terminals.

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