CN115879401A - Port configuration method of field programmable gate array - Google Patents
Port configuration method of field programmable gate array Download PDFInfo
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Abstract
A port configuration method of a field programmable gate array is used for quickly establishing connection configuration between a port of a test object of the field programmable gate array and a gasket. The method comprises the following steps: receiving a connection configuration instruction between a first port of a test object and a pad of the FPGA; the test object is constructed through a logic unit in the FPGA; any pad on the FPGA is connected to an external circuit through a packaged pin; writing the pad code indicated in the connection configuration instruction into a storage address corresponding to the first port in a register; and establishing connection configuration between the first port and the pad corresponding to the pad code according to the pad code in the storage address corresponding to the first port.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a port configuration method for a field programmable gate array.
Background
The Field Programmable Gate Array (FPGA) has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and is widely applied to the Field of digital circuit design.
In the process of testing and verifying the circuit logic of the chip through the field programmable gate array, the connection configuration of a test object and an external circuit is often required to be adjusted. Specifically, the test object is used to simulate the function of the chip, and the input/output ports of the test object are connected to the pads, then the pads are connected to the package pins, and then connected to the external circuit through the package pins. In the test modulation process, when an external circuit to which the input/output port of the test object is connected needs to be changed, the connection configuration relationship between the port and the pad in the configuration file needs to be re-burned so as to establish the connection configuration between the port and the pad corresponding to another pin. The disadvantage of this method is that the compilation time of the configuration file is long, so that it takes a lot of time to change the connection relationship between the port and the pad.
Therefore, a solution for quickly establishing the connection configuration between the ports and the pads of the test object of the fpga is needed.
Disclosure of Invention
The application provides a port configuration method of a Field Programmable Gate Array (FPGA), which is used for quickly establishing connection configuration between a port of a test object of the FPGA and a gasket.
In a first aspect, the present application provides a port configuration method for a field programmable gate array FPGA, including: receiving a connection configuration instruction between a first port of a test object and a pad of the FPGA; the test object is constructed through a logic unit in the FPGA; any gasket on the FPGA is connected to an external circuit through a packaged pin; writing the pad code indicated in the connection configuration instruction into a storage address corresponding to the first port in a register; and establishing connection configuration between the first port and the pad corresponding to the pad code according to the pad code in the storage address corresponding to the first port.
In the technical scheme, the connection configuration between the first port of the test object and the pad is established according to the connection configuration instruction, so that when the first port needs to establish connection configuration with other pads, only the connection configuration instruction needs to be changed instead of changing the connection configuration between the first port and the pad by rewriting and burning the configuration file of the FPGA, the operation is convenient, and the time for rewriting and burning the configuration file can be saved.
In one possible design, before receiving a connection configuration instruction between the first port of the test object and the pad of the FPGA, the method further includes: reading a configuration file from the FPGA; the configuration file is burnt with each pad respectively associated with each port of the test object; determining from the configuration file each pad associated with the first port; determining a pad code indicated in the connection configuration instruction from among the pads associated with the first port.
In the technical scheme, the incidence relation between the first port of the test object and the pad is burned in the configuration file and is kept unchanged all the time, when the connection configuration between the first port and the pad is changed, the connection configuration between the first port and the pad can be reestablished only by changing the connection configuration instruction, so that the operation is convenient, and the time for rewriting and burning the configuration file can be saved.
In one possible design, before the writing the pad code indicated in the connection configuration instruction into the memory address corresponding to the first port in the register, the method further includes: and determining the pad code indicated in the connection configuration instruction as at least one of the pads associated with the first port in the configuration file.
In one possible design, the establishing, according to a pad code in a memory address corresponding to the first port, a connection configuration between the first port and a pad corresponding to the pad code includes: and inputting the pad codes in the storage addresses corresponding to the first ports and the pads associated with the first ports into a selector, and establishing connection configuration between the first ports and the pads corresponding to the pad codes through the selector.
In the technical scheme, the connection configuration between the first port and the pad is established through the selector according to the connection configuration instruction, so that the operation is convenient, and the time for rewriting and burning the configuration file can be saved.
In one possible design, the selector has N input bits; m pads related to the first port are provided, wherein N is more than or equal to M; inputting the pad codes in the storage address corresponding to the first port and the pads associated with the first port into a selector, comprising: forming each pad associated with the first port into a first input column of N lengths; wherein each pad associated with the first port in the first input column is set to a first value and each pad not associated with the first port is set to a second value; coding pads in a storage address corresponding to the first port to form N second input columns; the memory address corresponding to the first port is set as a first value when each pad associated with the first port exists in the memory address corresponding to the first port, and the memory address corresponding to the first port does not exist in the memory address corresponding to the first port; inputting the first input column and the second input column to a selector.
In one possible design, the establishing, by the selector, a connection configuration between the first port and a pad corresponding to the pad code includes: performing an AND gate operation on the first input column and the second input column according to bits; and establishing connection configuration between the first port and the gasket corresponding to the gasket code according to the operation result.
In one possible design, the first port is an input-output, INOUT, port; the inputting the first input column and the second input column to a selector, comprising: inputting the first input column, the second input column, and an OE signal to a selector; the OE signal represents the first port as an input port for a first value, and the OE signal represents the first port as an output port for a second value.
In one possible design, the selector is implemented by a programmable logic unit of a field programmable gate array.
In one possible design, the register is a volatile register.
In the technical scheme, the volatile register is convenient to modify, the volatile register can be directly written through the serial communication terminal, data are not stored when the volatile register is powered off, and normal work of the FPGA and use of other personnel cannot be influenced after the FPGA is restarted.
In one possible design, the connection configuration instruction is transmitted to the serial communication interface of the FPGA through a serial port debugging tool.
In the above technical scheme, if the connection configuration between the port and the pad needs to be changed, the selector can reestablish the connection configuration between the port and the pad according to the connection configuration instruction only by transmitting the connection configuration instruction to the FPGA through the serial port debugging tool.
In a second aspect, an embodiment of the present application provides a port configuration device for a field programmable gate array FPGA, including:
the receiving module is used for receiving a connection configuration instruction between a first port of a test object and a pad of the FPGA; the test object is constructed through a logic unit in the FPGA; any pad on the FPGA is connected to an external circuit through a packaged pin;
the control module is used for writing the pad codes indicated in the connection configuration instruction into a storage address corresponding to the first port in a register;
and the connector is used for establishing connection configuration between the first port and the pad corresponding to the pad code according to the pad code in the storage address corresponding to the first port.
In a possible design, before receiving a connection configuration instruction between a first port of a test object and a pad of an FPGA, the control module is further configured to read a configuration file from the FPGA; the configuration file is burnt with each pad respectively associated with each port of the test object; the apparatus further comprises a determining module for determining from the configuration file each gasket associated with the first port; determining a pad code indicated in the connection configuration instruction from each pad associated with the first port.
In a possible design, before writing the pad code indicated in the connection configuration instruction into the memory address corresponding to the first port in the register, the determining module is further configured to determine that the pad code indicated in the connection configuration instruction is at least one of the pads associated with the first port in the configuration file.
In a possible design, the control module is further configured to input, to a selector, a pad code in a storage address corresponding to the first port and each pad associated with the first port, and establish, through the selector, a connection configuration between the first port and the pad corresponding to the pad code.
In one possible design, the selector has N input bits; m pads associated with the first port are provided, and N is greater than or equal to M; the control module is further used for forming each gasket related to the first port into N first input columns in length; wherein each pad associated with the first port in the first input column is set to a first value and each pad not associated with the first port is set to a second value; the control module is further configured to encode pads in the storage address corresponding to the first port to form N second input columns; the memory address corresponding to the first port is set as a first value when each pad associated with the first port exists in the memory address corresponding to the first port, and the memory address corresponding to the first port does not exist in the memory address corresponding to the first port; the control module is further configured to input the first input column and the second input column to a selector.
In one possible design, the selector is further configured to bitwise and-gate the first input column and the second input column; and establishing connection configuration between the first port and the gasket corresponding to the gasket code according to the operation result.
In one possible design, the first port is an input-output, INOUT, port; the control module is further used for inputting the first input column, the second input column and an OE signal to a selector; the OE signal represents the first port as an input port for a first value and the OE signal represents the first port as an output port for a second value.
In one possible design, the selector is implemented by a programmable logic unit of a field programmable gate array.
In one possible design, the register is a volatile register.
In one possible design, the connection configuration instruction is transmitted to the serial communication interface of the FPGA through a serial port debugging tool.
In a third aspect, an embodiment of the present application further provides a computing device, including:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory and executing the method as described in any one of the possible designs of the first aspect according to the obtained program instructions.
In a fourth aspect, the present application further provides a computer-readable storage medium, in which computer-readable instructions are stored, and when the computer-readable instructions are read and executed by a computer, the method described in any one of the possible designs of the first aspect is implemented.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a port configuration method of a field programmable gate array FPGA, which is applicable to the embodiment of the present application;
FIG. 2 is a flowchart illustrating a method for inputting signals to a selector according to an embodiment of the present disclosure;
fig. 3 is a first schematic diagram illustrating an implementation principle of a selector according to an embodiment of the present application;
fig. 4 is a second schematic diagram of an implementation principle of a selector according to an embodiment of the present application;
fig. 5 is a third schematic diagram of an implementation principle of a selector according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a port configuration apparatus of a field programmable gate array according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the embodiments of the present application, a plurality means two or more. The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order.
In the embodiments of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically connected, electrically connected or can communicate with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communication between the two components or interaction relationship of the two components. The specific meaning of the foregoing terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Fig. 1 exemplarily shows a flow chart of a port configuration method of a field programmable gate array FPGA according to an embodiment of the present application, and as shown in fig. 1, the method includes the following steps:
In the embodiment of the application, the test object is constructed by a logic unit in the FPGA, and the test object has at least one port, and the port of the test object is used for inputting or outputting signals. The gasket pad is packaged inside the FPGA, and a port inside the FPGA is led to the outside of the FPGA for packaging, but because a lead is too thin, the pressure of welding cannot be borne, the port needs to be connected to a large metal block firstly, the metal block is used as a support for welding, and the metal block bearing the pressure is the gasket. The pin is a pin which can be seen after being packaged on the FPGA. The pads are in one-to-one relationship with the pins, each pad is connected to one pin, and any pad on the FPGA is connected to an external circuit through a packaged pin. That is, in an FPGA one port of a test object is connected to a selected one or more pads, each pad being connected to a corresponding pin, each pin in turn being connected to an external circuit, which in turn can connect the test object to the external circuit.
The connection configuration instruction is used for indicating which pad or pads in the pads associated with the first port establish connection configuration with the first port, signal transmission can be performed between the first port after the connection configuration is established and the corresponding pads, and the connection configuration instruction can be transmitted to the serial communication interface of the FPGA through a serial port debugging tool.
Before receiving a connection configuration instruction between a first port of a test object and a pad of the FPGA in step 101, it is necessary to read a configuration file from the FPGA, and then determine each pad associated with the first port from the configuration file.
In the embodiment of the application, the configuration file is burned with the pads respectively associated with the ports of the test object. The pads respectively associated with the ports are determined by a tester according to the functions of the ports and the pads expected to be connected by each port in the test process, then the tester writes the association relationship between each port and each pad respectively associated with each port into a configuration file, and then burns the configuration file into the FPGA.
After determining the pads associated with the first port, the pad code indicated in the connection configuration instruction is determined from the pads associated with the first port. The pad code indicated in the connection configuration instruction indicates which pad or pads of the pads with which the first port is specifically associated are conductive.
And 102, writing the pad code indicated in the connection configuration instruction into a storage address corresponding to the first port in the register.
Before writing the pad code indicated in the connection configuration instruction into the memory address corresponding to the first port in the register, the method further includes: determining the pad code indicated in the connection configuration instruction as at least one of the pads associated with the first port in the configuration file.
In the embodiment of the present application, the register may be a volatile register (ROM register). The ROM register is convenient to modify, can be directly written through a serial communication terminal, is a volatile register, and is characterized in that data is not stored when power is down, and normal work of the FPGA and use of other personnel cannot be influenced after restarting.
And 103, establishing connection configuration between the first port and the pad corresponding to the pad code according to the pad code in the storage address corresponding to the first port.
In step 103, when the connection configuration between the first port and the pad corresponding to the pad code is established according to the pad code in the storage address corresponding to the first port, the pad code in the storage address corresponding to the first port and each pad associated with the first port may be input to the selector, and the connection configuration between the first port and the pad corresponding to the pad code may be established through the selector.
In the embodiment of the application, the selector is realized by a programmable logic unit of a field programmable gate array, and each port realizes the connection configuration with the gasket through the selector. Wherein the selector has N input bits. The number of the pads related to the first port is M, and N is larger than or equal to M.
Specifically, the pad codes in the memory address corresponding to the first port and the respective pads associated with the first port may be input to the selector through the method flow shown in fig. 2.
In step 201, the pads associated with the first port are formed into first input columns of N lengths.
Wherein each pad associated with a first port in the first input column is set to a first value and each pad associated with a non-first port is set to a second value. Wherein the first value may be set to 1 and the second value may be set to 0. That is, each input bit of the first input column of the selector may be used to represent a pad associated with the first port, but in practice, the number of pads associated with the first port may be less than N, and thus an input bit set to a first value in the first input column corresponds to a pad associated with the first port, and an input bit set to a second value in the first input column indicates that the input bit does not temporarily correspond to a pad associated with the first port.
It should be noted that the order of the pads associated with the first port and the pads associated with the first port are designed in advance and burned into the configuration file. For example, assume that the selector is an 8-from-1 selector. Example 1: assuming that the port 0001 has an association relationship with the pad a, the pad B, the pad C, and the pad D, the first input column of the selector corresponding to the port 0001 may be 11110000, wherein the first four input bits of the first input column have a value of 1, and may correspond to the pad a, the pad B, the pad C, and the pad D, respectively. The last four input bits of the first input column have a value of 0 and temporarily do not correspond to a pad. Example 2: assuming that the port 0001 has an association relationship with the pad a, the pad F and the pad C, the first input column of the selector corresponding to the port 0001 may be 11100000, wherein the first three input bits of the first input column have a value of 1, and may correspond to the pad a, the pad F and the pad C, respectively. The last five input bits of the first input column have a value of 0 and temporarily do not correspond to a pad.
The first value is set when each pad associated with the first port exists in the memory address corresponding to the first port, and the second value is set when each pad does not exist in the memory address corresponding to the first port. Wherein the first value may be set to 1 and the second value may be set to 0.
For example, assuming that the port 0001 has an association relationship with the pad a, the pad B, the pad C, and the pad D, the first input column input to the selector corresponding to the port 0001 is 11110000. Example 1: the pad code indicated in the connection configuration instruction is 01000000, that is, the second input bit of the second input column has a value of 1, indicating that the current port 0001 needs to establish a connection with the pad B. Example 2: the pad code indicated in the connection configuration command is 11000000, that is, the values of the first input bit and the second input bit of the second input column are both 1, which indicates that the current port 0001 needs to establish a connection with the pad a and the pad B.
When the connection configuration between the first port and the pad corresponding to the pad code is established through the selector, the and gate operation may be performed on the first input column and the second input column in a bitwise manner, and then the connection configuration between the first port and the pad corresponding to the pad code may be established according to the operation result.
For example, assuming that the port 0001 has an association relationship with the pad a, the pad B, the pad C, and the pad D, the first input column input to the selector corresponding to the port 0001 is 11110000, the pad code indicated in the connection configuration instruction is 01000000, the selector performs a bitwise and operation on the first input column and the second input column, and the obtained operation result is 01000000, and the selector performs connection configuration between the port 0001 and the pad B according to the operation result, that is, the port 0001 and the pad B are connected, so that signal transmission between the port 0001 and the pad B is possible.
In addition, each input bit of the second input column can be subjected to an OR gate operation according to bits, the obtained operation result is 0 or 1, and when the operation result is 1, the enable end is indicated to be effective; when the operation result is 0, it indicates that the enable terminal is invalid.
It is understood that the first port may be used as an input port only or an output port only, or as both an input port and an output port. When the first port is an input/output INOUT port, in addition to inputting the first input column and the second input column to the selector, the input/output INOUT port also includes an OE signal indicating whether the first port is currently used as an input port or an output port. Specifically, when the first port is an input/output port, the first input column, the second input column, and an OE signal are input to the selector, the OE signal has a first value and represents the first port as an input port, and the OE signal has a second value and represents the first port as an output port.
Further, the ports may be divided into three different types of bound ports, test ports, and dedicated ports. Binding a port means that the port is in fixed communication with its associated pad or pads without replacing other pads with the port. For the binding port, it is only necessary to directly communicate with the associated pad, and a connection configuration between the port and the pad may not be established through the selector.
The special port is only related to part of the same type of pads on the FPGA, and then the special port establishes connection configuration with one or more associated pads in the same type of pads according to the connection configuration instruction, so that the number of input bits of a selector corresponding to the special port is small, and the calculation amount during establishing the configuration relationship between the port and the pads can be saved. Fig. 3 exemplarily shows an implementation schematic diagram of the selector when the port type is a dedicated port and the port is taken as an input port.
The first column input to the selector in fig. 3 is a 16-length first input column of pads associated with the port, where the first 8 bits in the first input column have a value of 1, indicating that there are 8 pads associated with the port. The second column is an input column with 16 lengths formed by pad coding in the storage address corresponding to the port, wherein the value of the 8 th bit in the second input column is 1, which indicates that the pad corresponding to the 8 th bit is connected to the port. And the selector performs AND gate operation on the first input column and the second input column according to bits, the operation result is 0000000100000000, and the selector establishes the connection configuration between the port and the pad corresponding to the 8 th bit according to the operation result. When a port is used as an input, the direction of transmission of the signal is from the pad to the port.
Fig. 4 exemplarily shows an implementation schematic diagram of the selector when the port type is a dedicated port and the port is an output port. Similar to the implementation principle of the selector when the port is used as the input port, the description of the present application is omitted, and the difference from the port being used as the input port is that the transmission direction of the signal is from the port to the pad.
Fig. 5 exemplarily shows an implementation schematic diagram of the selector when the port type is a dedicated port and the port is an input/output port.
When the port is an input/output port, the selector may be implemented by a combination of the input port and the output port, and OE, DI, and DO 3 signals are introduced for this purpose. When the port is used as an Input port, OE is set to 0, DO is set to 0, DI is set to 1 when OE is set to 0, and then the Input mode is entered, and the transmission direction of signals is from the pad to the port; when the port is used as an Output port, OE is set to 1, and OE is set to 1, DI is set to 0, and then Output mode is entered, wherein the signal is transmitted from the port to the pad.
The test port refers to that the port has a correlation with all pads with test functions on the FPGA, so that the test port needs to select one or more pads from all the pads with test functions according to a connection configuration instruction to establish connection configuration, and the input bit number of a selector corresponding to the test port needs to be greater than or equal to the number of the pads with test functions, so that the calculation amount is large when the connection configuration relationship between the test port and the pads is established, and the number of the test ports can be reduced properly. The implementation principle of the selector corresponding to the test port is similar to that of the selector corresponding to the dedicated port, and details are not repeated in this application again, but the difference is that the number of input bits of the selector corresponding to the test port is large.
The method for configuring the port of the FPGA is characterized in that the connection configuration between the first port of a test object and the pad is established according to a connection configuration instruction, when the first port needs to establish the connection configuration with other pads, only the connection configuration instruction needs to be changed, instead of changing the connection configuration between the first port and the pad by rewriting and burning the configuration file of the FPGA, so that the operation is convenient, and the time for rewriting and burning the configuration file can be saved.
Based on the same technical concept, fig. 6 exemplarily shows a port configuration apparatus of a field programmable gate array FPGA provided by the embodiment of the present application. As shown in fig. 6, the apparatus 600 includes:
a receiving module 601, configured to receive a connection configuration instruction between a first port of a test object and a pad of an FPGA; the test object is constructed through a logic unit in the FPGA; any pad on the FPGA is connected to an external circuit through a packaged pin;
a control module 602, configured to write the pad code indicated in the connection configuration instruction into a storage address corresponding to the first port in a register;
the connector 603 is configured to establish a connection configuration between the first port and a pad corresponding to the pad code according to the pad code in the storage address corresponding to the first port.
In a possible design, before receiving a connection configuration instruction between a first port of a test object and a pad of an FPGA, the control module 602 is further configured to read a configuration file from the FPGA; each pad associated with each port of the test object is burned in the configuration file; the apparatus further comprises a determining module 604 for determining pads associated with the first port from the configuration file; the determining module 604 is further configured to determine, from the pads associated with the first port, the pad code indicated in the connection configuration instruction.
In a possible design, before writing the pad code indicated in the connection configuration instruction into the memory address corresponding to the first port in the register, the determining module 604 is further configured to determine that the pad code indicated in the connection configuration instruction is at least one of the pads associated with the first port in the configuration file.
In a possible design, the control module 602 is further configured to input, to a selector, a pad code in a storage address corresponding to the first port and each pad associated with the first port, and establish, through the selector, a connection configuration between the first port and the pad corresponding to the pad code.
In one possible design, the connector 603 has N input bits; m pads related to the first port are provided, wherein N is more than or equal to M; the control module 602 is further configured to form each pad associated with the first port into N first input columns; wherein each pad associated with the first port in the first input column is set to a first value and each pad not associated with the first port is set to a second value; the control module 602 is further configured to encode pads in a memory address corresponding to the first port to form N second input columns; the memory address corresponding to the first port is set as a first value when each pad associated with the first port exists in the memory address corresponding to the first port, and the memory address corresponding to the first port does not exist in the memory address corresponding to the first port; the control module 602 is further configured to input the first input column and the second input column to a selector.
In one possible design, the connector 603 is further configured to perform a bitwise and operation on the first input column and the second input column; and establishing connection configuration between the first port and the gasket corresponding to the gasket code according to the operation result.
In one possible design, the first port is an input-output, INOUT, port; the control module 602 is further configured to input the first input column, the second input column, and an OE signal to a selector; the OE signal represents the first port as an input port for a first value and the OE signal represents the first port as an output port for a second value.
In one possible design, the connector 603 is implemented by a programmable logic unit of a field programmable gate array.
In one possible design, the register is a volatile register.
In one possible design, the connection configuration instruction is transmitted to the serial communication interface of the FPGA through a serial port debugging tool.
Based on the same technical concept, the embodiment of the present application provides a computing device, as shown in fig. 7, including at least one processor 701 and a memory 702 connected to the at least one processor, where a specific connection medium between the processor 701 and the memory 702 is not limited in this embodiment, and the processor 701 and the memory 702 in fig. 7 are connected through a bus as an example. The bus may be divided into an address bus, a data bus, a control bus, etc.
In this embodiment of the application, the memory 702 stores instructions executable by the at least one processor 701, and the at least one processor 701 may execute the port configuration method of the field programmable gate array FPGA by executing the instructions stored in the memory 702.
The processor 701 is a control center of the computing device, and may connect various parts of the computing device by using various interfaces and lines, and perform resource setting by executing or executing instructions stored in the memory 702 and calling data stored in the memory 702.
Alternatively, the processor 701 may include one or more processing units, and the processor 701 may integrate an application processor, which mainly handles an operating system, a user interface, application programs, and the like, and a modem processor, which mainly handles wireless communication. It will be appreciated that the modem processor described above may not be integrated into the processor 701. In some embodiments, processor 701 and memory 702 may be implemented on the same chip, or in some embodiments, they may be implemented separately on separate chips.
The processor 701 may be a general-purpose processor, such as a Central Processing Unit (CPU), a digital signal processor, an Application Specific Integrated Circuit (ASIC), a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present Application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor.
Based on the same technical concept, embodiments of the present application further provide a computer-readable storage medium, where a computer-executable program is stored, and the computer-executable program is used to enable a computer to execute the port configuration method of the field programmable gate array FPGA listed in any of the above manners.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A port configuration method of a Field Programmable Gate Array (FPGA), which is characterized by comprising the following steps:
receiving a connection configuration instruction between a first port of a test object and a pad of the FPGA; the test object is constructed through a logic unit in the FPGA; any pad on the FPGA is connected to an external circuit through a packaged pin;
writing the pad code indicated in the connection configuration instruction into a storage address corresponding to the first port in a register;
and establishing connection configuration between the first port and the pad corresponding to the pad code according to the pad code in the storage address corresponding to the first port.
2. The method of claim 1, wherein before receiving the connection configuration instruction between the first port of the test object and the pad of the FPGA, the method further comprises:
reading a configuration file from the FPGA; the configuration file is burnt with each pad respectively associated with each port of the test object;
determining from the configuration file each pad associated with the first port;
determining a pad code indicated in the connection configuration instruction from each pad associated with the first port.
3. The method of claim 1, wherein before writing the pad code indicated in the connection configuration instruction into the memory address corresponding to the first port in the register, the method further comprises:
and determining the pad codes indicated in the connection configuration instructions to be at least one of the pads associated with the first port in the configuration file.
4. The method of claim 1, wherein the establishing a connection configuration between the first port and a pad corresponding to the pad code according to the pad code in the memory address corresponding to the first port comprises:
and inputting the pad codes in the storage addresses corresponding to the first ports and the pads associated with the first ports into a selector, and establishing connection configuration between the first ports and the pads corresponding to the pad codes through the selector.
5. The method of claim 4, wherein the selector has N input bits; m pads associated with the first port are provided, and N is greater than or equal to M;
inputting the pad codes in the storage address corresponding to the first port and the pads associated with the first port into a selector, comprising:
forming each pad associated with the first port into a first input column of N lengths; wherein each pad associated with the first port in the first input column is set to a first value and each pad not associated with the first port is set to a second value;
coding pads in a storage address corresponding to the first port to form N second input columns; the memory address corresponding to the first port is not present, and the memory address corresponding to the first port is set as a second value;
inputting the first input column and the second input column to a selector.
6. The method of claim 4, wherein said establishing, by said selector, a connection configuration between said first port and a pad corresponding to said pad code comprises:
performing an AND gate operation on the first input column and the second input column according to bits;
and establishing connection configuration between the first port and the gasket corresponding to the gasket code according to the operation result.
7. The method of claim 5, wherein the first port is an input output, INOUT, port;
the inputting the first input column and the second input column to a selector comprises:
inputting the first input column, the second input column, and an OE signal to a selector; the OE signal represents the first port as an input port for a first value, and the OE signal represents the first port as an output port for a second value.
8. The method of claim 4, wherein the selector is implemented by a programmable logic unit of a field programmable gate array.
9. The method of claim 1, wherein the register is a volatile register.
10. The method of claim 1, wherein the connection configuration instruction is transmitted to the serial communication interface of the FPGA through a serial port debugging tool.
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| CN202211737233.0A CN115879401A (en) | 2022-12-30 | 2022-12-30 | Port configuration method of field programmable gate array |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117873954A (en) * | 2024-01-24 | 2024-04-12 | 上海合见工业软件集团有限公司 | Ultra-large scale cluster FPGA interconnection coding method, electronic equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117873954A (en) * | 2024-01-24 | 2024-04-12 | 上海合见工业软件集团有限公司 | Ultra-large scale cluster FPGA interconnection coding method, electronic equipment and medium |
| CN117873954B (en) * | 2024-01-24 | 2024-08-02 | 上海合见工业软件集团有限公司 | Ultra-large scale cluster FPGA interconnection coding method, electronic equipment and medium |
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