JP2000057121A - Semiconductor integrated circuit device and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the test time by simultaneously testing a semiconductor memory and its other functions such as a peripheral circuit. SOLUTION: When a tester inputs a high level switching control signal FC to a test function switching circuit 6. The circuit 6 connects a timer 3 and a RAM 5 and writes the test data of a register 22 in the RAM 5. After that, the test data of the RAM 5 is read and stored in a register 23, the data of the registers 23 and 22 are compared by a comparator 25 and when a disagreement of test data exists, the comparator 25 outputs a disagreement signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of inspecting the same, and more particularly to a technique effective when applied to shorten the time of probe inspection and screening.

[0002]

2. Description of the Related Art According to studies made by the present inventor, for example, a ROM (Read Only Memory) and a RAM (Random Access Memory) have been proposed.
In a microcomputer incorporating a semiconductor memory such as y), various buses such as an address bus and a data bus are shared with ROM, RAM, and other peripheral circuits. Therefore, when performing an inspection such as a probe inspection or a screening, the RAM and other peripheral circuits such as a ROM are individually performed.

An example of this type of semiconductor integrated circuit device is described in detail in November 30, 1984.
Japan, published by Ohm Co., Ltd., The Institute of Electronics, Information and Communication Engineers (ed.), “LSI Handbook” P541 to P547, and this document includes ROM and RAM (Rando).
m Access Memory) is described.

[0004]

However, it has been found by the present inventors that the above-described inspection techniques for semiconductor integrated circuit devices have the following problems.

That is, with the increase in the memory capacity of the RAM built in the microcomputer, the RA
There is a problem that the test required for M becomes longer and the manufacturing efficiency of the semiconductor integrated circuit device is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device and a test method thereof, which can significantly reduce the test time by simultaneously testing a semiconductor memory and other functions such as peripheral circuits. is there.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit device of the present invention, an address bus for transmitting an address signal, a data bus for transmitting a data signal, and a write enable signal, based on a test signal input when an electrical test is performed. And the read signal line to which the read enable signal is transmitted is separated from the semiconductor memory,
A test function switching unit that outputs a write valid signal when the semiconductor memory writes test data and outputs a read valid signal when reading test data, based on a write valid signal of the test function switching unit. After writing the test data to the semiconductor memory, the test data written to the semiconductor memory is read based on the read signal of the test function switching unit, and the read test data and the test data before being written to the semiconductor memory are read. And a test control means comprising a test function control unit for comparing with a test function.

Further, in the semiconductor integrated circuit device according to the present invention, the test function control section stores a first storage section for storing test data to be written in the semiconductor memory and a test data read from the semiconductor memory. A first comparing unit that compares the second storage unit with the test data stored in the first storage unit and the test data stored in the second storage unit, and outputs a mismatch signal when there is a mismatch; Unit, a counter unit that outputs a timer counter signal obtained by counting up an input clock signal to a semiconductor memory as a test address, and a third storage unit that stores final address data of test data stored in the semiconductor memory When,
The second comparison section compares the counter data counted up by the counter section with the final address data stored in the third storage section, and outputs a match signal when they match.

Furthermore, the semiconductor integrated circuit device of the present invention
The test function control section comprises a timer.

Further, in the semiconductor integrated circuit device according to the present invention, the semiconductor memory comprises a RAM.

Further, according to the method for testing a semiconductor integrated circuit device of the present invention, an address bus connected to a semiconductor memory, a data bus, a read signal line transmitting a read enable signal, and a write signal transmitting a write enable signal are provided. The line is separated, and the electrical inspection of the peripheral circuit is performed while the electrical inspection of the semiconductor memory is performed.

In the method for testing a semiconductor integrated circuit device according to the present invention, the test address input to the semiconductor memory is a timer counter signal counted up by a timer, and the timer counter signal is used as a test address. The address is sequentially designated by inputting the data into the semiconductor memory, and the test data is automatically read or written.

As described above, at the time of probe inspection and screening, electrical inspection of at least one of the peripheral circuit and the processor can be performed while electrical inspection of the built-in semiconductor memory is performed. can do.

Further, the test of the semiconductor memory can be easily performed by automatically writing, reading, and automatically comparing the read results of the test data in the semiconductor memory.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit device provided with a test function switching circuit according to one embodiment of the present invention, and FIG. 2 is provided in the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 3 is a signal timing chart from writing of data to reading of data in the RAM, and FIG. 4A is an inspection in the semiconductor integrated circuit device according to the embodiment of the present invention. Illustration of the process,
(B) is an explanatory diagram of the inspection content in each inspection process, and (c) is an explanatory diagram of the inspection content when a test function switching circuit is used.

In the present embodiment, a semiconductor integrated circuit device which is a single-chip microcomputer includes a peripheral circuit 1, a ROM (peripheral circuit) 2, a timer (test control means, a test function control unit) 3, and a CPU (processor).
4, RAM (semiconductor memory) 5, and test function switching circuit (test control means, test function switching unit) 6
It is constituted by.

The peripheral circuit 1 includes, for example, a DMA
A DMA controller or a serial interface, which is a control circuit for performing (Direct Memory Access) processing. The ROM 2 is a read-only memory, and the ROM 2 is also one of the peripheral circuits.
The timer 3 counts up a timer clock or the like and outputs a timer counter signal.

The RAM 5 is a semiconductor memory capable of reading and writing data, and the test function switching circuit 6 switches the connection destination of the RAM 5 based on the switching control signal FC.

These peripheral circuit 1, ROM 2, timer 3
Are connected to the CPU 4 via a data bus 7 for transmitting data signals, an address bus 8 for transmitting address signals, a write signal line 9 for transmitting a write enable signal, and a read signal line 10 for transmitting a read enable signal. It is connected.

The RAM 5 has a RAM data bus 11 for transmitting data signals in the RAM 5,
The RAM 6 is connected to the test function switching circuit 6 via a RAM address bus 12 for transmitting an address signal in M5, a RAM write signal line 13 for transmitting a write enable signal and a RAM read signal line 14 for transmitting a read enable signal in the RAM 5, respectively. .

The test function switching circuit 6 is connected to a data bus 7, an address bus 8, a write signal line 9, and a read signal line 10. The timer 3 is connected to the test function switching circuit 6 via a RAM write data bus 15, a RAM read data bus 16, a RAM address bus 17, a RAM read / write signal line 18, and control signal lines 19 to 21. ing.

Based on the switching control signal FC input to the test function switching circuit 6, the RAM data bus 11, RAM address bus 12, RAM write signal line 13, and RAM read signal line 14 connected to the RAM 5 are connected. , Data bus 7, address bus 8, write signal line 9, read signal line 10, or any one of RAM write data bus 15, RAM read data bus 16, RAM address bus 17, and RAM read / write signal line 18. The connection destination is switched so that each connection is made.

The timer 3 includes a register (first storage unit) 22, a register (second storage unit) 23, a register (third storage unit) 24, and a comparator (first comparison unit).
25, a comparator (second comparison unit) 26, a timer counter (counter unit) 27, and buffers 28 and 29 provided with control gates.

The registers 22 to 24 store data, and the comparators 25 and 26 compare whether or not the input data matches, and output a mismatch signal NC if they do not match. The timer counter 27 increments and counts up in synchronization with a count clock CC such as a clock signal.

Further, the test function switching circuit 6 includes AND circuits 30, 31, inverters 32, 33, N-channel MOS transistors 34 to 36, and buffers 37 to 44 provided with control gates.

The register 22 is connected to one input of the buffer 37 and the input of the comparator 25 via the RAM write data bus 15.
The other input of the comparator 25 has a buffer 28,
29 are connected to the output unit, and a predetermined external terminal is connected to the output unit of the comparator 25.

A timer counter 27 is connected to the input of the buffer 28, and the input of the buffer 29 is
The register 23 is connected. The count clock CC described above is input to the timer counter 27,
One input of the comparator 26 has a timer counter 2
7 is connected, and the register 24 is connected to the other input section.

The output of the buffer 38 is connected to the register 23 via the RAM read data bus 16, and the input of the buffer 40 is connected to the timer counter 27 via the RAM address bus 17. The output of the comparator 26 is connected to a timer counter 27. The output signal of the comparator 26 is output as a counter clear (coincidence signal) CR, and the timer counter 27 is cleared.

The output section of the buffer 37, the buffer 3
8 and the other connection of the transistor 34
AM data bus 11 is connected, and transistor 3
The data bus 7 is connected to one of the connection portions 4.

The output of the inverter 33 has a buffer 3
Control gate of 9, 41, 44, transistor 3
4 and the control signal line 19 are connected, and the control gate of the buffer 28 is connected to the control signal line 19.

The input portion of the buffer 39 is connected to the address bus 8, and the output portions of the buffers 39 and 40 are connected to the RAM address bus 12. The write signal line 9 is connected to an input portion of the buffer 41.

The RAM write signal line 13 is connected to the outputs of the buffers 41 and 42 and the other connection of the transistor 35. The count clock CC is input to the input portions of the buffers 42 and 43, respectively.

The output of the comparator 26 is connected to a control signal line 21. The control signal line 21 is connected to one input of an AND circuit 31 and the input of an inverter 32. The output of the inverter 32 is connected to one input of the AND circuit 30.

A switching control signal FC set in, for example, a function test is input to the other inputs of the AND circuits 30 and 32, the input of the inverter 33, the control gate of the buffer 40, and the control signal line 20. The control gate of the buffer 29 is connected to the control signal line 20.

The output of the AND circuit 30 is connected to the gate of the transistor 36 and the control gates of the buffers 37 and 42. The output signal of the AND circuit 30 becomes the write valid signal RW, The write enable signal at the time.

The output of the AND circuit 31 is connected to the gate of the transistor 35 and the control gates of the buffers 38 and 42. The output signal of the AND circuit 31 becomes the read valid signal RR, and the test of the RAM 5 The read enable signal at the time. A ground potential, which is a reference potential, is connected to one connection portion of the transistors 35 and 36.

A read signal line 10 is connected to an input section of the buffer 44. Output units of buffers 43 and 44,
The RAM read signal line 14 is connected to the other connection of the transistor 36.

Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS. 1, 2 and 3.

First, in the normal case, the switching control signal FC is at the Lo level, and the AND circuits 30, 31
Output signal WR, read enable signal RR
Are Lo level outputs.

The Lo level signal is also input to the control gates of the buffers 29 and 40, and the buffers are turned off (non-conductive). The control gates of the buffers 28, 39, 41, 44 and the gate of the transistor 34
The Hi-level signal inverted by the inverter 33 is input and is ON (conductive).

Therefore, in the normal state, the RAM 5 is connected to the data bus 7, the address bus 8, the write signal line 9, and the read signal line 10 via the transistor 34 and the buffers 39, 41, 44, respectively. Also in the timer 3, the comparator 25 and the register 23 are not connected, and the timer counter 27 and the comparator 25 are connected via the buffer 28.

FIG. 2 is a timing chart at the time of data writing in the RAM 5. In FIG. 2, the counter data of the timer counter 27 (= the address of the RAM 5), which is the test address, and the write data (= R
AM write data), count clock CC, RAM
5, the write enable signal input to the RAM 5, the RAM data bus 11, the address bus 8 of the ROM 2, the read signal line 10 of the ROM 2, and the signal timing of the RAM data bus 11 of the ROM 2, respectively.

FIG. 3 is a timing chart in the case of switching from data writing to data reading in the RAM 5. In FIG. 3, from the top to the bottom, the counter data of the timer counter 27, which is the test address (= the address of the RAM 5), the write data stored in the register 22 (= the write data of the RAM = the data for the comparison), Data, count clock CC, count clear CR, write enable signal for RAM5, read enable signal for RAM5, RA
The signal timings on the M data bus 11, the mismatch signal NC output from the comparator 25, the address bus 8 of the ROM 2, the read signal line 10 of the ROM 2, and the data bus 7 of the ROM 2 are shown.

Before the test, the RAM is stored in the register 22 in advance.
5, the test data to be written is stored, and the register 24 stores the final address in the RAM 5.

Then, a Hi-level switching control signal FC is input to the test function switching circuit 6 from a tester or the like. When the switching control signal FC becomes high level, the buffers 29 and 40 are turned on (conduction).

The buffer 28 in which the Lo level inverted by the inverter 33 is input to the control gate,
The transistors 39, 41, and 44 are turned off (disconnected), and the transistor 34 is also turned off.

The output section of the AND circuit 30 in which the Hi level has been input to one and the other input sections outputs a Hi level write valid signal RW. The buffers 37 and 42 are turned on by the write valid signal RW, and the transistor 36 is also turned on. Further, the output of the AND circuit 31, that is, the read valid signal RR becomes Lo level.

The RAM 5 receives counter data incremented by the timer counter 27 via the buffer 40 as address data. Also, in the RAM 5,
The test data stored in the register 22 via the buffer 37 and the count clock CC serving as a read enable signal via the buffer 42 are input, and the data is written to the RAM 5.

As shown in FIG. 2, data is written to the RAM 5 until the comparator 26 outputs the Hi-level counter clear CR, that is, the counter data of the timer counter 27 and the final address stored in the register 24. Is done automatically until matches.

As shown in FIG. 3, when the Hi-level counter clear CR is output from the comparator 26, the timer counter 27 is reset, and the write valid signal WR output from the AND circuit 30 is Lo level and logical product. Circuit 3
1, the read valid signal RR, which is the output of the high level, goes high, so that the buffers 37 and 42 and the transistor 36 are turned off.
F, the buffers 38 and 43, and the transistor 35 are turned on.

A count clock CC serving as a write enable signal is input to the RAM 5 via a buffer 43. Further, the counter data incremented by the timer counter 27 is input to the RAM 5 via the buffer 40 as address data.
Outputs the written test data via the buffer 38.

The data output via the buffer 38 is input to the register 23, and the comparator 25 compares the test data stored in the register 23 with the test data stored in the register 22. In some cases, a mismatch signal NC is output.
The mismatch signal NC output from the comparator 25
Is monitored by a tester or the like so that the RAM 5
Can be automatically tested for defects.

At the time of testing the RAM 5, the data bus 7, the address bus 8, the write signal line 9, and the read signal line 1 connected to the peripheral circuit 1, the ROM 2, and the like.
0 becomes unnecessary, and as shown in FIGS.
5, the data bus 7, the address bus 8, the write signal line 9, and the read signal line 10
Test can be performed in parallel with the ROM 2 or the like.

The inspection process of the semiconductor integrated circuit device will be described with reference to the flowchart of the inspection process of FIGS.

In the semiconductor integrated circuit device, FIG.
As shown in FIG. 1A, a probe inspection step and a screening step are included as an inspection step. In the probe inspection, a probe needle is applied to a bonding pad formed on a semiconductor chip, and the electric potential of each semiconductor chip is reduced. Perform a dynamic test. The screening is performed in order to remove a product having a latent defect from the semiconductor integrated circuit device that has become a product.

In these probe tests and screenings, as shown in FIG. 4B, a CPU test for testing the operating characteristics of the CPU, a peripheral circuit test for testing the operating characteristics of the peripheral circuits, and an input / output signal / power supply. DC test for testing DC (direct current) operating characteristics at terminals, AC test for testing dynamic operating characteristics such as propagation delay time between input and output terminals, minimum clock pulse width, and maximum operating frequency, ROM operating characteristics And a RAM test for testing the operating characteristics of the RAM.

In the semiconductor integrated circuit device provided with the test function switching circuit 6, the ROM test and the RAM test can be simultaneously performed in the probe test and the screening as shown in FIG.

Therefore, in each of the probe test and the screening, the ROM test and the RAM test can be performed in parallel, so that the test time can be greatly reduced.

Thus, according to the present embodiment, the test function switching circuit 6 can automatically perform the RAM test and the ROM test in parallel, so that the test time for the probe test and the screening can be greatly reduced. Test efficiency can be improved.

In this embodiment, the ROM test and the RAM test are performed in parallel in each of the probe inspection and the screening, but the RAM test and the peripheral circuit test or the RAM test and the CPU test are simultaneously performed in parallel. By doing so, the test time for probe testing and screening can be significantly reduced,
Test efficiency can be improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0065]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the test control means can perform an electrical test on at least one of the peripheral circuit and the processor while performing an electrical test on the built-in semiconductor memory. The examination time for examination and screening can be greatly reduced.

(2) In the present invention, a timer can be used as a test function control section, so that a low-cost and simple circuit configuration can be achieved.

(3) Further, according to the present invention, the test control means can automatically perform test data writing, reading, and reading result comparison in the semiconductor memory, so that probe testing and screening in the semiconductor memory can be performed. Inspection can be facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit device provided with a test function switching circuit according to an embodiment of the present invention.

FIG. 2 is a signal timing chart when writing data to a RAM provided in the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a signal timing chart from data writing to data reading of a RAM.

4A is an explanatory diagram of an inspection process in a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 4B is an explanatory diagram of inspection contents in each inspection process, and FIG.
FIG. 4 is an explanatory diagram of inspection contents when a test function switching circuit is used.

[Explanation of symbols]

Reference Signs List 1 peripheral circuit 2 ROM (peripheral circuit) 3 timer (test control means, test function control unit) 4 CPU (processor) 5 RAM (semiconductor memory) 6 test function switching circuit (test control means, test function switching unit) 7 data bus Reference Signs List 8 address bus 9 write signal line 10 read signal line 11 RAM data bus 12 RAM address bus 13 RAM write signal line 14 RAM read signal line 15 RAM write data bus 16 RAM read data bus 17 RAM address bus 18 RAM read / write signal line 19 to 21 control signal line 22 register (first storage unit) 23 register (second storage unit) 24 register (third storage unit) 25 comparator (first comparison unit) 26 comparator (second comparison unit) ) 27 Timer counter (counter part) 2 , 29 buffer 30, 31 AND circuits 32, 33 inverter 34 to 36 transistors 37-44 buffer NC mismatch signal CR counter clear (coincidence signal) WR write enable signal RR read enable signal

Continued on the front page (72) Inventor Michihiro Horiuchi 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido F-term in Hitachi Hokkai Semiconductor Co., Ltd. 5B062 CC01 JJ05 5L106 AA01 AA07 DD01

Claims (6)

[Claims] 1. A semiconductor integrated circuit device provided with a semiconductor memory, comprising: an address bus for transmitting an address signal based on a test signal input at the time of performing an electrical test; and a data to which a data signal is transmitted. A bus, a write signal line to which a write enable signal is transmitted, and a read signal line to which a read enable signal is transmitted are separated from the semiconductor memory, and when the semiconductor memory writes test data, a write enable signal is output. A test function switching unit that outputs a read valid signal when reading data; and a test data switching unit that writes test data to the semiconductor memory based on a write valid signal of the test function switching unit. Reading the test data written in the semiconductor memory based on the signal; The semiconductor integrated circuit device, characterized in that with more becomes test control means and the test function control unit for comparing the pre-test data for writing to said test data read out of the semiconductor memory. 2. The semiconductor integrated circuit device according to claim 1, wherein the test function control unit stores a test data to be written into the semiconductor memory, and a test read from the semiconductor memory. A second storage unit for storing data; test data stored in the first storage unit;
A first comparing section that compares the test data stored in the storage section of the first section and outputs a mismatch signal when there is a mismatch, and a timer counter signal obtained by counting up an input clock signal as a test address. A counter unit that outputs to the memory; a third storage unit that stores the final address data of the test data stored in the semiconductor memory; counter data that is counted up by the counter unit; and a third storage unit. A semiconductor integrated circuit device, comprising: a second comparison unit that compares the stored last address data and outputs a match signal when they match. 3. The semiconductor integrated circuit device according to claim 2, wherein said test function control unit is a timer. 4. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor memory is an RA.
M. A semiconductor integrated circuit device. 5. A method for testing a semiconductor integrated circuit device provided with a semiconductor memory, comprising: an address bus connected to the semiconductor memory; a data bus; a read signal line to which a read enable signal is transmitted; and a write enable signal. A test signal of a semiconductor integrated circuit device, wherein a write signal line to which the signal is transmitted is separated, and an electrical test of at least one of a peripheral circuit and a processor is performed while an electrical test of the semiconductor memory is performed. 6. The test method for a semiconductor integrated circuit device according to claim 5, wherein the test address input to the semiconductor memory is a timer counter signal counted up by a timer, and the timer counter signal is used for testing. An inspection method of a semiconductor integrated circuit device, wherein an address is sequentially designated by inputting the address to the semiconductor memory, and test data is automatically read or written.