JP2009260224A - Method of dicing semiconductor wafer, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that easily manufactures the semiconductor device and is excellent in productivity. <P>SOLUTION: The method of manufacturing the semiconductor device includes the processes of: forming an insulating resin layer 12 covering a plurality of projection electrodes 10a on a circuit surface S1; fitting a semiconductor wafer 10 to a dicing frame 14 and a dicing tape 16; dicing the semiconductor wafer 10 and insulating resin layer 12 from the side of the circuit surface S1 of the semiconductor wafer 10 to divide the semiconductor wafer into a plurality of individual semiconductor chips 20; positioning the projection electrode 10a of a semiconductor chip 20 and a circuit electrode on a substrate in a state wherein the picked-up semiconductor chip 20 is held by a positioning head, and then temporarily fixing them; and heating and press-fixing the semiconductor chip 20 and substrate using a connection head to electrically connect the projection electrode 10a of the semiconductor chip 20 to the circuit electrode of the substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer dicing method and a semiconductor device manufacturing method.

  In recent years, with the progress of miniaturization and high functionality of electronic devices, semiconductor devices are required to be miniaturized, thinned, and improved in electrical characteristics (corresponding to high-frequency transmission, etc.). In response to the demand for these semiconductor devices, a conductive protruding electrode called a bump is formed on a semiconductor chip from a conventional method of connecting a semiconductor chip to a substrate by wire bonding, and the protruding electrode and a circuit electrode on the substrate are formed. The transition to the flip chip connection method to connect the devices has begun.

  Known flip-chip connection methods include metal bonding using solder, tin, etc., metal bonding by applying ultrasonic vibration, and method of maintaining mechanical contact using the shrinkage force of the resin. ing. Among these, from the viewpoint of productivity and connection reliability, a method of metal bonding using solder, tin or the like is widely used. In particular, a method using solder is applied to mounting of an MPU (Micro Processing Unit) or the like because it exhibits high connection reliability.

By the way, when a semiconductor chip is mounted on a substrate by a flip chip connection method, there is a problem that thermal stress derived from a difference in thermal expansion coefficient between the semiconductor chip and the substrate is concentrated on the connection portion and the connection portion may be broken. there were. Therefore, in order to disperse the thermal stress and improve the connection reliability, it is necessary to seal and fill the gap formed between the semiconductor chip and the substrate with a resin (for example, see Patent Documents 1 to 5 below). .
JP 2004-349561 A Japanese Patent Laid-Open No. 2000-10082 JP 2003-142529 A JP 2001-332520 A JP 2005-028734 A

  As a method for sealing and filling the resin, generally, after connecting the semiconductor chip and the substrate, a method of injecting a liquid sealing resin into the gap between the semiconductor chip and the substrate using a capillary phenomenon is adopted. Yes. However, since MPU or the like has a large chip, it may be difficult to uniformly fill the liquid resin. In addition, the COF (Chip On Film), which is a package for mounting a liquid crystal driver IC, has a narrow gap between the semiconductor chip and the substrate as the pitch of the circuit electrodes is reduced. Injection may be difficult.

  Therefore, after supplying a resin (paste-like or film-like) for sealing and filling a gap formed between the semiconductor chip and the substrate to the semiconductor chip or the substrate surface in advance, flip-chip connection is performed, thereby making the semiconductor There has been proposed a method for manufacturing a semiconductor device that completes sealing and filling with a resin simultaneously with connection between a chip and a substrate.

  However, when supplying the paste-like resin individually to the semiconductor chip or the substrate, it is necessary to control the coating pattern and the coating amount so as not to contaminate the circuit electrodes other than the connection portion between the semiconductor chip and the substrate. In some cases, it is difficult to control the coating pattern and the coating amount due to changes in the viscosity of the resin over time. On the other hand, when supplying a film-like resin individually to a semiconductor chip or a substrate, a device for attaching a film-like resin to each semiconductor chip or each substrate is required separately, or each semiconductor chip or each substrate On the other hand, since it takes time to attach the film-like resin, the productivity of the semiconductor device may be lowered.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor wafer dicing method and a semiconductor device manufacturing method capable of easily manufacturing a semiconductor device and excellent in productivity.

  The semiconductor wafer dicing method according to the present invention includes a first step of preparing a semiconductor wafer having a plurality of protruding electrodes provided on one main surface, and forming an insulating resin layer on one main surface, A second step of embedding the protruding electrode in the insulating resin layer, and a third step of attaching the dicing tape to the other main surface of the semiconductor wafer and the annular dicing frame so that the semiconductor wafer is fixed to the dicing frame. And a fourth step of dicing into a plurality of semiconductor chips by dicing the semiconductor wafer and the insulating resin layer from one main surface side.

  In the semiconductor wafer dicing method according to the present invention, in the second step, an insulating resin layer covering the plurality of protruding electrodes is formed on one main surface of the semiconductor wafer, and in the fourth step, a plurality of semiconductor wafers are formed. Separated into semiconductor chips. Therefore, it is possible to form a semiconductor chip in which an insulating resin layer is previously disposed on the circuit surface. Therefore, the gap formed between the semiconductor chip and the substrate can be sealed and filled with the resin simply by mounting the semiconductor chip, on which the insulating resin layer is previously arranged on the circuit surface, on the substrate. As a result, there is no need to control the application pattern and application amount of the paste-like resin, or to apply the film-like resin individually to the semiconductor chip or substrate, so that the semiconductor device can be easily manufactured. In addition, productivity can be improved.

  In the semiconductor wafer dicing method according to the present invention, in the fourth step, the semiconductor wafer and the insulating resin layer are diced from one main surface side so that the semiconductor wafer is divided into a plurality of semiconductor chips. . Here, dicing with the circuit surface of the semiconductor wafer facing upward (direction in which the circuit surface of the semiconductor wafer faces the dicing blade or the like) is called “face-up dicing”, and the circuit surface of the semiconductor wafer is directed downward (the circuit surface of the semiconductor wafer). Dicing with the opposite surface facing the dicing blade or the like is referred to as “face-down dicing”.

  Here, when the semiconductor wafer is diced by face-down dicing, the semiconductor wafer is diced with the surface of the insulating resin layer attached to the dicing tape. At this time, the semiconductor wafer is positioned on the soft insulating resin layer, and the semiconductor wafer is liable to be damaged due to vibration during dicing, and the dicing conditions must be precisely controlled.

  However, in the semiconductor wafer dicing method according to the present invention, as described above, since the semiconductor wafer and the insulating resin layer are diced (face-up dicing) from one main surface side of the semiconductor wafer, the semiconductor wafer is diced. As a result, the damage to the semiconductor wafer is reduced as compared to the case of dicing the semiconductor wafer by face-down dicing.

  Preferably, the light transmittance with respect to visible light of the insulating resin layer is 10% or more. If the light transmittance of the insulating resin layer with respect to visible light is less than 10%, it is difficult to recognize the alignment reference mark formed on one main surface of the semiconductor wafer through the insulating resin layer. Tend to be.

  Preferably, in the second step, an insulating resin layer is formed on one main surface by affixing a film having an insulating resin composition on the surface to one main surface, and a plurality of protruding electrodes are formed. Embed in the insulating resin layer.

  Preferably, the insulating resin composition constituting the insulating resin layer contains a polyimide resin, an epoxy resin, and a curing agent.

  On the other hand, in the method for manufacturing a semiconductor device according to the present invention, a first step of preparing a semiconductor wafer provided with a plurality of protruding electrodes on one main surface, and forming an insulating resin layer on one main surface. A second step of embedding a plurality of protruding electrodes in the insulating resin layer, and a step of attaching a dicing tape to the other main surface of the semiconductor wafer and an annular dicing frame so that the semiconductor wafer is fixed to the dicing frame. 3 steps, a fourth step in which the semiconductor wafer and the insulating resin layer are diced from one main surface side so as to be separated into a plurality of semiconductor chips, and a fifth step in which the semiconductor chips are separated from the dicing tape and picked up. And the position of the projecting electrode of the semiconductor chip and the circuit electrode on the substrate in a state where the semiconductor chip picked up in the fifth step is held by the alignment head A sixth step of temporarily fixing the semiconductor chip and the substrate using the alignment head, and connecting the semiconductor chip and the substrate using the connection head or the connection stage set to a temperature higher than the alignment head. And a seventh step of electrically connecting the protruding electrode of the semiconductor chip and the circuit electrode of the substrate by thermocompression bonding.

  In the method for manufacturing a semiconductor device according to the present invention, in the second step, an insulating resin layer covering the plurality of protruding electrodes is formed on one main surface of the semiconductor wafer, and in the fourth step, the semiconductor wafer Separated into semiconductor chips. Therefore, it is possible to form a semiconductor chip in which an insulating resin layer is previously disposed on the circuit surface. Therefore, the gap formed between the semiconductor chip and the substrate can be sealed and filled with the resin simply by mounting the semiconductor chip, on which the insulating resin layer is previously arranged on the circuit surface, on the substrate. As a result, there is no need to control the application pattern and application amount of the paste-like resin, or to apply the film-like resin individually to the semiconductor chip or substrate, so that the semiconductor device can be easily manufactured. In addition, productivity can be improved.

  In the semiconductor device manufacturing method according to the present invention, in the fourth step, the semiconductor wafer and the insulating resin layer are diced from one main surface side so that the semiconductor wafer is divided into a plurality of semiconductor chips. . Therefore, setting of dicing conditions is very easy as compared with the case of semiconductor wafer dicing by face-down dicing. As a result, the productivity can be further improved.

  By the way, when the protruding electrode of the semiconductor chip is Au and the circuit electrode of the substrate is Sn plated copper, the connection temperature is set to Sn and Au in order to metal-bond the protruding electrode of the semiconductor chip and the circuit electrode of the substrate. It is necessary to set the eutectic temperature to 278 ° C. or higher, and to set the temperature of the head or stage of the connection device holding the semiconductor chip to 300 ° C. or higher. However, when the insulating resin layer is heated at such a high temperature, the insulating resin layer is cured while holding the semiconductor chip, that is, before the protruding electrode of the semiconductor chip and the circuit electrode of the substrate are joined. As a result, the semiconductor chip and the substrate may not be well bonded by the insulating resin layer. Here, there is also a connection device capable of pulse heat control that can rapidly raise the temperature, but it is necessary to perform temperature control such as temperature rise and cooling each time the connection is made, and the connection time becomes longer, so productivity is increased. Decreases. For this reason, it is advantageous to improve the productivity to manufacture the semiconductor device in a state where the set temperature of the connection device is kept constant (constant heat).

  Therefore, in the semiconductor device manufacturing method according to the present invention, in the sixth step, the semiconductor chip picked up in the fifth step is held by the alignment head, and the protruding electrode of the semiconductor chip, the circuit electrode on the substrate, The semiconductor chip and the substrate are temporarily fixed using the alignment head, and in the seventh step, the semiconductor chip and the substrate are thermocompression bonded using a connection head having a temperature higher than that of the alignment head. Thus, the protruding electrode of the semiconductor chip and the circuit electrode of the substrate are electrically connected. That is, two heads are used: an alignment head for temporary fixing and a high-temperature connection head for thermocompression bonding of the semiconductor chip and the substrate. Therefore, it is possible to suppress a change in the cured state of the insulating resin layer due to thermal history or the like before the protruding electrode of the semiconductor chip and the circuit electrode of the substrate are joined.

  Preferably, the light transmittance with respect to visible light of the insulating resin layer is 10% or more. If the light transmittance of the insulating resin layer with respect to visible light is less than 10%, it is difficult to recognize the alignment reference mark formed on one main surface of the semiconductor wafer through the insulating resin layer. Tend to be.

  Preferably, foaming does not occur in the insulating resin layer when the temperature at which the semiconductor chip and the substrate are thermally connected is 300 ° C. or higher. In this way, generation of voids due to foaming and reduction in insulation reliability and adhesive strength due to the voids can be suppressed, and the reliability of the obtained semiconductor device can be ensured.

  Preferably, in the second step, an insulating resin layer is formed on one main surface by affixing a film having an insulating resin composition on the surface to one main surface, and a plurality of protruding electrodes are formed. Embed in the insulating resin layer.

  Preferably, the insulating resin composition constituting the insulating resin layer contains a polyimide resin, an epoxy resin, and a curing agent.

  According to the present invention, it is possible to provide a semiconductor wafer dicing method and a semiconductor device manufacturing method capable of easily manufacturing a semiconductor device and excellent in productivity.

  Preferred embodiments of the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted. In the description, the terms “upper” and “lower” may be used, which correspond to the upper and lower directions of the drawing.

  A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, a semiconductor wafer 10 as shown in FIG. 1 is prepared. The semiconductor wafer 10 has a circuit surface (one main surface) S1 and a back surface (the other main surface) S2 which is a surface opposite to the circuit surface S1. A plurality of protruding electrodes 10a protruding from the circuit surface S1 are formed on the circuit surface S1. Note that the thickness of the semiconductor wafer 10 at this time is preferably set to a desired thickness by back grinding the semiconductor wafer 10 in advance, for example, about 100 μm to 550 μm.

  Subsequently, as shown in FIG. 2, an insulating resin layer 12 is formed on the circuit surface S <b> 1 of the semiconductor wafer 10. At this time, the insulating resin layer 12 is formed so that the plurality of protruding electrodes 10a formed on the circuit surface S1 of the semiconductor wafer 10 are embedded in the insulating resin layer 12 (see FIG. 2).

  The insulating resin layer 12 may be formed by applying a resin varnish on the circuit surface S1 of the semiconductor wafer 10 by spin coating, and then drying the resin varnish. The circuit surface S1 of the semiconductor wafer 10 may be formed by printing the resin varnish. It may be formed by drying after being coated on top, or may be formed by bonding a film-like resin to the circuit surface S1 of the semiconductor wafer 10 using a roll laminator or a vacuum laminator. Among these, from the viewpoint of workability, it is preferable to form the insulating resin layer 12 using a film-like resin.

  Here, as the film-like resin, a resin composition capable of forming a film alone may be used, or a resin composition is applied on a support film (not shown) such as a PET film subjected to a release treatment. A dried product may be used. In the case of using a resin composition coated and dried on a support film that has been subjected to a mold release treatment, the resin composition is attached to the circuit surface S1 of the semiconductor wafer 10, and the mold release treatment support film is attached. The insulating resin layer 12 is formed on the circuit surface S1 of the semiconductor wafer 10 by peeling.

  The insulating resin layer 12 is preferably provided with a visible light transmission property so that an alignment reference mark (not shown) formed on the circuit surface S1 of the semiconductor wafer 1 can be recognized. It is desirable to exhibit a transmittance of 10% or more for 555 nm light. When the light transmittance of visible light of the insulating resin layer 12 is less than 10%, the alignment reference mark formed on the circuit surface S1 of the semiconductor wafer 10 can be recognized through the insulating resin layer 12. It tends to be difficult.

  The insulating resin layer 12 is preferably one that does not generate voids under high temperature connection conditions. For example, in COF (Chip On Film), since the connection temperature is 300 ° C. or higher, there is a concern that voids are generated due to resin foaming due to thermal decomposition of the resin. By forming the insulating resin layer 12 using a resin composition that does not occur, voids can be suppressed.

  The insulating resin layer 12 desirably contains a thermosetting component and its curing agent. Examples of the thermosetting component include epoxy resin, bismaleimide resin, polyamide resin, polyimide resin, triazine resin, cyanoacrylate resin, phenol resin, unsaturated polyester resin, melamine resin, urea resin, benzoxazine resin, polyurethane resin, Examples include polyisocyanate resins, furan resins, resorcinol resins, xylene resins, benzoguanamine resins, diallyl phthalate resins, silicone resins, polyvinyl butyral resins, siloxane-modified epoxy resins, siloxane-modified polyamideimide resins, and acrylate resins. From the viewpoint of properties, epoxy resins, benzoxazine resins, siloxane-modified epoxy resins, and siloxane-modified polyamideimide resins. These can be used alone or as a mixture of two or more. Examples of the curing agent include phenol resin, aliphatic amine, alicyclic amine, aromatic polyamine, polyamide, aliphatic acid anhydride, alicyclic acid anhydride, aromatic acid anhydride, dicyandiamide, organic acid dihydrazide, Examples thereof include boron trifluoride amine complexes, imidazoles, tertiary amines, and organic peroxides. These can be used alone or as a mixture of two or more. Particularly preferred from the viewpoint of heat resistance as a combination of a thermosetting component and a curing agent are an epoxy resin and a phenol resin, and an epoxy resin and an imidazole.

  The insulating resin layer 12 may contain a thermoplastic component, for example, polyester resin, polyether resin, polyamide resin, polyamideimide resin, polyimide resin, polyacrylate resin, polyvinyl butyral resin, polyurethane resin, phenoxy resin, Examples thereof include polyacrylate resins, polybutadienes, acrylonitrile butadiene copolymers, acrylonitrile butadiene rubber styrene resins, styrene butadiene copolymers, and acrylic acid copolymers. These can be used alone or in combination of two or more. Among these, a polyimide resin and a phenoxy resin are preferable from the viewpoints of heat resistance and film formability.

  The insulating resin layer 12 may contain an inorganic filler for low thermal expansion, and the filler type, particle size, blending amount, etc. are set so that the transmittance for visible light does not decrease below 10%. Is preferred.

  Furthermore, you may mix | blend additives, such as a hardening accelerator, a silane coupling agent, a titanium coupling agent, antioxidant, a leveling agent, and an ion trap agent, with the insulating resin layer 12. These may be used alone or in combination of two or more. What is necessary is just to adjust about a compounding quantity so that the effect of each additive may express.

  The thickness of the insulating resin layer 12 is preferably such that the insulating resin layer 12 can sufficiently fill a space between the semiconductor chip 20 (described in detail later) and the substrate 26 (described in detail later). Usually, if the thickness of the insulating resin layer 12 corresponds to a value obtained by adding the height of the protruding electrode 10a and the height of the circuit electrode 26a of the substrate 26, the space between the semiconductor chip 20 and the substrate 26 can be filled. is there.

  Subsequently, as shown in FIG. 3, the insulating resin layer 12 is disposed on the circuit surface S <b> 1 of the semiconductor wafer 10 (the protruding electrode 10 a is embedded in the insulating resin layer 12). A dicing tape 16 is attached to the back surface S2 of the semiconductor wafer 10 and the lower edge 14a of the dicing frame 14. Here, the dicing frame 14 is an annular (ring-shaped) metal member, and is used as a fixing jig for the semiconductor wafer 10 when the semiconductor wafer 10 is diced. The dicing frame 14 has an inner diameter larger than the outer shape of the semiconductor wafer 10 and is disposed on the dicing tape 16 so as to surround the semiconductor wafer 10.

  Moreover, the dicing tape 16 has the base film 16a and the adhesion layer 16b formed in the surface of the base film 16a. The dicing tape 16 is not particularly limited as long as the adhesive force of the adhesive layer 16b is reduced by at least one of heating and ultraviolet irradiation so that the adhesive layer 16b can be peeled from the base film 16a. A conventionally well-known thing can be used.

  Subsequently, as shown in FIG. 4, the semiconductor wafer 10 mounted on the dicing frame 14 and the dicing tape 16 is placed on the stage 18 of the dicing apparatus. Next, the dicing pattern formed on the circuit surface S1 of the semiconductor wafer 10 is recognized through the insulating resin layer 12 from the circuit surface S1 side of the semiconductor wafer 10 using a camera or the like. Then, based on the recognized dicing pattern, in the state where the circuit surface S1 of the semiconductor wafer 10 faces upward (the state where the circuit surface S1 of the semiconductor wafer 10 faces the dicing blade DB), by the dicing blade DB, the semiconductor wafer 10 Is diced together with the insulating resin layer 12 (so-called face-up dicing), and is separated into a plurality of semiconductor chips 20.

  Although there is no restriction | limiting in particular as a size of the semiconductor chip 20, For example, in the case of the semiconductor chip for COF, it is made to become a rectangular shape of about 1 mm-2 mm x 10 mm-25 mm. In order to peel the semiconductor chip 20 from the dicing tape 16, the adhesive layer 16b of the dicing tape 16 is cured by irradiating ultraviolet rays from both sides of the circuit surface S1 and the back surface S2, thereby reducing the adhesive strength of the adhesive layer 16b. It is preferable to use a dicing tape 16 that can be formed.

  Subsequently, one of the semiconductor chips 20 is picked up using a pickup device (not shown), and the semiconductor chip 20 is sucked and held by the alignment head 22 as shown in FIG. The semiconductor chip 20 and the substrate 26 placed on the alignment stage 24 are aligned while holding the semiconductor chip 20 by the alignment head 22. The alignment between the semiconductor chip 20 and the substrate 26 is performed using a recognition camera 28 that can recognize both the upper and lower sides at the same time, and an alignment reference mark (not shown) formed on the circuit surface S1 of the semiconductor chip 20. ) Or by recognizing the alignment mark (not shown) or the circuit electrode 26a formed on the circuit surface S3 of the substrate 26 (upward arrow and downward in FIG. 5). (See arrow for.)

  Subsequently, as shown in FIG. 6, the semiconductor chip 20, the insulating resin layer 12, the substrate 26, and the like are heated and pressurized by the alignment head 22 and the alignment stage 24, thereby the surface of the insulating resin layer 12. And the substrate 26 are temporarily fixed. Although the heating temperature at this time will not be restrict | limited especially if the insulating resin layer 12 is the temperature which shows adhesiveness, For example, it can set to about 40 to 100 degreeC.

  Subsequently, as shown in FIG. 7, the semiconductor chip 20 and the substrate 26 are pressure-bonded while the semiconductor chip 20, the insulating resin layer 12, the substrate 26, and the like are heated by the connection head 30 and the connection stage 32. Thus, the gap formed between the semiconductor chip 20 and the substrate 26 by melting the insulating resin layer 12 is sealed and filled with the insulating resin layer 12, while the protruding electrode 10 a of the semiconductor chip 20 and the substrate 26 are The circuit electrode 26a is electrically connected. As a result, a semiconductor device in which the semiconductor chip 20 and the substrate 26 are electrically connected can be obtained. In order to further accelerate the curing of the insulating resin layer 12, a heat treatment may be subsequently performed using a heating oven or the like.

  In the present embodiment as described above, the insulating resin layer 12 covering the plurality of protruding electrodes 10a is formed on the circuit surface S1 of the semiconductor wafer 10, and the semiconductor wafer 10 is separated into a plurality of semiconductor chips 20. Yes. Therefore, it is possible to form the semiconductor chip 20 in which the insulating resin layer 12 is previously disposed on the circuit surface S1. Therefore, the gap formed between the semiconductor chip 20 and the substrate 26 is sealed and filled with the resin only by mounting the semiconductor chip 20 on which the insulating resin layer 12 is previously disposed on the circuit surface S1 on the substrate 26. Will be able to. As a result, it is not necessary to control the application pattern and the application amount of the paste-like resin, or to individually attach the film-like resin to the semiconductor chip 20 or the substrate 26, so that the semiconductor device can be easily manufactured. It is possible to improve productivity.

  In the present embodiment, the semiconductor wafer 10 and the insulating resin layer 12 are diced from the circuit surface S1 side, so that the semiconductor wafer 10 is separated into a plurality of semiconductor chips 20. Therefore, damage to the semiconductor wafer is reduced as compared with the case of dicing the semiconductor wafer 10 by face-down dicing.

  In the present embodiment, the insulating resin layer 12 is formed so that the plurality of protruding electrodes 10 a formed on the circuit surface S <b> 1 of the semiconductor wafer 10 are embedded in the insulating resin layer 12. Therefore, it is possible to save the effort required to cue the protruding electrode 10a, such as sharpening the tip of the protruding electrode 10a or adjusting the thickness of the insulating resin layer 12. As a result, it becomes possible to further improve productivity. In addition, it is possible to ensure electrical connection between the protruding electrode 10a and the circuit electrode 26a by adjusting the fluidity of the insulating resin layer 12 without cueing the protruding electrode 10a.

  By the way, when the protruding electrode 10a of the semiconductor chip 20 is Au and the circuit electrode 26a of the substrate 26 is Sn plated copper, the protruding electrode 10a of the semiconductor chip 20 and the circuit electrode 26a of the substrate 26 are metal-bonded. In addition, it is necessary to set the connection temperature to 278 ° C. or higher, which is the eutectic temperature of Sn and Au, and it is necessary to set the temperature of the head or stage of the connection device holding the semiconductor chip to 300 ° C. or higher. However, when the insulating resin layer 12 is heated at such a high temperature, while the semiconductor chip 20 is held, that is, before the protruding electrode 10a of the semiconductor chip 20 and the circuit electrode 26a of the substrate 26 are joined. The insulating resin layer 12 may be cured, and the semiconductor chip 20 and the substrate 26 may not be adhered to each other by the insulating resin layer 12 in some cases. Here, there is also a connection device capable of pulse heat control that can rapidly raise the temperature, but it is necessary to perform temperature control such as temperature rise and cooling each time the connection is made, and the connection time becomes longer, so productivity is increased. Decreases. For this reason, it is advantageous to improve the productivity to manufacture the semiconductor device in a state where the set temperature of the connection device is kept constant (constant heat).

  Therefore, in the present embodiment, as described above, the protruding electrode 10a of the semiconductor chip 20 and the circuit electrode 26a on the substrate 26 are aligned with the picked-up semiconductor chip 20 held by the alignment head 22. The semiconductor chip 20 and the substrate 26 are temporarily fixed using the alignment head 22, and the semiconductor chip 20 and the substrate 26 are thermocompression bonded using the connection head 30 having a temperature higher than that of the alignment head 22. The 20 protruding electrodes 10a and the circuit electrode 26a of the substrate 26 are electrically connected. That is, two heads are used: an alignment head 22 for temporary fixing and a high-temperature connection head 30 for thermocompression bonding of the semiconductor chip 20 and the substrate 26. Therefore, before the protruding electrode 10a of the semiconductor chip 20 and the circuit electrode 26a of the substrate 26 are joined, it is possible to suppress a change in the cured state of the insulating resin layer 12 due to thermal history or the like.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, in this embodiment, the semiconductor chip 20 and the substrate 26 are temporarily fixed using the alignment head 22, but when the temperature does not need to be set to a high temperature, the alignment head 22 is not used. The picked-up semiconductor chip 20 may be held by the direct connection head 22 and the semiconductor chip 20 and the substrate 26 may be thermocompression bonded.

  The present invention can also be applied to COF. Specifically, after the semiconductor wafer 10 is separated into a plurality of semiconductor chips 20, one of the semiconductor chips 20 is picked up using a pickup device (not shown), and as shown in FIG. The semiconductor chip 20 is mounted on the alignment stage 24 so that the back surface S2 of the chip 20 faces downward, that is, toward the alignment stage 24 side of the alignment apparatus (not shown). Then, alignment between the semiconductor chip 20 and the highly transparent polyimide substrate 34 having the Sn plated wiring 34a formed on the surface S4 is performed.

  The alignment of the semiconductor chip 20 and the polyimide substrate 34 is performed by using the recognition camera 36 capable of recognizing one direction with the polyimide substrate 34 disposed on the circuit surface S1 side of the semiconductor chip 20. An alignment reference mark (not shown) or protruding electrode 10a formed on the circuit surface S1 of the semiconductor chip 20 and the surface S4 of the polyimide substrate 34 from the surface (back surface) S5 side opposite to S4. This is performed by recognizing the alignment reference mark (not shown) or the Sn-plated wiring 34a formed on (see the downward arrow in FIG. 8).

  Subsequently, as shown in FIG. 9, the surface of the insulating resin layer 12 and the polyimide substrate are pressed by pressing the semiconductor chip 20, the insulating resin layer 12, the polyimide substrate 34, and the like by the crimping head 38 and the alignment stage 24. 34 is temporarily fixed. At this time, the pressure bonding head 38 and the alignment stage 24 may be heated. Although the heating temperature will not be restrict | limited especially if the insulating resin layer 12 is the temperature which shows adhesiveness, For example, it can set to about 40 to 100 degreeC.

  Subsequently, as illustrated in FIG. 10, the semiconductor chip 20 and the polyimide substrate 34 are pressure-bonded while the semiconductor chip 20, the insulating resin layer 12, the polyimide substrate 34, and the like are heated by the connection head 30 and the connection stage 32. As a result, the protruding electrode 10a of the semiconductor chip 20 and the polyimide substrate are sealed and filled with the insulating resin layer 12 while the insulating resin layer 12 is melted and the gap formed between the semiconductor chip 20 and the polyimide substrate 34 is sealed. 34 is electrically connected to the Sn plating wiring 34a. As a result, a semiconductor device in which the semiconductor chip 20 and the polyimide substrate 34 are electrically connected can be obtained. In order to further accelerate the curing of the insulating resin layer 12, a heat treatment may be subsequently performed using a heating oven or the like. The above connection method is particularly effective when the polyimide substrate 34 is handled in a reel-to-reel system.

FIG. 1 is a view showing a step of the method of manufacturing a semiconductor device according to this embodiment. FIG. 2 is a diagram showing a step subsequent to FIG. FIG. 3 is a diagram showing a step subsequent to FIG. FIG. 4 is a diagram showing a step subsequent to FIG. FIG. 5 is a diagram showing a step subsequent to FIG. FIG. 6 is a diagram showing a step subsequent to FIG. FIG. 7 is a view showing a step subsequent to FIG. FIG. 8 is a diagram illustrating one process of a method for manufacturing another semiconductor device according to the present embodiment. FIG. 9 is a diagram showing a step subsequent to FIG. FIG. 10 is a diagram showing a step subsequent to FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer, 10a ... Projection electrode, 12 ... Insulating resin layer, 14 ... Dicing frame, 16 ... Dicing tape, 20 ... Semiconductor chip, 22 ... Positioning head, 26 ... Substrate, 26a ... Circuit electrode, 30 ... Connection Head, 36 ... pressure bonding head, S1 ... circuit surface (one main surface), S2 ... back surface (the other main surface).

Claims (9)

A first step of preparing a semiconductor wafer provided with a plurality of protruding electrodes on one main surface;
A second step of forming an insulating resin layer on the one main surface and embedding the plurality of protruding electrodes in the insulating resin layer;
A third step in which a dicing tape is attached to the other main surface of the semiconductor wafer and an annular dicing frame so that the semiconductor wafer is fixed to the dicing frame;
A semiconductor wafer dicing method comprising: a fourth step of dicing the semiconductor wafer and the insulating resin layer into a plurality of semiconductor chips by dicing from the one main surface side.   2. The semiconductor wafer dicing method according to claim 1, wherein the insulating resin layer has a light transmittance of 10% or more with respect to visible light.   In the second step, an insulating resin layer is formed on the one main surface by pasting a film having an insulating resin composition on the surface to the one main surface, and the plurality of protruding electrodes The method for dicing a semiconductor wafer according to claim 1, wherein the semiconductor resin is embedded in the insulating resin layer.   4. The semiconductor wafer dicing according to claim 1, wherein the insulating resin composition constituting the insulating resin layer contains a polyimide resin, an epoxy resin, and a curing agent. 5. Method. A first step of preparing a semiconductor wafer provided with a plurality of protruding electrodes on one main surface;
A second step of forming an insulating resin layer on the one main surface and embedding the plurality of protruding electrodes in the insulating resin layer;
A third step in which a dicing tape is attached to the other main surface of the semiconductor wafer and an annular dicing frame so that the semiconductor wafer is fixed to the dicing frame;
A fourth step of dicing into a plurality of semiconductor chips by dicing the semiconductor wafer and the insulating resin layer from the one main surface side;
A fifth step of separating and picking up the semiconductor chip from the dicing tape;
In a state in which the semiconductor chip picked up in the fifth step is held by the alignment head, the protruding electrode of the semiconductor chip and the circuit electrode on the substrate are aligned, and the semiconductor chip is used by using the alignment head And a sixth step of temporarily fixing the substrate and
The semiconductor chip and the substrate are heated and pressure-bonded using a connection head or a connection stage set to a temperature higher than that of the alignment head, thereby electrically connecting the protruding electrode of the semiconductor chip and the circuit electrode of the substrate. And a seventh step of mechanically connecting the semiconductor device.   6. The method for manufacturing a semiconductor device according to claim 5, wherein the insulating resin layer has a light transmittance of 10% or more with respect to visible light.   7. The semiconductor device according to claim 5, wherein foaming does not occur in the insulating resin layer when a temperature at which the semiconductor chip and the substrate are heated and connected is 300 ° C. or higher. Manufacturing method.   In the second step, an insulating resin layer is formed on the one main surface by pasting a film having an insulating resin composition on the surface to the one main surface, and the plurality of protruding electrodes Embedded in the insulating resin layer. The method of manufacturing a semiconductor device according to claim 5, wherein   The manufacturing method of a semiconductor device according to claim 5, wherein the insulating resin composition constituting the insulating resin layer contains a polyimide resin, an epoxy resin, and a curing agent. Method.

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