JP5136305B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP5136305B2
JP5136305B2 JP2008231246A JP2008231246A JP5136305B2 JP 5136305 B2 JP5136305 B2 JP 5136305B2 JP 2008231246 A JP2008231246 A JP 2008231246A JP 2008231246 A JP2008231246 A JP 2008231246A JP 5136305 B2 JP5136305 B2 JP 5136305B2
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Japan
Prior art keywords
insulating resin
resin layer
semiconductor chip
substrate
semiconductor
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JP2008231246A
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Japanese (ja)
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JP2009260220A (en
Inventor
哲也 榎本
一尊 本田
朗 永井
恵一 畠山
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
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Priority to JP2008231246A priority Critical patent/JP5136305B2/en
Publication of JP2009260220A publication Critical patent/JP2009260220A/en
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Publication of JP5136305B2 publication Critical patent/JP5136305B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of efficiently manufacturing a semiconductor device which has high reliability of connection between a semiconductor chip and a substrate. <P>SOLUTION: The method of manufacturing the semiconductor device includes a coating process of forming an insulating resin layer 3 such that projection electrodes 2 formed on one surface S1 of a semiconductor wafer 1 are embedded, a dicing preparation process of fixing the semiconductor wafer 1 on a dicing tape 5, a dicing process of cutting the semiconductor wafer 1 together with the insulating resin layer 3 to obtain a semiconductor chip 8, a pickup process of picking up the semiconductor chip 8 having the insulating resin layer 3, a position adjusting process of positioning an electrode 12a provided to the surface of a substrate 12 and the projection electrode 2 of the semiconductor chip 8, and a connection process of pressing the semiconductor chip 8 against the substrate 12 and applying heat after the position adjusting process to mount the semiconductor chip 8 on the substrate 12. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device.

近年の電子機器の小型化、高機能化等の進展に伴い、半導体装置に対して小型化及び薄型化が求められ、また高周波伝送への対応などの電気特性の向上も求められている。上記のような要求を満たすため、半導体装置の製造過程のうち、基板上に半導体チップを実装する工程についても種々の検討がなされている。   With recent progress in downsizing and higher functionality of electronic devices, semiconductor devices are required to be reduced in size and thickness, and to improve electrical characteristics such as compatibility with high-frequency transmission. In order to satisfy the above requirements, various studies have been made on the process of mounting a semiconductor chip on a substrate in the process of manufacturing a semiconductor device.

従来、半導体チップを基板上に実装して半導体装置を製造する際、ワイヤーボンディングによって半導体チップを基板に接続する方式が主に採用されていた。しかし、近年、フリップチップ接続方式への移行が始まっている。このフリップチップ接続方式は、半導体チップに形成されたバンプと呼ばれる突起電極と、基板に形成された電極とを直接接続するものである。   Conventionally, when a semiconductor device is manufactured by mounting a semiconductor chip on a substrate, a method of connecting the semiconductor chip to the substrate by wire bonding has been mainly employed. However, in recent years, the transition to the flip chip connection method has begun. In this flip chip connection method, bump electrodes called bumps formed on a semiconductor chip are directly connected to electrodes formed on a substrate.

フリップチップ接続方式としては、はんだやスズなどを用いて金属接合させる方法、超音波振動を用いて金属接合させる方法、樹脂の収縮力を利用して機械的接触を保持する方法などが知られている。これらの方法のなかでも、生産性や接続信頼性の観点から、はんだやスズなどを用いて金属接合させる方法が広く採用されている。はんだを用いて金属接合させる方法は特に高い接続信頼性を示すことから、ＭＰＵ（Ｍｉｃｒｏ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉｔ）などの実装に採用されている。   Known flip-chip connection methods include metal bonding using solder, tin, etc., metal bonding using ultrasonic vibration, and method of maintaining mechanical contact using the shrinkage force of the resin. Yes. Among these methods, from the viewpoint of productivity and connection reliability, a method of metal bonding using solder, tin or the like is widely adopted. Since the method of metal bonding using solder shows particularly high connection reliability, it is adopted for mounting such as MPU (Micro Processing Unit).

フリップチップ接続方式によって基板に半導体チップを実装する場合、外部環境から接続部を保護し且つ外部応力が接続部に集中しないようにするため、通常、半導体チップと基板の間の空隙を樹脂材料で封止充填する。封止充填方法としては、半導体チップを基板に実装した後に、液状の樹脂材料を毛細管現象によって注入して硬化させる方法が知られている（例えば、特許文献１〜３を参照）。また、基板に半導体チップを実装する前に半導体チップ又は基板の表面に予め封止用の樹脂層（接着剤層）を形成し、その後、基板への半導体チップの実装を行う方法も知られている（例えば、特許文献４，５を参照）。
特開２００４−３４９５６１号公報 特開２０００−１００８６２号公報 特開２００３−１４２５２９号公報 特開２００１−３３２５２０号公報 特開２００５−２８７３４号公報 When a semiconductor chip is mounted on a substrate by a flip chip connection method, the gap between the semiconductor chip and the substrate is usually made of a resin material in order to protect the connection portion from the external environment and prevent external stress from concentrating on the connection portion. Seal and fill. As a sealing and filling method, there is known a method in which after a semiconductor chip is mounted on a substrate, a liquid resin material is injected and cured by a capillary phenomenon (see, for example, Patent Documents 1 to 3). Also known is a method of forming a sealing resin layer (adhesive layer) on the surface of the semiconductor chip or the substrate in advance before mounting the semiconductor chip on the substrate, and then mounting the semiconductor chip on the substrate. (For example, see Patent Documents 4 and 5).
JP 2004-349561 A Japanese Patent Laid-Open No. 2000-10082 JP 2003-142529 A JP 2001-332520 A JP 2005-28734 A

ところで、基板に実装する半導体チップがＭＰＵなどの比較的大型のものである場合、半導体チップを基板に実装した後、毛細管現象を利用して樹脂材料を空隙に注入しても、接続部に気泡が残存しやすく、効率的に充填作業を行うことが困難であった。このため、半導体装置の生産性が低下するという問題があった。   By the way, when the semiconductor chip to be mounted on the substrate is a relatively large one such as an MPU, even after the semiconductor chip is mounted on the substrate, even if the resin material is injected into the gap using the capillary phenomenon, the connection portion has no bubbles. Remained easily and it was difficult to perform the filling operation efficiently. For this reason, there has been a problem that productivity of the semiconductor device is lowered.

また、基板に半導体チップを実装する前に半導体チップ又は基板の表面に予め封止用の樹脂層を形成した場合、基板に半導体チップを接続する工程に至るまでに熱などによって樹脂層の性質（溶融粘度など）が変化してしまい、接続不良が発生する恐れがある。   Further, when a sealing resin layer is formed in advance on the surface of the semiconductor chip or the substrate before mounting the semiconductor chip on the substrate, the properties of the resin layer (such as heat) before the process of connecting the semiconductor chip to the substrate ( The melt viscosity and the like may change, resulting in poor connection.

本発明は、上記事情に鑑みてなされたものであり、半導体チップと基板との高い接続信頼性を有する半導体装置を効率的に製造できる方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and an object thereof is to provide a method capable of efficiently manufacturing a semiconductor device having high connection reliability between a semiconductor chip and a substrate.

本発明に係る半導体装置の製造方法は、半導体ウェハの一方面に形成された複数の突起電極を埋め込むように、当該一方面上に絶縁性樹脂層を形成する被覆工程と、半導体ウェハの他方面とダイシングテープとを貼り合わせ、ダイシングテープを介して半導体ウェハをダイシング装置のステージ上に固定するダイシング準備工程と、絶縁性樹脂層側から半導体ウェハを絶縁性樹脂層とともに切断し、一方面上に突起電極を有し且つ切断された絶縁性樹脂層によって当該一方面が被覆された半導体チップを得るダイシング工程と、ステージ上の半導体チップを当該切断された絶縁性樹脂層とともにピックアップするピックアップ工程と、半導体チップを実装すべき基板に対し、当該切断された絶縁性樹脂層側を向けて半導体チップを保持しながら、当該基板の表面に設けられた電極と半導体チップの突起電極との位置を合わせる位置調整工程と、位置調整工程後、半導体チップを当該基板に押し当てるとともに熱を加えることによって、半導体チップを当該基板に実装する接続工程とを備える。   A method for manufacturing a semiconductor device according to the present invention includes a covering step of forming an insulating resin layer on one surface so as to embed a plurality of protruding electrodes formed on one surface of a semiconductor wafer, and the other surface of the semiconductor wafer. And a dicing preparation process for fixing the semiconductor wafer on the stage of the dicing apparatus via the dicing tape, and cutting the semiconductor wafer together with the insulating resin layer from the insulating resin layer side, A dicing step for obtaining a semiconductor chip having a protruding electrode and having the one surface coated with the cut insulating resin layer; and a pickup step for picking up the semiconductor chip on the stage together with the cut insulating resin layer; Holding the semiconductor chip with the cut insulating resin layer side facing the substrate on which the semiconductor chip is to be mounted A position adjusting step for aligning the position of the electrode provided on the surface of the substrate and the protruding electrode of the semiconductor chip; and after the position adjusting step, the semiconductor chip is pressed against the substrate and heated to thereby apply the semiconductor chip And a connecting step for mounting on a substrate.

本発明によれば、半導体ウェハの一方面を絶縁性樹脂層で被覆した後、半導体ウェハをダイシングすることによって、絶縁性樹脂層を一方面上に有する複数の半導体チップが一括して得られる。このため、接続工程後に毛細管現象を利用して充填する場合や個片化された半導体チップの表面に後から個別に絶縁性接着剤層を形成する場合と比較し、半導体装置の生産性を向上できる。   According to the present invention, after coating one surface of a semiconductor wafer with an insulating resin layer, the semiconductor wafer is diced to collectively obtain a plurality of semiconductor chips having the insulating resin layer on the one surface. For this reason, the productivity of semiconductor devices is improved compared to the case where the capillarity is used for filling after the connection process and the case where an insulating adhesive layer is individually formed on the surface of the separated semiconductor chip later. it can.

また、本発明によれば、位置調整工程を実施した後、接続工程を実施するため、接続工程の前に絶縁性樹脂層の性質が熱によって変化することを十分に抑制できる。したがって、絶縁性樹脂層が接続工程において十分に性能を発揮でき、良好な接続が可能となり、接続信頼性が高い半導体装置を製造できる。   Moreover, according to this invention, after implementing a position adjustment process, since a connection process is implemented, it can fully suppress that the property of an insulating resin layer changes with a heat | fever before a connection process. Therefore, the insulating resin layer can sufficiently exhibit performance in the connection step, enables good connection, and manufactures a semiconductor device with high connection reliability.

本発明に係る半導体装置の製造方法は、位置調整工程後であり且つ接続工程前に、半導体チップを基板上に仮固定する接続準備工程を更に備えることが好ましい。接続工程に先立ち、半導体チップを基板上の所定の位置に仮固定しておくと、仮固定後に基板、絶縁性樹脂層及び半導体チップからなる積層体を圧着装置へと移送できる。例えば、圧着装置に上記積層体を連続的に搬送し、搬送される積層体と基板とを連続的に接続すれば、半導体装置をより一層効率的に製造できる。   The method for manufacturing a semiconductor device according to the present invention preferably further includes a connection preparation step of temporarily fixing the semiconductor chip on the substrate after the position adjustment step and before the connection step. If the semiconductor chip is temporarily fixed at a predetermined position on the substrate prior to the connecting step, the laminated body including the substrate, the insulating resin layer, and the semiconductor chip can be transferred to the crimping apparatus after the temporary fixing. For example, the semiconductor device can be manufactured more efficiently if the laminate is continuously conveyed to the crimping apparatus and the conveyed laminate and the substrate are continuously connected.

本発明においては、絶縁性樹脂層は可視光透過率が１０％以上であることが好ましい。かかる構成を採用することにより、ダイシング工程において、切断すべき箇所を把握しやすいという利点がある。これに加え、位置調整工程において突起電極の位置の確認を通常の可視光カメラ等で行うことができる。   In the present invention, the insulating resin layer preferably has a visible light transmittance of 10% or more. By adopting such a configuration, there is an advantage that it is easy to grasp a portion to be cut in the dicing process. In addition, the position of the protruding electrode can be confirmed with a normal visible light camera or the like in the position adjusting step.

被覆工程において、絶縁性樹脂組成物からなるフィルムを半導体ウェハの一方面上に貼り合わせることによって、絶縁性樹脂層を形成することが好ましい。絶縁性樹脂層は、基板又は半導体チップの表面に絶縁性樹脂組成物を塗工して形成してもよいが、予めフィルム状に成形されたものを使用すれば、作業効率を一層向上できる。   In the covering step, it is preferable to form the insulating resin layer by bonding a film made of the insulating resin composition onto one surface of the semiconductor wafer. The insulating resin layer may be formed by coating an insulating resin composition on the surface of a substrate or a semiconductor chip, but if a film formed in advance is used, the working efficiency can be further improved.

更に、絶縁性樹脂層は、３００℃以上の温度で接続を行っても樹脂発泡が生じない絶縁性樹脂組成物からなることが好ましい。接続工程後において接続部に残存する気泡は、半導体装置の接続信頼性を低下させる一因となる。従って、上記要件を満たす絶縁性樹脂組成物を使用することによって、半導体装置の接続信頼性をより一層向上できる。   Furthermore, the insulating resin layer is preferably made of an insulating resin composition that does not cause foaming of the resin even when connected at a temperature of 300 ° C. or higher. Bubbles remaining in the connection portion after the connection process contribute to a decrease in connection reliability of the semiconductor device. Therefore, the connection reliability of the semiconductor device can be further improved by using an insulating resin composition that satisfies the above requirements.

また、絶縁性樹脂層は、ポリイミド樹脂とエポキシ樹脂と硬化剤とを含有することが好ましい。これらの成分を含有せしめることにより、絶縁性樹脂層の高い耐熱性を達成できるとともに、接続工程において絶縁性樹脂層を熱硬化させることができる。   The insulating resin layer preferably contains a polyimide resin, an epoxy resin, and a curing agent. By containing these components, the high heat resistance of the insulating resin layer can be achieved, and the insulating resin layer can be thermally cured in the connecting step.

本発明によれば、半導体チップと基板との高い接続信頼性を有する半導体装置を効率的に製造できる。   According to the present invention, a semiconductor device having high connection reliability between a semiconductor chip and a substrate can be efficiently manufactured.

以下、添付図面を参照しながら本発明の実施形態を詳細に説明する。なお、図面の説明において、同一の要素には同一の符号を付し、重複する説明を省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

＜第１実施形態＞
図１〜図７を参照しながら、第１実施形態に係る半導体装置の製造方法について説明する。 <First Embodiment>
A method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS.

まず、図１に示されるような半導体ウェハ１を用意する。半導体ウェハ１は、半導体プロセスにより回路が形成された回路面（一方面）Ｓ１と、回路面Ｓ１の反対側の面である裏面（他方面）Ｓ２とを有する。半導体ウェハ１の回路面Ｓ１には、回路面Ｓ１から突出する複数の突起電極２及びダイシングパターン（図示せず）が形成される。   First, a semiconductor wafer 1 as shown in FIG. 1 is prepared. The semiconductor wafer 1 has a circuit surface (one surface) S1 on which a circuit is formed by a semiconductor process, and a back surface (other surface) S2 that is a surface opposite to the circuit surface S1. A plurality of protruding electrodes 2 and a dicing pattern (not shown) protruding from the circuit surface S1 are formed on the circuit surface S1 of the semiconductor wafer 1.

半導体ウェハ１の厚さは５０〜６００μｍであることが好ましく、５０〜５５０μｍであることがより好ましく、５０〜４００μｍであることが更に好ましい。半導体ウェハ１の厚さが５０μｍ未満であると、半導体ウェハ１の破損が生じやすく、他方、６００μｍを超えると、薄型の半導体装置を製造しにくくなる。また、突起電極２の高さ（図１に示すｔ２）は、１〜２００μｍであることが好ましく、１〜１００μｍであることがより好ましい。 The thickness of the semiconductor wafer 1 is preferably 50 to 600 μm, more preferably 50 to 550 μm, and still more preferably 50 to 400 μm. If the thickness of the semiconductor wafer 1 is less than 50 μm, the semiconductor wafer 1 is likely to be damaged. On the other hand, if it exceeds 600 μm, it is difficult to manufacture a thin semiconductor device. The height of the projecting electrode 2 (t 2 shown in FIG. 1) is preferably 1 to 200 [mu] m, and more preferably 1 to 100 [mu] m.

半導体ウェハ１の材質としては、例えばシリコン、ガリウム砒素が挙げられる。突起電極２の材質としては、金、銀、銅、ニッケル、インジウム、パラジウム、スズ、鉛、ビスマスなどが挙げられる。突起電極２は、上記材質のうち単一の金属で構成されてもよいし、二種以上の金属で構成されてもよい。突起電極２は、組成の異なる金属層が積層されたものであってもよい。   Examples of the material of the semiconductor wafer 1 include silicon and gallium arsenide. Examples of the material of the protruding electrode 2 include gold, silver, copper, nickel, indium, palladium, tin, lead, and bismuth. The protruding electrode 2 may be composed of a single metal among the above materials, or may be composed of two or more kinds of metals. The protruding electrode 2 may be a laminate of metal layers having different compositions.

次に、図２に示すように、半導体ウェハ１の回路面Ｓ１に形成された複数の突起電極２を埋め込むように、回路面Ｓ１上に絶縁性樹脂層３を形成する（被覆工程）。絶縁性樹脂層３を形成する絶縁性樹脂組成物は、高い耐熱性を有するとともに、熱硬化性を有するものが好ましい。絶縁性樹脂組成物については後で詳細に説明する。   Next, as shown in FIG. 2, an insulating resin layer 3 is formed on the circuit surface S1 so as to embed a plurality of protruding electrodes 2 formed on the circuit surface S1 of the semiconductor wafer 1 (covering step). The insulating resin composition forming the insulating resin layer 3 preferably has high heat resistance and thermosetting properties. The insulating resin composition will be described in detail later.

絶縁性樹脂層３の形成方法として、スピンコートや印刷法などにより絶縁性樹脂組成物を含有する塗工液を回路面Ｓ１にスピンコート又は印刷法によって塗布した後、乾燥する方法、あるいは、フィルム状に形成された絶縁性樹脂組成物を半導体ウェハ１の回路面Ｓ１上に貼り合わせる方法（ラミネート法）が挙げられる。作業性の観点から、ラミネート法を採用することが好ましい。ラミネート法はロール式ラミネータや真空式ラミネータ等を用いて実施できる。   As a method for forming the insulating resin layer 3, a method of applying a coating liquid containing an insulating resin composition to the circuit surface S1 by spin coating or printing by spin coating or printing, and then drying, or a film A method of laminating the insulating resin composition formed in a shape on the circuit surface S1 of the semiconductor wafer 1 (laminating method) is mentioned. From the viewpoint of workability, it is preferable to employ a laminating method. The laminating method can be performed using a roll laminator, a vacuum laminator, or the like.

絶縁性樹脂層３の厚さは、絶縁性樹脂層３が半導体チップ８と実装すべき基板１２（図５を参照）との間を充分に充填できる厚さであることが好ましい。通常、絶縁性樹脂層３の厚さ（図２に示すｔ３）が、突起電極２（図１に示すｔ２）の高さと基板１２の電極１２ａの高さ（図５に示すｔ１２ａ）の合計に相当するものであれば、半導体チップ８と基板１２との間の空隙を絶縁性樹脂組成物で十分に充填できる。具体的には、絶縁性樹脂層３の厚さは５μｍ以上であることが好ましく、１０μｍ以上であることがより好ましい。なお、絶縁性樹脂層３の厚さが５μｍ未満であると、ラミネート法によって絶縁性樹脂層３を形成することが困難となる傾向があり、ラミネート法によって形成される絶縁性樹脂層３に皺や気泡が生じやすくなる。 The thickness of the insulating resin layer 3 is preferably such that the insulating resin layer 3 can sufficiently fill the space between the semiconductor chip 8 and the substrate 12 to be mounted (see FIG. 5). Usually, the thickness of the insulating resin layer 3 (t 3 shown in FIG. 2) is such that the height of the protruding electrode 2 (t 2 shown in FIG. 1) and the height of the electrode 12a of the substrate 12 (t 12a shown in FIG. 5). As long as it corresponds to the sum of the above, the gap between the semiconductor chip 8 and the substrate 12 can be sufficiently filled with the insulating resin composition. Specifically, the thickness of the insulating resin layer 3 is preferably 5 μm or more, and more preferably 10 μm or more. If the thickness of the insulating resin layer 3 is less than 5 μm, it tends to be difficult to form the insulating resin layer 3 by the laminating method. And bubbles are likely to occur.

また、絶縁性樹脂層３は、可視光透過率が１０％以上であることが好ましく、１５％以上であることがより好ましく、２０％以上であることが更に好ましい。可視光透過率が上記範囲となるように絶縁性樹脂層３の組成及び厚さを調整することにより、後段のダイシング工程において、切断すべき箇所を把握しやすいという利点がある。また、更に後段の位置調整工程において突起電極２の位置の確認を通常の可視光カメラ等で行うことができる。ここでいう「可視光透過率」は、市販の分光光度計を用いて測定可能であり、波長５５５ｎｍの光の透過率を測定して得られる値を意味する。   The insulating resin layer 3 preferably has a visible light transmittance of 10% or more, more preferably 15% or more, and still more preferably 20% or more. By adjusting the composition and thickness of the insulating resin layer 3 so that the visible light transmittance is in the above range, there is an advantage that it is easy to grasp the portion to be cut in the subsequent dicing process. Further, the position of the protruding electrode 2 can be confirmed with a normal visible light camera or the like in a subsequent position adjustment step. "Visible light transmittance" here is measurable with a commercially available spectrophotometer and means a value obtained by measuring the transmittance of light having a wavelength of 555 nm.

次に、図３に示すように、半導体ウェハ１の裏面Ｓ２及びウェハリング４の下縁４ａにダイシングテープ５を貼り付ける。このダイシングテープ５を介して、半導体ウェハ１の回路面Ｓ１が上方を向いた状態で、ダイシング装置のステージ６上に半導体ウェハ１を固定する（ダイシング準備工程）。   Next, as shown in FIG. 3, a dicing tape 5 is attached to the back surface S <b> 2 of the semiconductor wafer 1 and the lower edge 4 a of the wafer ring 4. The semiconductor wafer 1 is fixed on the stage 6 of the dicing apparatus with the circuit surface S1 of the semiconductor wafer 1 facing upward via the dicing tape 5 (dicing preparation step).

ウェハリング４は、リング状の金属製部材であり、半導体ウェハ１のダイシング時における半導体ウェハ１の固定治具として機能する。ウェハリング４は、その内径が半導体ウェハ１の外形より大きくなっており、半導体ウェハ１を囲むようにダイシングテープ５上に配置される。   The wafer ring 4 is a ring-shaped metal member and functions as a fixing jig for the semiconductor wafer 1 when the semiconductor wafer 1 is diced. The wafer ring 4 has an inner diameter larger than the outer shape of the semiconductor wafer 1 and is disposed on the dicing tape 5 so as to surround the semiconductor wafer 1.

ダイシングテープ５は、基材フィルム５ａと、基材フィルム５ａの表面に形成された粘着層５ｂを有する。ダイシングテープ５としては、加熱及び紫外線照射の少なくとも一方によって、粘着層５ｂの粘着力が低下するものを使用することが好ましい。   The dicing tape 5 has a base film 5a and an adhesive layer 5b formed on the surface of the base film 5a. As the dicing tape 5, it is preferable to use a tape whose adhesive strength of the adhesive layer 5b is reduced by at least one of heating and ultraviolet irradiation.

続いて、半導体ウェハ１の回路面Ｓ１に形成されたダイシングパターン（図示せず）を、絶縁性樹脂層３を通して認識した後、図４に示されるように、ダイシングブレード７によって、絶縁性樹脂層３の上面Ｓ３側から半導体ウェハ１を絶縁性樹脂層３とともに切断する（ダイシング工程）。これにより、切断された半導体ウェハ１と、その回路面Ｓ１に設けられた突起電極２とを有する複数の半導体チップ８が得られる。半導体チップ８は、切断された絶縁性樹脂層３によって回路面Ｓ１が被覆されている。半導体チップ８のサイズは、用途や要求性能に応じて適宜設定すればよい。例えば、ＣＯＦで使用される半導体チップは、通常、ダイシング工程によって横１〜２ｍｍ、縦１０〜２０ｍｍの矩形に切断されたものである。   Subsequently, after a dicing pattern (not shown) formed on the circuit surface S1 of the semiconductor wafer 1 is recognized through the insulating resin layer 3, as shown in FIG. The semiconductor wafer 1 is cut together with the insulating resin layer 3 from the upper surface S3 side of the substrate 3 (dicing step). Thereby, the several semiconductor chip 8 which has the cut | disconnected semiconductor wafer 1 and the protruding electrode 2 provided in the circuit surface S1 is obtained. The semiconductor chip 8 is covered with the circuit surface S <b> 1 by the cut insulating resin layer 3. The size of the semiconductor chip 8 may be set as appropriate according to the application and required performance. For example, a semiconductor chip used in COF is usually cut into a rectangle having a width of 1 to 2 mm and a length of 10 to 20 mm by a dicing process.

ダイシング工程の終了後、ピックアップ装置（図示せず）を用いて半導体チップ８をピックアップする（ピックアップ工程）。半導体チップ８をピックアップする前に、粘着層５ｂに対して加熱又は紫外線照射を行うことによって、その粘着力を低下させることが好ましい。   After completion of the dicing process, the semiconductor chip 8 is picked up using a pickup device (not shown) (pickup process). Before picking up the semiconductor chip 8, it is preferable to reduce the adhesive force by heating or irradiating the adhesive layer 5b.

次に、図５に示すように、圧着ヘッド３０ａ及びステージ３０ｂを有する圧着装置３０と、可視光カメラ１３とを使用し、基板１２の電極１２ａと、半導体チップ８の突起電極２との位置合わせを行う（位置調整工程）。まず、ピックアップされた半導体チップ８の裏面Ｓ２を圧着ヘッド３０ａに吸着させる。他方、電極１２ａが形成された面を上方に向けた状態で基板１２をステージ３０ｂ上に載置する。続いて、半導体チップ８の回路面Ｓ１に形成されている位置合わせ用基準マーク（図示せず）を、絶縁性樹脂層３を通して可視光カメラ１３で認識するとともに、基板１２の電極１２ａが形成された一方面Ｓ４上の位置合わせ用基準マーク（図示せず）を可視光カメラ１３で認識することによって位置合わせを行う。   Next, as shown in FIG. 5, using the crimping device 30 having the crimping head 30 a and the stage 30 b and the visible light camera 13, the alignment between the electrode 12 a of the substrate 12 and the protruding electrode 2 of the semiconductor chip 8 is performed. (Position adjustment process). First, the back surface S2 of the picked-up semiconductor chip 8 is attracted to the crimping head 30a. On the other hand, the substrate 12 is placed on the stage 30b with the surface on which the electrode 12a is formed facing upward. Subsequently, an alignment reference mark (not shown) formed on the circuit surface S1 of the semiconductor chip 8 is recognized by the visible light camera 13 through the insulating resin layer 3, and the electrode 12a of the substrate 12 is formed. The alignment is performed by recognizing the alignment reference mark (not shown) on the other surface S4 with the visible light camera 13.

位置調整工程後、図６に示すように、圧着装置３０を使用し、半導体チップ８を基板１２に押し当てるとともに熱を加えることによって、半導体チップ８を基板１２に実装する（接続工程）。圧着装置３０の圧着ヘッド３０ａ及びステージ３０ｂは、いずれもヒータが内蔵されており、表面の温度を所望の温度にそれぞれ設定できるようになっている。   After the position adjustment process, as shown in FIG. 6, the semiconductor chip 8 is mounted on the substrate 12 by pressing the semiconductor chip 8 against the substrate 12 and applying heat using the crimping device 30 (connection process). Each of the pressure bonding head 30a and the stage 30b of the pressure bonding apparatus 30 has a built-in heater so that the surface temperature can be set to a desired temperature.

圧着装置３０の圧着ヘッド３０ａ及びステージ３０ｂの温度は、接続不良を防止するために、突起電極２と電極１２ａの間に樹脂が残存しないように絶縁性樹脂層３が十分流動する温度に設定することが好ましい。また、突起電極２と電極１２ａの間に共晶を形成させて接続する場合、絶縁性樹脂層３が十分に流動する温度かつ接続部の温度が突起電極２の材質及び電極１２ａの材質の共晶温度を超えるような温度に設定することが好ましい。例えば、突起電極２が金めっきによって形成され、他方、電極１２ａがスズめっきで形成される場合、金とスズとの共晶温度（２７８℃）を超えるように接続部を加熱することが好ましい。例えば、圧着ヘッド３０ａを３００〜５００℃、ステージ３０ｂを５０〜１５０℃に設定することが好ましい。加熱時間を０．５〜１０秒とすることが好ましい。   The temperature of the pressure bonding head 30a and the stage 30b of the pressure bonding apparatus 30 is set to a temperature at which the insulating resin layer 3 flows sufficiently so that no resin remains between the protruding electrode 2 and the electrode 12a in order to prevent poor connection. It is preferable. When the eutectic is formed and connected between the protruding electrode 2 and the electrode 12a, the temperature at which the insulating resin layer 3 flows sufficiently and the temperature of the connecting portion is the same as the material of the protruding electrode 2 and the material of the electrode 12a. It is preferable to set the temperature to exceed the crystallization temperature. For example, when the protruding electrode 2 is formed by gold plating and the electrode 12a is formed by tin plating, it is preferable to heat the connecting portion so as to exceed the eutectic temperature of gold and tin (278 ° C.). For example, it is preferable to set the pressure-bonding head 30a to 300 to 500 ° C and the stage 30b to 50 to 150 ° C. The heating time is preferably 0.5 to 10 seconds.

接続工程によって、半導体チップ８の突起電極２と、基板１２の電極１２ａとを電気的に接続する。また、半導体チップ８と基板１２との間に介在する絶縁性樹脂層３の硬化物３ａによって半導体チップ８と基板１２とを接着する。これにより、図７に示すような半導体装置２０が製造される。引き続き、絶縁性樹脂層３の硬化を更に進行させるために、加熱オーブンなどを用いて加熱処理を行ってもよい。   Through the connecting step, the protruding electrode 2 of the semiconductor chip 8 and the electrode 12a of the substrate 12 are electrically connected. Further, the semiconductor chip 8 and the substrate 12 are bonded by the cured product 3 a of the insulating resin layer 3 interposed between the semiconductor chip 8 and the substrate 12. Thereby, the semiconductor device 20 as shown in FIG. 7 is manufactured. Subsequently, in order to further advance the curing of the insulating resin layer 3, heat treatment may be performed using a heating oven or the like.

（絶縁性樹脂組成物）
上述の被覆工程において、絶縁性樹脂層３の形成に使用する絶縁性樹脂組成物について説明する。当該絶縁性樹脂組成物は、熱硬化性成分とその硬化剤とを含有することが好ましい。 (Insulating resin composition)
The insulating resin composition used for forming the insulating resin layer 3 in the above coating step will be described. The insulating resin composition preferably contains a thermosetting component and its curing agent.

熱硬化性成分としては、例えば、エポキシ樹脂、ビスマレイミド樹脂、ポリアミド樹脂、ポリイミド樹脂、トリアジン樹脂、シアノアクリレート樹脂、不飽和ポリエステル樹脂、メラミン樹脂、尿素樹脂、ベンゾオキサジン樹脂、ポリウレタン樹脂、ポリイソシアネート樹脂、フラン樹脂、レゾルシノール樹脂、キシレン樹脂、ベンゾグアナミン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、ポリビニルブチラール樹脂、シロキサン変性エポキシ樹脂、シロキサン変性ポリアミドイミド樹脂、アクリレート樹脂などが挙げられ、特に好ましいのは耐熱性の観点からエポキシ樹脂、ベンゾオキサジン樹脂、シロキサン変性エポキシ樹脂、シロキサン変性ポリアミドイミド樹脂である。これらの熱硬化性成分は一種を単独で用いてもよく、二種以上を併用してもよい。   Examples of thermosetting components include epoxy resins, bismaleimide resins, polyamide resins, polyimide resins, triazine resins, cyanoacrylate resins, unsaturated polyester resins, melamine resins, urea resins, benzoxazine resins, polyurethane resins, polyisocyanate resins. , Furan resin, resorcinol resin, xylene resin, benzoguanamine resin, diallyl phthalate resin, silicone resin, polyvinyl butyral resin, siloxane-modified epoxy resin, siloxane-modified polyamideimide resin, acrylate resin, etc. To epoxy resin, benzoxazine resin, siloxane-modified epoxy resin, and siloxane-modified polyamideimide resin. These thermosetting components may be used individually by 1 type, and may use 2 or more types together.

硬化剤としては、例えば、フェノール樹脂、脂肪族アミン、脂環式アミン、芳香族ポリアミン、ポリアミド、脂肪族酸無水物、脂環式酸無水物、芳香族酸無水物、ジシアンジアミド、有機酸ジヒドラジド、三フッ化ホウ素アミン錯体、イミダゾール類、第３級アミン、有機過酸化物等が挙げられる。これらの硬化剤は一種を単独で用いてもよく、二種以上を併用してもよい。   Examples of the curing agent include phenol resin, aliphatic amine, alicyclic amine, aromatic polyamine, polyamide, aliphatic acid anhydride, alicyclic acid anhydride, aromatic acid anhydride, dicyandiamide, organic acid dihydrazide, Examples thereof include boron trifluoride amine complexes, imidazoles, tertiary amines, and organic peroxides. These curing agents may be used alone or in combination of two or more.

絶縁性樹脂層３における熱硬化性成分と硬化剤の組み合わせとして、耐熱性の観点から、熱硬化性成分としてエポキシ樹脂を使用し、硬化剤としてフェノール樹脂又はイミダゾール類を使用することが好ましい。より一層耐熱性を向上させる観点から、熱硬化性成分として、ポリイミド樹脂及びエポキシ樹脂を使用することが好ましい。なお、ポリイミド樹脂を含有せしめることにより、耐熱性及び接着性が向上するとともに、絶縁性樹脂組成物のフィルム形成性が向上する。   As a combination of the thermosetting component and the curing agent in the insulating resin layer 3, it is preferable to use an epoxy resin as the thermosetting component and a phenol resin or imidazole as the curing agent from the viewpoint of heat resistance. From the viewpoint of further improving the heat resistance, it is preferable to use a polyimide resin and an epoxy resin as the thermosetting component. In addition, by including a polyimide resin, heat resistance and adhesiveness are improved, and film forming properties of the insulating resin composition are improved.

絶縁性樹脂層３は熱可塑性成分を更に含有してもよい。熱可塑性成分としては、例えば、ポリエステル樹脂、ポリエーテル樹脂、ポリアミド樹脂、ポリアミドイミド樹脂、ポリイミド樹脂、ポリアクリレート樹脂、ポリビニルブチラール樹脂、ポリウレタン樹脂、フェノキシ樹脂、ポリアクリレート樹脂、ポリブタジエン、アクリロニトリルブタジエン共重合体、アクリロニトリルブタジエンゴムスチレン樹脂（ＡＢＳ）、スチレンブタジエン共重合体（ＳＢＲ）、アクリル酸共重合体などが挙げられる。これらの熱可塑性成分は、一種を単独で用いてもよく、二種以上を併用してもよい。上記の熱可塑性成分のなかでも、耐熱性及びフィルム形成性の観点から、ポリイミド樹脂及びフェノキシ樹脂が好ましい。   The insulating resin layer 3 may further contain a thermoplastic component. Examples of the thermoplastic component include polyester resin, polyether resin, polyamide resin, polyamideimide resin, polyimide resin, polyacrylate resin, polyvinyl butyral resin, polyurethane resin, phenoxy resin, polyacrylate resin, polybutadiene, acrylonitrile butadiene copolymer , Acrylonitrile butadiene rubber styrene resin (ABS), styrene butadiene copolymer (SBR), acrylic acid copolymer and the like. These thermoplastic components may be used individually by 1 type, and may use 2 or more types together. Among the above thermoplastic components, a polyimide resin and a phenoxy resin are preferable from the viewpoints of heat resistance and film formability.

絶縁性樹脂層３は、無機化合物からなるフィラー（無機微粒子）を更に含有してもよい。フィラーを配合することにより、絶縁性樹脂層３の熱膨張係数を低くすることができる。これに加え、フィラーを配合することにより、絶縁性樹脂層３の粘着性を制御したり、熱伝導性又はダイシング性を向上させたり、溶融粘度を調整したりすることができる。フィラーとしては、アルミナ、窒化アルミニウム、窒化ホウ素、結晶性シリカ又は非晶性シリカ、ムライト（二酸化ケイ素と酸化アルミニウムの複合酸化物）、二酸化ケイ素と酸化チタンの複合酸化物、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウムを使用することが好ましい。なお、上記フィラーは一種を単独で使用してもよく、二種以上を併用してもよい。   The insulating resin layer 3 may further contain a filler (inorganic fine particles) made of an inorganic compound. By blending the filler, the thermal expansion coefficient of the insulating resin layer 3 can be lowered. In addition to this, by blending a filler, the adhesiveness of the insulating resin layer 3 can be controlled, the thermal conductivity or the dicing property can be improved, or the melt viscosity can be adjusted. As fillers, alumina, aluminum nitride, boron nitride, crystalline silica or amorphous silica, mullite (composite oxide of silicon dioxide and aluminum oxide), composite oxide of silicon dioxide and titanium oxide, aluminum hydroxide, hydroxylation It is preferable to use magnesium, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, or magnesium oxide. In addition, the said filler may be used individually by 1 type, and may use 2 or more types together.

フィラーの平均粒径は、０．００５〜５．０μｍであることが好ましく、０．００５〜２．５μｍであることがより好ましく、０．００５〜２．０μｍであることが更に好ましい。平均粒径が０．００５μｍ未満又は５．０μｍを超えるフィラーを使用すると、平均粒径が上記範囲内であるフィラーを使用した場合と比較し、突起電極２と電極１２ａの間にフィラーが残存して接続不良が発生する恐れがある。これに加え、絶縁性樹脂組成物の成膜性が不十分となる傾向となる。なお、フィラーの配合量は、絶縁性樹脂層３の要求される性能に応じて適宜調整すればよい。   The average particle size of the filler is preferably 0.005 to 5.0 μm, more preferably 0.005 to 2.5 μm, and still more preferably 0.005 to 2.0 μm. When a filler having an average particle size of less than 0.005 μm or more than 5.0 μm is used, the filler remains between the protruding electrode 2 and the electrode 12a as compared with the case of using a filler having an average particle size within the above range. Connection failure may occur. In addition to this, the film formability of the insulating resin composition tends to be insufficient. In addition, what is necessary is just to adjust the compounding quantity of a filler suitably according to the performance by which the insulating resin layer 3 is requested | required.

また、絶縁性樹脂層３は、硬化促進剤、シランカップリング剤、チタンカップリング剤、酸化防止剤、レベリング剤、イオントラップ剤などの添加剤を更に含有してもよい。これらの添加剤は一種を単独で使用してもよく、二種以上を併用してもよい。添加剤の配合量は、各添加剤の効果が発現するように適宜調整すればよい。   The insulating resin layer 3 may further contain additives such as a curing accelerator, a silane coupling agent, a titanium coupling agent, an antioxidant, a leveling agent, and an ion trapping agent. These additives may be used individually by 1 type, and may use 2 or more types together. What is necessary is just to adjust the compounding quantity of an additive suitably so that the effect of each additive may express.

絶縁性樹脂層３は、上述の通り、可視光透過率が１０％以上であることが好ましい。絶縁性樹脂層３の可視光透過率が１０％以上となるように、絶縁性樹脂層３の組成、フィラーの材質、粒径などを設定することが好ましい。   As described above, the insulating resin layer 3 preferably has a visible light transmittance of 10% or more. It is preferable to set the composition of the insulating resin layer 3, the material of the filler, the particle size, etc. so that the visible light transmittance of the insulating resin layer 3 is 10% or more.

また、絶縁性樹脂層３は、３００℃以上の温度で接続を行っても樹脂発泡が生じない絶縁性樹脂組成物からなることが好ましい。このような絶縁性樹脂組成物を使用することにより、樹脂発泡に起因するボイドの発生を抑制できるため、半導体装置の接続信頼性をより一層向上できる。なお、上記熱処理後における樹脂発泡の発生の有無は、図５に示す圧着装置３０と同様の構成の装置を用いて評価を行うことができる。まず、ステージ１０上にガラス基板（厚さ０．７ｍｍ）、絶縁性樹脂層（厚さ９０〜１００μｍ）及びガラス基板（厚さ０．１５μｍ）をこの順序で積層する。この積層体に対して表面温度３００〜４００℃の圧着ヘッド３０ａを０．５〜５秒間押し当てる。硬化後の絶縁性樹脂層における気泡の存否を目視で観察することによって評価することができる。   Insulating resin layer 3 is preferably made of an insulating resin composition that does not cause foaming of resin even when connected at a temperature of 300 ° C. or higher. By using such an insulating resin composition, generation of voids due to resin foaming can be suppressed, so that the connection reliability of the semiconductor device can be further improved. In addition, the presence or absence of generation | occurrence | production of the resin foam after the said heat processing can be evaluated using the apparatus of the structure similar to the crimping | compression-bonding apparatus 30 shown in FIG. First, a glass substrate (thickness 0.7 mm), an insulating resin layer (thickness 90 to 100 μm), and a glass substrate (thickness 0.15 μm) are stacked in this order on the stage 10. A pressure-bonding head 30a having a surface temperature of 300 to 400 ° C. is pressed against the laminated body for 0.5 to 5 seconds. It can be evaluated by visually observing the presence or absence of bubbles in the insulating resin layer after curing.

絶縁性樹脂組成物からなるフィルムは、例えば、シリコーン等によって表面が離型処理されたポリエチレンテレフタレート（ＰＥＴ）フィルムなどの支持フィルム上に絶縁性樹脂を含有する塗工液を塗布し、これを乾燥させることによって得ることができる。   For a film made of an insulating resin composition, for example, a coating liquid containing an insulating resin is applied on a support film such as a polyethylene terephthalate (PET) film whose surface has been release-treated with silicone or the like, and then dried. Can be obtained.

以上、説明した通り、第１実施形態に係る半導体装置の製造方法によれば、半導体ウェハ１の回路面Ｓ１を絶縁性樹脂層３で被覆した後、半導体ウェハ１をダイシングすることによって、絶縁性樹脂層３を一方面上に有する複数の半導体チップ８が一括して得られる。このため、接続工程後に毛細管現象を利用して充填する場合や個片化された半導体チップの表面に後から個別に絶縁性接着剤層を形成する場合と比較し、半導体装置の生産性を向上できる。   As described above, according to the manufacturing method of the semiconductor device according to the first embodiment, after the circuit surface S1 of the semiconductor wafer 1 is covered with the insulating resin layer 3, the semiconductor wafer 1 is diced, thereby insulating the semiconductor wafer 1. A plurality of semiconductor chips 8 having the resin layer 3 on one surface are obtained in a lump. For this reason, the productivity of semiconductor devices is improved compared to the case where the capillarity is used for filling after the connection process and the case where an insulating adhesive layer is individually formed on the surface of the separated semiconductor chip later. it can.

また、位置調整工程を実施した後、接続工程を実施するため、接続工程の前に絶縁性樹脂層３の熱硬化の進行を十分に抑制できる。したがって、絶縁性樹脂層３が接続工程において十分に性能を発揮でき、良好な接続が可能となり、接続信頼性が高い半導体装置２０を製造できる。   Moreover, since a connection process is implemented after implementing a position adjustment process, the progress of the thermosetting of the insulating resin layer 3 can fully be suppressed before a connection process. Therefore, the insulating resin layer 3 can sufficiently exhibit performance in the connection process, enables good connection, and manufactures the semiconductor device 20 with high connection reliability.

＜第２実施形態＞
図８〜９を参照しながら、第２実施形態に係る半導体装置の製造方法について説明する。本実施形態は、ピックアップ工程までは上記第１実施形態と同様に実施できるため、ここでは位置調整工程以降の工程について説明する。 Second Embodiment
A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. Since this embodiment can be carried out in the same manner as the first embodiment up to the pick-up step, the steps after the position adjustment step will be described here.

本実施形態における位置調整工程は、圧着ヘッド３０ａ及びステージ３０ｂを有する圧着装置３０を使用する代わりに、圧着ヘッド４０ａ及びステージ４０ｂを有する仮固定装置４０を使用する点において上記第１実施形態における位置調整工程と相違する。   The position adjustment step in the present embodiment uses the temporary fixing device 40 having the crimping head 40a and the stage 40b instead of using the crimping device 30 having the crimping head 30a and the stage 30b. It is different from the adjustment process.

すなわち、図８に示すように、仮固定装置４０及び可視光カメラ１３を使用し、基板１２の電極１２ａと、半導体チップ８の突起電極２との位置合わせを行う。まず、ピックアップされた半導体チップ８の裏面Ｓ２を圧着ヘッド４０ａに吸着させる。他方、電極１２ａが形成された面を上方に向けた状態で基板１２をステージ４０ｂ上に載置する。続いて、半導体チップ８の回路面Ｓ１に形成されている位置合わせ用基準マーク（図示せず）を、絶縁性樹脂層３を通して可視光カメラ１３で認識するとともに、基板１２の電極１２ａが形成された一方面Ｓ４上の位置合わせ用基準マーク（図示せず）を可視光カメラ１３で認識して、位置合わせを行う。   That is, as shown in FIG. 8, the temporary fixing device 40 and the visible light camera 13 are used to align the electrode 12 a of the substrate 12 and the protruding electrode 2 of the semiconductor chip 8. First, the back surface S2 of the picked-up semiconductor chip 8 is attracted to the crimping head 40a. On the other hand, the substrate 12 is placed on the stage 40b with the surface on which the electrode 12a is formed facing upward. Subsequently, an alignment reference mark (not shown) formed on the circuit surface S1 of the semiconductor chip 8 is recognized by the visible light camera 13 through the insulating resin layer 3, and the electrode 12a of the substrate 12 is formed. The alignment reference mark (not shown) on the other surface S4 is recognized by the visible light camera 13, and alignment is performed.

位置調整工程後、図９に示すように、仮固定装置４０を使用し、半導体チップ８を基板１２に押し当てるとともに熱を加えることによって、半導体チップ８を基板１２に仮固定する（接続準備工程）。仮固定装置４０の圧着ヘッド４０ａ及びステージ４０ｂは、いずれもヒータが内蔵されており、表面の温度を所望の温度にそれぞれ設定できるようになっている。   After the position adjustment step, as shown in FIG. 9, the semiconductor chip 8 is temporarily fixed to the substrate 12 by pressing the semiconductor chip 8 against the substrate 12 and applying heat by using the temporary fixing device 40 (connection preparation step). ). The crimping head 40a and the stage 40b of the temporary fixing device 40 each have a built-in heater so that the surface temperature can be set to a desired temperature.

仮固定装置４０の圧着ヘッド４０ａ及びステージ４０ｂの温度は、接続準備工程において、絶縁性樹脂層３が粘着性を示す温度であり且つ絶縁性樹脂層３の硬化反応が促進されない温度であればよく、例えば、４０〜１００℃程度に設定することが好ましい。なお、接続準備工程においては、圧着ヘッド４０ａ及びステージ４０ｂの一方のみによって加温してもよく、あるいは、加温することなく、圧着ヘッド４０ａによる加圧のみによって仮固定を行ってもよい。   The temperature of the pressure-bonding head 40a and the stage 40b of the temporary fixing device 40 may be a temperature at which the insulating resin layer 3 exhibits adhesiveness and does not accelerate the curing reaction of the insulating resin layer 3 in the connection preparation step. For example, it is preferable to set to about 40-100 degreeC. In the connection preparation step, heating may be performed by only one of the crimping head 40a and the stage 40b, or temporary fixing may be performed only by pressurization by the crimping head 40a without heating.

接続準備工程後、基板１２、絶縁性樹脂層３及び半導体チップ８がこの順序で積層された積層体１８を圧着装置３０に搬送する。その後、上記第１実施形態と同様にして接続工程を実施し、半導体チップ８を基板１２に実装する（図６参照）。   After the connection preparation step, the stacked body 18 in which the substrate 12, the insulating resin layer 3, and the semiconductor chip 8 are stacked in this order is conveyed to the crimping device 30. Thereafter, a connection step is performed in the same manner as in the first embodiment, and the semiconductor chip 8 is mounted on the substrate 12 (see FIG. 6).

第２実施形態に係る半導体装置の製造方法によれば、上記第１実施形態に係る半導体装置の製造方法による効果に加えて、次のような効果が奏される。すなわち、第２実施形態における位置調整工程は、比較的低温に設定された圧着ヘッド４０ａを用いて実施されるため、当該工程における絶縁性樹脂層３の硬化を一層確実に防止できる。   According to the method for manufacturing a semiconductor device according to the second embodiment, in addition to the effects of the method for manufacturing a semiconductor device according to the first embodiment, the following effects can be obtained. That is, since the position adjustment process in the second embodiment is performed using the pressure-bonding head 40a set at a relatively low temperature, it is possible to more reliably prevent the insulating resin layer 3 from being cured in the process.

なお、上記第１実施形態における位置調整工程は、接続用の圧着ヘッド３０ａを用いて実施するものであり、この位置調整工程において圧着ヘッド３０ａの温度を低く設定し、その後の接続工程で温度を高く設定する操作を行えば、絶縁性樹脂層３の硬化を防止できる。このような温度設定の操作に関し、第２実施形態においては、位置調整工程と接続工程とを別々の装置を用いて行うため、温度が安定するまで待機する必要がないため、一層作業効率を向上できる。   Note that the position adjustment step in the first embodiment is performed using the connection pressure bonding head 30a. In this position adjustment step, the temperature of the pressure bonding head 30a is set low, and the temperature is adjusted in the subsequent connection step. If the operation of setting it high is performed, curing of the insulating resin layer 3 can be prevented. With regard to such temperature setting operation, in the second embodiment, the position adjustment process and the connection process are performed using separate devices, so there is no need to wait until the temperature stabilizes, thus further improving work efficiency. it can.

＜第３実施形態＞
図１０〜１３を参照しながら、第３実施形態に係る半導体装置の製造方法について説明する。本実施形態は、ピックアップ工程までは上記第１実施形態と同様に実施できるため、ここでは位置調整工程以降の工程について説明する。本実施形態は、半導体チップ８を基板１２に実装する代わりに、電極２２ａが一方面Ｓ５に形成された光透過性を有する基板２２に実装する点において、上記第１実施形態と相違する。なお、光透過性を有する基板２２として例えばポリイミドなどが挙げられ、電極２２ａとして例えばスズめっき配線が挙げられる。 <Third Embodiment>
A method for manufacturing a semiconductor device according to the third embodiment will be described with reference to FIGS. Since this embodiment can be carried out in the same manner as the first embodiment up to the pick-up step, the steps after the position adjustment step will be described here. This embodiment is different from the first embodiment in that instead of mounting the semiconductor chip 8 on the substrate 12, the electrode 22a is mounted on the light-transmitting substrate 22 formed on the one surface S5. In addition, a polyimide etc. are mentioned as the board | substrate 22 which has a light transmittance, for example, a tin plating wiring is mentioned as the electrode 22a.

本実施形態における位置調整工程は、圧着ヘッド３０ａ及びステージ３０ｂを有する圧着装置３０を使用する代わりに、圧着ヘッド５０ａ及びステージ５０ｂを有する仮固定装置５０を使用する点において上記第１実施形態における位置調整工程と相違する。   The position adjustment step in the present embodiment uses the temporary fixing device 50 having the crimping head 50a and the stage 50b instead of using the crimping device 30 having the crimping head 30a and the stage 30b. It is different from the adjustment process.

図１０に示すように、仮固定装置５０及び可視光カメラ１３を使用し、光透過性を有する基板２２の電極２２ａと、半導体チップ８の突起電極２との位置合わせを行う。光透過性を有する基板２２は、図示しない基板保持部によって保持されつつステージ５０ｂの表面に対して平行な方向（図１０の矢印Ｈの方向）に移動可能となっている。まず、ピックアップされた半導体チップ８の裏面Ｓ２をステージ５０ｂの表面上に固定する。他方、基板保持部を用いて、電極２２ａが一方面Ｓ５に形成された光透過性を有する基板２２を半導体チップ８の上方に搬送する。続いて、半導体チップ８の回路面Ｓ１に形成されている位置合わせ用基準マーク（図示せず）を、絶縁性樹脂層３及び光透過性を有する基板２２を通して可視光カメラ１３で認識するとともに、光透過性を有する基板２２の電極２２ａが形成された一方面Ｓ５上の位置合わせ用基準マーク（図示せず）を可視光カメラ１３で認識して、光透過性を有する基板２２の矢印Ｈ方向の位置を調整する。なお、基板保持部によって光透過性を有する基板２２を移動させることにより位置調整を行う代わりに、ステージ５０ｂによって半導体チップ８を移動させることによって、半導体チップの突起電極２と光透過性を有する基板２２との位置調整を行っても構わない。   As shown in FIG. 10, the temporary fixing device 50 and the visible light camera 13 are used to align the electrode 22 a of the light-transmitting substrate 22 and the protruding electrode 2 of the semiconductor chip 8. The light-transmitting substrate 22 is movable in a direction parallel to the surface of the stage 50b (in the direction of arrow H in FIG. 10) while being held by a substrate holding portion (not shown). First, the back surface S2 of the picked-up semiconductor chip 8 is fixed on the surface of the stage 50b. On the other hand, the substrate 22 having light transmissivity, on which the electrode 22a is formed on the one surface S5, is transported above the semiconductor chip 8 by using the substrate holder. Subsequently, the alignment reference mark (not shown) formed on the circuit surface S1 of the semiconductor chip 8 is recognized by the visible light camera 13 through the insulating resin layer 3 and the light-transmitting substrate 22, and The alignment reference mark (not shown) on the one surface S5 on which the electrode 22a of the substrate 22 having optical transparency is formed is recognized by the visible light camera 13, and the arrow H direction of the substrate 22 having optical transparency is recognized. Adjust the position. Instead of adjusting the position by moving the light-transmitting substrate 22 by the substrate holding portion, the semiconductor chip 8 is moved by the stage 50b, so that the protruding electrode 2 of the semiconductor chip and the light-transmitting substrate are moved. Position adjustment with 22 may be performed.

位置調整工程後、図１１に示すように、仮固定装置５０の圧着ヘッド５０ａを使用し、半導体チップ８を、光透過性を有する基板２２に押し当てるとともに熱を加えることによって、半導体チップ８を基板２２に仮固定する（接続準備工程）。仮固定装置５０の圧着ヘッド５０ａ及びステージ５０ｂには、いずれもヒータが内蔵されており、表面の温度を所望の温度にそれぞれ設定できるようになっている。また、圧着ヘッド５０ａはステージ５０ｂの表面に対して垂直方向（図１１の矢印Ｖの方向）に移動可能となっている。   After the position adjustment step, as shown in FIG. 11, the semiconductor chip 8 is pressed by pressing the semiconductor chip 8 against the light-transmitting substrate 22 and applying heat using the crimping head 50 a of the temporary fixing device 50. Temporary fixing to the substrate 22 (connection preparation step). The pressure-bonding head 50a and the stage 50b of the temporary fixing device 50 each have a built-in heater so that the surface temperature can be set to a desired temperature. The crimping head 50a is movable in the direction perpendicular to the surface of the stage 50b (in the direction of arrow V in FIG. 11).

仮固定装置５０の圧着ヘッド５０ａ及びステージ５０ｂの温度は、接続準備工程において、絶縁性樹脂層３が粘着性を示す温度であり且つ絶縁性樹脂層３の硬化反応が促進されない温度であればよく、例えば、４０〜１００℃程度に設定することが好ましい。なお、接続準備工程においては、圧着ヘッド５０ａ及びステージ５０ｂの一方のみによって加温してもよく、あるいは、加温することなく、圧着ヘッド５０ａによる加圧のみによって仮固定を行ってもよい。   The temperature of the crimping head 50a and the stage 50b of the temporary fixing device 50 may be a temperature at which the insulating resin layer 3 exhibits adhesiveness and does not promote the curing reaction of the insulating resin layer 3 in the connection preparation step. For example, it is preferable to set to about 40-100 degreeC. In the connection preparation step, heating may be performed by only one of the crimping head 50a and the stage 50b, or temporary fixing may be performed only by pressing with the crimping head 50a without heating.

接続準備工程後、半導体チップ８、絶縁性樹脂層３及び基板２２がこの順序で積層された積層体１９を圧着装置６０に搬送機（図示しない）等を用いて搬送する。図１２に示すように、圧着装置６０を使用し、光透過性を有する基板２２を半導体チップ８に押し当てるとともに熱を加えることによって、半導体チップ８を基板２２に実装する（接続工程）。圧着装置６０の圧着ヘッド６０ａ及びステージ６０ｂは、いずれもヒータが内蔵されており、表面の温度を所望の温度にそれぞれ設定できるようになっている。また、圧着ヘッド６０ａはステージ６０ｂの表面に対して垂直方向（図１２の矢印Ｖの方向）に移動可能となっている。   After the connection preparation step, the stacked body 19 in which the semiconductor chip 8, the insulating resin layer 3, and the substrate 22 are stacked in this order is transported to the crimping device 60 using a transporter (not shown) or the like. As shown in FIG. 12, the semiconductor chip 8 is mounted on the substrate 22 by pressing the light-transmitting substrate 22 against the semiconductor chip 8 and applying heat using the crimping device 60 (connection process). Each of the crimping head 60a and the stage 60b of the crimping device 60 has a built-in heater so that the surface temperature can be set to a desired temperature. Further, the crimping head 60a is movable in the direction perpendicular to the surface of the stage 60b (in the direction of arrow V in FIG. 12).

圧着装置６０の圧着ヘッド６０ａ及びステージ６０ｂの温度は、接続工程において、絶縁性樹脂層３が十分に硬化する温度であり且つ接続部の温度が突起電極２の材質及び電極２２ａの材質の共晶温度を超えるように設定することが好ましい。例えば、突起電極２が金めっきによって形成され、他方、電極２２ａがスズめっきで形成される場合、金とスズとの共晶温度（２７８℃）を超えるように接続部を加熱することが好ましい。例えば、圧着ヘッド６０ａを５０〜１５０℃、ステージ６０ｂを３００〜５００℃に設定することが好ましい。加熱時間を０．５〜１０秒とすることが好ましく、０．５〜５秒とすることがより好ましい。   The temperature of the pressure bonding head 60a and the stage 60b of the pressure bonding apparatus 60 is a temperature at which the insulating resin layer 3 is sufficiently cured in the connection step, and the temperature of the connection portion is a eutectic of the material of the protruding electrode 2 and the material of the electrode 22a. It is preferable to set so as to exceed the temperature. For example, when the protruding electrode 2 is formed by gold plating and the electrode 22a is formed by tin plating, it is preferable to heat the connection portion so as to exceed the eutectic temperature (278 ° C.) of gold and tin. For example, it is preferable to set the pressure-bonding head 60 a to 50 to 150 ° C. and the stage 60 b to 300 to 500 ° C. The heating time is preferably 0.5 to 10 seconds, more preferably 0.5 to 5 seconds.

接続工程によって、半導体チップ８の突起電極２と、光透過性を有する基板２２の電極２２ａとを電気的に接続する。また、半導体チップ８と基板２２との間に介在する絶縁性樹脂層３の硬化物３ａによって半導体チップ８と基板２２とを接着する。これにより、図１３に示すような半導体装置２１が製造される。引き続き、絶縁性樹脂層３の硬化を更に進行させるために、加熱オーブンなどを用いて加熱処理を行ってもよい。   Through the connecting step, the protruding electrode 2 of the semiconductor chip 8 and the electrode 22a of the light-transmitting substrate 22 are electrically connected. Further, the semiconductor chip 8 and the substrate 22 are bonded by the cured product 3 a of the insulating resin layer 3 interposed between the semiconductor chip 8 and the substrate 22. Thereby, the semiconductor device 21 as shown in FIG. 13 is manufactured. Subsequently, in order to further advance the curing of the insulating resin layer 3, heat treatment may be performed using a heating oven or the like.

第３実施形態に係る半導体装置の製造方法では、光透過性を有する基板２２の供給をリール・ツー・リール（Ｒｅｅｌ ｔｏ Ｒｅｅｌ）方式によって行うことが好ましい。すなわち、第３実施形態に係る半導体装置の製造方法では、位置調整工程及び接続工程において、リール・ツー・リール方式によってフレキシブルな基板２２を仮固定装置５０及び圧着装置６０に連続的に供給することが好ましい。半導体チップ８と基板２２との仮固定及び接続を連続的に実施することによって、半導体装置をより一層効率的に製造できる。   In the method of manufacturing a semiconductor device according to the third embodiment, it is preferable to supply the light-transmitting substrate 22 by a reel-to-reel method. That is, in the method of manufacturing a semiconductor device according to the third embodiment, the flexible substrate 22 is continuously supplied to the temporary fixing device 50 and the crimping device 60 by the reel-to-reel method in the position adjustment process and the connection process. Is preferred. By continuously fixing and connecting the semiconductor chip 8 and the substrate 22 continuously, the semiconductor device can be manufactured more efficiently.

第３実施形態に係る半導体装置の製造方法によれば、上記第１実施形態に係る半導体装置の製造方法による効果に加えて、次のような効果が奏される。すなわち、第３実施形態における位置調整工程は、比較的低温に設定された圧着ヘッド５０ａを用いて実施されるため、当該工程における絶縁性樹脂層３の硬化を確実に防止できる。また、第３実施形態においては、位置調整工程と接続工程とを別々の装置を用いて行うため、温度が安定するまで待機する必要がないため、一層作業効率を向上できる。   According to the method for manufacturing a semiconductor device according to the third embodiment, in addition to the effects of the method for manufacturing a semiconductor device according to the first embodiment, the following effects are exhibited. That is, since the position adjustment process in the third embodiment is performed using the pressure-bonding head 50a set at a relatively low temperature, it is possible to reliably prevent the insulating resin layer 3 from being cured in the process. In the third embodiment, since the position adjustment process and the connection process are performed using separate devices, there is no need to wait until the temperature stabilizes, and therefore the working efficiency can be further improved.

突起電極を有する半導体ウェハを示す断面図である。It is sectional drawing which shows the semiconductor wafer which has a protruding electrode. 回路面上に絶縁性樹脂層が形成された半導体ウェハを示す断面図である。It is sectional drawing which shows the semiconductor wafer in which the insulating resin layer was formed on the circuit surface. 半導体ウェハをダイシング装置上に固定した状態を示す断面図である。It is sectional drawing which shows the state which fixed the semiconductor wafer on the dicing apparatus. 半導体ウェハをダイシングしている状態を示す断面図である。It is sectional drawing which shows the state which is dicing the semiconductor wafer. 半導体チップと基板の位置調整を行っている状態を示す断面図である。It is sectional drawing which shows the state which is adjusting the position of a semiconductor chip and a board | substrate. 半導体チップと基板の接続を行っている状態を示す断面図である。It is sectional drawing which shows the state which has connected the semiconductor chip and the board | substrate. 本発明の第１，２実施形態に係る方法によって製造された半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device manufactured by the method based on 1st, 2 embodiment of this invention. 半導体チップと基板の位置調整を行っている状態を示す断面図である。It is sectional drawing which shows the state which is adjusting the position of a semiconductor chip and a board | substrate. 半導体チップと基板の仮固定を行っている状態を示す断面図である。It is sectional drawing which shows the state which is temporarily fixing a semiconductor chip and a board | substrate. 半導体チップと光透過性基板の位置調整を行っている状態を示す断面図である。It is sectional drawing which shows the state which is adjusting the position of a semiconductor chip and a transparent substrate. 半導体チップと光透過性基板の仮固定を行っている状態を示す断面図である。It is sectional drawing which shows the state which is temporarily fixing a semiconductor chip and a transparent substrate. 半導体チップと光透過性基板の接続を行っている状態を示す断面図である。It is sectional drawing which shows the state which has connected the semiconductor chip and the transparent substrate. 本発明の第３実施形態に係る方法によって製造された半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device manufactured by the method concerning 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１…半導体ウェハ、２…突起電極、３…絶縁性樹脂層、５…ダイシングテープ、６…ダイシング装置のステージ、８…半導体チップ、１２，２２…基板、１２ａ，２２ａ…電極、１３…可視光カメラ、２０，２１…半導体装置、３０，６０…圧着装置、４０，５０…仮固定装置、Ｓ１…回路面（半導体ウェハの一方面）、Ｓ２…裏面（半導体ウェハの他方面）。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 2 ... Projection electrode, 3 ... Insulating resin layer, 5 ... Dicing tape, 6 ... Stage of dicing apparatus, 8 ... Semiconductor chip, 12, 22 ... Substrate, 12a, 22a ... Electrode, 13 ... Visible light Camera, 20, 21 ... Semiconductor device, 30, 60 ... Crimping device, 40, 50 ... Temporary fixing device, S1 ... Circuit surface (one surface of the semiconductor wafer), S2 ... Back surface (the other surface of the semiconductor wafer).

Claims (5)

半導体ウェハの一方面に形成された複数の突起電極を埋め込むように、当該一方面上に絶縁性樹脂層を形成する被覆工程と、
前記半導体ウェハの他方面とダイシングテープとを貼り合わせ、前記ダイシングテープを介して当該半導体ウェハをダイシング装置のステージ上に固定するダイシング準備工程と、
前記絶縁性樹脂層側から前記半導体ウェハを前記絶縁性樹脂層とともに切断し、一方面上に突起電極を有し且つ切断された前記絶縁性樹脂層によって当該一方面が被覆された半導体チップを得るダイシング工程と、
前記ステージ上の前記半導体チップを前記切断された絶縁性樹脂層とともにピックアップするピックアップ工程と、
前記半導体チップを実装すべき基板に対し、前記切断された絶縁性樹脂層側を向けて前記半導体チップを保持しながら、前記基板の表面に設けられた電極と、前記半導体チップの前記突起電極との位置を合わせる位置調整工程と、
前記位置調整工程後、前記半導体チップを前記基板に押し当てるとともに熱を加えることによって、前記半導体チップを前記基板に実装する接続工程と、
を備え、
前記絶縁性樹脂層は、可視光透過率が１０％以上である、半導体装置の製造方法。 A covering step of forming an insulating resin layer on the one surface so as to embed a plurality of protruding electrodes formed on one surface of the semiconductor wafer;
A dicing preparation step of bonding the other surface of the semiconductor wafer and a dicing tape, and fixing the semiconductor wafer on a stage of a dicing apparatus via the dicing tape;
The semiconductor wafer is cut together with the insulating resin layer from the side of the insulating resin layer, and a semiconductor chip having a protruding electrode on one surface and covered with the cut insulating resin layer is obtained. Dicing process,
A pickup step of picking up the semiconductor chip on the stage together with the cut insulating resin layer;
An electrode provided on a surface of the substrate while holding the semiconductor chip with the cut insulating resin layer side facing the substrate on which the semiconductor chip is to be mounted; and the protruding electrode of the semiconductor chip; A position adjustment process for adjusting the position of
After the position adjusting step, by pressing the semiconductor chip against the substrate and applying heat, a connecting step of mounting the semiconductor chip on the substrate;
Equipped with a,
The method for manufacturing a semiconductor device, wherein the insulating resin layer has a visible light transmittance of 10% or more . 前記位置調整工程後であり且つ前記接続工程前に、前記半導体チップを前記基板上に仮固定する接続準備工程を更に備える、請求項１に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, further comprising a connection preparation step of temporarily fixing the semiconductor chip on the substrate after the position adjustment step and before the connection step. 前記被覆工程において、絶縁性樹脂組成物からなるフィルムを前記半導体ウェハの一方面上に貼り合わせることによって、前記絶縁性樹脂層を形成する、請求項１又は２に記載の半導体装置の製造方法。 In the coating process, by laminating a film made of an insulating resin composition on one surface of the semiconductor wafer, to form the insulating resin layer, a method of manufacturing a semiconductor device according to claim 1 or 2. 前記絶縁性樹脂層は、３００℃以上の温度で接続を行っても樹脂発泡が生じない絶縁性樹脂組成物からなる、請求項１〜３のいずれか一項に記載の半導体装置の製造方法。 The said insulating resin layer is a manufacturing method of the semiconductor device as described in any one of Claims 1-3 which consists of an insulating resin composition which does not produce resin foam even if it connects at the temperature of 300 degreeC or more. 前記絶縁性樹脂層は、ポリイミド樹脂とエポキシ樹脂と硬化剤とを含有する、請求項１〜４のいずれか一項に記載の半導体装置の製造方法。 The said insulating resin layer is a manufacturing method of the semiconductor device as described in any one of Claims 1-4 containing a polyimide resin, an epoxy resin, and a hardening | curing agent.
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