JP5890960B2 - Flip chip mounting method - Google Patents

Flip chip mounting method Download PDF

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JP5890960B2
JP5890960B2 JP2011034782A JP2011034782A JP5890960B2 JP 5890960 B2 JP5890960 B2 JP 5890960B2 JP 2011034782 A JP2011034782 A JP 2011034782A JP 2011034782 A JP2011034782 A JP 2011034782A JP 5890960 B2 JP5890960 B2 JP 5890960B2
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semiconductor chip
suction
chip
support
circuit board
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JP2012174861A (en
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さやか 脇岡
さやか 脇岡
中山　篤
篤 中山
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Sekisui Chemical Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Description

本発明は、半導体チップを回路基板に実装するフリップチップ実装方法に関し、特に、半導体チップの実装前に、半導体チップの回路面に予め絶縁性樹脂層を形成しておき、回路基板への実装と同時に半導体チップと回路基板との間の樹脂封止を行うフリップチップ実装方法に関する。   The present invention relates to a flip chip mounting method for mounting a semiconductor chip on a circuit board, and in particular, an insulating resin layer is formed in advance on the circuit surface of the semiconductor chip before mounting the semiconductor chip, The present invention also relates to a flip chip mounting method in which resin sealing is performed between a semiconductor chip and a circuit board.

近年、携帯電話、ノート型パーソナルコンピュータなどの電子機器の小型化や高性能化などに伴い、電子機器内に設けられる半導体集積回路の小型化・高密度化が益々図られている。この半導体集積回路の小型化や高密度化に伴い、半導体チップを回路基板に実装する方法として、従来のワイヤーボンディング接続方式に代えて、半導体チップにバンプと呼ばれる突起電極を形成することによって半導体チップを回路基板に直接接続するフリップチップ実装が着目され、近年ではこのフリップチップ実装が広く採用されるようになっている。フリップチップ実装は、半導体チップの回路面に対して半田などの材料でバンプ（突起電極）を複数形成し、このバンプを回路基板上に形成された複数の電極に加熱溶融により接合することによって、半導体チップと回路基板とを電気接続する方式のものである。このフリップチップ実装は、多数のバンプを回路基板上に一括で接合できるため、従来のワイヤーボンディング接続方式に比べて、実装面積を小さくできるうえ、電気的特性が良好、モールド封止が不要などの利点を有している。   In recent years, along with miniaturization and high performance of electronic devices such as mobile phones and notebook personal computers, semiconductor integrated circuits provided in the electronic devices have been increasingly miniaturized and densified. As a method of mounting a semiconductor chip on a circuit board as the semiconductor integrated circuit becomes smaller and higher in density, the semiconductor chip is formed by forming bump electrodes called bumps on the semiconductor chip instead of the conventional wire bonding connection method. Attention has been focused on flip-chip mounting in which the circuit board is directly connected to the circuit board. In recent years, this flip-chip mounting has been widely adopted. In flip chip mounting, a plurality of bumps (projection electrodes) are formed on a circuit surface of a semiconductor chip with a material such as solder, and the bumps are bonded to a plurality of electrodes formed on a circuit board by heating and melting. In this method, the semiconductor chip and the circuit board are electrically connected. In this flip chip mounting, a large number of bumps can be bonded together on the circuit board. Therefore, compared to the conventional wire bonding connection method, the mounting area can be reduced, electrical characteristics are good, and mold sealing is not required. Has advantages.

一方、フリップチップ実装においては、半導体チップと回路基板との接合部の接続信頼性を確保するため、半導体チップと回路基板との隙間に、毛細管現象を利用して液状樹脂を注入し硬化させることにより、半導体チップと実装基板との間の空隙を樹脂封止することが一般的に行われている（アンダーフィル）。しかし、アンダーフィルを用いたフリップチップ実装方法においては、製造コストが高い、液状樹脂の充填に時間がかかるなどの問題を有するうえ、半導体チップが狭ピッチ化し、かつ、半導体チップと回路基板との間の隙間が狭くなりつつある近年の現状では、液状樹脂の注入が困難となるという問題も有している。   On the other hand, in flip chip mounting, a liquid resin is injected into the gap between the semiconductor chip and the circuit board using a capillary phenomenon and cured in order to ensure the connection reliability of the joint between the semiconductor chip and the circuit board. Thus, it is generally performed that the gap between the semiconductor chip and the mounting substrate is resin-sealed (underfill). However, the flip chip mounting method using the underfill has problems such as high manufacturing cost and time required for filling the liquid resin, and the semiconductor chip has a narrow pitch. In the recent situation where the gap between them is becoming narrower, there is a problem that it becomes difficult to inject liquid resin.

そこで、アンダーフィルを用いたフリップチップ実装方法に代わる手段として、半導体チップまたは回路基板に予め樹脂封止用のペースト状樹脂（ＮＣＰ）やフィルム状樹脂（ＮＣＦ）を設け、半導体チップと回路基板との接合と同時に樹脂を溶融・硬化させることにより、半導体チップと回路基板との間の樹脂封止を行う実装方法が提案されている。例えば特許文献１には、半導体ウェハのバンプが形成された回路面（突起電極側面）に対して絶縁性樹脂層を形成した後に、半導体ウェハの裏面を研削して薄化し、その後、半導体ウェハをダイシングして複数の半導体チップに小片化して、半導体チップを回路基板に対して加圧および加熱により接合することで、同時に絶縁性樹脂層を介して半導体チップと回路基板との間を樹脂封止したフリップチップ実装方法が開示されている。   Therefore, as an alternative to the flip chip mounting method using underfill, a resin-like paste resin (NCP) or film resin (NCF) is provided in advance on a semiconductor chip or circuit board, A mounting method has been proposed in which a resin is sealed between a semiconductor chip and a circuit board by melting and curing the resin simultaneously with bonding. For example, in Patent Document 1, an insulating resin layer is formed on a circuit surface (side surface of a bump electrode) on which a bump of a semiconductor wafer is formed, and then the back surface of the semiconductor wafer is ground and thinned. Dicing into multiple semiconductor chips and bonding the semiconductor chip to the circuit board by pressurization and heating to simultaneously seal the gap between the semiconductor chip and the circuit board via the insulating resin layer A flip chip mounting method is disclosed.

特開２００９−２６０２１３号公報JP 2009-260213 A

上記したフリップチップ実装方法においては、図１０に示すように、半導体ウェハ１００のダイシングにより形成された半導体チップ１０１を、まず、フリップチップボンダーなどの実装用装置の運搬用ステージ１０２に、バンプ１０３および絶縁性樹脂層１０７が設けられた回路面を下にして配置する。そして、半導体チップ１０１の回路面とは反対の裏面に、上方から吸着ツール１０４を密着させ、この状態で、吸着ツール１０４の下面に図示しない吸引機構により吸引力を作用させて、半導体チップ１０１を吸着ツール１０４の下面に吸着させることで、運搬用ステージ１０２から半導体チップ１０１のピックアップを行う。その後、吸着ツール１０４を下降させ、半導体チップ１０１をボンディングステージ１０５に保持された回路基板１０６に加熱させながら押し付けることで、半導体チップ１０１が回路基板１０６に実装される。半導体チップ１０１の実装後は、再び吸着ツール１０４により次の新たな半導体チップ１０１が運搬用ステージ１０２からピックアップされ、同様にボンディングステージ１０５に保持された回路基板１０６に実装される手順が繰り返される。   In the flip chip mounting method described above, as shown in FIG. 10, the semiconductor chip 101 formed by dicing the semiconductor wafer 100 is first applied to the transport stage 102 of a mounting apparatus such as a flip chip bonder and the bump 103 and The circuit surface on which the insulating resin layer 107 is provided is disposed with the circuit surface facing down. Then, the suction tool 104 is brought into close contact with the back surface opposite to the circuit surface of the semiconductor chip 101 from above, and in this state, a suction force is applied to the lower surface of the suction tool 104 by a suction mechanism (not shown) to attach the semiconductor chip 101. The semiconductor chip 101 is picked up from the transport stage 102 by being attracted to the lower surface of the suction tool 104. Thereafter, the suction tool 104 is lowered and the semiconductor chip 101 is mounted on the circuit board 106 by pressing the semiconductor chip 101 against the circuit board 106 held on the bonding stage 105 while heating. After the mounting of the semiconductor chip 101, the procedure for the next new semiconductor chip 101 to be picked up again from the transport stage 102 by the suction tool 104 and mounted on the circuit board 106 held on the bonding stage 105 is repeated.

しかしながら、上記したフリップチップ実装方法において、吸着ツール１０４により運搬用ステージ１０２から半導体チップ１０１のピックアップを行う際に、吸着ツール１０４の温度が、半導体チップ１０１の実装時の温度と同程度の高い温度に設定されていると、熱によって半導体チップ１０１の回路面に形成された絶縁性樹脂層１０７が溶融し、この溶融した樹脂が垂れ下がって下方の運搬用ステージ１０２の上面に付着して、これを汚染するという問題が生じる。運搬用ステージ１０２の上面に樹脂が付着すると、次に運搬用ステージ１０２上に配置する半導体チップ１０１に樹脂が付着してしまうため、運搬用ステージ１０２上から樹脂をきれいに取り除く必要があるが、運搬用ステージ１０２上に樹脂が付着する度にこれを除去するのでは、その都度、実装用装置の駆動を止める必要があり、実装工程が長時間停止するなどの弊害が生じる。また、運搬用ステージ１０２に樹脂が付着しない場合であっても、樹脂が熱で軟化することにより、運搬用ステージ１０２の形状が絶縁性樹脂層１０７の樹脂面に転写されることがある。この場合、絶縁性樹脂層１０７の樹脂面に凹凸が生じるため、実装時に噛み込みボイドが発生しやすくなったり、絶縁信頼性が低下したりする恐れがある。一方、半導体チップ１０１の絶縁性樹脂層１０７の溶融を防ぐためには、実装後の吸着ツール１０４を十分に冷却した状態で半導体チップ１０１をピックアップする必要があるが、実装時に３００℃近くまで昇温させた吸着ツール１０４を十分に冷却させるためにはかなりの時間がかかるため、この冷却時間により実装作業の効率が著しく悪くなり、目標数の半導体チップの実装を短時間で達成するのが困難になるという問題が生じる。   However, in the flip chip mounting method described above, when the semiconductor chip 101 is picked up from the transport stage 102 by the suction tool 104, the temperature of the suction tool 104 is as high as the temperature at the time of mounting the semiconductor chip 101. When the insulating resin layer 107 formed on the circuit surface of the semiconductor chip 101 is melted by heat, the melted resin hangs down and adheres to the upper surface of the transport stage 102 below, The problem of contamination arises. If the resin adheres to the upper surface of the transport stage 102, the resin will then adhere to the semiconductor chip 101 placed on the transport stage 102, so it is necessary to cleanly remove the resin from the transport stage 102. If the resin is removed every time it adheres to the stage 102, it is necessary to stop driving the mounting apparatus each time, resulting in problems such as stopping the mounting process for a long time. Even when the resin does not adhere to the transport stage 102, the shape of the transport stage 102 may be transferred to the resin surface of the insulating resin layer 107 due to softening of the resin by heat. In this case, since unevenness is generated on the resin surface of the insulating resin layer 107, there is a possibility that a biting void is likely to occur during mounting, or that the insulation reliability is lowered. On the other hand, in order to prevent melting of the insulating resin layer 107 of the semiconductor chip 101, it is necessary to pick up the semiconductor chip 101 in a state where the suction tool 104 after mounting is sufficiently cooled. Since it takes a considerable amount of time to sufficiently cool the sucked suction tool 104, the efficiency of the mounting operation is remarkably deteriorated due to this cooling time, and it is difficult to achieve the mounting of the target number of semiconductor chips in a short time. Problem arises.

本発明は、上記した問題に着目してなされたもので、半導体チップの実装前に、半導体チップの回路面に予め絶縁性樹脂層を形成しておき、回路基板への実装と同時に半導体チップと回路基板との間の樹脂封止を行うフリップチップ実装方法において、半導体チップを回路基板に効率よく実装することができるフリップチップ実装方法を提供することを目的とする。   The present invention has been made paying attention to the above-described problems. Before mounting the semiconductor chip, an insulating resin layer is formed in advance on the circuit surface of the semiconductor chip, and simultaneously with mounting on the circuit board, An object of the present invention is to provide a flip-chip mounting method capable of efficiently mounting a semiconductor chip on a circuit board in a flip-chip mounting method for performing resin sealing with a circuit board.

本発明の前記目的は、回路面に突起電極を有しかつ前記回路面に絶縁性樹脂層が形成された半導体チップを、前記回路面を下にして支持具上に載置するチップ準備工程と、前記支持具上に載置された前記半導体チップに対して、空気の吸引孔を備えた吸着面を下面に有する吸着手段を上方から近づけ、前記吸着面が前記半導体チップと接触しない位置で、前記吸引孔による空気の吸引により前記半導体チップを前記支持具上からピックアップして前記吸着面に非接触で吸着させるチップピックアップ工程と、前記半導体チップを加熱しながら前記吸着手段により前記半導体チップの前記回路面を回路基板に押圧して、前記回路基板と前記半導体チップとを電気的に接続するチップ実装工程とを備えるフリップチップ実装方法により達成される。   The object of the present invention is to provide a chip preparation step of placing a semiconductor chip having a protruding electrode on a circuit surface and an insulating resin layer formed on the circuit surface on a support with the circuit surface facing down. The suction means having a suction surface with an air suction hole on the lower surface is approached from above with respect to the semiconductor chip placed on the support, and the suction surface is not in contact with the semiconductor chip. A chip pick-up step of picking up the semiconductor chip from above the support by suction of air through the suction hole and sucking the semiconductor chip in a non-contact manner; and heating the semiconductor chip by the suction means while heating the semiconductor chip. This is achieved by a flip chip mounting method comprising a chip mounting step of pressing a circuit surface against a circuit board and electrically connecting the circuit board and the semiconductor chip.

本発明の好ましい実施態様においては、前記チップピックアップ工程において、前記半導体チップのピックアップ時の前記吸着面と前記半導体チップとの距離が０．１ｍｍ〜１ｍｍの範囲であることを特徴としている。   In a preferred embodiment of the present invention, in the chip pickup step, a distance between the suction surface and the semiconductor chip at the time of picking up the semiconductor chip is in a range of 0.1 mm to 1 mm.

本発明のさらに好ましい実施態様においては、前記チップピックアップ工程において、前記半導体チップのピックアップ時の前記吸着手段の温度が１００℃〜２００℃の範囲であることを特徴としている。   In a further preferred aspect of the present invention, in the chip pickup step, the temperature of the suction means when picking up the semiconductor chip is in the range of 100 ° C. to 200 ° C.

本発明のフリップチップ実装方法によれば、吸着手段により支持具上の半導体チップをピックアップする際に、吸着手段を半導体チップに接触させることなく、吸引孔による空気吸引により半導体チップを支持具上から吸い上げて吸着面に吸着させるので、実装後の吸着手段が高い温度に保持されていたとしても、半導体チップに形成された絶縁性樹脂層が溶融して支持具上に付着したり、絶縁性樹脂層に支持具の形状が転写されたりすることを防止できる。さらに、吸着手段を高い温度に保持した状態で半導体チップのピックアップ作業を行うことができるので、実装後の吸着手段の冷却時間を短くすることができ、半導体チップの実装作業を効率よく行うことができる。   According to the flip chip mounting method of the present invention, when the semiconductor chip on the support is picked up by the suction means, the semiconductor chip is removed from the support by air suction through the suction hole without bringing the suction means into contact with the semiconductor chip. Since it is sucked up and adsorbed on the adsorption surface, even if the adsorbing means after mounting is kept at a high temperature, the insulating resin layer formed on the semiconductor chip melts and adheres to the support, or the insulating resin It is possible to prevent the shape of the support from being transferred to the layer. Furthermore, since the pick-up operation of the semiconductor chip can be performed with the suction means held at a high temperature, the cooling time of the suction means after mounting can be shortened, and the semiconductor chip mounting work can be performed efficiently. it can.

本発明の一実施形態であるフリップチップ実装方法を用いた半導体装置の製造方法の手順を説明する模式図である。It is a schematic diagram explaining the procedure of the manufacturing method of the semiconductor device using the flip chip mounting method which is one Embodiment of this invention. 第１工程を示す図である。It is a figure which shows a 1st process. 第２工程を示す図である。It is a figure which shows a 2nd process. チップピックアップ工程を示す図である。It is a figure which shows a chip pick-up process. チップ実装工程を示す図である。It is a figure which shows a chip mounting process. チップ実装工程を示す図である。It is a figure which shows a chip mounting process. チップ実装工程を示す図である。It is a figure which shows a chip mounting process. チップ実装工程を示す図である。It is a figure which shows a chip mounting process. 吸着ツールの冷却に要する時間を示すグラフである。It is a graph which shows the time which cooling of a suction tool requires. 従来のフリップチップ実装方法の手順を説明する模式図である。It is a schematic diagram explaining the procedure of the conventional flip chip mounting method.

以下、本発明に係るフリップチップ実装方法の好適な実施形態について、添付図面を参照しながら説明する。図１は、本発明の一実施形態に係るフリップチップ実装方法を用いた半導体装置の製造工程の手順を説明する模式図を示している。この半導体装置の製造方法においては、まず、半導体ウェハ１が用意される（第１工程）。半導体ウェハ１は、例えば、シリコン、ガリウム砒素などの半導体からなり、例えば円板状を有している。半導体ウェハ１の一方の面の回路面Ｓには、図２に示すように、例えば金、銅、銀−錫半田、アルミニウム、ニッケルなどによって形成された突起電極（バンプ）２が所定のピッチで複数設けられている。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a flip chip mounting method according to the invention will be described with reference to the accompanying drawings. FIG. 1 is a schematic diagram illustrating a procedure of a manufacturing process of a semiconductor device using a flip chip mounting method according to an embodiment of the present invention. In this semiconductor device manufacturing method, first, a semiconductor wafer 1 is prepared (first step). The semiconductor wafer 1 is made of a semiconductor such as silicon or gallium arsenide, and has a disk shape, for example. On the circuit surface S on one surface of the semiconductor wafer 1, as shown in FIG. 2, protruding electrodes (bumps) 2 made of, for example, gold, copper, silver-tin solder, aluminum, nickel, etc. are formed at a predetermined pitch. A plurality are provided.

次に、この半導体ウェハ１の突起電極２が設けられた回路面（以下、「突起電極側面」ともいう。）Ｓ上に、図３に示すように、絶縁性樹脂層３を形成する作業が行われる（第２工程）。絶縁性樹脂層３は、後述する半導体チップ１０の回路基板４への実装時に、半導体チップ１０と回路基板４との間の空隙を樹脂封止するためのものであり、例えばフィルム状樹脂をロールラミネータや真空ラミネータなどで半導体ウェハ１の回路面Ｓに貼り合わせることによって形成することができる。この他、絶縁性樹脂層３は、例えばペースト状樹脂を印刷法やスピンコート法などによって半導体ウェハ１の突起電極側面Ｓに塗布し、これを乾燥させることによっても形成することができる。   Next, as shown in FIG. 3, an operation of forming an insulating resin layer 3 on a circuit surface (hereinafter also referred to as “projection electrode side surface”) S on which the protruding electrode 2 of the semiconductor wafer 1 is provided is performed. Performed (second step). The insulating resin layer 3 is for resin-sealing a gap between the semiconductor chip 10 and the circuit board 4 when mounting the semiconductor chip 10 to be described later on the circuit board 4. For example, a film-like resin is rolled. It can be formed by bonding to the circuit surface S of the semiconductor wafer 1 with a laminator or a vacuum laminator. In addition, the insulating resin layer 3 can also be formed by applying a paste-like resin to the protruding electrode side surface S of the semiconductor wafer 1 by, for example, a printing method or a spin coating method and drying it.

絶縁性樹脂層３を形成する材料としては、特に限定はされないが、例えば、エポキシ樹脂と硬化剤とを含有していることが好ましい。エポキシ樹脂としては、特に限定されないが、多環式炭化水素骨格を主鎖に有するエポキシ樹脂を含有することが好ましい。上記多環式炭化水素骨格を主鎖に有するエポキシ樹脂を含有することで、絶縁性樹脂層３により形成される半導体チップ１０と回路基板４との間の封止樹脂（以下、単に「封止樹脂」という。）は、剛直で分子の運動が阻害されるため、優れた機械的強度および耐熱性を発揮する。上記多環式炭化水素骨格を主鎖に有するエポキシ樹脂としては、特に限定されないが、例えば、ジシクロペンタジエンジオキシド、ジシクロペンタジエン骨格を有するフェノールノボラックエポキシ樹脂等のジシクロペンタジエン骨格を有するエポキシ樹脂（以下、「ジシクロペンタジエン型エポキシ樹脂」ともいう。）、１−グリシジルナフタレン、２−グリシジルナフタレン、１，２−ジグリジジルナフタレン、１，５−ジグリシジルナフタレン、１，６−ジグリシジルナフタレン、１，７−ジグリシジルナフタレン、２，７−ジグリシジルナフタレン、トリグリシジルナフタレン、１，２，５，６−テトラグリシジルナフタレン等のナフタレン骨格を有するエポキシ樹脂（以下、「ナフタレン型エポキシ樹脂」ともいう。）、テトラヒドロキシフェニルエタン型エポキシ樹脂、テトラキス（グリシジルオキシフェニル）エタン、３，４−エポキシ−６−メチルシクロヘキシルメチル−３，４−エポキシ−６−メチルシクロヘキサンカルボネートなどが挙げられる。中でも、ジシクロペンタジエン型エポキシ樹脂、ナフタレン型エポキシ樹脂、アントラセン型エポキシ樹脂を好ましく挙げることができる。   Although it does not specifically limit as a material which forms the insulating resin layer 3, For example, it is preferable to contain an epoxy resin and a hardening | curing agent. Although it does not specifically limit as an epoxy resin, It is preferable to contain the epoxy resin which has a polycyclic hydrocarbon skeleton in a principal chain. By containing an epoxy resin having the above-mentioned polycyclic hydrocarbon skeleton in the main chain, a sealing resin (hereinafter simply referred to as “sealing”) between the semiconductor chip 10 formed by the insulating resin layer 3 and the circuit board 4. Resin ”) is rigid and inhibits the movement of molecules, and therefore exhibits excellent mechanical strength and heat resistance. The epoxy resin having the polycyclic hydrocarbon skeleton in the main chain is not particularly limited. For example, an epoxy resin having a dicyclopentadiene skeleton such as dicyclopentadiene dioxide and a phenol novolac epoxy resin having a dicyclopentadiene skeleton. (Hereinafter also referred to as “dicyclopentadiene type epoxy resin”), 1-glycidylnaphthalene, 2-glycidylnaphthalene, 1,2-diglycidylnaphthalene, 1,5-diglycidylnaphthalene, 1,6-diglycidylnaphthalene, Epoxy resins having a naphthalene skeleton such as 1,7-diglycidylnaphthalene, 2,7-diglycidylnaphthalene, triglycidylnaphthalene, 1,2,5,6-tetraglycidylnaphthalene (hereinafter also referred to as “naphthalene type epoxy resin”) ), Tetrahi B hydroxyphenyl ethane type epoxy resins, tetrakis (glycidyloxyphenyl) ethane, etc. 3,4-epoxy-6-methylcyclohexyl-3,4-epoxy-6-methylcyclohexane carbonate and the like. Among these, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, and anthracene type epoxy resin can be preferably exemplified.

また、絶縁性樹脂層３を形成する材料には、上記エポキシ樹脂と反応可能な官能基を有する高分子化合物を含有してもよい。上記した高分子化合物は、造膜成分としての役割を果たす。また、上記した高分子化合物を含有することで、絶縁性樹脂層３により形成される封止樹脂は靭性をもち、優れた耐衝撃性を発揮することができる。上記した高分子化合物としては、特に限定されないが、例えば、アミノ基、ウレタン基、イミド基、水酸基、カルボキシル基、エポキシ基などを有する高分子化合物が挙げられる。中でも、エポキシ基を有する高分子化合物が好ましく、エポキシ基を有する高分子化合物を含有することで、絶縁性樹脂層３により形成される封止樹脂は、上記したエポキシ樹脂に由来する優れた機械的強度、耐熱性および耐湿性と、上記したエポキシ基を有する高分子化合物に由来する優れた靭性とを兼備するため、得られる半導体チップ積層体は、耐冷熱サイクル性、耐ハンダリフロー性、寸法安定性などに優れるものとなり、高い接合信頼性および接続信頼性を発揮する。さらに、絶縁性樹脂層３を形成する材料は、ベンゾオキサジン化合物やエピスルフィド化合物を含有していてもよい。   The material forming the insulating resin layer 3 may contain a polymer compound having a functional group capable of reacting with the epoxy resin. The polymer compound described above plays a role as a film forming component. Moreover, by containing the above-described polymer compound, the sealing resin formed by the insulating resin layer 3 has toughness and can exhibit excellent impact resistance. Although it does not specifically limit as an above-described high molecular compound, For example, the high molecular compound which has an amino group, a urethane group, an imide group, a hydroxyl group, a carboxyl group, an epoxy group etc. is mentioned. Among them, a polymer compound having an epoxy group is preferable. By containing the polymer compound having an epoxy group, the sealing resin formed by the insulating resin layer 3 has excellent mechanical properties derived from the above-described epoxy resin. In order to combine strength, heat resistance and moisture resistance with the excellent toughness derived from the above-mentioned polymer compound having an epoxy group, the resulting semiconductor chip laminate has cold cycle resistance, solder reflow resistance, and dimensional stability. It exhibits superior bonding reliability and high connection reliability. Furthermore, the material forming the insulating resin layer 3 may contain a benzoxazine compound or an episulfide compound.

また、硬化剤としては、特に限定されないが、フェノール系硬化剤、酸無水物硬化剤、イミダゾール系硬化剤などを好ましく挙げることができる。これらは、単独または二種以上の混合物として使用することができる。   Moreover, it does not specifically limit as a hardening | curing agent, However, A phenol type hardening | curing agent, an acid anhydride hardening | curing agent, an imidazole type hardening | curing agent etc. can be mentioned preferably. These can be used alone or as a mixture of two or more.

上記した構成の絶縁性樹脂層３において、１００℃〜２００℃の温度範囲内に最低溶融粘度が存在し、最低溶融粘度が、１０Ｐａ・ｓ〜１００，０００Ｐａ・ｓの範囲内にある絶縁性樹脂層３をより好適に用いることができる。本発明に係るフリップチップ実装方法を用いることにより、たとえ溶融粘度が低い樹脂であっても、効率よく実装することができる。   In the insulating resin layer 3 having the above-described configuration, the minimum melt viscosity exists in the temperature range of 100 ° C. to 200 ° C., and the minimum melt viscosity is in the range of 10 Pa · s to 100,000 Pa · s. The layer 3 can be used more suitably. By using the flip chip mounting method according to the present invention, even a resin having a low melt viscosity can be mounted efficiently.

図１に戻って、次に、絶縁性樹脂層３が突起電極側面Ｓ上に形成された半導体ウェハ１を、必要に応じて接着シートなどに固定して、その裏面（突起電極側面Ｓとは反対の面）を研削して所望の厚さまで薄化した後、絶縁性樹脂層３も含めてダイシングして、複数の半導体チップ１０に個片化する作業が行われる（第３工程）。上記ダイシングの方法としては、特に限定されないが、例えば、従来公知のダイヤモンド製の回転砥石９などを用いて切断分離する方法やレーザーダイシング法などを用いることができる。   Returning to FIG. 1, next, the semiconductor wafer 1 on which the insulating resin layer 3 is formed on the protruding electrode side surface S is fixed to an adhesive sheet or the like as necessary, and the back surface (the protruding electrode side surface S is defined as After the opposite surface) is ground and thinned to a desired thickness, the work including dicing the insulating resin layer 3 and dividing it into a plurality of semiconductor chips 10 is performed (third step). The dicing method is not particularly limited. For example, a method of cutting and separating using a conventionally known diamond rotating grindstone 9 or the like, a laser dicing method, or the like can be used.

次に、複数の個片に分割された半導体チップ１０のうち、その１つがチップ供給装置５によって取り出されると、次に、チップ供給装置５から支持具６への半導体チップ１０の受け渡し作業が行われる（第４工程、チップ準備工程）。支持具６は、上下方向に昇降動作可能であるとともに、上下反転して実装用装置の吸着ツール７との間を往復動作可能に構成されており、半導体チップ１０を吸着保持できるように、その表面には吸引孔（図示せず）が形成されている。この吸引孔には、図示しない配管を介してポンプと接続されており、支持具６の表面を上方から半導体チップ１０の突起電極側面Ｓに接触させて、ポンプにより前記吸引孔に吸引力を作用させることで、半導体チップ１０を支持具６の表面に吸着させることができる。このように、支持具６への半導体チップ１０の受け渡しが完了すると、次に、支持具６を上下反転させることで、半導体チップ１０は突起電極側面Ｓを下にして支持具６上に載置され、この状態で、支持具６を実装用装置の吸着ツール７の下方に移送する。   Next, when one of the semiconductor chips 10 divided into a plurality of pieces is taken out by the chip supply device 5, next, the semiconductor chip 10 is transferred from the chip supply device 5 to the support 6. (4th process, chip preparation process). The support 6 can be moved up and down in the vertical direction, and can be moved up and down to reciprocate between the suction tool 7 of the mounting apparatus, so that the semiconductor chip 10 can be sucked and held. A suction hole (not shown) is formed on the surface. The suction hole is connected to a pump via a pipe (not shown). The surface of the support 6 is brought into contact with the protruding electrode side surface S of the semiconductor chip 10 from above, and a suction force is applied to the suction hole by the pump. By doing so, the semiconductor chip 10 can be adsorbed on the surface of the support 6. Thus, when the delivery of the semiconductor chip 10 to the support 6 is completed, the support 6 is then turned upside down, so that the semiconductor chip 10 is placed on the support 6 with the protruding electrode side S facing down. In this state, the support 6 is transferred below the suction tool 7 of the mounting apparatus.

吸着ツール７は、例えばセラミックなどの良好な熱伝導性を有する材料により形成されており、上下方向に昇降動作可能であるとともに、回路基板４を吸着保持する実装用装置のボンディングステージ８との間を往復動作可能に構成されている。吸着ツール７の下面には、図４に示すように、吸引孔７０が形成されている。この吸引孔７０には、図示しない配管を介してポンプと接続されており、ポンプによる空気吸引によって吸引孔７０に吸引力を発生させることができるようになっている。   The suction tool 7 is made of, for example, a material having good thermal conductivity such as ceramic, can be moved up and down in the vertical direction, and between the bonding stage 8 of the mounting apparatus that holds the circuit board 4 by suction. Are configured to be capable of reciprocating. As shown in FIG. 4, a suction hole 70 is formed on the lower surface of the suction tool 7. The suction hole 70 is connected to a pump via a pipe (not shown) so that a suction force can be generated in the suction hole 70 by air suction by the pump.

支持具６が吸着ツール７の下方に移送されると、図１および図４に示すように、次に、吸着ツール７による半導体チップ１０のピックアップ作業が行われる（第５工程、チップピックアップ工程）。支持具６上に載置された半導体チップ１０に対して、吸着ツール７を上方から近づけると同時に、ポンプを駆動して吸着ツール下面の吸引孔７０に吸引力を発生させることで、支持具６上の半導体チップ１０は突起電極側面Ｓが下方を向いた状態で吸着ツール７の下面（吸着面）に吸着される。このとき、本実施形態では、前記ポンプの駆動を制御して、吸着ツール７の吸着面の吸引孔７０に発生させる吸引力の大きさ（吸引孔により吸引する空気吸引量）を調整することによって、吸着ツール７の吸着面が、半導体チップ１０の裏面とは全く接触しない半導体チップ１０の裏面よりも上方に位置した状態で、吸引孔７０による吸引作用により半導体チップ１０を支持具６上から吸い上げ、これを非接触で該吸着面に吸着させることで、半導体チップ１０のピックアップができるように構成されている。   When the support 6 is transferred below the suction tool 7, as shown in FIGS. 1 and 4, the semiconductor chip 10 is then picked up by the suction tool 7 (fifth step, chip pickup step). . The suction tool 7 is brought closer to the semiconductor chip 10 placed on the support tool 6 from above, and at the same time, the pump is driven to generate a suction force in the suction hole 70 on the lower surface of the suction tool. The upper semiconductor chip 10 is attracted to the lower surface (suction surface) of the suction tool 7 with the protruding electrode side S facing downward. At this time, in this embodiment, by controlling the driving of the pump, the magnitude of the suction force generated in the suction hole 70 on the suction surface of the suction tool 7 (the amount of air sucked by the suction hole) is adjusted. In the state where the suction surface of the suction tool 7 is located above the back surface of the semiconductor chip 10 that is not in contact with the back surface of the semiconductor chip 10, the semiconductor chip 10 is sucked up from the support 6 by the suction action by the suction hole 70. The semiconductor chip 10 can be picked up by adsorbing it to the adsorption surface in a non-contact manner.

上記した半導体チップ１０のピックアップ時における吸着ツール７の吸着面と半導体チップ１０の裏面との距離Ｄ（図４に示す）としては、０．１ｍｍ〜１ｍｍの範囲内にあることが好ましい。上記した距離Ｄが、１ｍｍよりも大きいと、半導体チップ１０を吸着できず吸着エラーが生じる場合がある。これを防ぐために、吸引孔７０に発生させる吸引力を大きくした場合、半導体チップ１０が勢いよく吸着ツール７の吸着面に吸着されるので、半導体チップ１０に破損などが生じたり、半導体チップ１０が大幅にずれた状態で吸着ツール７の吸着面に吸引され、アライメント時にエラーが生じたりする場合がある。一方、上記した距離Ｄが、０．１ｍｍよりも小さいと、ピックアップ時に吸着ツール７が半導体チップ１０に近づき過ぎてしまい、その結果、詳細は後述するが、吸着ツール７の温度が高い温度に設定されていると、この輻射熱によって半導体チップ１０の回路面Ｓに形成された絶縁樹脂層３が溶融し、この溶融した樹脂が垂れ下がって下方の支持具６の表面に付着してこれを汚染したり、絶縁性樹脂層３に支持具６の形状が転写されたりするおそれがある。よって、ピックアップ時の吸着ツール７の吸着面と半導体チップ１０の裏面との距離Ｄは、０．１ｍｍ〜１ｍｍの範囲内にあることが好ましく、さらに言えば、０．２ｍｍ〜０．８ｍｍの範囲内にあることがより好ましい。   The distance D (shown in FIG. 4) between the suction surface of the suction tool 7 and the back surface of the semiconductor chip 10 when the semiconductor chip 10 is picked up is preferably in the range of 0.1 mm to 1 mm. If the distance D is larger than 1 mm, the semiconductor chip 10 cannot be sucked and a suction error may occur. In order to prevent this, when the suction force generated in the suction hole 70 is increased, the semiconductor chip 10 is vigorously attracted to the suction surface of the suction tool 7, so that the semiconductor chip 10 is damaged or the semiconductor chip 10 is In some cases, the suction is caused by the suction surface of the suction tool 7 in a state of being largely displaced, and an error may occur during alignment. On the other hand, if the distance D is smaller than 0.1 mm, the suction tool 7 gets too close to the semiconductor chip 10 during pick-up, and as a result, the temperature of the suction tool 7 is set to a high temperature, as will be described in detail later. If so, the insulating resin layer 3 formed on the circuit surface S of the semiconductor chip 10 is melted by the radiant heat, and the melted resin hangs down and adheres to the surface of the lower support 6 to contaminate it. The shape of the support 6 may be transferred to the insulating resin layer 3. Therefore, the distance D between the suction surface of the suction tool 7 and the back surface of the semiconductor chip 10 at the time of pickup is preferably within a range of 0.1 mm to 1 mm, and more specifically, a range of 0.2 mm to 0.8 mm. More preferably, it is within.

なお、半導体チップ１０のピックアップ時に、吸着ツール７の吸着面の吸引孔７０に発生させる吸引力の大きさ（吸引孔により吸引する空気の吸引量）としては、吸着ツール７に設けられた吸引孔７０の数や形状、半導体チップ１０の大きさや重さ、また、ピックアップ時の吸着ツール７の吸着面と半導体チップ１０の裏面との距離などに応じて、適宜調整される。   The suction force generated in the suction hole 70 on the suction surface of the suction tool 7 when the semiconductor chip 10 is picked up (the suction amount of air sucked by the suction hole) is the suction hole provided in the suction tool 7. The number is adjusted as appropriate according to the number and shape of 70, the size and weight of the semiconductor chip 10, and the distance between the suction surface of the suction tool 7 and the back surface of the semiconductor chip 10 at the time of pickup.

半導体チップ１０が吸着ツール７に吸着されて、支持具６上からピックアップされると、次に、図１および図５〜図７に示すように、吸着ツール７をボンディングステージ８上に移送して、半導体チップ１０を回路基板４にボンディングする作業が行われる（第６工程、チップ実装工程）。ボンディングステージ８は、水平方向またはθ方向に位置調整できるようになっている。ボンディングステージ８には、回路面Ｓ´が上方を向くようにして回路基板４が載置されている。回路基板４の回路面Ｓ´には、例えば銅電極、または銅表面に錫めっき（あるいはニッケル表面に金めっき）が施された複数の電極４０が形成されており、吸着ツール７および／またはボンディングステージ８の位置を調整することで、半導体チップ１０の突起電極２を回路基板４の電極４０に対して位置合わせできるようになっている。この位置合わせは、図５に示す認識カメラ１１を用いることにより行われる。認識カメラ１１は、吸着ツール７とボンディングステージ８との間に挿入されるように往復動可能であり、半導体チップ１の突起電極側面Ｓおよび回路基板４の回路面Ｓ´にそれぞれ対応するように設けられたアライメントマーク（図示せず）を画像認識することができるように構成されている。認識カメラ１１が半導体チップ１と回路基板４との間に挿入され、各々のアライメントマークが認識カメラ１１により認識されると、検出された画像認識データに基づき、各々のアライメントマークが予め規定された位置関係となるように吸着ツール７またはボンディングステージ８の位置を調整することで、半導体チップ１０の突起電極２と回路基板４の電極４０とのアライメントが行われるようになっている。なお、この半導体チップ１０の突起電極２と回路基板４の電極４０とのアライメントにおいて、絶縁性樹脂層３は、ある程度の透明性を有していることが好ましい。具体的には、ヘイズ値が７５％以下、より好適には７０％以下であることが好ましい。   When the semiconductor chip 10 is attracted to the suction tool 7 and picked up from the support 6, the suction tool 7 is then transferred onto the bonding stage 8 as shown in FIGS. 1 and 5 to 7. Then, an operation of bonding the semiconductor chip 10 to the circuit board 4 is performed (sixth step, chip mounting step). The position of the bonding stage 8 can be adjusted in the horizontal direction or the θ direction. The circuit board 4 is placed on the bonding stage 8 so that the circuit surface S ′ faces upward. On the circuit surface S ′ of the circuit board 4, for example, a copper electrode or a plurality of electrodes 40 with a tin plating on the copper surface (or a gold plating on the nickel surface) are formed, and the suction tool 7 and / or bonding is performed. By adjusting the position of the stage 8, the protruding electrode 2 of the semiconductor chip 10 can be aligned with the electrode 40 of the circuit board 4. This alignment is performed by using the recognition camera 11 shown in FIG. The recognition camera 11 can reciprocate so as to be inserted between the suction tool 7 and the bonding stage 8, and corresponds to the protruding electrode side surface S of the semiconductor chip 1 and the circuit surface S ′ of the circuit board 4. An image of a provided alignment mark (not shown) can be recognized. When the recognition camera 11 is inserted between the semiconductor chip 1 and the circuit board 4 and each alignment mark is recognized by the recognition camera 11, each alignment mark is defined in advance based on the detected image recognition data. By adjusting the position of the suction tool 7 or the bonding stage 8 so as to be in a positional relationship, the protruding electrode 2 of the semiconductor chip 10 and the electrode 40 of the circuit board 4 are aligned. In the alignment between the protruding electrode 2 of the semiconductor chip 10 and the electrode 40 of the circuit board 4, it is preferable that the insulating resin layer 3 has a certain degree of transparency. Specifically, the haze value is preferably 75% or less, more preferably 70% or less.

半導体チップ１０と回路基板４との位置合わせの後、半導体チップ１０を吸着保持させたまま吸着ツール７を下降させることで、半導体チップ１０の突起電極側面Ｓを回路基板４の回路面Ｓ´に接触させる。半導体チップ１０が回路基板４０に接触すると、吸着ツール７によって半導体チップ１０の突起電極側面Ｓを回路基板４の回路面Ｓ´に押圧しながら、吸着ツール７を図示しない加熱手段により予め設定されている加熱温度（約２２０℃〜３２０℃）まで加熱して、半導体チップ１０を加熱することで、半導体チップ１０と回路基板４とのボンディングが開始される。これにより、図７に示すように、半導体チップ１０の突起電極２と回路基板４の電極４０とが電気的に接続されると同時に、絶縁性樹脂層３が加熱によって溶融し、半導体チップ１０と回路基板４との間の空隙が絶縁性樹脂層３によって樹脂封止される。所定の時間の加圧および加熱により、半導体チップ１０と回路基板４とのボンディングが完了すると、吸着ツール７による半導体チップ１０の吸着保持が解除され、図８に示すように、吸着ツール７は上昇し待機位置に戻る。なお、半導体チップ１０の加熱ボンディングにあたっては、ボンディングステージ８を一定温度に加熱しながら行ってもよい。このとき、ボンディングステージ８の加熱温度としては、７０℃〜１５０℃程度であることが好ましい。   After the alignment of the semiconductor chip 10 and the circuit board 4, the suction tool 7 is lowered while the semiconductor chip 10 is held by suction, so that the protruding electrode side surface S of the semiconductor chip 10 becomes the circuit surface S ′ of the circuit board 4. Make contact. When the semiconductor chip 10 comes into contact with the circuit board 40, the suction tool 7 is preset by a heating means (not shown) while pressing the protruding electrode side surface S of the semiconductor chip 10 against the circuit surface S 'of the circuit board 4 by the suction tool 7. By heating to the heating temperature (about 220 ° C. to 320 ° C.) and heating the semiconductor chip 10, bonding between the semiconductor chip 10 and the circuit board 4 is started. As a result, as shown in FIG. 7, the protruding electrode 2 of the semiconductor chip 10 and the electrode 40 of the circuit board 4 are electrically connected, and at the same time, the insulating resin layer 3 is melted by heating, and the semiconductor chip 10 The gap between the circuit board 4 and the circuit board 4 is resin-sealed by the insulating resin layer 3. When the bonding between the semiconductor chip 10 and the circuit board 4 is completed by pressurization and heating for a predetermined time, the suction holding of the semiconductor chip 10 by the suction tool 7 is released, and the suction tool 7 is raised as shown in FIG. Return to the standby position. Note that the semiconductor chip 10 may be heated and bonded while the bonding stage 8 is heated to a constant temperature. At this time, the heating temperature of the bonding stage 8 is preferably about 70 ° C. to 150 ° C.

吸着ツール７が、ボンディングステージ８上方の待機位置に戻ると、図１に示すように、吸着ツール７は再び、支持具６上方に移送され、支持具６から次の新たな半導体チップ１０を同様に非接触で吸い上げてピックアップする。このとき、吸着ツール７は、上記したチップ実装工程において、半導体チップ１０と回路基板４とのボンディングのために、約２２０℃〜３２０℃の高温に加熱されているので、この熱によって、半導体チップ１０ピックアップ時に、支持具６上の半導体チップ１０の絶縁樹脂層３の溶融を防ぐためには、予め、実装後の吸着ツール７を冷却する必要がある。ここで、従来技術のように、吸着ツール７の吸着面を半導体チップ１０の裏面に、一旦、完全に接触させた上で半導体チップ１０をピックアップする方法では、ピックアップ時（つまりは、吸着ツール７と半導体チップ１０との接触時）に、吸着ツール７の熱が支持具６上の半導体チップ１０に直に伝わって樹脂が溶融し、これが支持具６上に垂れ落ちるおそれがある。そのため、絶縁性樹脂層３の溶融を防止できる温度（例えば４０℃〜１００℃程度）まで吸着ツール７を十分に冷却させる必要があるが、図９に示すように、実装時に３００℃近くまで加熱された吸着ツール７を、例えば６０℃まで冷却するためには、約１０秒程度の時間がかかるため、この冷却時間の分だけ、従来技術の方法では、新たな半導体チップ１０の回路基板４への実装作業が遅れることになる。   When the suction tool 7 returns to the standby position above the bonding stage 8, as shown in FIG. 1, the suction tool 7 is transferred again above the support tool 6, and the next new semiconductor chip 10 is similarly transferred from the support tool 6. Suck up and pick up without contact. At this time, the suction tool 7 is heated to a high temperature of about 220 ° C. to 320 ° C. for bonding the semiconductor chip 10 and the circuit board 4 in the above chip mounting process. In order to prevent melting of the insulating resin layer 3 of the semiconductor chip 10 on the support 6 during 10 pick-up, it is necessary to cool the suction tool 7 after mounting in advance. Here, as in the prior art, in the method of picking up the semiconductor chip 10 once the suction surface of the suction tool 7 is brought into full contact with the back surface of the semiconductor chip 10 at the time of pickup (that is, the suction tool 7). When the suction tool 7 is in contact with the semiconductor chip 10), the heat of the suction tool 7 is directly transmitted to the semiconductor chip 10 on the support 6 and the resin is melted, which may drop on the support 6. Therefore, it is necessary to sufficiently cool the suction tool 7 to a temperature at which the insulating resin layer 3 can be prevented from melting (for example, about 40 ° C. to 100 ° C.). However, as shown in FIG. For example, it takes about 10 seconds to cool the sucked tool 7 to 60 ° C., for example, so that the conventional method uses the circuit board 4 of the new semiconductor chip 10 for this cooling time. Implementation work will be delayed.

これに対して、本実施形態においては、上記したように、吸着ツール７は、その吸着面が半導体チップ１０の裏面とは全く接触しない非接触の状態で、半導体チップ１０を支持具６上から吸い上げてピックアップするから、このピックアップ時には、吸着ツール７の熱が支持具６上の半導体チップ１０には直接的には伝わらない。よって、ピックアップ時の吸着ツール７の温度が比較的高い温度に設定されていたとしても、支持具６上で半導体チップ１０の絶縁性樹脂層３が溶融することはなく、これが支持具６上に垂れ落ちるおそれがないので、吸着ツール７の冷却時間を短縮させることができる。本実施形態におけるピックアップ時の吸着ツール７の温度（吸着面の温度）としては、例えば、１００℃から最高で２００℃程度にまで設定することが可能である。これにより、図９に示すように、３００℃近くの吸着ツール７を、例えば１５０℃まで冷却するのにかかる時間としては、約３秒程度であるため、本実施形態では、従来技術と比べると、実装後の吸着ツール７の冷却時間を大幅に短縮することができる。よって、次々に半導体チップ１０をピックアップして回路基板４に実装できるので、実装タクトタイムを短縮することができ、半導体チップ１０の実装作業を効率よく行うことができる。   On the other hand, in the present embodiment, as described above, the suction tool 7 allows the semiconductor chip 10 to be removed from above the support 6 in a non-contact state where the suction surface does not contact the back surface of the semiconductor chip 10 at all. Since the suction is picked up and picked up, the heat of the suction tool 7 is not directly transmitted to the semiconductor chip 10 on the support 6 at the time of picking up. Therefore, even if the temperature of the suction tool 7 at the time of pick-up is set to a relatively high temperature, the insulating resin layer 3 of the semiconductor chip 10 is not melted on the support tool 6, and this is on the support tool 6. Since there is no possibility of dripping, the cooling time of the suction tool 7 can be shortened. The temperature of the suction tool 7 at the time of pickup in this embodiment (temperature of the suction surface) can be set, for example, from 100 ° C. up to about 200 ° C. As a result, as shown in FIG. 9, the time taken to cool the suction tool 7 close to 300 ° C. to, for example, 150 ° C. is about 3 seconds, so in this embodiment, compared to the prior art. The cooling time of the suction tool 7 after mounting can be greatly shortened. Therefore, since the semiconductor chips 10 can be picked up one after another and mounted on the circuit board 4, the mounting tact time can be shortened, and the mounting work of the semiconductor chips 10 can be performed efficiently.

上記したとおり、本実施形態に係るフリップチップ実装方法（第４工程〜第６工程）では、吸着ツール７により支持具６上の半導体チップ１０をピックアップする際に、吸着ツール７の吸着面が半導体チップ１０の裏面と接触しない所定の間隔をあけた状態で、半導体チップ１０を支持具６上から吸い上げて非接触で吸着面に吸着されるように、前記吸着面の吸引孔７０に発生させる吸引力の大きさ（吸引孔により吸引する空気吸引量）を調整するから、実装後の高温に加熱された吸着ツール７が比較的高い温度状態であっても、支持具６上の半導体チップ１０を不具合なくピックアップすることができるので、実装後の吸着ツール７の冷却時間を短くすることができ、優れた半導体チップ１０の実装効率を実現できる。   As described above, in the flip chip mounting method (fourth to sixth steps) according to the present embodiment, when the semiconductor chip 10 on the support 6 is picked up by the suction tool 7, the suction surface of the suction tool 7 is a semiconductor. Suction generated in the suction hole 70 of the suction surface so that the semiconductor chip 10 is sucked up from above the support 6 and is suctioned to the suction surface in a non-contact manner with a predetermined interval not contacting the back surface of the chip 10. Since the magnitude of the force (the amount of air sucked through the suction holes) is adjusted, the semiconductor chip 10 on the support 6 can be moved even when the suction tool 7 heated to a high temperature after mounting is in a relatively high temperature state. Since it can be picked up without any trouble, the cooling time of the suction tool 7 after mounting can be shortened, and excellent mounting efficiency of the semiconductor chip 10 can be realized.

以下に実施例を掲げて本発明をさらに詳しく説明するが、本発明はこの実施例のみに限定されない。絶縁性樹脂層の材料としては、下記に示す各材料（１）〜（８）を、固形分濃度５０重量％となるようにメチルエチルケトンに加え、ホモディスパーを用いて攪拌混合することにより調整した。得られた配合液を、５μｍメッシュで遠心濾過した後、離型処理したＰＥＴフィルム上にアプリケーター（テスター産業社製）を用いて塗工し、１００℃５分で乾燥させて、厚み４０μｍのフィルム状絶縁性樹脂を得た。
（１）エポキシ樹脂
・ＨＰ−７２００（ジシクロペンタジエン型エポキシ樹脂、ＤＩＣ社製）
・ＥＸＡ−４７１０（ナフタレン型エポキシ樹脂、ＤＩＣ社製）
（２）エポキシ基を有する高分子化合物
・Ｇ−２０５０Ｍ（グリシジル基含有アクリル樹脂、重量平均分子量２０万、エポキシ当量３４０、日油社製）
（３）硬化剤
・ＹＨ−３０９（ビシクロ骨格を有する酸無水物、三菱化学社製）
（５）硬化促進剤
・フジキュア７０００（液状イミダゾール、Ｔ＆Ｋ ＴＯＫＡ社製）
（６）接着性付与剤
・エポキシシランカップリング剤（ＫＢＭ−４０３、信越化学社製）
（７）チキソトロピー付与剤
・ＡＣ４０３０（応力緩和ゴム系高分子、ガンツ化成社製）
（８）シリカフィラー
・ＳＥ−１０５０−ＳＰＴ（フェニルトリメトキシシラン表面処理球状シリカ、平均粒子径０．３μｍ、アドマテックス社製）
・ＳＸ００９−ＭＪＦ（フェニルトリメトキシシラン表面処理球状シリカ、平均粒子径０．０５μｍ、アドマテックス社製） Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited to these examples. As the material for the insulating resin layer, the following materials (1) to (8) were added to methyl ethyl ketone so as to have a solid content concentration of 50% by weight, and the mixture was stirred and mixed using a homodisper. The resulting blended solution is subjected to centrifugal filtration with a 5 μm mesh, and then coated on a release-treated PET film using an applicator (manufactured by Tester Sangyo Co., Ltd.), dried at 100 ° C. for 5 minutes, and a film having a thickness of 40 μm. An insulating resin was obtained.
(1) Epoxy resin HP-7200 (Dicyclopentadiene type epoxy resin, manufactured by DIC)
EXA-4710 (Naphthalene type epoxy resin, manufactured by DIC)
(2) Polymer compound having an epoxy group G-2050M (glycidyl group-containing acrylic resin, weight average molecular weight 200,000, epoxy equivalent 340, manufactured by NOF Corporation)
(3) Curing agent YH-309 (an acid anhydride having a bicyclo skeleton, manufactured by Mitsubishi Chemical Corporation)
(5) Curing accelerator-Fujicure 7000 (liquid imidazole, manufactured by T & K TOKA)
(6) Adhesiveness imparting agent ・ Epoxysilane coupling agent (KBM-403, manufactured by Shin-Etsu Chemical Co., Ltd.)
(7) Thixotropic agent AC4030 (stress relaxation rubber polymer, manufactured by Ganz Kasei Co., Ltd.)
(8) Silica filler SE-1050-SPT (Phenyltrimethoxysilane surface-treated spherical silica, average particle size 0.3 μm, manufactured by Admatechs)
SX009-MJF (phenyltrimethoxysilane surface-treated spherical silica, average particle size 0.05 μm, manufactured by Admatechs)

直径３０ｃｍおよび厚み７５０μｍであり、表面に、高さ３０μｍおよび直径３０μｍの円形状の銅ピラー電極の上に高さ１５μｍの半田電極が形成された、トータル高さ４５μｍの突起電極（バンプ）が５０μｍピッチで多数形成されている半導体ウェハ（シリコンウェハ）を用意し、この半導体ウェハの突起電極側面に、上記した方法により作製したフィルム状絶縁性樹脂を、真空ラミネーターによって貼り合わせることによって絶縁性樹脂層を形成した。これを半導体ウェハの厚さが約１００μｍになるまで研削した後、ダイシング装置（ＤＦＤ６３６１：ＤＩＳＣＯ社製）を用いて、送り速度５０ｍｍ／秒で、半導体ウェハを７ｍｍ×７ｍｍのチップサイズに分割して、半導体チップを得た。   A bump electrode having a total height of 45 μm is formed by forming a solder electrode having a height of 15 μm on a surface of a circular copper pillar electrode having a diameter of 30 μm and a thickness of 750 μm and a height of 30 μm and a diameter of 30 μm. A semiconductor wafer (silicon wafer) formed with a large number of pitches is prepared, and the insulating resin layer is formed by bonding the film-like insulating resin produced by the above-described method to the side surface of the protruding electrode of the semiconductor wafer with a vacuum laminator. Formed. After this is ground until the thickness of the semiconductor wafer becomes about 100 μm, the semiconductor wafer is divided into 7 mm × 7 mm chip size at a feed rate of 50 mm / sec using a dicing machine (DFD6361: manufactured by DISCO). A semiconductor chip was obtained.

得られた半導体チップを、表面が凹凸形状の支持具上に、絶縁性樹脂層が形成された突起電極側面を下にして載置した。なお、支持具上には、厚さ５０μｍのＰＥＴフィルムを成膜した。半導体チップに対して、空気の吸引孔を下面に備えた吸着ツールを上方から近づけ、吸着ツール下面の吸着面が半導体チップの裏面（突起電極側面と反対側の面）と接触しない、半導体チップの裏面から上方に０．５ｍｍ離れた位置で、吸引孔に吸引力を作用させることにより、半導体チップを支持具上から吸い上げて非接触で吸着面に吸着させた。このときの吸着ツールの温度を、それぞれ、４０℃、６０℃、８０℃、１００℃、１２０℃、１５０℃に設定した場合について、絶縁性樹脂層の樹脂面に支持具の凹凸形状が転写されたかどうか、また支持具上に樹脂が付着しているか否かについて観察を行った。樹脂面に支持具の凹凸形状が転写されておらず、かつ支持具上に樹脂が付着していない場合を「○」と、支持具上に樹脂は付着していないが樹脂面に支持具の凹凸形状が転写されている場合を「△」と、支持具上に樹脂が付着し支持具が樹脂で汚染されている場合を「×」と、それぞれ評価した。その評価結果を、表１に示す。なお、比較例として、従来技術と同じように、吸着ツールの吸着面を半導体チップの裏面に、一旦、完全に接触させた上で、吸引孔に吸引力を作用させることにより、半導体チップを支持具上からピックアップした場合について、吸着ツールの温度を、それぞれ、４０℃、６０℃、８０℃、１００℃、１２０℃、１５０℃に設定した場合についても同様の評価を行った。比較例の評価結果も表１に併せて示す。   The obtained semiconductor chip was placed on a support having an uneven surface with the side surface of the protruding electrode on which the insulating resin layer was formed facing down. A PET film having a thickness of 50 μm was formed on the support. The suction tool with an air suction hole on the lower surface is approached from above with respect to the semiconductor chip, and the suction surface on the lower surface of the suction tool is not in contact with the back surface of the semiconductor chip (the surface opposite to the protruding electrode side surface). By applying a suction force to the suction hole at a position 0.5 mm upward from the back surface, the semiconductor chip was sucked up from above the support and was sucked onto the suction surface in a non-contact manner. When the temperature of the suction tool at this time is set to 40 ° C., 60 ° C., 80 ° C., 100 ° C., 120 ° C., and 150 ° C., the uneven shape of the support is transferred to the resin surface of the insulating resin layer. Observation was made as to whether or not the resin adhered to the support. When the uneven shape of the support is not transferred to the resin surface and the resin is not attached on the support, “○” indicates that the resin is not attached to the support but the support surface is not attached to the resin surface. The case where the uneven shape was transferred was evaluated as “Δ”, and the case where the resin adhered to the support and the support was contaminated with the resin was evaluated as “x”. The evaluation results are shown in Table 1. As a comparative example, as with the prior art, the suction surface of the suction tool is once brought into full contact with the back surface of the semiconductor chip, and the semiconductor chip is supported by applying a suction force to the suction hole. The same evaluation was performed when the temperature of the adsorption tool was set to 40 ° C., 60 ° C., 80 ° C., 100 ° C., 120 ° C., and 150 ° C., respectively, when picked up from the tool. The evaluation results of the comparative examples are also shown in Table 1.

Figure 0005890960
Figure 0005890960

表１から分かるように、実施例のフリップチップ実装方法の方が、比較例のフリップチップ実装方法よりも、吸着ツールの温度がより高温の状態でも、支持具に樹脂が付着するなどの不具合が生じることなく、支持具から半導体チップをピックアップ可能であることが確認された。よって、実施例のフリップチップ実装方法では、実装により高温（２２０℃〜３２０℃程度）に加熱された吸着ツールの冷却時間を短くすることが可能であり、優れた半導体チップの実装効率を実現できることが確認された。   As can be seen from Table 1, the flip chip mounting method of the example has problems such as resin adhering to the support even when the temperature of the suction tool is higher than the flip chip mounting method of the comparative example. It was confirmed that the semiconductor chip can be picked up from the support without any occurrence. Therefore, in the flip chip mounting method of the embodiment, the cooling time of the suction tool heated to a high temperature (about 220 ° C. to 320 ° C.) by mounting can be shortened, and excellent semiconductor chip mounting efficiency can be realized. Was confirmed.

２ 突起電極
３ 絶縁性樹脂層
４ 回路基板
６ 支持具
７ 吸着ツール
１０ 半導体チップ
Ｓ 回路面
2 Protruding electrode 3 Insulating resin layer 4 Circuit board 6 Support 7 Adsorption tool 10 Semiconductor chip S Circuit surface

Claims (1)

回路面に突起電極を有しかつ前記回路面に絶縁性樹脂層が形成された半導体チップを、前記回路面を下にして支持具上に載置するチップ準備工程と、
前記支持具上に載置された前記半導体チップに対して、空気の吸引孔を備えた吸着面を下面に有する吸着手段を上方から近づけ、前記吸着面が前記半導体チップと接触しない位置で、前記吸引孔による空気の吸引により前記半導体チップを前記支持具上からピックアップして前記吸着面に吸着させるチップピックアップ工程と、
前記半導体チップを加熱しながら前記吸着手段により前記半導体チップの前記回路面を回路基板に押圧して、前記回路基板と前記半導体チップとを電気的に接続するチップ実装工程と、
前記チップ実装工程の後に前記吸着手段を冷却する冷却工程とを備え、
前記チップピックアップ工程において、前記半導体チップのピックアップ時の前記吸着面と前記半導体チップとの距離が０．２ｍｍ〜１ｍｍの範囲であり、
前記チップピックアップ工程において、前記半導体チップのピックアップ時の前記吸着手段の温度が１００℃〜２００℃であることを特徴とするフリップチップ実装方法。 A chip preparing step of placing a semiconductor chip having a protruding electrode on a circuit surface and having an insulating resin layer formed on the circuit surface on a support with the circuit surface facing down;
With respect to the semiconductor chip placed on the support, an adsorption means having an adsorption surface with an air suction hole on the lower surface is approached from above, and the adsorption surface is not in contact with the semiconductor chip, A chip pickup step of picking up the semiconductor chip from above the support by suction of air through a suction hole and sucking it on the suction surface;
A chip mounting step of electrically connecting the circuit board and the semiconductor chip by pressing the circuit surface of the semiconductor chip against the circuit board by the suction means while heating the semiconductor chip ;
A cooling step of cooling the suction means after the chip mounting step ,
In the chip pickup step, a distance between the suction surface and the semiconductor chip at the time of picking up the semiconductor chip is in a range of 0.2 mm to 1 mm,
In the chip pick-up step, the temperature of the suction means when picking up the semiconductor chip is 100 ° C. to 200 ° C.
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