JP6925021B2 - Flip chip mounting method - Google Patents
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- JP6925021B2 JP6925021B2 JP2017061978A JP2017061978A JP6925021B2 JP 6925021 B2 JP6925021 B2 JP 6925021B2 JP 2017061978 A JP2017061978 A JP 2017061978A JP 2017061978 A JP2017061978 A JP 2017061978A JP 6925021 B2 JP6925021 B2 JP 6925021B2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本発明は、フリップチップ実装方法に関する。特に、生産性に優れたフリップチップ実装方法に関する。 The present invention relates to a flip chip mounting method. In particular, the present invention relates to a highly productive flip chip mounting method.
近年、電子機器のさらなる配線等の高密度化、高周波化に対応可能な半導体パッケージの実装方式として、フリップチップボンディングが利用されている。一般的に、フリップチップボンディングでは、半導体チップに形成されたはんだバンプと、基板に形成されたはんだめっきされた配線とをはんだ付けした後、半導体チップと基板の間隙を、絶縁性樹脂組成物と呼ばれる材料で封止する。 In recent years, flip-chip bonding has been used as a mounting method for a semiconductor package capable of further increasing the density and frequency of wiring of electronic devices. Generally, in flip-chip bonding, after soldering a solder bump formed on a semiconductor chip and a solder-plated wiring formed on a substrate, a gap between the semiconductor chip and the substrate is formed with an insulating resin composition. Seal with a material called.
通常、フリップチップボンディングでは、半導体チップと基板をはんだ付け等で接合した後、半導体チップと基板の間隙に、熱硬化性の半導体樹脂封止組成物であるアンダーフィル剤を充填する（以下、「後供給型」という）。しかしながら、近年では、まず、アンダーフィル剤を基板に塗布し、半導体チップを載せた後、アンダーフィル剤の硬化と、半導体チップと基板の接続とを同時に行うことにより、工程の短縮および硬化時間の短縮を可能とし、その結果、低コストかつ低エネルギーで作製できる、先供給型フリップチップボンディングプロセスが注目され、このプロセス向けの封止材樹脂組成物（以下、「先供給型封止用樹脂組成物」という）への要求が高まっている。 Usually, in flip-chip bonding, after bonding a semiconductor chip and a substrate by soldering or the like, an underfill agent, which is a thermosetting semiconductor resin encapsulating composition, is filled in a gap between the semiconductor chip and the substrate (hereinafter, "" "Post-supply type"). However, in recent years, by first applying an underfill agent to a substrate, mounting a semiconductor chip, and then curing the underfill agent and connecting the semiconductor chip and the substrate at the same time, the process can be shortened and the curing time can be shortened. A pre-supplied flip-chip bonding process, which enables shortening and, as a result, can be produced at low cost and low energy, has attracted attention, and a sealing material resin composition for this process (hereinafter, "pre-supplied type encapsulating resin composition"). The demand for "things") is increasing.
この先供給型フリップチップボンディングプロセスに関して、半導体チップの実装前に、半導体チップの回路面に予め絶縁性樹脂層を形成しておき、回路基板への実装と同時に半導体チップと回路基板との間の樹脂封止を行うフリップチップ実装方法において、半導体チップを回路基板に効率よく実装することができるフリップチップ実装方法を提供することを目的として、回路面に突起電極を有しかつ前記回路面に絶縁性樹脂層が形成された半導体チップを、前記回路面を下にして支持具上に載置するチップ準備工程と、前記支持具上に載置された前記半導体チップに対して、空気の吸引孔を備えた吸着面を下面に有する吸着手段を上方から近づけ、前記吸着面が前記半導体チップと接触しない位置で、前記吸引孔による空気の吸引により前記半導体チップを前記支持具上からピックアップして前記吸着面に非接触で吸着させるチップピックアップ工程と、前記半導体チップを加熱しながら前記吸着手段により前記半導体チップの前記回路面を回路基板に押圧して、前記回路基板と前記半導体チップとを電気的に接続するチップ実装工程とを備えるフリップチップ実装方法が、報告されている（特許文献１）。 Regarding this pre-supplied flip chip bonding process, an insulating resin layer is formed in advance on the circuit surface of the semiconductor chip before mounting the semiconductor chip, and the resin between the semiconductor chip and the circuit board is simultaneously mounted on the circuit board. In the flip chip mounting method for sealing, for the purpose of providing a flip chip mounting method capable of efficiently mounting a semiconductor chip on a circuit board, a protruding electrode is provided on the circuit surface and insulation is provided on the circuit surface. A chip preparation step in which the semiconductor chip on which the resin layer is formed is placed on the support with the circuit surface facing down, and an air suction hole is provided in the semiconductor chip placed on the support. The suction means having the provided suction surface on the lower surface is brought closer from above, and the semiconductor chip is picked up from the support by suction of air through the suction hole at a position where the suction surface does not come into contact with the semiconductor chip, and the suction is performed. A chip pickup step of non-contact adsorption to the surface, and pressing the circuit surface of the semiconductor chip against the circuit board by the adsorption means while heating the semiconductor chip to electrically press the circuit board and the semiconductor chip against the circuit board. A flip chip mounting method including a chip mounting step for connecting has been reported (Patent Document 1).
上記フリップチップ実装方法の大きな特徴は、「吸着ツール７が、ボンディングステージ８上方の待機位置に戻ると、図１に示すように、吸着ツール７は再び、支持具６上方に移送され、支持具６から次の新たな半導体チップ１０を同様に非接触で吸い上げてピックアップする。このとき、吸着ツール７は、上記したチップ実装工程において、半導体チップ１０と回路基板４とのボンディングのために、約２２０℃〜３２０℃の高温に加熱されているので、この熱によって、半導体チップ１０ピックアップ時に、支持具６上の半導体チップ１０の絶縁樹脂層３の溶融を防ぐためには、予め、実装後の吸着ツール７を冷却する必要がある」（特許文献１の第００２８段落）ことである。
A major feature of the flip chip mounting method is that "when the suction tool 7 returns to the standby position above the bonding stage 8, the suction tool 7 is again transferred above the support 6 and the support, as shown in FIG. Similarly, the next
しかしながら、上記フリップチップ実装方法では、実装後の吸着ツールを冷却するため、吸着ツールを冷却するための時間が必要となり、この吸着ツールの冷却時間が、生産効率を低下させてしまう。 However, in the flip chip mounting method, since the suction tool after mounting is cooled, a time for cooling the suction tool is required, and the cooling time of the suction tool lowers the production efficiency.
本発明は、従来技術から吸着ツールの冷却時間の省略を可能にすることにより、フリップチップ実装の生産効率を著しく高くするフリップチップ実装方法を提供することを目的とする。 An object of the present invention is to provide a flip chip mounting method that significantly increases the production efficiency of flip chip mounting by making it possible to omit the cooling time of the suction tool from the prior art.
本発明は、以下の構成を有することによって上記問題を解決したフリップチップ実装方法に関する。
〔１〕（Ａ）回路面に、先端に接合金属を有する突起電極が形成された半導体チップを、回路面を下にして、空気の吸引孔を備えた吸着面を下面に有する支持具の下に載置した後、半導体チップを支持具の吸着面に吸着するチップ準備工程と、
（Ｂ）回路基板の回路上に、熱硬化性樹脂の反応基と、硬化剤の反応基との当量比が０．５〜０．７５である絶縁性樹脂組成物層を形成する回路基板準備工程と、
（Ｃ）空気の吸引孔を備えた吸着面を下面に有する支持具を上方から近づけ、回路面に突起電極が形成された半導体チップを、ピックアップして、支持具の吸着面に吸着させる、チップピックアップ工程と、
（Ｄ）支持具により吸着された半導体チップを加熱しながら、半導体チップの回路面を回路基板の絶縁樹脂組成物層に押圧して、回路基板と半導体チップとを接続するチップ実装工程とを、この順に、有し、
（Ｃ）工程において、半導体チップのピックアップ時の、支持具の吸着面と半導体チップの上面との距離が０．２ｍｍ〜１ｍｍの範囲であり、
（Ｄ）工程後、支持具の冷却工程を設けずに、次の半導体チップのフリップチップ実装を行うことを特徴とする、フリップチップ実装方法。
〔２〕（Ｄ）工程において、２１０℃〜２８０℃で加熱して、半導体チップの突起電極の先端の接合金属を溶融させ、接合金属が凝固することにより、回路基板と半導体チップとを電気的接続する、上記〔１〕記載のフリップチップ実装方法。
〔３〕（Ｄ）工程において、支持具以外の加熱により、半導体チップの突起電極の先端の接合金属を溶融させ、接合金属が凝固することにより、回路基板と前記半導体チップとを電気的接続する、上記〔２〕記載のフリップチップ実装方法。
〔４〕（Ｄ）工程後、さらに、加圧オーブンにより、０．５〜１．０ＭＰａであり、かつ１５０〜１８０℃で、回路基板に形成された絶縁性樹脂組成物層を硬化させる、上記〔１〕〜〔３〕のいずれか記載のフリップチップ実装方法。
〔５〕回路基板に形成される絶縁性樹脂組成物層が、無機充填剤を２０〜７０質量％含む、上記〔１〕〜〔４〕のいずれか記載のフリップチップ実装方法。
〔６〕（Ｃ）工程において、半導体チップのピックアップ時の支持具の温度が、１８０〜３００℃である、上記〔１〕〜〔５〕のいずれか記載のフリップチップ実装方法。
The present invention relates to a flip chip mounting method that solves the above problems by having the following configuration.
[1] (A) A semiconductor chip having a protruding electrode having a bonded metal at its tip formed on the circuit surface, with the circuit surface facing down, and under a support having a suction surface with air suction holes on the lower surface. A chip preparation process in which the semiconductor chip is adsorbed on the suction surface of the support after being placed on the support tool.
(B) Preparation of a circuit board for forming an insulating resin composition layer in which the equivalent ratio of the reactive group of the thermosetting resin and the reactive group of the curing agent is 0.5 to 0.75 on the circuit of the circuit board. Process and
(C) A chip having a support having a suction surface provided with an air suction hole on the lower surface, approaching from above, picking up a semiconductor chip having a protruding electrode formed on the circuit surface, and sucking it onto the suction surface of the support. Pickup process and
(D) The chip mounting step of connecting the circuit board and the semiconductor chip by pressing the circuit surface of the semiconductor chip against the insulating resin composition layer of the circuit board while heating the semiconductor chip attracted by the support. Have in this order
In the step (C), the distance between the suction surface of the support and the upper surface of the semiconductor chip at the time of picking up the semiconductor chip is in the range of 0.2 mm to 1 mm.
(D) A flip-chip mounting method, characterized in that the next semiconductor chip is flip-chip mounted without providing a support cooling step after the step.
[2] In the step (D), the circuit board and the semiconductor chip are electrically heated by heating at 210 ° C. to 280 ° C. to melt the bonding metal at the tip of the protruding electrode of the semiconductor chip and solidifying the bonding metal. The flip chip mounting method according to the above [1] for connecting.
[3] In the step (D), the bonding metal at the tip of the protruding electrode of the semiconductor chip is melted by heating other than the support, and the bonding metal solidifies to electrically connect the circuit board and the semiconductor chip. , The flip chip mounting method according to the above [2].
[4] After the step (D), the insulating resin composition layer formed on the circuit board is further cured at 0.5 to 1.0 MPa and 150 to 180 ° C. by a pressure oven. The flip chip mounting method according to any one of [1] to [3].
[5] The flip chip mounting method according to any one of the above [1] to [4], wherein the insulating resin composition layer formed on the circuit board contains 20 to 70% by mass of an inorganic filler.
[6] The flip chip mounting method according to any one of [1] to [5] above, wherein in the step (C), the temperature of the support when picking up the semiconductor chip is 180 to 300 ° C.
本発明〔１〕によれば、従来技術から吸着ツールの冷却時間の省略を可能にすることにより、フリップチップ実装の生産効率を著しく高くするフリップチップ実装方法を提供することができる。 According to the present invention [1], it is possible to provide a flip chip mounting method that remarkably increases the production efficiency of flip chip mounting by making it possible to omit the cooling time of the suction tool from the prior art.
本発明のフリップチップ実装方法は、（Ａ）回路面に、先端に接合金属を有する突起電極が形成された半導体チップを、回路面を下にして、空気の吸引孔を備えた吸着面を下面に有する支持具の下に載置するチップ準備工程と、
（Ｂ）回路基板の回路上に、熱硬化性樹脂の反応基と、硬化剤の反応基との当量比が０．５〜０．７５である絶縁性樹脂組成物層を形成する回路基板準備工程と、
（Ｃ）空気の吸引孔を備えた吸着面を下面に有する支持具を上方から近づけ、回路面に突起電極が形成された半導体チップを、ピックアップして、支持具の吸着面に吸着させる、チップピックアップ工程と、
（Ｄ）支持具により吸着された半導体チップを加熱しながら、半導体チップの回路面を回路基板の絶縁樹脂組成物層に押圧して、回路基板と半導体チップとを接続するチップ実装工程とを、この順に、有し、
（Ｃ）工程において、半導体チップのピックアップ時の吸着面と半導体チップとの距離が０．２ｍｍ〜１ｍｍの範囲であり、
（Ｄ）工程後、支持具の冷却工程を設けずに、次の半導体チップのフリップチップ実装を行うことを特徴とする。
In the flip chip mounting method of the present invention, a semiconductor chip having a protruding electrode having a bonded metal at its tip formed on the circuit surface (A) is placed on the circuit surface, and the suction surface provided with an air suction hole is placed on the lower surface with the circuit surface facing down. The chip preparation process to be placed under the support provided in
(B) Preparation of a circuit board for forming an insulating resin composition layer in which the equivalent ratio of the reactive group of the thermosetting resin and the reactive group of the curing agent is 0.5 to 0.75 on the circuit of the circuit board. Process and
(C) A chip having a support having a suction surface provided with an air suction hole on the lower surface, approaching from above, picking up a semiconductor chip having a protruding electrode formed on the circuit surface, and sucking it onto the suction surface of the support. Pickup process and
(D) The chip mounting step of connecting the circuit board and the semiconductor chip by pressing the circuit surface of the semiconductor chip against the insulating resin composition layer of the circuit board while heating the semiconductor chip attracted by the support. Have in this order
In the step (C), the distance between the suction surface at the time of picking up the semiconductor chip and the semiconductor chip is in the range of 0.2 mm to 1 mm.
After the step (D), the next flip chip mounting of the semiconductor chip is performed without providing the cooling step of the support.
図１〜７に、本発明のフリップチップ実装方法の一例の模式図を示す。図１に、（Ａ）チップ準備工程の模式図を示す。図１に示すように、（Ａ）工程では、回路面１３に、先端に接合金属１２を有する突起電極１３が形成された半導体チップ１０を、回路面１３を下にして、空気の吸引孔４１を備えた吸着面を下面に有する支持具４０の下に載置する。
1 to 7 show a schematic view of an example of the flip chip mounting method of the present invention. FIG. 1 shows a schematic diagram of (A) chip preparation process. As shown in FIG. 1, in the step (A), the
図２に、回路基板の模式図を示す。図２では、回路基板２０は、回路２１を有する。図３に、（Ｂ）回路基板準備工程の模式図を示す。図３に示すように、（Ｂ）工程では、回路基板２０の回路上に絶縁性樹脂組成物層３０を形成する。
FIG. 2 shows a schematic diagram of the circuit board. In FIG. 2, the
図４に、（Ｃ）チップピックアップ工程の模式図を示す。図４に示すように、（Ｃ）工程では、空気の吸引孔４１を備えた吸着面４２を下面に有する支持具４０を上方から近づけ、回路面１３に突起電極１２が形成された半導体チップ１０を、ピックアップして、支持具４０の吸着面４２に吸着させる。図４からはわからないが、支持具４０の吸着面４２と半導体チップ１０との距離は、０．２ｍｍ〜１ｍｍの範囲である。
FIG. 4 shows a schematic diagram of the chip pickup process (C). As shown in FIG. 4, in the step (C), the
図５に、（Ｄ）チップ実装工程の直前の模式図を示す。図５では、半導体チップの突起電極先１２と、回路基板２０の回路２１の位置合わせをする。図６に、（Ｄ）チップ実装工程の模式図を示す。図６に示すように、（Ｄ）工程では、支持具４０により吸着された半導体チップ１０を加熱しながら、半導体チップ１０の回路面１３を回路基板２０上の絶縁樹脂組成物層３０に押圧して、回路基板２０と半導体チップ１０とを接続する。
FIG. 5 shows a schematic diagram immediately before the (D) chip mounting process. In FIG. 5, the
図７に、フリップチップ実装体の模式図を示す。（Ｄ）工程後、支持具を取り外し、フリップチップ実装体１が、得られる。図には記載されていないが、取り外した支持具は、冷却工程を設けずに、次の半導体チップのフリップチップ実装を行う。以下、工程順に、詳細に説明する。
FIG. 7 shows a schematic diagram of the flip chip mounting body. After the step (D), the support is removed to obtain the flip
〔（Ａ）工程〕
（Ａ）工程のチップ準備工程チップ準備工程では、回路面に、先端に接合金属を有する突起電極が形成された半導体チップを、回路面を下にして、空気の吸引孔を備えた吸着面を下面に有する支持具の下に載置した後、半導体チップを支持具の吸着面に吸着する。
[Step (A)]
(A) Chip preparation step In the chip preparation step, a semiconductor chip having a protruding electrode having a bonded metal at the tip thereof is formed on the circuit surface, and a suction surface having an air suction hole is provided with the circuit surface facing down. After placing the semiconductor chip under the support provided on the lower surface, the semiconductor chip is attracted to the suction surface of the support.
回路面に、先端に接合金属を有する突起電極が形成された半導体チップは、特に、限定されないが、突起電極は、例えば、銅バンプや銅ピラー上に接合金属が形成されたものが、挙げられる。接合金属には、錫、鉛、銅、ビスマス、銀、亜鉛、インジウム等からなるハンダ合金等を使用することができ、環境問題から、鉛フリーハンダ合金である錫銀系が、好ましい。 The semiconductor chip in which the protruding electrode having the bonding metal at the tip is formed on the circuit surface is not particularly limited, and examples of the protruding electrode include those in which the bonding metal is formed on a copper bump or a copper pillar. .. As the bonding metal, a solder alloy composed of tin, lead, copper, bismuth, silver, zinc, indium and the like can be used, and a tin-silver alloy, which is a lead-free solder alloy, is preferable from the viewpoint of environmental problems.
支持具は、例えば、セラミックスなどの高熱伝導性の材料で形成され、上下方向に昇降動作可能であり、かつ回路基板を吸着保持する実装用装置のボンディングステージとの間を、往復動作可能である。支持具の下面には、吸引孔が形成されている。この吸引孔は、配管を介してポンプと接続され、ポンプによる空気吸引により吸引孔に吸引力を発生させる。 The support is made of a material having high thermal conductivity such as ceramics, can move up and down in the vertical direction, and can move back and forth between the support and the bonding stage of the mounting device that attracts and holds the circuit board. .. A suction hole is formed on the lower surface of the support. This suction hole is connected to a pump via a pipe, and a suction force is generated in the suction hole by air suction by the pump.
〔（Ｂ）工程〕
（Ｂ）工程の回路基板準備工程では、回路基板の回路上に、樹脂の反応基と、硬化剤の反応基との当量比が０．５〜０．７５である絶縁性樹脂組成物層を形成する。
[Step (B)]
In the circuit board preparation step of the step (B), an insulating resin composition layer in which the equivalent ratio of the reactive group of the resin and the reactive group of the curing agent is 0.5 to 0.75 is formed on the circuit of the circuit board. Form.
基板には、エポキシ樹脂、ガラス−エポキシ樹脂、ポリイミド樹脂等が挙げられるが、これらに限定されない。配線には、銅等が、挙げられる。配線上には、はんだめっきがなされていてもよく、はんだとしては、環境問題から、鉛フリーハンダ合金である錫銀銅系が好ましい。 Examples of the substrate include, but are not limited to, epoxy resin, glass-epoxy resin, and polyimide resin. Examples of the wiring include copper and the like. The wiring may be solder-plated, and the solder is preferably tin-silver-copper, which is a lead-free solder alloy, from the viewpoint of environmental problems.
絶縁性樹脂組成物は、特に限定されないが、以下、好ましい絶縁性樹脂組成物であるエポキシ樹脂組成物について説明する。絶縁性樹脂組成物は、少なくとも（ＵＡ）熱硬化性樹脂、（ＵＢ）硬化剤を含むと好ましい。 The insulating resin composition is not particularly limited, but the epoxy resin composition, which is a preferable insulating resin composition, will be described below. The insulating resin composition preferably contains at least a (UA) thermosetting resin and a (UB) curing agent.
（ＵＡ）成分としては、信頼性の観点から、エポキシ樹脂が、好ましい。エポキシ樹脂としては、ビスフェノールＡ型エポキシ樹脂、臭素化ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ナフタレン型エポキシ樹脂、ビフェニル型エポキシ樹脂、ノボラック型エポキシ樹脂、アミノフェノール系エポキシ樹脂、脂環式エポキシ樹脂、エーテル系またはポリエーテル系エポキシ樹脂、オキシラン環含有エポキシ樹脂等が挙げられ、ビスフェノールＦ型エポキシ樹脂、アミノフェノール系エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ナフタレン型エポキシ樹脂が、絶縁性樹脂組成物のガラス転移点、耐リフロー性、および耐湿性の観点から好ましい。 As the (UA) component, an epoxy resin is preferable from the viewpoint of reliability. As the epoxy resin, bisphenol A type epoxy resin, brominated bisphenol A type epoxy resin, bisphenol F type epoxy resin, naphthalene type epoxy resin, biphenyl type epoxy resin, novolak type epoxy resin, aminophenol type epoxy resin, alicyclic epoxy Examples thereof include resins, ether-based or polyether-based epoxy resins, and oxylan ring-containing epoxy resins. Bisphenol F-type epoxy resins, aminophenol-based epoxy resins, bisphenol A-type epoxy resins, and naphthalene-type epoxy resins are insulating resin compositions. It is preferable from the viewpoint of glass transition point, reflow resistance, and moisture resistance.
ビスフェノールＦ型エポキシ樹脂は、好ましくは、式（１）： The bisphenol F type epoxy resin is preferably given by the formula (1):
で示され、式中、ｎは平均値を表し、好ましくは０〜６、より好ましくは０〜３である。エポキシ当量は、１５０〜９００ｇ／ｅｑが好ましい。 In the formula, n represents an average value, preferably 0 to 6, more preferably 0 to 3. The epoxy equivalent is preferably 150 to 900 g / eq.
アミノフェノール系エポキシ樹脂は、好ましくは、式（２）： The aminophenol-based epoxy resin is preferably given by the formula (2):
で示され、２個の官能基がオルト位、またはパラ位にあるものがより好ましい。 It is more preferable that the two functional groups are in the ortho-position or the para-position, which are indicated by.
ビスフェノールＡ型エポキシ樹脂は、好ましくは、式（３）： The bisphenol A type epoxy resin is preferably given by the formula (3):
で示され、式中、ｍは平均値を表し、好ましくは０〜６、特に好ましくは０〜３である、エポキシ樹脂が挙げられる。エポキシ当量は、１７０〜１０００ｇ／ｅｑが好ましい。 In the formula, m represents an average value, preferably 0 to 6, particularly preferably 0 to 3, and examples thereof include epoxy resins. The epoxy equivalent is preferably 170 to 1000 g / eq.
（ＵＡ）成分は、単独でも２種以上を併用してもよい。 The (UA) component may be used alone or in combination of two or more.
（ＵＢ）成分としては、アミン系硬化剤、酸無水物系硬化剤、フェノール系硬化剤等が挙げられ、アミン系硬化剤が、絶縁性樹脂組成物の耐リフロー性、および耐湿性の観点から好ましい。 Examples of the (UB) component include an amine-based curing agent, an acid anhydride-based curing agent, a phenol-based curing agent, and the like, and the amine-based curing agent is used from the viewpoint of reflow resistance and moisture resistance of the insulating resin composition. preferable.
アミン系硬化剤は、脂肪族ポリアミン；芳香族アミン；ポリアミノアミド、ポリアミノイミド、ポリアミノエステルおよびポリアミノ尿素等の変成ポリアミン；第三級アミン系；イミダゾール系；ヒドラジド系；ジシアンアミド系；メラミン系の化合物等が挙げられ、芳香族アミン系化合物が好ましい。 Amine-based curing agents include aliphatic polyamines; aromatic amines; modified polyamines such as polyaminoamides, polyaminoimides, polyamino esters and polyaminoureas; tertiary amines; imidazole-based; hydrazide-based; dicyanamide-based; melamine-based compounds, etc. However, aromatic amine compounds are preferable.
芳香族アミン系化合物は、１個の芳香族環を有する芳香族アミン化合物および／または２個の芳香族環を有する芳香族アミン化合物を含むことが、より好ましい。 It is more preferable that the aromatic amine compound contains an aromatic amine compound having one aromatic ring and / or an aromatic amine compound having two aromatic rings.
１個の芳香族環を有する芳香族アミン化合物としては、メタフェニレンジアミン等が挙げられ、式（４）または式（５）： Examples of the aromatic amine compound having one aromatic ring include meta-phenylenediamine and the like, and formula (4) or formula (5):
で示されるものが、好ましい。 The one indicated by is preferable.
２個の芳香族環を有する芳香族アミン化合物としては、ジアミノジフェニルメタン、ジアミノジフェニルスルフォン等が挙げられ、式（６）または式（７）： Examples of the aromatic amine compound having two aromatic rings include diaminodiphenylmethane and diaminodiphenyl sulfone, and formula (6) or formula (7):
（式中、Ｒは、水素、または炭素数１〜５個のアルキル基を表す）で示されるものが好ましく、式（８）または式（９）でＲが炭素数２個のアルキル基であるものが、より好ましい。 (In the formula, R represents hydrogen or an alkyl group having 1 to 5 carbon atoms), and R is an alkyl group having 2 carbon atoms in the formula (8) or the formula (9). Is more preferable.
（ＵＢ）成分は、単独でも２種以上を併用してもよい。 The (UB) component may be used alone or in combination of two or more.
また、（ＵＡ）熱硬化性樹脂の１当量に対して、（ＵＢ）硬化剤の当量は、０．５〜０．７５である。（ＵＢ）硬化剤の当量が０．５未満では、本発明のフリップチップ実装方法では、絶縁性樹脂組成物が硬化せず、一方、当量が０．７５を超えると、本発明のフリップチップ実装方法での（Ｄ）チップ実装工程中に、実装時に絶縁性樹脂組成物が硬化しまい、半導体チップと回路基板の電気接続を阻害してしまう。 The equivalent of the (UB) curing agent is 0.5 to 0.75 with respect to 1 equivalent of the (UA) thermosetting resin. When the equivalent of the (UB) curing agent is less than 0.5, the insulating resin composition is not cured by the flip chip mounting method of the present invention, while when the equivalent exceeds 0.75, the flip chip mounting of the present invention is performed. During the chip mounting step (D) in the method, the insulating resin composition is cured during mounting, which hinders the electrical connection between the semiconductor chip and the circuit board.
絶縁性樹脂組成物は、さらに、（ＵＣ）フィラーを含むと、硬化後の絶縁性樹脂組成物の熱膨張係数の観点から好ましい。（ＵＣ）成分としては、シリカ、アルミナ、窒化ケイ素、マイカ、ホワイトカーボン等が挙げられ、硬化後の絶縁性樹脂組成物の熱膨張係数の低下、およびコストの観点から、シリカが好ましい。シリカは、非晶質シリカ、結晶性シリカ、溶融シリカ、粉砕シリカ、ナノシリカ等、当技術分野で使用される各種シリカを使用することができ、硬化後の絶縁性樹脂組成物の熱膨張係数低下の点から非晶質シリカが好ましい。（ＵＣ）成分の粒径は、半導体チップと基板の間隙への充填性の観点から０．１〜２．０μｍが好ましく、０．１〜１．０μｍがより好ましい。ここで、平均粒径は、レーザー回折式粒度分布測定装置により測定する。また、（ＵＣ）成分の形状は、特に限定されず、球状、リン片状、不定形等が挙げられ、封止用液状樹脂組成物の流動性の観点から、球状が好ましい。 It is preferable that the insulating resin composition further contains (UC) filler from the viewpoint of the coefficient of thermal expansion of the insulating resin composition after curing. Examples of the (UC) component include silica, alumina, silicon nitride, mica, and white carbon, and silica is preferable from the viewpoint of reducing the coefficient of thermal expansion of the insulating resin composition after curing and cost. As the silica, various silicas used in the art such as amorphous silica, crystalline silica, fused silica, pulverized silica, and nanosilica can be used, and the thermal expansion coefficient of the insulating resin composition after curing is lowered. Amorphous silica is preferable from the above viewpoint. The particle size of the component (UC) is preferably 0.1 to 2.0 μm, more preferably 0.1 to 1.0 μm, from the viewpoint of filling the gap between the semiconductor chip and the substrate. Here, the average particle size is measured by a laser diffraction type particle size distribution measuring device. The shape of the (UC) component is not particularly limited, and examples thereof include a spherical shape, a flaky shape, an amorphous shape, and the like, and the spherical shape is preferable from the viewpoint of the fluidity of the liquid resin composition for sealing.
（ＵＣ）成分は、単独でも２種以上を併用してもよい。 The (UC) component may be used alone or in combination of two or more.
絶縁性樹脂組成物は、絶縁性樹脂組成物１００質量部に対して、（ＵＡ）成分を、好ましくは１０〜７０質量部、より好ましくは２０〜５０質量部含むことが、絶縁性樹脂組成物のガラス転移点、耐リフロー性、および耐湿性の観点から、好ましい。 The insulating resin composition contains the component (UA) in an amount of preferably 10 to 70 parts by mass, more preferably 20 to 50 parts by mass with respect to 100 parts by mass of the insulating resin composition. It is preferable from the viewpoint of glass transition point, reflow resistance, and moisture resistance.
また、絶縁性樹脂組成物１００質量部に対して、（ＵＣ）成分を、好ましくは２０〜７０質量部、より好ましくは３０〜５０質量部含むことが、絶縁性樹脂組成物の流動性、および硬化後の絶縁性樹脂組成物の熱膨張係数低下の観点から、好ましい。 Further, the fluidity of the insulating resin composition and the fluidity of the insulating resin composition are such that the (UC) component is preferably contained in an amount of 20 to 70 parts by mass, more preferably 30 to 50 parts by mass with respect to 100 parts by mass of the insulating resin composition. It is preferable from the viewpoint of lowering the coefficient of thermal expansion of the insulating resin composition after curing.
絶縁性樹脂組成物には、本発明の目的を損なわない範囲で、更に必要に応じ、カーボンブラックなどの顔料、染料、シランカップリング剤、消泡剤、酸化防止剤、その他の添加剤等、更に有機溶剤等を配合することができる。 The insulating resin composition may contain pigments such as carbon black, dyes, silane coupling agents, antifoaming agents, antioxidants, other additives, etc., as necessary, as long as the object of the present invention is not impaired. Further, an organic solvent or the like can be blended.
絶縁性樹脂組成物は、例えば、（ＵＡ）成分〜（ＵＣ）成分およびその他の添加剤等を同時にまたは別々に、必要により加熱処理を加えながら、撹拌、溶融、混合、分散させることにより得ることができる。これらの混合、撹拌、分散等の装置としては、特に限定されるものではないが、撹拌、加熱装置を備えたライカイ機、３本ロールミル、ボールミル、プラネタリーミキサー、ビーズミル等を使用することができる。また、これら装置を適宜組み合わせて使用してもよい。 The insulating resin composition can be obtained, for example, by stirring, melting, mixing, and dispersing the (UA) component to the (UC) component and other additives simultaneously or separately, with heat treatment if necessary. Can be done. The device for mixing, stirring, dispersing, etc. is not particularly limited, but a Raikai machine equipped with a stirring and heating device, a three-roll mill, a ball mill, a planetary mixer, a bead mill, and the like can be used. .. Moreover, you may use these devices in combination as appropriate.
絶縁性樹脂組成物は、温度：２５℃での粘度が１〜１００Ｐａ・ｓであると、好ましい。ここで、粘度は、Ｂｒｏｏｋｆｉｅｌｄ社製粘度計（型番：ＤＶ−１）で測定する。 The insulating resin composition preferably has a viscosity at a temperature of 25 ° C. of 1 to 100 Pa · s. Here, the viscosity is measured with a viscometer manufactured by Brookfield (model number: DV-1).
本発明のフリップチップ実装方法の後工程で行う絶縁性樹脂組成物の硬化は、１５０〜１８０℃で、９０〜１５０分間行うことが好ましい。 The curing of the insulating resin composition performed in the subsequent step of the flip chip mounting method of the present invention is preferably performed at 150 to 180 ° C. for 90 to 150 minutes.
路基板の回路上に、上述の絶縁性樹脂組成物を、ディスペンサー等で塗布し、絶縁性樹脂組成物層を形成する。 The above-mentioned insulating resin composition is applied onto the circuit of the road substrate with a dispenser or the like to form an insulating resin composition layer.
絶縁性樹脂組成物層の厚さは、デバイスの厚みの観点から、１０〜２５０μｍであると、好ましい。 The thickness of the insulating resin composition layer is preferably 10 to 250 μm from the viewpoint of the thickness of the device.
〔（Ｃ）工程〕
（Ｃ）工程のチップピックアップ工程では、支持具により吸着された半導体チップを加熱しながら、半導体チップの回路面を回路基板の絶縁樹脂組成物層に押圧して、回路基板と半導体チップとを接続する。この（Ｃ）工程においては、半導体チップのピックアップ時の、支持具の吸着面と半導体チップの上面との距離が０．２ｍｍ〜１ｍｍの範囲である。
[Step (C)]
In the chip pick-up step of the step (C), the circuit board of the semiconductor chip is pressed against the insulating resin composition layer of the circuit board while heating the semiconductor chip attracted by the support, and the circuit board and the semiconductor chip are connected. do. In this step (C), the distance between the suction surface of the support and the upper surface of the semiconductor chip at the time of picking up the semiconductor chip is in the range of 0.2 mm to 1 mm.
支持具の吸着面と半導体チップの上面との距離が、１ｍｍを超えると、半導体チップを吸着できず、吸着エラーが発生する場合がある。一方、支持具の吸着面と半導体チップの上面との距離が、０．２ｍｍ未満であると、支持具からの輻射熱の影響で絶縁樹脂層が溶融し垂れ下がってしまう。 If the distance between the suction surface of the support and the upper surface of the semiconductor chip exceeds 1 mm, the semiconductor chip cannot be sucked and a suction error may occur. On the other hand, if the distance between the suction surface of the support and the upper surface of the semiconductor chip is less than 0.2 mm, the insulating resin layer melts and hangs down due to the influence of radiant heat from the support.
また、（Ｃ）工程において、半導体チップのピックアップ時の支持具の温度が、１８０〜３００℃であると、生産性の観点から、好ましい。 Further, in the step (C), it is preferable that the temperature of the support at the time of picking up the semiconductor chip is 180 to 300 ° C. from the viewpoint of productivity.
〔（Ｄ）工程〕
（Ｄ）工程のチップ実装工程では、支持具により吸着された半導体チップを加熱しながら、半導体チップの回路面を回路基板の絶縁樹脂組成物層に押圧して、回路基板と半導体チップとを接続する。
[Step (D)]
In the chip mounting step of the step (D), the circuit board of the semiconductor chip is pressed against the insulating resin composition layer of the circuit board while heating the semiconductor chip attracted by the support, and the circuit board and the semiconductor chip are connected. do.
（Ｄ）工程で使用する装置としては、例えば、ダイボンダー等が、挙げられる。 Examples of the device used in the step (D) include a die bonder and the like.
（Ｄ）工程において、２１０℃〜２８０℃で加熱して、半導体チップの突起電極の先端の接合金属を溶融させ、接合金属が凝固することにより、回路基板と半導体チップとを電気的接続すると、生産性の観点から、好ましい。 In the step (D), heating is performed at 210 ° C. to 280 ° C. to melt the bonding metal at the tip of the protruding electrode of the semiconductor chip, and the bonding metal solidifies to electrically connect the circuit board and the semiconductor chip. It is preferable from the viewpoint of productivity.
（Ｄ）工程において、例えば、赤外線加熱、摩擦熱、熱風）等の支持具以外の加熱により、半導体チップの突起電極の先端の接合金属を溶融させ、接合金属が凝固することにより、回路基板と前記半導体チップとを電気的接続すると、生産性の観点から、より好ましい。 In the step (D), the bonding metal at the tip of the protruding electrode of the semiconductor chip is melted by heating other than the support such as infrared heating, frictional heat, hot air), and the bonding metal solidifies to form a circuit board. It is more preferable to electrically connect the semiconductor chip from the viewpoint of productivity.
〔（Ｄ）工程の後工程〕
（Ｄ）工程後、支持具の冷却工程を設けずに、次の半導体チップのフリップチップ実装を行う。この（Ｄ）工程後、支持具の冷却工程を設けないことにより、本発明者らは、フリップチップ実装方法による１時間当たりの生産個数を、従来技術の約２．９倍に高める、という非常に顕著な効果を得ることができた。
[Post-process of step (D)]
After the step (D), the next flip chip mounting of the semiconductor chip is performed without providing the cooling step of the support. By not providing a cooling step for the support after the step (D), the present inventors can increase the number of products produced per hour by the flip chip mounting method to about 2.9 times that of the conventional technique. A remarkable effect could be obtained.
また、（Ｄ）工程後、さらに、加圧オーブンにより、０．５〜１．０ＭＰａであり、かつ１５０〜１８０℃で、回路基板に形成された絶縁性樹脂組成物層を硬化させると、フリップチップ実装体の信頼性向上の観点から、好ましい。また、加圧オーブンによる加熱は、３０〜２４０分間であると、生産性の観点から、より好ましい。 Further, after the step (D), when the insulating resin composition layer formed on the circuit board is further cured by a pressure oven at 0.5 to 1.0 MPa and 150 to 180 ° C., it flips. This is preferable from the viewpoint of improving the reliability of the chip mount. Further, heating in a pressure oven is more preferably 30 to 240 minutes from the viewpoint of productivity.
本発明について、実施例により説明するが、本発明はこれらに限定されるものではない。なお、以下の実施例において、部、％はことわりのない限り、重量部、重量％を示す。 The present invention will be described with reference to Examples, but the present invention is not limited thereto. In the following examples, parts and% indicate parts by weight and% by weight unless otherwise specified.
表１〜２に記載したビスフェノールＦ型エポキシ樹脂には、新日鐵住金化学株式会社ビスフェノールＦ型エポキシ樹脂（品名：ＹＤＦ８１７０、エポキシ当量：１５８ｇ／ｅｑ）を、
ナフタレン型エポキシ樹脂には、ＤＩＣ株式会社ナフタレン型エポキシ樹脂（品名：４０３２Ｄ、エポキシ当量：１４４ｇ／ｅｑ）を、
フィラーには、株式会社アドマテックス製シリカ（品名：ＳＯ−Ｅ２、平均粒径：０．５μｍ）を、
硬化剤には、株式会社ＡＤＥＫＡ製変性芳香族アミン型硬化剤（品名：ＥＨ−１０５Ｌ、アミン当量：６１ｇ／ｅｑ）を、
使用した。
また、無機基板には、株式会社ウォルツ製基板（品名：ＷＡＬＴＳ−ＴＥＧ ＩＰ８０−０１０１ＪＹ（ＳｉＮ）、幅：１０．０ｍｍ×長さ：１０．０ｍｍ×厚さ：０．７２５ｍｍ）を、
有機基板には、株式会社ウォルツ製基板（品名：ＷＡＬＴＳ−ＫＩＴ ＣＣ８０−０１０２ＪＹ［ＭＡＰ］ＭｏｄｅｌＩ（Ｃｕ＋ＯＳＰ仕様）、幅：１７．０ｍｍ×長さ：１７．０ｍｍ×厚さ：０．３５６ｍｍ）を、
使用した。
製造工程の蘭の「冷却あり」は、（Ｄ）工程後、支持具の冷却を行った。
「冷却なし」は、（Ｄ）工程後、支持具の冷却を行わずに、次の半導体チップのフリップチップ実装を行った。
「リフロー」は、リフロー炉（ＨＥＬＬＥＲ製、型番：１８０９ＭＫＩＩＩ）を用い、
「ＰＯ」は、加圧オーブン（ＡｂｌｅＰｒｉｎｔ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．Ｌｔｄ．製、型番：ＶＦＳ−６０Ａ−ＪＰ）を用い、
「ＩＲ」は、赤外線加熱（ＰａｃＴｅｃ−Ｐａｃｋａｇｉｎｇ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＧｍｂＨ製、型番：ＬＡＰＬＡＣＥ−ＦＣ）を用いた。
The bisphenol F type epoxy resin shown in Tables 1 and 2 includes a bisphenol F type epoxy resin (product name: YDF8170, epoxy equivalent: 158 g / eq) of Nippon Steel & Sumitomo Metal Corporation.
For the naphthalene type epoxy resin, DIC Corporation naphthalene type epoxy resin (product name: 4032D, epoxy equivalent: 144 g / eq) is used.
As the filler, silica manufactured by Admatex Co., Ltd. (product name: SO-E2, average particle size: 0.5 μm) is used.
As the curing agent, a modified aromatic amine type curing agent (product name: EH-105L, amine equivalent: 61 g / eq) manufactured by ADEKA Corporation was used.
used.
For the inorganic substrate, a substrate manufactured by Waltz Co., Ltd. (product name: WALTS-TEG IP80-0101JY (SiN), width: 10.0 mm x length: 10.0 mm x thickness: 0.725 mm) is used.
For the organic substrate, a substrate manufactured by Waltz Co., Ltd. (product name: WALTS-KIT CC80-012JY [MAP] ModelI (Cu + OSP specification), width: 17.0 mm x length: 17.0 mm x thickness: 0.356 mm) is used.
used.
For the orchid "with cooling" in the manufacturing process, the support was cooled after the step (D).
For "no cooling", after the step (D), the next semiconductor chip was flip-chip mounted without cooling the support.
"Reflow" uses a reflow furnace (manufactured by HELLER, model number: 1809MKIII).
For "PO", a pressure oven (manufactured by AblePrint Technology Co. Ltd., model number: VFS-60A-JP) was used.
For "IR", infrared heating (manufactured by PacTech-Packaging Technologies GmbH, model number: LAPLACE-FC) was used.
〔実施例１〜８、比較例１〜３〕
表１〜２に示す配合で、原料を秤量し、３本ロールミルを用いて混合し、熱硬化性樹脂組成物を調製し、表１〜２に示す組合せで評価を行った。
[Examples 1 to 8 and Comparative Examples 1 to 3]
The raw materials were weighed according to the formulations shown in Tables 1 and 2, and mixed using a three-roll mill to prepare a thermosetting resin composition, which was evaluated by the combinations shown in Tables 1 and 2.
《（Ｂ）回路基板準備工程》
７０℃に加熱したパナソニックＦＳエンジニアリング株式会社製ダイボンダー（型番：ＦＣＢ３）上に載置した基板の回路上に、熱硬化性樹脂組成物を、エアーディスペンサーを用い、塗布量：４．０ｍｇ、フローマーク：クロスパターン（半導体チップの対角線を「×」の形状）で、塗布した。
<< (B) Circuit board preparation process >>
A thermosetting resin composition was applied to a circuit of a substrate placed on a die bonder (model number: FCB3) manufactured by Panasonic FS Engineering Co., Ltd. heated to 70 ° C. using an air dispenser, and a coating amount: 4.0 mg, flow mark. : A cross pattern (the diagonal line of the semiconductor chip is in the shape of "x") was applied.
《（Ｃ）チップピックアップ工程》
次に、半導体チップの回路面の反対面を、支持具であるセラミックス吸着ツールを用いて、ピックアップした。セラミックス吸着ツールは、ツールサイズ：７×７ｍｍ、ツール材質：セラミックス、ピックアップ温度：２００℃で、使用した。また、半導体チップの仕様は、株式会社ウォルツ製基板（品名：ＷＡＬＴＳ−ＴＥＧ ＣＣ８０−０１０１ＪＹ＿（ＳｉＮ）＿ＭｏｄｅｌＩ、幅：７．３ｍｍ×長さ：７．３ｍｍ×厚さ：０．７２５ｍｍ）であった。
<< (C) Chip pickup process >>
Next, the opposite surface of the circuit surface of the semiconductor chip was picked up using a ceramic adsorption tool which is a support. The ceramic adsorption tool was used at a tool size of 7 × 7 mm, a tool material: ceramics, and a pickup temperature of 200 ° C. The specifications of the semiconductor chip were a substrate manufactured by Waltz Co., Ltd. (product name: WALTS-TEG CC80-0101JY_ (SiN) _ModelI, width: 7.3 mm x length: 7.3 mm x thickness: 0.725 mm). ..
《（Ｄ）チップ実装工程》
ダイボンダーで、実装荷重：４０Ｎ、実装時間：０．６秒で、チップを熱圧着し。回路基板と半導体チップとの電気接続を行い、評価用試料を作製した。
<< (D) Chip mounting process >>
With a die bonder, the chip is heat-bonded with a mounting load of 40 N and a mounting time of 0.6 seconds. An evaluation sample was prepared by electrically connecting the circuit board and the semiconductor chip.
〔ボイドの評価〕
作成した試料のボイドの有無を、超音波顕微鏡（Ｃ−ＳＡＭ）画像，１５２８８０ピクセルを用い、観察した（ｎ＝１０）。ボイドがない場合を「◎」、ボイドが電極周辺になく、かつボイドが２個以下の場合を「○」、ボイドが電極周辺にある、またはボイドが３個以上の場合を「×」とした。表１、２に、結果を示す。
[Void evaluation]
The presence or absence of voids in the prepared sample was observed using an ultrasonic microscope (C-SAM) image, 152880 pixels (n = 10). The case where there is no void is marked with "◎", the case where there are no voids around the electrode and there are two or less voids is marked with "○", and the case where there are voids around the electrode or there are three or more voids is marked with "x". .. The results are shown in Tables 1 and 2.
〔粘性の評価〕
１６５℃で２時間加熱した後の絶縁性樹脂組成物層の粘性を、攪拌棒によって円を描くようにして攪拌しながら攪拌棒を持ち上げて引き離した場合の糸引きの有無で確認した。絶縁性樹脂組成物層が硬化して、糸引きがなく粘性がなかった場合を「○」、絶縁性樹脂組成物層が硬化せず、糸引きがあり粘性があった場合を「×」とした。表１、２に、結果を示す。
[Evaluation of viscosity]
The viscosity of the insulating resin composition layer after heating at 165 ° C. for 2 hours was confirmed by the presence or absence of stringing when the stirring rod was lifted and pulled apart while stirring in a circular motion with the stirring rod. When the insulating resin composition layer is cured and has no stringiness and is not viscous, it is evaluated as "○", and when the insulating resin composition layer is not cured and has stringiness and is not viscous, it is evaluated as "x". bottom. The results are shown in Tables 1 and 2.
表１〜２からわかるように、実施例１〜８の全てで、ボイド観察の結果が良好で、１６５℃、２時間で硬化した。特に、実施例１〜５、６〜８は、ボイドが全くなかった。これに対して、従来技術と同様に、（Ｄ）工程の後、支持具の冷却工程を設けた比較例１は、ボイドが観察された。熱硬化性樹脂の反応基と、硬化剤の反応基との当量比が低すぎる比較例２は、絶縁性樹脂層が硬化しなかった。熱硬化性樹脂の反応基と、硬化剤の反応基との当量比が高すぎる比較例３は、ボイドが観察された。 As can be seen from Tables 1 and 2, in all of Examples 1 to 8, the results of void observation were good, and the mixture was cured at 165 ° C. for 2 hours. In particular, Examples 1-5 and 6-8 had no voids at all. On the other hand, as in the prior art, voids were observed in Comparative Example 1 in which the support cooling step was provided after the step (D). In Comparative Example 2 in which the equivalent ratio of the reactive group of the thermosetting resin to the reactive group of the curing agent was too low, the insulating resin layer was not cured. Voids were observed in Comparative Example 3 in which the equivalent ratio of the reactive group of the thermosetting resin to the reactive group of the curing agent was too high.
以上のように、本発明のフリップチップ実装方法は、従来技術から吸着ツールの冷却時間の省略を可能にすることにより、フリップチップ実装の生産効率を著しく高くすることができ、非常に有用である。 As described above, the flip-chip mounting method of the present invention is extremely useful because the production efficiency of flip-chip mounting can be remarkably increased by making it possible to omit the cooling time of the suction tool from the prior art. ..
１ フリップチップ実装体
１０ 半導体チップ
１１ 突起電極
１２ 接合金属
１２Ａ 接合後の接合金属
１３ 回路面
２０ 回路基板
２１ 回路
３０ 絶縁性樹脂組成物層
４０ 支持具
４１ 空気の吸引孔
４２ 吸着面
1 Flip chip mount 10 Semiconductor chip 11
Claims (3)
（Ｂ）回路基板の回路上に、熱硬化性樹脂の反応基と、硬化剤の反応基との当量比が０．５〜０．７５である絶縁性樹脂組成物層を形成する回路基板準備工程と、
（Ｃ）空気の吸引孔を備えた吸着面を下面に有する支持具を上方から近づけ、回路面に突起電極が形成された半導体チップを、ピックアップして、１８０〜３００℃に加熱した支持具の吸着面に吸着させる、チップピックアップ工程と、
（Ｄ）支持具により吸着された半導体チップを、２１０℃〜２８０℃で加熱して、半導体チップの回路面を回路基板の絶縁樹脂組成物層に押圧して、半導体チップの突起電極の先端の接合金属を溶融させ、接合金属が凝固することにより、回路基板と半導体チップとを電気的接続するチップ実装工程とを、この順に、有し、
（Ｃ）工程において、半導体チップのピックアップ時の、支持具の吸着面と半導体チップの上面との距離が０．２ｍｍ〜１ｍｍの範囲であり、
（Ｄ）工程後、支持具が半導体チップの突起電極の先端の接合金属を溶融させた温度で、支持具の冷却工程を設けずに、次の半導体チップのフリップチップ実装を行うことを特徴とする、フリップチップ実装方法。 (A) A semiconductor chip having a protruding electrode having a bonded metal at its tip formed on the circuit surface is placed under a support having a suction surface having an air suction hole on the lower surface with the circuit surface facing down. Chip preparation process and
(B) Preparation of a circuit board for forming an insulating resin composition layer in which the equivalent ratio of the reactive group of the thermosetting resin and the reactive group of the curing agent is 0.5 to 0.75 on the circuit of the circuit board. Process and
(C) A support having a suction surface having an air suction hole on the lower surface is brought close to the support from above, and a semiconductor chip having a protruding electrode formed on the circuit surface is picked up and heated to 180 to 300 ° C. Chip pick-up process and suction surface
(D) a semiconductor chip that is adsorbed by the support, and heated at 2 10 ° C. to 280 ° C., to press the circuit surface of the semiconductor chip to the insulating resin composition layer of the circuit board, the tip of the bump electrode of the semiconductor chip The chip mounting process of electrically connecting the circuit board and the semiconductor chip by melting the bonding metal and solidifying the bonding metal is provided in this order.
In the step (C), the distance between the suction surface of the support and the upper surface of the semiconductor chip at the time of picking up the semiconductor chip is in the range of 0.2 mm to 1 mm.
After the step (D), in support is to melt the bonding metal tip of the projection electrodes of the semiconductor chip temperature, without providing the cooling step of the support, and characterized by performing the flip-chip mounting of the next semiconductor chip Flip chip mounting method.
Priority Applications (1)
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