JP2009232366A - 信号処理装置 - Google Patents
信号処理装置 Download PDFInfo
- Publication number
- JP2009232366A JP2009232366A JP2008077787A JP2008077787A JP2009232366A JP 2009232366 A JP2009232366 A JP 2009232366A JP 2008077787 A JP2008077787 A JP 2008077787A JP 2008077787 A JP2008077787 A JP 2008077787A JP 2009232366 A JP2009232366 A JP 2009232366A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- distortion
- duty cycle
- duty
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
- H03K5/086—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/003—Changing the DC level
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
- H04L25/4919—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using balanced multilevel codes
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Abstract
【解決手段】位相検出回路21は、0と1の出現確率が異なるデータ信号の位相の進みおよび遅れを検出する。AND回路43はデータ信号の立ち上がりを検出し、AND回路44は立ち下がりを検出する。+DCD検出回路45は、位相検出回路21とAND回路43および44の検出結果に基づいて、デューティサイクルのプラス側の歪みを検出し、−DCD検出回路46は、デューティサイクルのマイナス側の歪みを検出する。デューティ調整回路12は、+DCD検出回路45と−DCD検出回路46の検出結果に基づいて、デューティサイクルを調整することにより、デューティサイクルの歪みを補正する。本発明は、例えば、データ信号を受信する受信装置に適用することができる。
【選択図】図1
Description
Claims (6)
- 0と1の出現確率が異なるデータ信号のデューティサイクルの歪みを補正する補正回路
を備える信号処理装置。 - 前記補正回路は、
前記データ信号の位相の進みおよび遅れを検出する位相検出回路と、
前記データ信号の立ち上がりおよび立ち下がりを検出するエッジ検出回路と、
前記位相検出回路と前記エッジ検出回路の検出結果に基づいて、前記デューティサイクルの歪みを検出する歪み検出回路と、
前記歪み検出回路の検出結果に基づいて、前記デューティサイクルを調整することにより、前記デューティサイクルの歪みを補正するデューティ調整回路と
を備える
請求項1に記載の信号処理装置。 - 前記補正回路は、
前記歪み検出回路により歪みが検出された頻度に基づいて、前記デューティ調整回路による調整の度合を表すデューティ調整値の増減値を決定する調整値決定回路
をさらに備え、
前記デューティ調整回路は、前記デューティ調整値の増減値に基づいて、前記デューティサイクルを調整する
請求項2に記載の信号処理装置。 - 前記歪み検出回路は、前記デューティサイクルのプラス側およびマイナス側の歪みを検出し、
前記調整値決定回路は、前記歪み検出回路により前記デューティサイクルのプラス側の歪みが検出された頻度と、前記デューティサイクルのマイナス側の歪みが検出された頻度の差分が所定の範囲内の値である場合、前記デューティ調整値の増減値をゼロに決定する
請求項3に記載の信号処理装置。 - 前記歪み検出回路は、前記位相検出回路による検出結果と、前記エッジ検出回路による検出結果の組み合わせに基づいて、前記デューティサイクルの歪みを検出する
請求項2に記載の信号処理装置。 - 前記位相検出回路は、アレクサンダ型の位相比較器である
請求項2に記載の信号処理装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008077787A JP4735992B2 (ja) | 2008-03-25 | 2008-03-25 | 信号処理装置 |
EP09155222A EP2114010A1 (en) | 2008-03-25 | 2009-03-16 | Signal processing device |
CN200910128779A CN101546995A (zh) | 2008-03-25 | 2009-03-19 | 信号处理设备 |
US12/408,827 US7956660B2 (en) | 2008-03-25 | 2009-03-23 | Signal processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008077787A JP4735992B2 (ja) | 2008-03-25 | 2008-03-25 | 信号処理装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009232366A true JP2009232366A (ja) | 2009-10-08 |
JP4735992B2 JP4735992B2 (ja) | 2011-07-27 |
Family
ID=41077562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008077787A Expired - Fee Related JP4735992B2 (ja) | 2008-03-25 | 2008-03-25 | 信号処理装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7956660B2 (ja) |
EP (1) | EP2114010A1 (ja) |
JP (1) | JP4735992B2 (ja) |
CN (1) | CN101546995A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9552310B2 (en) | 2013-10-31 | 2017-01-24 | Fujitsu Limited | Signal control circuit, information processing apparatus, and signal control method |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101331442B1 (ko) * | 2012-06-29 | 2013-11-21 | 포항공과대학교 산학협력단 | 듀티 싸이클 보정기능이 루프 내에 내장된 지연고정루프 |
CN103684440B (zh) * | 2012-09-04 | 2017-10-27 | 瑞昱半导体股份有限公司 | 时脉与数据回复电路以及时脉与数据回复方法 |
US8629694B1 (en) * | 2012-10-10 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of voltage scaling techniques |
US8994427B2 (en) * | 2013-07-09 | 2015-03-31 | Oracle International Corporation | Method and apparatus for duty cycle distortion compensation |
CN104038185B (zh) * | 2014-05-23 | 2017-02-22 | 大连理工大学 | 上升沿检测电路 |
CN107078723B (zh) * | 2017-01-23 | 2020-08-25 | 深圳市汇顶科技股份有限公司 | 信号处理系统和信号处理的方法 |
CN111273726B (zh) * | 2018-12-05 | 2021-06-29 | 锐迪科(重庆)微电子科技有限公司 | 占空比偏差补偿电路、方法及芯片 |
KR20210031278A (ko) | 2019-09-11 | 2021-03-19 | 삼성전자주식회사 | 파라미터의 에러를 검출하는 파라미터 모니터링 회로, 듀티 사이클 정정 회로 및 임피던스 정정 회로 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0661991A (ja) * | 1992-06-19 | 1994-03-04 | Advanced Micro Devices Inc | Dcdジッタを訂正する方法および装置 |
JPH06334496A (ja) * | 1993-05-20 | 1994-12-02 | Sony Corp | 2値化回路 |
JP2001124813A (ja) * | 1999-10-27 | 2001-05-11 | Nec Ic Microcomput Syst Ltd | クロックデューティ検査回路およびクロックデューティ検査が可能なマイクロコンピュータ |
JP2008543184A (ja) * | 2005-05-24 | 2008-11-27 | フィニサー コーポレイション | クロック修正のためのパターン依存位相検出器 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7049866B2 (en) * | 2004-03-24 | 2006-05-23 | Agere Systems Inc. | Compensating for leakage currents in loop filter capacitors in PLLs and the like |
KR100800144B1 (ko) * | 2006-05-12 | 2008-02-01 | 주식회사 하이닉스반도체 | 지연 고정 루프 장치 및 지연 고정 방법 |
EP1898582A1 (en) * | 2006-09-08 | 2008-03-12 | Realtek Semiconductor Corp. | Method and apparatus for correcting duty cycle distortion |
JP4646073B2 (ja) | 2006-09-22 | 2011-03-09 | Kddi株式会社 | 劣化を伴うデジタルデータ複製方法および装置 |
-
2008
- 2008-03-25 JP JP2008077787A patent/JP4735992B2/ja not_active Expired - Fee Related
-
2009
- 2009-03-16 EP EP09155222A patent/EP2114010A1/en not_active Withdrawn
- 2009-03-19 CN CN200910128779A patent/CN101546995A/zh active Pending
- 2009-03-23 US US12/408,827 patent/US7956660B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0661991A (ja) * | 1992-06-19 | 1994-03-04 | Advanced Micro Devices Inc | Dcdジッタを訂正する方法および装置 |
JPH06334496A (ja) * | 1993-05-20 | 1994-12-02 | Sony Corp | 2値化回路 |
JP2001124813A (ja) * | 1999-10-27 | 2001-05-11 | Nec Ic Microcomput Syst Ltd | クロックデューティ検査回路およびクロックデューティ検査が可能なマイクロコンピュータ |
JP2008543184A (ja) * | 2005-05-24 | 2008-11-27 | フィニサー コーポレイション | クロック修正のためのパターン依存位相検出器 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9552310B2 (en) | 2013-10-31 | 2017-01-24 | Fujitsu Limited | Signal control circuit, information processing apparatus, and signal control method |
Also Published As
Publication number | Publication date |
---|---|
US20090243685A1 (en) | 2009-10-01 |
CN101546995A (zh) | 2009-09-30 |
EP2114010A1 (en) | 2009-11-04 |
US7956660B2 (en) | 2011-06-07 |
JP4735992B2 (ja) | 2011-07-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4735992B2 (ja) | 信号処理装置 | |
US10679716B2 (en) | Calibration apparatus and method for sampler with adjustable high frequency gain | |
US8098724B2 (en) | Automatic calibration in high-speed serial interface receiver circuitry | |
US9264219B1 (en) | Clock and data recovery circuit and method | |
US7733143B2 (en) | Duty cycle correction circuit for high-speed clock signals | |
US10009166B2 (en) | Hybrid clock data recovery circuit and receiver | |
JP2009118186A (ja) | クロックデータ復元装置 | |
US10666234B2 (en) | Transmission circuit and integrated circuit | |
TWI282920B (en) | Method of adjusting vertical offset, retiming apparatus, and receiver system | |
KR20200069201A (ko) | 신속하게 안정화하는 직교 위상 검출 및 정정을 제공하는 시스템 및 방법 | |
WO2018204010A1 (en) | Apparatus and method for cancelling pre-cursor inter-symbol-interference | |
US9543961B2 (en) | Current detection circuit and pile-up detection circuit | |
JP4656260B2 (ja) | 受信装置 | |
JP6536347B2 (ja) | 周波数検出方法 | |
US9698808B1 (en) | Phase measurement and correction circuitry | |
US20170019114A1 (en) | Phase detection circuit and signal recovery circuit that includes phase detection circuit | |
US20190181819A1 (en) | Automatic gain control apparatus and automatic gain control method | |
JP2011171895A (ja) | Cdr回路 | |
JP2012151699A (ja) | ラッチ回路、cdr回路、および受信装置 | |
CN107846207B (zh) | 差动信号偏斜检测电路 | |
US9813227B2 (en) | At-rate SERDES clock data recovery with controllable offset | |
JP5560646B2 (ja) | オーバーサンプリング回路、及びそれを用いたシリアル通信システム | |
US9304535B2 (en) | Baud rate phase detector with no error latches | |
EP3954046B1 (en) | Dynamic integration time adjustment of a clocked data sampler using a static analog calibration circuit | |
JP6475202B2 (ja) | 位相比較回路、及びその制御方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100305 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100630 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100805 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100924 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110331 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110413 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140513 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |