JP2009218370A - Production process of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production process of a semiconductor device that reduces its cost while assuring its performance. <P>SOLUTION: An AlN layer 3, a GaN layer 4, an i-AlGaN layer 5, an n-AlGaN layer 6, and an n-GaN layer 7 are formed on a substrate 1 on which a through-hole 2 is formed. Further, a source electrode 9s, a drain electrode 9d, and a gate electrode 9g are formed to form a semiconductor element. After that, ultraviolet rays are irradiated directed to the through-hole 2 in an HF solution to isolate the AlN layer 3 from the substrate 1. Later, the AlN layer 3 is removed, and an insulating substrate is laminated to the back of the GaN layer 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a GaN (gallium nitride) -based high electron mobility transistor (HEMT).

  In recent years, GaN-based semiconductor devices such as GaN-based HEMTs are expected to be applied as high breakdown voltage / high-speed devices because of the wide band gap of GaN. So far, in the GaN-based HEMT, the best output characteristics are obtained when a SiC substrate is used as the substrate. This is because the lattice constants of GaN and SiC are close, so there are few defects in the GaN layer grown on the SiC substrate, and because the thermal conductivity of the SiC substrate is high, the thermal radiation characteristics are high.

  In addition, in a GaN-based semiconductor device capable of high-frequency operation, a semi-insulating SiC substrate is particularly used. This is to keep the parasitic capacitance low. However, the price of a semi-insulating SiC substrate is very high compared to a conductive SiC substrate. This may impede the spread of GaN-based semiconductor devices such as GaN-based HEMTs despite their excellent performance.

  Therefore, research for manufacturing GaN-based semiconductor devices at low cost has been conducted. For example, in a manufacturing method, first, a nitride-based semiconductor crystal layer is epitaxially grown on a SiC substrate, and then hydrogen ions are implanted into the semiconductor crystal layer. Next, the surface of the semiconductor crystal layer is bonded to the surface of a support substrate such as a silicon substrate. Then, the semiconductor crystal layer is separated along the portion where hydrogen ions are implanted. In this way, a structure in which the semiconductor crystal layer is located on the support substrate is obtained. Thereafter, if a semiconductor element or the like is formed in the semiconductor crystal layer, a semiconductor device can be obtained.

  However, in this conventional method, hydrogen ions remain in the semiconductor crystal layer on the support substrate, which is a heat dissipation member. For this reason, this hydrogen ion becomes a defect and sufficient performance cannot be obtained.

JP 2007-220899 A

  An object of the present invention is to provide a semiconductor device manufacturing method capable of reducing cost while ensuring performance.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

  In one aspect of the method for manufacturing a semiconductor device, a compound semiconductor crystal layer is formed on a crystal growth substrate in which a through hole is formed, and then, in a predetermined etching solution, the crystal growth substrate is irradiated with ultraviolet rays. The compound semiconductor crystal layer is separated from the crystal growth substrate.

  According to the above method for manufacturing a semiconductor device, even if an expensive crystal growth substrate that affects the crystallinity of the compound semiconductor crystal layer is selected, the crystal growth substrate is not included in the semiconductor device, so that it is repeatedly used. can do. Accordingly, the consumption of the crystal growth substrate can be reduced and the cost can be reduced. On the other hand, since the crystallinity of the compound semiconductor crystal layer is ensured, the performance can be maintained.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. 1A to 1T are cross-sectional views showing a method of manufacturing a GaN-based HEMT (semiconductor device) according to the first embodiment in the order of steps.

  In this embodiment, first, as shown in FIGS. 1A and 2, a substrate 1 in which a plurality of through holes 2 are formed is formed as a crystal growth substrate. For example, the diameter of the through hole 2 is 5 μm, and the repetition period (center distance between adjacent through holes 2) is 10 μm. The substrate 1 is made of, for example, semi-insulating SiC.

  Here, a method of forming the through hole 2 will be described. First, a seed metal layer is formed on the back surface of a disk-shaped semi-insulating SiC substrate by a sputtering method. In forming the seed metal layer, for example, a Ti layer having a thickness of 10 nm is formed, and then a Cu layer having a thickness of 200 nm is formed. Further, for example, a Ni layer having a thickness of 100 nm may be formed after forming a Ti layer having a thickness of 10 nm. After the seed metal layer is formed, a resist film having a thickness of about 3 μm is formed thereon, and the resist film is patterned to form a resist pattern that covers a region where the through hole 2 is to be formed. Next, a Ni layer having a thickness of about 3 μm is formed on the seed metal layer by electroplating. At this time, the temperature of the warm bath layer is 50 ° C. to 60 ° C., and the plating rate is about 0.5 μm / min. Thereafter, the resist pattern is removed. Further, the seed metal layer exposed from the Ni layer is removed by ion milling. As a result, a metal mask that opens a region where the through hole 2 is to be formed is formed. The milling rate of the Ti layer is about 15 nm / min, the milling rate of the Cu layer is about 53 nm / min, and the milling rate of the Ni layer is about 25 nm / min.

Subsequently, using a mixed gas of SF ₆ and O ₂ , the semi-insulating SiC substrate is etched from the back side using an antenna power of 900 W, a bias power of 150 W, and a Ni layer as a metal mask. The etching rate is about 0.75 μm / min. Next, the Ni layer and the seed metal layer are removed by ion milling. In this way, the through hole 2 can be formed. An example of the SEM photograph of the through hole 2 is shown in FIG.

  After the through hole 2 is formed, as shown in FIG. 1B, an AlN layer 3 having a thickness of about 50 nm is formed as a nucleation layer on the substrate 1 by a hydride vapor phase epitaxy (HVPE) method. . The AlN layer 3 constitutes a part of the compound semiconductor crystal layer.

Next, as shown in FIGS. 1C to 1E, a GaN layer 4 having a thickness of about 3 μm is formed on the AlN layer 3 by HVPE. As the source gas, for example, a mixed gas of GaCl and NH ₃ is used. The pressure is normal pressure and the growth temperature is 1000 ° C. Under such conditions, the GaN layer 4 grows in a conical shape at the initial stage of growth, as shown in FIG. 1C. Thereafter, the GaN layer 4 also grows in the lateral direction, and the opening due to the through hole 2 disappears as shown in FIG. 1D. Further, when the GaN layer 4 grows, the surface becomes flat as shown in FIG. 1E. The GaN layer 4 constitutes a part of the compound semiconductor crystal layer.

After the formation of the GaN layer 4, as shown in FIG. 1F, an i-AlGaN layer 5 having a thickness of about 5 nm is formed on the GaN layer 4. The i-AlGaN layer 5 is an AlGaN layer that is not intentionally doped with impurities. Next, an n-AlGaN layer 6 having a thickness of about 30 nm is formed on the i-AlGaN layer 5 as an electron supply layer. The n-AlGaN layer 6 is an n-type AlGaN layer doped with Si at a concentration of about 5 × 10 ¹⁸ cm ⁻³ . Thereafter, an n-GaN layer 7 having a thickness of about 10 nm is formed on the n-AlGaN layer 6. The n-GaN layer 7 is an n-type GaN layer doped with Si at a concentration of about 5 × 10 ¹⁸ cm ⁻³ . The i-AlGaN layer 5, the n-AlGaN layer 6, and the n-GaN layer 7 constitute a part of the compound semiconductor crystal layer.

  Subsequently, as shown in FIG. 1G, a resist pattern 51 is formed on the n-GaN layer 7 to open a region where a source electrode is to be formed and a region where a drain electrode is to be formed.

  Next, dry etching using a chlorine-based gas is performed on the n-GaN layer 7 using the resist pattern 51 as a mask, whereby two openings 8 are formed in the n-GaN layer 7 as shown in FIG. 1H. Form. In addition, regarding the depth of the opening 8, a part of the n-GaN layer 7 may be left, or a part of the n-AlGaN layer 6 may be removed. That is, the depth of the opening 8 does not need to match the thickness of the n-GaN layer 7.

  Thereafter, as shown in FIG. 1I, a source electrode 9 s is formed in one opening 8, and a drain electrode 9 d is formed in the other opening 8. In forming the source electrode 9s and the drain electrode 9d, for example, a Ti layer is formed by an evaporation method, and an Al layer is formed thereon by an evaporation method. Then, the resist pattern 51 is removed. That is, in forming the source electrode 9s and the drain electrode 9d, for example, vapor deposition and lift-off techniques are used.

  Subsequently, heat treatment is performed at 600 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 9s and the drain electrode 9d.

  Next, as shown in FIG. 1J, a passivation film 10 covering the source electrode 9s and the drain electrode 9d is formed on the n-GaN layer 7 by plasma enhanced chemical vapor deposition (PECVD). . For example, a silicon nitride film is formed as the passivation film 10.

  Subsequently, as shown in FIG. 1K, a resist pattern 52 that opens a region where a gate electrode is to be formed is formed on the passivation film 10.

  Next, the passivation film 10 is etched using the resist pattern 52 as a mask, thereby forming an opening 11 in the passivation film 10 as shown in FIG. 1L.

  Thereafter, as shown in FIG. 1M, a gate electrode 9g is formed in the opening 11. In forming the gate electrode 9g, for example, an Ni layer is formed by an evaporation method, and an Au layer is formed thereon by an evaporation method.

  Then, as shown in FIG. 1N, the resist pattern 52 is removed. That is, for example, vapor deposition and lift-off techniques are used in forming the gate electrode 9g.

  Next, as shown in FIG. 1O, a passivation film 12 covering the drain electrode 9g is formed on the passivation film 10 by PECVD. For example, a silicon nitride film is formed as the passivation film 12.

  Thereafter, as shown in FIG. 1P, a surface protective layer 61 is formed on the passivation film 12. The surface protective layer 61 is made of a material having hydrofluoric acid resistance such as wax or resist. Subsequently, a substrate 62 is attached on the surface protective layer 61. As the substrate 62, for example, a substrate having hydrofluoric acid resistance such as a Si substrate or a resin substrate is used.

  Next, as shown in FIG. 1Q, the AlN layer 3 is separated from the substrate 1. In this separation, as shown in FIG. 4, the structure before separation is immersed in a hydrofluoric acid (HF) solution in a tank 71, and ultraviolet rays are irradiated from the back surface. Irradiation with ultraviolet rays is performed using, for example, a mercury lamp. When ultraviolet rays are irradiated into the through hole 2, electrons accumulate in the vicinity of the interface between the SiC substrate 1 and the AlN layer 3. Due to the influence of the electrons, the etching of the substrate 1 is promoted near the interface as shown in FIG. As a result, the substrate 1 and the AlN layer 3 are separated from each other. That is, in this embodiment, the AlN layer 3 is separated from the substrate 1 by photoelectrochemical etching.

  After separation of the substrate 1 and the AlN layer 3, as shown in FIG. 1R, the back surface side of the GaN layer 4 is polished by a chemical mechanical polishing (CMP) method or the like. As a result, the AlN layer 3 is removed, and the back surface of the GaN layer 4 becomes flat.

Next, for example, as shown in FIG. 1S, the substrate 21 is bonded to the back surface of the GaN layer 4 as an insulating heat dissipation member by a wafer direct bonding method. As the substrate 21, an AlN substrate, an amorphous SiC substrate, an amorphous C (diamond like carbon (DLC)) substrate, or the like is used. In this bonding, the back surface of the GaN layer 4 is cleaned by acid cleaning, and then the back surface is made hydrophilic by O ₂ plasma treatment or the like. Similarly, hydrophilic treatment is performed on the surface of the substrate 21. Then, the surfaces subjected to the hydrophilic treatment are overlapped and joined. Thereafter, heat treatment is performed at a temperature within a range where the HEMT including the gate electrode 9g, the source electrode 9s, and the drain electrode 9d is not destroyed, for example, 400 ° C., and the bonding strength between the substrate 21 and the GaN layer 4 is improved.

  Subsequently, as shown in FIG. 1T, the surface protective layer 61 and the substrate 62 are removed. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  On the other hand, for the substrate 1 separated from the AlN layer 3, the surface in contact with the AlN layer 3 is polished and flattened by a CMP method or the like. It can be said that the state of the substrate 1 after planarization has not changed except that it is slightly thinner than before the formation of the AlN layer 3. Therefore, if the substrate 1 is processed after the formation of the AlN layer 3, a GaN-based HEMT can be formed repeatedly.

  Further, since the characteristics of the substrate 21 do not affect the crystallinity of the GaN layer 4, it is only necessary to ensure insulation and high heat dissipation (thermal conductivity). Therefore, the performance of the GaN-based HEMT does not deteriorate even when a less expensive one than a semi-insulating SiC substrate such as an AlN substrate, an amorphous SiC substrate, or an amorphous C substrate is used. As described above, in the first embodiment, even if an expensive substrate 1 as a crystal growth substrate is used, the substrate 1 is not a constituent element of the GaN-based HEMT, and the substrate 21 is inexpensive. Since sufficient performance can be obtained even when using, cost can be reduced while obtaining high performance.

  It is also possible to use a diamond substrate as the substrate 21. In this case, the cost may increase, but higher heat dissipation can be obtained as compared with a semi-insulating SiC substrate. It is also possible to use a BN substrate as the substrate 21.

  In the semiconductor device manufactured by such a method, the crystallinity (the presence or absence of crystal defects, etc.) of the GaN layer 4 or the like that is a compound semiconductor crystal layer depends on the atomic arrangement of the substrate 1 and in the substrate 21 that is a heat dissipation member. It is independent from the atomic arrangement.

(Second Embodiment)
Next, a second embodiment will be described. 6A to 6B are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (semiconductor device) according to the second embodiment in the order of steps.

In the present embodiment, first, similarly to the first embodiment, processing up to separation of the AlN layer 3 from the substrate 1 is performed (FIG. 1Q). Next, as shown in FIG. 6A, a plasma-based ion implantation and deposition (PBII & D) method is used to form the DLC film 22 covering the AlN layer 3 on the back surface of the GaN layer 4 as an insulating heat dissipation member. To form. In forming the DLC film 22, for example, a structure including the substrate 62 and the GaN layer 4 is placed in a chamber, and C ₂ H ₂ plasma is generated in the chamber at a high frequency (pulse voltage: 20 kV, pulse width: 10 μs). Excited. Subsequently, a negative high voltage pulse (pulse voltage: −20 kV, pulse width: 5 μs) is applied. Such plasma excitation and voltage application are repeated until a DLC film 22 having a predetermined thickness is obtained.

  After the formation of the DLC film 22, as shown in FIG. 6B, the surface protective layer 61 and the substrate 62 are removed. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  The effect similar to 1st Embodiment can be acquired also by such 2nd Embodiment. Further, since it is not necessary to remove the AlN layer 3, the number of steps can be reduced as compared with the first embodiment.

  When applying a negative high voltage pulse, it is preferable to adjust the duty ratio of the high voltage pulse so that the process temperature is 200 ° C. or lower. For this purpose, the duty ratio is set to 10% or less, for example.

Moreover, it is preferable to clean the back surface of the GaN layer 4 using Ar gas before the DLC film 22 is formed. In addition, it is also preferable to improve adhesion with the DLC film 22 by attaching carbon atoms and hydrogen atoms to the back surface of the GaN layer 4 using CH ₄ gas. Also, nitrogen atoms are ion-implanted into the back surface of the GaN layer 4, and then carbon atoms are ion-implanted into the back surface of the GaN layer 4, thereby preventing adhesion of carbon atoms into the GaN layer 4. It is also preferable to improve it.

  Similarly, in order to improve adhesion, it is also preferable to form an amorphous SiC layer as an intermediate layer on the back surface of the GaN layer 4 by sputtering before forming the DLC film 22.

(Third embodiment)
Next, a third embodiment will be described. 7A to 7F are cross-sectional views showing a method of manufacturing a GaN-based HEMT (semiconductor device) according to the third embodiment in the order of steps.

  In the present embodiment, first, similarly to the first embodiment, processing up to the formation of the n-GaN layer 7 is performed (FIG. 1F). Next, as shown in FIG. 7A, a surface protective layer 61 is formed on the n-GaN layer 7, and a substrate 62 is attached thereon.

  Thereafter, as shown in FIG. 7B, the substrate 1 and the AlN layer 3 are separated. This separation is performed in the same manner as in the first embodiment.

  Subsequently, as shown in FIG. 7C, the back surface side of the GaN layer 4 is polished by a CMP method or the like. As a result, the AlN layer 3 is removed, and the back surface of the GaN layer 4 becomes flat.

  Next, as shown in FIG. 7D, for example, the substrate 21 is bonded to the back surface of the GaN layer 4 by a wafer direct bonding method.

  Thereafter, as shown in FIG. 7E, the surface protective layer 61 and the substrate 62 are removed.

  Subsequently, as shown in FIG. 7F, similarly to the first embodiment, the source electrode 9s and the drain electrode 9d are formed, the gate electrode 9 is formed, and the passivation films 10 and 12 are formed. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  According to the third embodiment as described above, the same effect as that of the first embodiment can be obtained. That is, even if the substrate is replaced before forming the gate electrode 9g, the source electrode 9s, and the drain electrode 9d, the same effect as that of the first embodiment can be obtained. Further, as in the second embodiment, the DLC film 22 may be formed with the AlN layer 3 left.

  Note that the GaN-based HEMT manufactured by these methods can be used, for example, for a high-power amplifier included in a base station for wireless communication. Moreover, it can be used for an AC-AC converter, an AC-DC converter, a high frequency power supply, etc. as a power supply application. In power supply applications, it is possible to reduce the size of passive components and reduce the number of elements by increasing the frequency by utilizing the high breakdown voltage, low loss, and high-speed switching characteristics of GaN. It becomes possible. And by these, size reduction, weight reduction, and cost reduction of a power converter device are realizable.

  The material of the nucleation layer is not limited to AlN, and can be appropriately selected depending on the crystal layer formed thereon. For example, when the crystal layer formed thereon is a GaN-based crystal layer, an AlN-based crystal layer can be used as the nucleation layer. Further, the material of the compound semiconductor crystal layer is not limited. For example, a nitride semiconductor such as GaN, AlN, or InN may be used alone, or a mixed crystal of two or more of these may be used.

  Further, the size, pitch and shape of the through holes 2 are not particularly limited. However, it is preferable that the opening of the compound semiconductor crystal layer due to the through hole 2 is such that it easily disappears as the compound semiconductor crystal layer grows in the lateral direction. It is also preferable that the etching solution can easily enter during separation.

  The material of the crystal growth substrate is not particularly limited, and a sapphire substrate, a zinc oxide substrate, or the like can be used in addition to the semi-insulating SiC substrate. However, in order to suppress defects in the compound semiconductor crystal layer, it is preferable to use a semi-insulating SiC substrate.

  Further, the growth conditions of the compound semiconductor crystal layer are not particularly limited. However, it is preferable that the opening easily disappears with the lateral growth. Various epitaxial lateral overgrowth (ELO) techniques have been developed for GaN-based crystal layers. For example, FIELO (facet-initiated ELO) technology based on the HVPE method as described above and FACELO (facet-controlled ELO) technology based on the metal-organic vapor phase epitaxy (MOVPE) method have been developed. ing.

  Further, the semiconductor element formed on the compound semiconductor crystal layer is not limited to HEMT. For example, an insulated gate bipolar transistor (IGBT) may be formed.

  An etching solution used for photoelectrochemical etching is not limited to a hydrofluoric acid solution (HF solution).

  Further, the method for forming the through hole 2 is not particularly limited, and for example, laser etching may be performed. In addition, the problem accompanying the through hole 2 may arise. For example, the GaN layer 4 may be damaged when the substrate 1 is vacuum-adsorbed. In such a case, an embedding material may be embedded in the through hole 2 from the back side after the through hole 2 is formed. The embedding material may be removed before separation. As the embedding material, for example, spin on glass (SOG) can be used. The embedding method is not particularly limited. For example, SOG may be applied to the back surface of the substrate 1 and sintered, and then the back surface may be flattened by CMP or the like. Such a method is described, for example, in Japanese Patent Application Laid-Open No. 2006-278609 as a method of embedding micropipes.

It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. FIG. 1B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1A. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1B. 1C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1C. 2D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1D. 2E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1E. 1F is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1F. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1G. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1H. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1I. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1J. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1K. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1L. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1M. 1N is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1N. FIG. 10 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 10. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1P. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1Q. 1R is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1R. FIG. 2 is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1S. 1 is a plan view showing a substrate 1. FIG. It is a figure which shows an example of the SEM photograph of the through-hole 2. FIG. FIG. 3 is a diagram showing a method for separating an AlN layer 3 from a substrate 1. It is a figure which shows the detail of photoelectrochemical etching. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 6A. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 3rd Embodiment. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7A. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7B. 7C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7C. FIG. 7D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7D. FIG. 7E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7E.

Explanation of symbols

1: Substrate 2: Through hole 3: AlN layer 4: GaN layer 5: i-AlGaN layer 6: n-AlGaN layer 7: n-GaN layer 9d: drain electrode 9g: gate electrode 9s: source electrode 10: passivation film 12 : Passivation film 21: Substrate 22: Substrate 62: Substrate

Claims (5)

Forming a compound semiconductor crystal layer on the crystal growth substrate in which the through hole is formed;
Separating the compound semiconductor crystal layer from the crystal growth substrate by irradiating the crystal growth substrate with ultraviolet rays in a predetermined etching solution;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein a nitride semiconductor crystal layer is used as the compound semiconductor crystal layer.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the nitride semiconductor crystal layer is made of one or two or more mixed crystals selected from the group consisting of GaN, AlN and InN.   The method for manufacturing a semiconductor device according to claim 1, wherein a SiC substrate is used as the crystal growth substrate.   5. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of attaching a substrate to the compound semiconductor layer after the separating step. 6.

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