JP2009206298A - Multi-layer printed wiring board, its inspecting method and its manufacturing method - Google Patents

Multi-layer printed wiring board, its inspecting method and its manufacturing method Download PDF

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JP2009206298A
JP2009206298A JP2008047049A JP2008047049A JP2009206298A JP 2009206298 A JP2009206298 A JP 2009206298A JP 2008047049 A JP2008047049 A JP 2008047049A JP 2008047049 A JP2008047049 A JP 2008047049A JP 2009206298 A JP2009206298 A JP 2009206298A
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wiring board
pattern
printed wiring
multilayer printed
inspection
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JP5050924B2 (en
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Hideaki Komoda
英明 菰田
Hideki Higashitani
秀樹 東谷
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Panasonic Corp
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<P>PROBLEM TO BE SOLVED: To solve the problem that, when a result of visual inspection in a state of an inner layer substrate is clearly expressed with the use of oil markers or stickers to detect the result after multi-layering, there is a risk of outflow of defective products due to erasing of the markers or peeling of the stickers, or the problem that, in a method of working with a retractable knife, a drill, or a metal mold, a surface of a printed wiring board is scratched when the board is laminated or foreign matters are stuck to the surface in a post process owing to machining dust produced at working or burr of the worked part. <P>SOLUTION: An inspecting pattern is constituted by a conductive pattern of each layer and a conductor electrically connecting the conductor pattern of each layer. The inspecting pattern corresponding to an individual wiring board with defects in an inner layer circuit has a configuration wherein a resistance value between the conductive pattern and the conductor is varied to indicate the presence of defects in the corresponding individual wiring board by the resistance value of the pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明はパソコン、移動体通信機器、ビデオカメラ等の各種電子機器に用いられる多層プリント配線板とその製造方法に関するものである。   The present invention relates to a multilayer printed wiring board used in various electronic devices such as a personal computer, a mobile communication device, and a video camera, and a manufacturing method thereof.

近年、電子機器の高機能化、高密度化に伴い、電子機器を構成する電子部品は、ますます小型化、高集積化、高速化、高機能化の傾向にあり、これらの要求に対応するために、プリント配線板も様々な形態が提案され、実用化されてきている。   In recent years, as electronic devices have higher functionality and higher density, electronic components that make up electronic devices are becoming increasingly smaller, highly integrated, faster, and more functional. For this reason, various forms of printed wiring boards have been proposed and put into practical use.

特に、多層化の際に内層基板や銅箔を接着させる接着層に直接、導電性ペーストを充填した後に積層一体化する技術が確立されたことにより、ドリル加工および金属めっきによる貫通スルーホールを必要とすることなく、任意の層間をIVH(インナースティシャル・バイア・ホール)で電気的に接続することが可能となった。   In particular, a through-hole is required for drilling and metal plating because the technology for stacking and integrating the conductive paste directly after filling the adhesive layer that adheres the inner layer substrate and copper foil when multilayering is established. Thus, any layer can be electrically connected by IVH (inner-stitial via hole).

以下に上記の従来のプリント配線板の製造方法について説明する。図5(a)〜(j)は従来のプリント配線板の製造方法を示す断面図である。   A method for manufacturing the above-described conventional printed wiring board will be described below. 5A to 5J are cross-sectional views showing a conventional method for manufacturing a printed wiring board.

はじめに図5(a)に示すようにプリプレグ1の両面にPET(ポリエチレンテレフタレート)などのフィルム2をラミネートし、これに図5(b)のようにドリル加工や炭酸ガスレーザ加工によってビア3を形成する。次に図5(c)に示すように印刷などの方法によりビア3内に導電体として導電性ペースト4を充填し、その後、フィルム2をプリプレグ1から剥離することにより図5(d)に示すような、ビア3内に導電性ペースト4が充填されたプリプレグ1を得る。そして図5(e)のようにこれの両面に銅箔5を配置し、熱プレスによって加熱加圧することで図5(f)となり、その後、両面の銅箔5をエッチングなどにより導電パターン6を形成し図5(g)に示す両面基板が完成する。こうして完成した両面基板を内層用のコア基板として用い、図5(h)に示すように内層用のコア基板の外側に別途、上記の手順と同様の方法で作製したビア3内に導電性ペースト4が充填されたプリプレグ1を配置し、さらにその外側に銅箔5を配置した後に、熱プレスによって加熱加圧し図5(i)となり、両面の銅箔5をエッチングなどにより導電パターンを形成し図5(j)に示す4層基板が完成する。   First, as shown in FIG. 5 (a), films 2 such as PET (polyethylene terephthalate) are laminated on both sides of the prepreg 1, and vias 3 are formed thereon by drilling or carbon dioxide laser processing as shown in FIG. 5 (b). . Next, as shown in FIG. 5C, the via 3 is filled with the conductive paste 4 as a conductor by a method such as printing, and then the film 2 is peeled off from the prepreg 1 so as to be shown in FIG. Thus, the prepreg 1 in which the conductive paste 4 is filled in the via 3 is obtained. Then, as shown in FIG. 5 (e), the copper foils 5 are arranged on both sides thereof and heated and pressed by hot press to obtain FIG. 5 (f). Thereafter, the conductive patterns 6 are formed on the copper foils 5 by etching or the like. The double-sided substrate formed as shown in FIG. The completed double-sided substrate is used as the inner layer core substrate. As shown in FIG. 5 (h), the conductive paste is provided in the via 3 prepared by the same method as described above, outside the inner layer core substrate. 4 is disposed, and a copper foil 5 is disposed outside the prepreg 1, and then heated and pressed by hot press to form FIG. 5 (i), and a conductive pattern is formed on the copper foil 5 on both sides by etching or the like. The four-layer substrate shown in FIG. 5 (j) is completed.

こうして完成したプリント配線板の導電パターン6の断線、ショートといった不良を検出する方法としては、従来より製品の実装ランド等から選択した検査ポイントに対応した位置に検査用プローブを配設した専用の検査治具を製品毎に作製し、この検査用プローブを製品の検査ポイントに当接させて電気導通の有無もしくは電気抵抗値の大小を確認することで良否を判定するという電気検査が一般に行われてきた。しかしながら近年では、導電パターン6の高密度化に伴ってパターン幅およびパターン間隙が小さくなる中で、上記の電気検査に加えて導電パターン6の形状を認識する外観検査によって断線、ショートとしては検出できないような欠損、凹み、細り、太り、銅残りといった潜在的不良を検出することが要求されてきている。   As a method for detecting defects such as disconnection or short-circuit of the conductive pattern 6 of the printed wiring board thus completed, a dedicated inspection in which an inspection probe is disposed at a position corresponding to an inspection point selected from a mounting land of a product conventionally. An electrical inspection is generally performed in which a jig is manufactured for each product, and this inspection probe is brought into contact with an inspection point of the product to determine whether the electrical conduction is present or not, and whether the electrical resistance value is large or small. It was. However, in recent years, as the pattern width and the pattern gap become smaller as the density of the conductive pattern 6 increases, in addition to the electrical inspection described above, it cannot be detected as a disconnection or short circuit by an appearance inspection that recognizes the shape of the conductive pattern 6. It has been required to detect potential defects such as defects, dents, thinnings, fats, and copper residues.

多層プリント配線板においてはこの外観検査を各層毎に行う必要がある。内層は多層化した後には内部に隠れるため、内層基板の状態で外観検査を行わなければならない。この段階で不良を検出した場合は、その場で廃棄するか、あるいはその検査結果を多層化後にも検知可能にするための何らかの手段を施さなければならない。   In a multilayer printed wiring board, it is necessary to perform this appearance inspection for each layer. Since the inner layer is hidden inside after being multi-layered, the appearance inspection must be performed in the state of the inner layer substrate. If a defect is detected at this stage, it must be discarded on the spot, or some measure must be taken to make the inspection result detectable even after multi-layering.

また一般に内層基板の段階ではプリント配線板1は、複数の個別配線板によって構成された集合プリント配線板の状態、すなわち、1枚の集合プリント配線板に個別配線板が、2行3列で6個、2行4列で8個、3行8列で24個などというように配置された状態である。ICチップ等の部品をはんだ付けする実装工程では、集合プリント配線板を切断によって分割した後の個々の個別配線板を用いるのが一般的であるが、プリント配線板の製造工程では、効率的に生産するために集合プリント配線板の状態で加工されていくのが一般的である。   Generally, at the stage of the inner layer substrate, the printed wiring board 1 is in a state of a collective printed wiring board constituted by a plurality of individual wiring boards, that is, the individual wiring boards are arranged in two rows and three columns in one collective printed wiring board. In this state, eight are arranged in 2 rows and 4 columns, and 24 are arranged in 3 rows and 8 columns. In the mounting process of soldering parts such as IC chips, it is common to use individual individual wiring boards after dividing the collective printed wiring board by cutting, but in the manufacturing process of the printed wiring board, it is efficient. In general, it is processed in the state of a collective printed wiring board for production.

そのため、内層基板において不良となる個別配線板を発見した場合であっても通常は、同一プリント配線板内に配置されている他の良品の個別配線板を生かすために廃棄することはなく次工程へと生産を進めていくことになる。そして、多層化後に各個別配線板毎に良否を判定し選別する。この時に完成品としての電気検査による断線、ショートの結果に加え、各層毎に行った外観検査の結果を再度確認し、これらの全てにおいて良品であったもののみを良品としなければならない。   Therefore, even if an individual wiring board that becomes defective in the inner layer board is found, it is normally not discarded to make use of other good individual wiring boards arranged in the same printed wiring board. Production will continue. And after multi-layering, the quality is judged and selected for each individual wiring board. At this time, in addition to the result of the disconnection and short circuit by the electrical inspection as a finished product, the result of the appearance inspection performed for each layer must be confirmed again, and only those that are good in all of these must be regarded as good.

内層基板の状態で行った外観検査の結果を多層化後に検知するための手段として、従来、次のような方法がとられていた。広く採用されている簡易な方法としては、不良を検出した個別配線板内に油性マーカーでマーキングしておき、これを多層化後に目視で判別するという方法が挙げられる。また油性マーカーによるマーキングに替えてシールを貼る方法や、所定のランドをカッターナイフ等で剥がすという方法も知られている。いずれの方法も、内部にあるマーキング、シール、ランドを外側から絶縁樹脂層を透かして判別するものである。なおマーキング等の位置は、外側の層の導電パターン6に隠れることのない判別可能な箇所を選択しておく必要がある。   Conventionally, the following method has been used as means for detecting the result of the appearance inspection performed in the state of the inner layer substrate after multilayering. As a simple method widely adopted, there is a method of marking with an oil marker in an individual wiring board in which a defect is detected, and visually discriminating this after multilayering. There are also known a method of sticking a seal instead of marking with an oil marker, and a method of peeling a predetermined land with a cutter knife or the like. In any method, the marking, seal, and land inside are distinguished from the outside through the insulating resin layer. It is necessary to select a position where the marking or the like can be discriminated without being hidden by the conductive pattern 6 on the outer layer.

また別なる方法として製品内の導電パターン6の一部を故意に完全な断線状態に加工し、完成品での電気検査で断線不良として検出するという方法も用いられてきた。断線状態にするための加工方法としては、カッターナイフ等の鋭利なもので剥がす方法や、ドリルにより座ぐり加工する方法や、ドリルや金型によるパンチングで穴加工する方法がある。製品内の導電パターン6を断線状態に加工する替わりに、専用の検査パターンを設けておき、この検査パターン内の回路を断線状態に加工する方法も知られている。   As another method, a method in which a part of the conductive pattern 6 in the product is intentionally processed into a complete disconnection state and is detected as a disconnection defect by an electrical inspection of the finished product has been used. As a processing method for making a disconnection state, there are a method of peeling with a sharp object such as a cutter knife, a method of spot facing with a drill, and a method of punching with a drill or a die. Instead of processing the conductive pattern 6 in the product into a disconnected state, a method is also known in which a dedicated inspection pattern is provided and a circuit in this inspection pattern is processed into a disconnected state.

なお、この出願の発明に関連する先行技術文献情報としては、例えば、特許文献1および2が知られている。
特開2001−68819号公報 特開2003−318553号公報
For example, Patent Documents 1 and 2 are known as prior art document information related to the invention of this application.
JP 2001-68819 A JP 2003-318553 A

しかしながら上記の従来のプリント配線板では、以下に述べるような問題点を有していた。   However, the above-described conventional printed wiring board has the following problems.

すなわち、内層基板の状態で行った外観検査の結果を多層化後に検知するための手段として、油性マーカーやシールによって明示する場合は、その後の製造工程においてバフ研磨等の機械研磨や、酸、アルカリ、有機溶剤による処理を経ることで、油性マーカーが消えてしまったりシールが剥がれ落ちたりし、その結果、多層化後に目視検査しても不良品と認識できずに良品として流出することがあるという課題を有していた。またこのように消えてしまったり剥がれ落ちたりすることなくマーキングやシールが多層化後まで残ったとしても、人が目視によって判定する以上は誤判定によって流出する危険性があるという課題を有していた。   That is, as a means for detecting the result of the appearance inspection performed in the state of the inner layer substrate after the multilayering, when it is clearly indicated by an oily marker or a seal, mechanical polishing such as buffing, acid, alkali, The oily marker disappears or the seal peels off after the treatment with the organic solvent, and as a result, even if it is visually inspected after multilayering, it may not be recognized as a defective product and may flow out as a good product. Had problems. In addition, even if the markings and seals remain until after multi-layering without disappearing or peeling off in this way, there is a problem that there is a risk of leaking out by misjudgment as long as human judgment makes it. It was.

また、カッターナイフ、ドリル、金型で加工する方法においては、加工によって生じた加工屑や加工部のバリが原因となって、プリント配線板を重ねた時に表面に傷が付いたり、後工程において異物付着不良が発生したりするという課題を有していた。   In addition, in the method of processing with a cutter knife, drill, or mold, the surface is damaged when the printed wiring board is overlaid due to processing waste generated by processing or burrs on the processed part, There has been a problem that foreign matter adhesion failure occurs.

本発明は上記従来の問題点を解決するものであり、検出漏れすることなく、また傷や異物付着といった二次不良を発生させることなく、内層基板の状態で行った外観検査の結果を多層化後に検知することが可能な多層プリント配線板とその製造方法を提供することを目的とする。   The present invention solves the above-mentioned conventional problems, and multi-layers the results of the appearance inspection performed in the state of the inner layer substrate without causing a detection failure and without causing secondary defects such as scratches and foreign matter adhesion. An object of the present invention is to provide a multilayer printed wiring board that can be detected later and a method for manufacturing the same.

前記従来の課題を解決するために、本発明の多層プリント配線板は、検査パターンは、各層に設けられた導電パターンおよび各層の導電パターンを電気的に接続する導電体からなり、内層回路に不良を有する個別配線板に対応した検査パターンには、その導電パターンと導電体の間に抵抗体を有することを特徴とするものである。この構成により、内層回路に不良を有する個別配線板がある場合は、この個別配線板に対応した検査パターンがその導電パターンと導電体の間に通常の接続状態よりも抵抗値が高くなるように加工されているので、多層化後に検査パターンの抵抗値を電気検査で測定することによって内層回路の不良の有無を検知することができる。さらに抵抗体を付与することで検査パターンの抵抗値を通常の接続状態よりも高くするものであり、従来のような検査パターンに対して穴加工や切り欠き加工をするものではないので、加工屑や加工部のバリが発生することはなく、これにより傷や異物付着が発生する危険性はない。また検査設備を使用した電気検査で良否判定をするものであるので誤判定によって不良が流出する危険性もない。   In order to solve the above conventional problems, in the multilayer printed wiring board of the present invention, the inspection pattern is composed of a conductive pattern provided in each layer and a conductor that electrically connects the conductive pattern of each layer, and the inner layer circuit is defective. The inspection pattern corresponding to the individual wiring board having a resistor has a resistor between the conductive pattern and the conductor. With this configuration, when there is a defective individual wiring board in the inner layer circuit, the inspection pattern corresponding to this individual wiring board has a higher resistance value than the normal connection state between the conductive pattern and the conductor. Since it has been processed, it is possible to detect the presence or absence of a defect in the inner layer circuit by measuring the resistance value of the inspection pattern by electrical inspection after multilayering. Furthermore, by adding a resistor, the resistance value of the inspection pattern is made higher than that of the normal connection state, and no drilling or notching processing is performed on the inspection pattern as in the past. In addition, there is no risk of burring on the machined portion, and there is no risk of scratches or foreign matter adhesion. In addition, since the quality is determined by electrical inspection using an inspection facility, there is no risk that defects will be leaked due to erroneous determination.

また本発明の多層プリント配線板は、検査パターンは、各層に設けられた導電パターンおよび各層の導電パターンを電気的に接続する導電体からなり、内層回路に不良を有する個別配線板に対応した検査パターンには、その導電パターンと導電体の間に多層プリント配線板を構成する樹脂と同一の樹脂で抵抗体を有することを特徴とするものである。この構成により、抵抗体は多層プリント配線板を構成する樹脂と同一の樹脂によって形成されるので、内層基板を加熱加圧して多層化する際に、抵抗体の樹脂が溶融し検査パターン部分から個別配線板の製品領域へ流れ込んでも、その流れ込んだ樹脂は元々存在する多層プリント配線板を構成する樹脂と同一の樹脂であるので製品の特性に悪影響を及ぼすことはない。   In the multilayer printed wiring board of the present invention, the inspection pattern is composed of a conductive pattern provided in each layer and a conductor electrically connecting the conductive pattern of each layer, and the inspection pattern corresponds to an individual wiring board having a defect in the inner layer circuit. The pattern is characterized in that the resistor is made of the same resin as that constituting the multilayer printed wiring board between the conductive pattern and the conductor. With this configuration, the resistor is formed of the same resin as that constituting the multilayer printed wiring board. Therefore, when the inner layer substrate is heated and pressed to form a multilayer, the resistor resin melts and is individually separated from the inspection pattern portion. Even if the resin flows into the product area of the wiring board, the resin that flows into the wiring board is the same resin as that of the multilayer printed wiring board that originally exists, so that the product characteristics are not adversely affected.

また本発明の多層プリント配線板は、表層の少なくとも個別配線板に対応した領域の導電層は、回路形成する前のベタの状態であるという構成を有する。また表層の検査パターンに対応した領域の導電層は回路形成されていることを特徴とするものである。この構成により、内層回路が形成され外層部分が回路形成を行う前の導電層のままの状態であるという所謂内層回路入り基板においても、内層回路の検査結果を検査パターン内の抵抗体の有無という形で記録しているので、検査パターン部分の導電層の回路形成を行えば個別配線板の製品部分の外層回路を形成しなくても検査パターンの抵抗値を測定することにより内層回路の不良の有無を検知することができる。   The multilayer printed wiring board of the present invention has a configuration in which at least a conductive layer in a region corresponding to the individual wiring board on the surface layer is in a solid state before forming a circuit. The conductive layer in a region corresponding to the inspection pattern on the surface layer is formed with a circuit. With this configuration, even in the so-called inner layer circuit-containing substrate in which the inner layer circuit is formed and the outer layer portion remains as a conductive layer before the circuit formation, the test result of the inner layer circuit is referred to as the presence or absence of a resistor in the test pattern. Therefore, if the circuit formation of the conductive layer of the inspection pattern part is performed, the resistance value of the inspection pattern is measured without forming the outer layer circuit of the product part of the individual wiring board. The presence or absence can be detected.

また本発明の多層プリント配線板は、個別配線板に対応した2つの検査パターンを有し、内層回路に不良を有する前記個別配線板に対応した前記検査パターンの内、一方の前記検査パターンにその導電パターンと導電体の間に抵抗体が形成されていることを特徴とするものである。また本発明の多層プリント配線板の検査方法は、2つの検査パターンの抵抗値を測定し、その2つの抵抗値の差を基準値と比較してその大小により、前記検査パターンに対応する個別配線板の不良の有無を判別することを特徴とするものである。この構成により、多層プリント配線板内において場所によるエッチング量のバラツキが生じて検査パターンの抵抗値の絶対量では抵抗体の有無を検知できない場合でも、互いに近接した位置に配置することによりエッチング量がほとんど等しくなるように形成された2つの検査パターンの抵抗値の差を求めることで抵抗体の有無を検出することができる。   Further, the multilayer printed wiring board of the present invention has two inspection patterns corresponding to the individual wiring boards, and one of the inspection patterns corresponding to the individual wiring board having a defect in the inner layer circuit is included in the inspection pattern. A resistor is formed between the conductive pattern and the conductor. The multilayer printed wiring board inspection method of the present invention measures the resistance value of two inspection patterns, compares the difference between the two resistance values with a reference value, and determines the individual wiring corresponding to the inspection pattern according to the magnitude. It is characterized by determining the presence or absence of a defective board. With this configuration, even if the etching amount varies depending on the location in the multilayer printed wiring board and the presence or absence of the resistor cannot be detected by the absolute amount of the resistance value of the inspection pattern, the etching amount can be reduced by arranging them at positions close to each other. The presence / absence of the resistor can be detected by obtaining the difference between the resistance values of the two inspection patterns formed to be almost equal.

本発明の多層プリント配線板とその製造方法によれば、検出漏れすることなく、また傷や異物付着といった二次不良を発生させることなく、内層基板の状態で行った外観検査の結果を多層化後に検知することが可能なプリント配線板とその製造方法が得られる。   According to the multilayer printed wiring board and the manufacturing method thereof of the present invention, the results of the appearance inspection performed in the state of the inner layer substrate are multilayered without causing a detection failure and without causing secondary defects such as scratches and foreign matter adhesion. A printed wiring board that can be detected later and a method for manufacturing the same are obtained.

以下、本発明の実施の形態を図面に基づいて説明する。図1は本発明の実施の形態1における多層プリント配線板の断面模式図である。図2は本発明の実施の形態1における多層プリント配線板の概略図である。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a multilayer printed wiring board according to Embodiment 1 of the present invention. FIG. 2 is a schematic diagram of the multilayer printed wiring board according to Embodiment 1 of the present invention.

(実施の形態1)
図2は本発明の実施の形態1における多層プリント配線板を示す概略図である。
(Embodiment 1)
FIG. 2 is a schematic diagram showing the multilayer printed wiring board according to Embodiment 1 of the present invention.

図2において、多層プリント配線板は個別配線板11と検査パターン12とで構成される。個別配線板11は搬送等でのダメージを軽減するために、回路形成をせずベタ状態であり、検査パターン12は各層に導電パターン6と導電体9を持つ構成である。   In FIG. 2, the multilayer printed wiring board is composed of an individual wiring board 11 and an inspection pattern 12. The individual wiring board 11 is in a solid state without forming a circuit in order to reduce damage due to conveyance or the like, and the inspection pattern 12 has a conductive pattern 6 and a conductor 9 in each layer.

図1に図2に示す多層プリント配線板の断面の模式図を示す。絶縁層7はプリプレグ1の硬化体であって、ガラス織布に熱硬化性樹脂を含浸させた硬化物であり、この絶縁層7と導電層が交互に構成され多層に形成されている。そして、この層内には導電体9があり、各層間毎に配された導電層に形成した導電パターン6の上面と下面が接続され電子回路を形成している。検査パターン12には、同一層内に不良が検出された場合にその導電パターン6表面に抵抗体8が付与される。   FIG. 1 shows a schematic diagram of a cross section of the multilayer printed wiring board shown in FIG. The insulating layer 7 is a cured body of the prepreg 1 and is a cured product obtained by impregnating a glass woven fabric with a thermosetting resin. The insulating layers 7 and the conductive layers are alternately formed and formed in multiple layers. In this layer, there is a conductor 9, and the upper and lower surfaces of the conductive pattern 6 formed in the conductive layer arranged for each layer are connected to form an electronic circuit. The inspection pattern 12 is provided with a resistor 8 on the surface of the conductive pattern 6 when a defect is detected in the same layer.

検査パターン12の抵抗値は、内層部に不良が存在する場合、抵抗体8を付与することにより抵抗値が異なるため、多層化後に検査パターン12の抵抗値を測定し基準値と比較することで、内部に不良部があることが容易にわかる。   When there is a defect in the inner layer portion, the resistance value of the inspection pattern 12 differs by applying the resistor 8. Therefore, the resistance value of the inspection pattern 12 is measured after multilayering and compared with a reference value. It is easy to see that there is a defective part inside.

絶縁層7に用いられる熱硬化性樹脂としては、例えばエポキシ樹脂、フェノール樹脂あるいはシアネート樹脂を用いることができるが、中でもエポキシ樹脂は耐熱性が高いためにより好ましい。また、樹脂にSiO2、Al23、Al(OH)3などの無機フィラーを混練させてもよい。導電パターン6は、電気導電性を有する物質、例えばCu(銅)箔や各種の導電性樹脂組成物からなっており、本実施の形態においてはCu箔を用いている。導電性ペースト4は、例えば金属粒子と熱硬化性樹脂とを混合した導電性樹脂組成物でなる熱硬化性の電気導電性物質であり、その金属粒子としては、Au、AgあるいはCuなどを用いることができる。金属粒子としてのAu、AgあるいはCuは、電気導電性および熱伝導性が高いために好ましく、中でもCuは電気導電性が高くマイグレーションも少なく、また低コストであるためより好ましい。抵抗体8は、導電性ペースト4と導電パターン6との間に介在し、両者間の導通を阻害する機能を持つもので、絶縁物を含む高抵抗のものが好ましく、樹脂、有機または無機フィラー含有樹脂などが好ましい。更に好ましくは、絶縁体に用いられたプリプレグに含浸された樹脂を用いることである。本実施の形態においては、絶縁体に用いられたプリプレグと同一の熱硬化性樹脂を用いた。 As the thermosetting resin used for the insulating layer 7, for example, an epoxy resin, a phenol resin, or a cyanate resin can be used, and among them, the epoxy resin is more preferable because of its high heat resistance. Further, an inorganic filler such as SiO 2, Al 2 O 3, Al (OH) 3 may be kneaded into the resin. The conductive pattern 6 is made of a material having electrical conductivity, for example, Cu (copper) foil or various conductive resin compositions, and Cu foil is used in the present embodiment. The conductive paste 4 is a thermosetting electric conductive material made of a conductive resin composition in which, for example, metal particles and a thermosetting resin are mixed. Au, Ag, Cu, or the like is used as the metal particles. be able to. Au, Ag, or Cu as the metal particles is preferable because of high electrical conductivity and thermal conductivity, and Cu is more preferable because of its high electrical conductivity, low migration, and low cost. The resistor 8 is interposed between the conductive paste 4 and the conductive pattern 6 and has a function of hindering conduction between the two, and preferably has a high resistance including an insulator, and is a resin, organic or inorganic filler. Containing resins are preferred. More preferably, a resin impregnated in the prepreg used for the insulator is used. In the present embodiment, the same thermosetting resin as the prepreg used for the insulator is used.

次に、抵抗体8の付与方法を示す。図3は、図1に示した多層プリント配線板のA面の内層平面図の模式図である。個別配線板11部の導電パターン6に欠損Bが発生しており不良であるため、検査パターン12の導電パターン6部に絶縁層と同一の熱硬化性エポキシ樹脂の未硬化物を2−ブタノンで溶解しこの溶液を塗布し抵抗体とした。本実施の形態では、樹脂を刷毛で塗り、常温乾燥後、100℃で30分硬化を行なったが、硬化処理を行なわなくても導電性ペーストと導電パターン間の抵抗値は変化し、検査パターン12の抵抗値は変化する。これにより、本実施の形態においては、積層後、検査パターン12の抵抗値は無限大となり、内層の導電パターンに不良があることがわかった。   Next, a method for applying the resistor 8 will be described. FIG. 3 is a schematic diagram of an inner layer plan view of the A surface of the multilayer printed wiring board shown in FIG. Since the defect B is generated in the conductive pattern 6 of the individual wiring board 11 part, the uncured material of the same thermosetting epoxy resin as the insulating layer is formed on the conductive pattern 6 part of the inspection pattern 12 with 2-butanone. It melt | dissolved and this solution was apply | coated and it was set as the resistor. In this embodiment, the resin was applied with a brush, dried at room temperature, and cured at 100 ° C. for 30 minutes. However, the resistance value between the conductive paste and the conductive pattern changed without performing the curing process, and the inspection pattern was changed. The resistance value of 12 changes. Thereby, in this Embodiment, after lamination | stacking, the resistance value of the test pattern 12 became infinite, and it turned out that there exists a defect in the conductive pattern of an inner layer.

また、抵抗体8を付与する他の方法として、検査パターン12の導電パターン6部にシート状の抵抗体を貼り付けることも有効である。シート状の抵抗体としてはポリイミドフィルムなどの高耐熱性のものが好ましい。   As another method for applying the resistor 8, it is also effective to attach a sheet-like resistor to the conductive pattern 6 portion of the inspection pattern 12. As the sheet-like resistor, a highly heat-resistant material such as a polyimide film is preferable.

(実施の形態2)
図4は、より正確に抵抗値差を検出するために、検査パターン12を複数にし、抵抗体8の有無による抵抗値の差を用いた例を示す。同一層内に不良が検出された場合に一方の検査パターン12の導電パターン6表面に抵抗体8が付与される。2つの検査パターンの抵抗値の差により内層の不良の有無を検査することにより、絶縁層厚、検査パターンの導電パターンの幅等の製品の固有特性、製造時のばらつき等を吸収することができる。
(Embodiment 2)
FIG. 4 shows an example in which a plurality of test patterns 12 are used in order to detect the resistance value difference more accurately, and the resistance value difference depending on the presence or absence of the resistor 8 is used. When a defect is detected in the same layer, the resistor 8 is applied to the surface of the conductive pattern 6 of one inspection pattern 12. By inspecting whether there is a defect in the inner layer based on the difference between the resistance values of the two inspection patterns, it is possible to absorb product characteristic such as the thickness of the insulating layer, the width of the conductive pattern of the inspection pattern, and variations during manufacturing. .

抵抗体8の付与は実施形態1と同様な方法を用いた。   The resistor 8 was applied using the same method as in the first embodiment.

本発明にかかる多層プリント配線板とその製造方法は、検出漏れすることなく、また傷や異物付着といった二次不良を発生させることなく、内層基板の状態で行った外観検査の結果を多層化後に検知することが可能となるので、パソコン、移動体通信機器、ビデオカメラ等の各種電子機器等に対して有用である。   The multilayer printed wiring board and the manufacturing method thereof according to the present invention are obtained after multilayering the results of the appearance inspection performed in the state of the inner layer substrate without causing a detection failure and without causing secondary defects such as scratches and foreign matter adhesion. Since it can be detected, it is useful for various electronic devices such as personal computers, mobile communication devices, and video cameras.

本発明の実施の形態1における多層プリント配線板の断面模式図Sectional schematic diagram of the multilayer printed wiring board in Embodiment 1 of the present invention 本発明の実施の形態1における多層プリント配線板の概略図Schematic diagram of multilayer printed wiring board in Embodiment 1 of the present invention 本発明の実施の形態1における多層プリント配線板の模式図Schematic diagram of multilayer printed wiring board in Embodiment 1 of the present invention 本発明の実施の形態2における多層プリント配線板の断面模式図Sectional schematic diagram of the multilayer printed wiring board in Embodiment 2 of the present invention 従来のプリント配線板の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the conventional printed wiring board

符号の説明Explanation of symbols

1 プリプレグ
2 フィルム
3 ビア
4 導電性ペースト
5 銅箔
6 導電パターン
7 絶縁層
8 抵抗体
9 導電体
11 個別配線板
12 検査パターン
DESCRIPTION OF SYMBOLS 1 Prepreg 2 Film 3 Via 4 Conductive paste 5 Copper foil 6 Conductive pattern 7 Insulating layer 8 Resistor 9 Conductor 11 Individual wiring board 12 Inspection pattern

Claims (13)

複数の個別配線板および前記個別配線板に対応したひとつ以上の検査パターンによって構成され、
導電層と、前記導電層と交互に積層された絶縁層を備え、
少なくとも内層の前記導電層には回路形成が施され、
前記検査パターンは、各層に設けられた導電パターンおよび前記各層の導電パターンを電気的に接続する導電体からなり、
内層回路に不良を有する個別配線板に対応した前記検査パターンには、その導電パターンと導電体の間に抵抗体を有することを特徴とする多層プリント配線板。
Consists of a plurality of individual wiring boards and one or more inspection patterns corresponding to the individual wiring boards,
A conductive layer and an insulating layer alternately stacked with the conductive layer;
At least the conductive layer of the inner layer is subjected to circuit formation,
The inspection pattern is composed of a conductive pattern provided in each layer and a conductor that electrically connects the conductive pattern of each layer,
A multilayer printed wiring board, wherein the inspection pattern corresponding to an individual wiring board having a defect in an inner layer circuit has a resistor between the conductive pattern and the conductor.
抵抗体は樹脂を含むことを特徴とする請求項1記載の多層プリント配線板。 The multilayer printed wiring board according to claim 1, wherein the resistor includes a resin. 抵抗体の樹脂は熱硬化性樹脂であることを特徴とする請求項2記載の多層プリント配線板。 The multilayer printed wiring board according to claim 2, wherein the resin of the resistor is a thermosetting resin. 抵抗体の樹脂は多層プリント配線板を構成する樹脂と同一であることを特徴とする請求項2記載の多層プリント配線板。 3. The multilayer printed wiring board according to claim 2, wherein the resin of the resistor is the same as the resin constituting the multilayer printed wiring board. 抵抗体は無機または有機フィラーを含むことを特徴とする請求項1記載の多層プリント配線板。 The multilayer printed wiring board according to claim 1, wherein the resistor includes an inorganic or organic filler. 表層の少なくとも個別配線板に対応した領域の導電層は、回路形成する前のベタの状態であることを特徴とする請求項1に記載する多層プリント配線板。 2. The multilayer printed wiring board according to claim 1, wherein the conductive layer in a region corresponding to at least the individual wiring board on the surface layer is in a solid state before circuit formation. 表層の検査パターンに対応した領域の導電層は回路形成されていることを特徴とする請求項6に記載する多層プリント配線板。 7. The multilayer printed wiring board according to claim 6, wherein the conductive layer in a region corresponding to the inspection pattern on the surface layer is formed with a circuit. 個別配線板に対応した2つの検査パターンを有し、内層回路に不良を有する前記個別配線板に対応した前記検査パターンの内、一方の前記検査パターンにその導電パターンと導電体の間に抵抗体が形成されていることを特徴とする請求項1に記載の多層プリント配線板。 One of the inspection patterns corresponding to the individual wiring board having two inspection patterns corresponding to the individual wiring board and having a defect in the inner layer circuit is provided with a resistor between the conductive pattern and the conductor. The multilayer printed wiring board according to claim 1, wherein the multilayer printed wiring board is formed. 請求項1の多層プリント配線板の検査パターンの抵抗値を測定し、基準値と比較してその大小により、前記検査パターンに対応する個別配線板の不良の有無を判断することを特徴とする多層プリント配線板の検査方法。 A resistance value of an inspection pattern of the multilayer printed wiring board according to claim 1 is measured, and the presence or absence of a defect of the individual wiring board corresponding to the inspection pattern is determined based on the magnitude of the resistance compared with a reference value. Inspection method for printed wiring boards. 請求項8の多層プリント配線板の2つの検査パターンの抵抗値を測定し、その2つの抵抗値の差を基準値と比較してその大小により、前記検査パターンに対応する個別配線板の不良の有無を判断することを特徴とする多層プリント配線板の検査方法。 A resistance value of two inspection patterns of the multilayer printed wiring board according to claim 8 is measured, a difference between the two resistance values is compared with a reference value, and a size of the individual wiring board corresponding to the inspection pattern is determined based on a magnitude thereof. A method for inspecting a multilayer printed wiring board, characterized by determining the presence or absence. 複数の個別配線板および前記個別配線板に対応したひとつ以上の検査パターンによって構成され、表面に内層回路と前記検査パターン用の導電パターンを有する内層基板を準備する工程と、
前記内層回路を検査する工程と、
前記内層回路に不良を有する前記個別配線板に対応した前記検査パターン用の導電パターンの表面に抵抗体を形成する工程と、
導電性ペーストが充填されたビアを備えたプリプレグを準備する工程と、
前記内層基板の表面に前記プリプレグを積層し、さらに最外層に導電層を積層する工程と、積層された前記内層基板と前記プリプレグと最外層の前記導電層とを加熱加圧し、少なくとも前記内層基板の前記検査パターン用の導電パターンと、最外層の前記導電層とを前記導電性ペーストを介して電気的に層間接続する工程とを含むことを特徴とする多層プリント配線板の製造方法。
A step of preparing an inner layer substrate having a plurality of individual wiring boards and one or more inspection patterns corresponding to the individual wiring boards, and having an inner layer circuit and a conductive pattern for the inspection pattern on the surface;
Inspecting the inner layer circuit;
Forming a resistor on the surface of the conductive pattern for the inspection pattern corresponding to the individual wiring board having a defect in the inner layer circuit;
Preparing a prepreg with vias filled with conductive paste;
Laminating the prepreg on the surface of the inner layer substrate and further laminating a conductive layer on the outermost layer, heating and pressurizing the laminated inner layer substrate, the prepreg, and the outermost conductive layer, at least the inner layer substrate And a step of electrically connecting the conductive pattern for the inspection pattern and the outermost conductive layer to each other through the conductive paste.
抵抗体を形成する工程は、樹脂を含む液状の抵抗体材料を検査パターン用の導電パターンの表面に塗布し、仮乾燥することを特徴とする請求項11に記載の多層プリント配線板の製造方法。 12. The method of manufacturing a multilayer printed wiring board according to claim 11, wherein the step of forming the resistor comprises applying a liquid resistor material containing a resin to the surface of the conductive pattern for the test pattern and temporarily drying the resist pattern. . 抵抗体を形成する工程は、シート状の抵抗体を検査パターン用の導電パターンの表面に貼り付けることを特徴とする請求項11に記載の多層プリント配線板の製造方法。 12. The method of manufacturing a multilayer printed wiring board according to claim 11, wherein the step of forming the resistor includes attaching a sheet-like resistor to the surface of the conductive pattern for the inspection pattern.
JP2008047049A 2008-02-28 2008-02-28 Multilayer printed wiring board, inspection method and manufacturing method thereof Expired - Fee Related JP5050924B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653848B2 (en) 2010-05-28 2014-02-18 Kabushiki Kaisha Toshiba Television apparatus, semiconductor package, and electronic device
KR20210074542A (en) * 2019-12-12 2021-06-22 주식회사 현대케피코 Manufacturing Method of Electronic Control Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653848B2 (en) 2010-05-28 2014-02-18 Kabushiki Kaisha Toshiba Television apparatus, semiconductor package, and electronic device
KR20210074542A (en) * 2019-12-12 2021-06-22 주식회사 현대케피코 Manufacturing Method of Electronic Control Device
KR102298664B1 (en) 2019-12-12 2021-09-03 주식회사 현대케피코 Manufacturing Method of Electronic Control Device

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