JP2009177604A - Synchronization signal detection circuit, image detection circuit, synchronization signal detection method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization signal detection circuit, an image detection circuit, a synchronization signal detection method and a program capable of preventing erroneous detection of the presence or absence of an image signal when the signal level of a composite image signal is lowered or when noise is mixed in the composite image signal. <P>SOLUTION: The synchronization signal detection circuit is for inputting a separate synchronization signal from a synchronous separation circuit outputting the separate synchronization signal by performing synchronizing separation of input composite image signal, and includes: an adding means for counting and accumulating the number of times of the Low level of the separate synchronization signal within one horizontal cycle; a horizontal synchronization detection means for detecting whether or not the adding result by the adding means is within the horizontal synchronization detection range corresponding to the pulse width of the horizontal synchronization signal; and a vertical synchronization detection means for detecting whether or not the adding result by the adding means is within the vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a synchronization signal detection circuit, a video detection circuit, a synchronization signal detection method, and a program for performing synchronization separation of an input composite video signal and detecting the presence or absence of the input video signal.

  In broadcasting station equipment and equipment that transmits composite video signals for broadcasting, not only the presence of simple signals but also the presence or absence of video signals are accurately detected to monitor the status of the input video signal. Video detection is required.

FIG. 8 is an example of a video detection circuit related to the present invention. A composite video signal in which a video signal and a composite synchronization signal (horizontal synchronization signal and vertical synchronization signal) are mixed in a time division manner is input (supplied) to the input terminal 51. When receiving the composite video signal, the synchronization separation circuit 52 performs synchronization separation and outputs a separation synchronization signal (composite synchronization signal) to the retriggerable multivibrator 53. When the composite video signal is normally input, the waveform is as shown in FIG. The synchronization separation circuit 52 is a circuit disclosed in Patent Documents 1 to 3, for example. The retriggerable multivibrator 53 detects the presence / absence of a pulse of the separation synchronization signal. Then, the retriggerable multivibrator 53 outputs a video detection signal indicating the presence or absence of the video signal. That is, the retriggerable multivibrator 53 outputs “0” indicating “no video signal” when the pulse stops changing, and “exists video signal” when the pulse changes within a predetermined time. “1” is output. In the video detection circuit shown in FIG. 8, when there is no video signal in the input composite video signal (the video signal is at the black level because the picture is black) and only the synchronization signal, the signal level of the separated synchronization signal depends on the signal level. Thus, the presence or absence of an input video signal can be detected.
JP-A-6-62272 JP-A-10-304222 JP 2001-333294 A

  However, in the video detection circuit shown in FIG. 8, for example, as shown in FIG. 5B, when the composite video signal to be input has a video signal and the signal level (amplitude) of the composite video signal is reduced, An abnormality such that a video signal appears in the separation synchronization signal output from the synchronization separation circuit 52 occurs. In such a case, the video detection circuit shown in FIG. 8 has a problem that the abnormality cannot be detected and the presence / absence of the video signal is erroneously detected.

  Further, in the video detection circuit shown in FIG. 8, for example, as shown in FIG. 5C, when the noise (noise pulse) is mixed in the input composite video signal, it is also output from the synchronization separation circuit 52. The separation synchronization signal has an abnormal waveform. In such a case, the video detection circuit shown in FIG. 8 has a problem that the presence or absence of the video signal is erroneously detected due to the influence of noise.

  The present invention has been made in view of the above circumstances. When the signal level of the input composite video signal is reduced or when noise is mixed in the input composite video signal, the presence or absence of the video signal is erroneously detected. It is an object of the present invention to provide a synchronization signal detection circuit, a video detection circuit, a synchronization signal detection method, and a program that can prevent the above.

  In order to achieve such an object, the synchronization signal detection circuit of the present invention is a synchronization signal detection circuit that inputs a separation synchronization signal from a synchronization separation circuit that performs synchronization separation of an input composite video signal and outputs a separation synchronization signal. The addition means for counting and accumulating the number of times of the low level of the separation synchronization signal within one horizontal cycle, and whether the addition result by the addition means is within the horizontal synchronization detection range corresponding to the pulse width of the horizontal synchronization signal. It comprises a horizontal synchronization detecting means for detecting, and a vertical synchronization detecting means for detecting whether the addition result by the adding means is within a vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal.

  The video detection circuit of the present invention is a synchronization signal detection circuit that inputs a separation synchronization signal from a synchronization separation circuit that performs synchronization separation of an input composite video signal and outputs a separation synchronization signal. An addition means for counting and accumulating the number of times of the low level of the synchronization signal, a horizontal synchronization detection means for detecting whether the addition result by the addition means is within a horizontal synchronization detection range corresponding to the pulse width of the horizontal synchronization signal, and addition Based on the vertical synchronization detection means for detecting whether the addition result by the means is within the vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal, the detection result by the horizontal synchronization detection means, and the detection result by the vertical synchronization detection means Video detection signal output means for performing a logical operation and outputting a video detection signal indicating the presence or absence of the video signal of the composite video signal.

  The synchronization signal detection method of the present invention counts and accumulates the number of low levels of the separated synchronization signal within one horizontal period, and the horizontal synchronization detection in which the addition result of the addition step corresponds to the pulse width of the horizontal synchronization signal. A horizontal synchronization detection step for detecting whether the range is within the range, and a vertical synchronization detection step for detecting whether the addition result of the addition step is within the vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal. It is characterized by that.

  The program of the present invention counts and accumulates the number of times of the low level of the separation synchronization signal within one horizontal cycle, and the addition result of the addition processing is within the horizontal synchronization detection range corresponding to the pulse width of the horizontal synchronization signal. Causing a computer to execute horizontal synchronization detection processing for detecting whether or not the addition result of the addition processing is within a vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal. It is characterized by.

  According to the present invention, it is possible to prevent erroneous detection of the presence or absence of a video signal when the signal level of the input composite video signal is reduced or when noise is mixed in the input composite video signal.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

[First Embodiment]
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the video detection circuit of this embodiment. As shown in FIG. 1, the video detection circuit of this embodiment includes an input terminal 1, a synchronization separation circuit 2, a synchronization signal detection circuit 3, a video detection signal output unit 304, and an output terminal 4. As a minimum configuration of the video detection circuit of the present invention, as shown in FIG. 7A, the minimum configuration of the synchronization signal detection circuit 3 (adding means 301, horizontal synchronization detection) shown in FIG. It is only necessary to include means 302, vertical synchronization detection means 303), and video detection signal output means 304.

  A composite video signal (for example, a broadcast analog video signal) in which a video signal and a composite synchronization signal (horizontal synchronization signal and vertical synchronization signal) are mixed in a time division manner is input (supplied) to the input terminal 1. This composite video signal is, for example, a signal of the NTSC (National Television Standards Committee) system. Note that the video signal included in the composite video signal varies depending on the design, and therefore cannot be used to detect the presence or absence of the video signal. Therefore, in the video detection circuit of the present embodiment, it is assumed that only the synchronization signal included in the composite video signal is used to detect the presence or absence of the input video signal.

  The synchronization separation circuit 2 separates the composite synchronization signal from the composite video signal supplied to the input terminal 1 and outputs it to the synchronization signal detection circuit 3 as a separation synchronization signal. In the separation synchronization signal, a horizontal synchronization signal indicating the left and right sides of the screen and a vertical synchronization signal indicating the upper and lower sides of the screen are mixed in a time division manner.

  The synchronization signal detection circuit 3 is an embodiment of the synchronization signal detection circuit of the present invention. As shown in FIG. 1, the synchronization signal detection circuit 3 includes an addition unit 301, a horizontal synchronization detection unit 302, a vertical synchronization detection unit 303, a clock generation unit 305, and a pulse generation unit 306. The synchronization signal detection circuit 3 receives the separation synchronization signal output from the synchronization separation circuit 2. As a minimum configuration of the synchronization signal detection circuit of the present invention, as shown in FIG. 7B, it is only necessary to have an adding means 301, a horizontal synchronization detection means 302, and a vertical synchronization detection means 303. . The operation (synchronization signal detection method) performed by the synchronization signal detection circuit 3 shown in FIG. 1 will be described below with reference to FIG.

  First, an addition step of counting and accumulating the number of times of the low level of the separation synchronizing signal within one horizontal cycle is performed (step S1). Hereinafter, the addition step will be described in detail. The adder 301 uses a free-running clock and counts (counts / accumulates) each clock when the input separation synchronization signal is “0” (Low level). A free-running clock is generated by the clock generation means 305. Further, the adding means 301 uses the pseudo H pulse and resets the count result for each pseudo H pulse (the count result is cleared to zero in a horizontal frequency cycle (1H: 1 horizontal cycle)). The count result is a result of counting and accumulating the number of times that the separation synchronization signal is “0” (hereinafter also referred to as an addition result). The pseudo H pulse is generated by dividing (÷ 910) the free-running clock generated by the clock generation unit 305 in the pulse generation unit 306. It should be noted that the free-running clock and the pseudo-H pulse are operated in a state where the frequency is not locked with respect to the input of the composite video signal and the phase is not in a fixed relationship. Even if the pseudo H pulse is just the center phase of horizontal synchronization (example 1 shown in FIG. 5 (d)), the adding means 301 counts in two places as shown in FIG. 5 (d). Within the range to be detected. When the amplitude (signal level) of the input composite video signal decreases, as shown in FIG. 5B, it is detected that the pulse is wider than the horizontal synchronizing signal and is not normal. In this way, the adding means 301 counts and accumulates the number of times that the separation synchronization signal is “0” within the pseudo H pulse period (1H: 1 horizontal period).

  Next, a horizontal synchronization detection step is performed to detect whether the addition result of the addition step is within a horizontal synchronization detection range corresponding to the pulse width of the horizontal synchronization signal (step S2). Hereinafter, the horizontal synchronization detection step will be described in detail. The horizontal synchronization detection means 302 is a range corresponding to the addition result immediately before being reset by the pseudo H pulse and 4.7 μs which is the pulse width of the horizontal synchronization signal (range of 50 to 100, hereinafter referred to as horizontal synchronization detection range). And whether or not the addition result is within the horizontal synchronization detection range. Note that the horizontal synchronization detection range is determined in advance. The horizontal synchronization detection unit 302 determines that the horizontal synchronization signal is detected when the addition result is within the horizontal synchronization detection range, and does not detect the horizontal synchronization signal when the addition result is outside the horizontal synchronization detection range. Judge that it is. Whether or not this horizontal synchronization signal is detected is hereinafter referred to as “horizontal synchronization detection result”.

  Next, a vertical synchronization detection step is performed to detect whether the addition result in the addition step is within a vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal (step S3). Hereinafter, the vertical synchronization detection step will be described in detail. The vertical synchronization detection means 303 is a range corresponding to the addition result immediately before being reset by the pseudo H pulse and the pulse width of the vertical synchronization signal of 63.556 μs-9.4 μs (range of 756 to 796; hereinafter, vertical synchronization) Detection range) and detects whether the addition result is within the vertical synchronization detection range. Note that the vertical synchronization detection range is determined in advance. The vertical synchronization detection unit 303 determines that the vertical synchronization signal is detected when the addition result is within the vertical synchronization detection range, and does not detect the vertical synchronization signal when the addition result is outside the vertical synchronization detection range. Judge that it is. Whether or not this vertical synchronization signal is detected is hereinafter referred to as “vertical synchronization detection result”.

  As described above, according to the present embodiment, in the synchronization signal detection circuit 3, the synchronization signal component included in the composite synchronization signal determines the presence or absence of synchronization using the fact that the time ratio with respect to one horizontal period is constant. is there.

  In a pulse width detection circuit that checks the interval from a predetermined pulse change point to the next pulse change point, it is erroneously detected that there is a video signal due to the influence of short-time noise mixing. However, in this embodiment, the synchronization signal detection circuit 3 cumulatively adds the number (ratio) of “0” (Low level) in the 1H (one horizontal period) period instead of the continuous pulse width as described above. ing. Therefore, it is difficult to be affected by short-time noise mixing as shown in FIG. 5C, so that the erroneous detection can be prevented.

  After step S3, a logical operation based on the detection result of the horizontal synchronization detection step and the detection result of the vertical synchronization detection step is performed, and as a result, a video detection signal indicating the presence or absence of the video signal of the composite video signal is output. A video detection signal output step may be performed. Hereinafter, the video detection signal output step will be described in detail. The video detection signal output unit 304 performs a logical operation (logical product or logical sum) based on the detection result of horizontal synchronization and the detection result of vertical synchronization. The result of this logical operation is output as a video detection result (presence / absence of a video signal). For example, when the detection result of horizontal synchronization is “with horizontal synchronization signal” and the detection result of vertical synchronization is “with vertical synchronization signal”, the video detection signal output unit 304 detects “with video signal”. . Then, the video detection signal output means 304 outputs a signal indicating the video detection result “video signal present” to the output terminal 4. A signal indicating the video detection result is referred to as a “video detection signal”.

  As described above, in this embodiment, the video detection signal output unit 304 uses both the horizontal synchronization detection result and the vertical synchronization detection result when detecting the presence or absence of a video signal. When both the horizontal synchronization signal and the vertical synchronization signal are detected as “present”, it is detected that there is a video signal. Therefore, when the amplitude (signal level) of the input composite video signal decreases, it can be prevented that the vertical synchronization is erroneously detected.

  As described above, according to the present embodiment, it is possible to realize video detection that does not erroneously detect the presence of a video signal with respect to a decrease in amplitude of an input composite video signal. Further, it is possible to realize video detection that is not easily affected by short-time noise (noise pulse) and that is not erroneously detected as having a video signal.

  The operation (video detection method) performed by the synchronization signal detection circuit 3 described above can also be executed by software. When executing processing by software, a program in which the steps shown in FIG. 6 are recorded as a processing sequence is installed and executed in a memory in a computer incorporated in dedicated hardware. Alternatively, the program is installed and executed on a general-purpose computer capable of executing various processes.

  Next, details of the above-described synchronization signal detection circuit 3 will be described with reference to FIG. FIG. 2 is a block diagram showing a detailed configuration of the synchronization signal detection circuit 3 shown in FIG.

  The clock generation circuit 18 is a 14.3 MHz oscillator and generates a free-running clock. The clock generated by the clock generation circuit 18 is supplied to the pseudo H counter 19 and the latch 15.

  The clock generation circuit described above corresponds to the clock generation means 305 shown in FIG.

  The pseudo H counter 19 divides (÷ 910) the clock supplied from the clock generation circuit 18 and supplies it to each unit as a pseudo H pulse ((c) shown in FIG. 2). These units are the selector 14, the H comparison circuit 16, the V comparison circuit 17, and the delay circuit 20. The waveform of the pseudo H pulse is shown in FIG. The clock output from the clock generation circuit 18 and the pseudo H pulse output from the pseudo H counter 19 are not synchronized in frequency or phase with respect to the input of the composite video signal. That is, the clock and the pseudo H pulse are operating in a state where the frequency is not locked with respect to the input of the composite video signal and the phase is not in a fixed relationship. Even if the pseudo H pulse is just the center phase of horizontal synchronization (example 1 shown in FIG. 5 (d)), since it is added at two locations, it is within the range where it is detected as normal. When the amplitude (signal level) of the input composite video signal decreases, as shown in FIG. 5B, it can be detected that the pulse is wider than the horizontal synchronizing signal and is not normal.

  The pseudo H counter 19 described above corresponds to the pulse generation unit 306 shown in FIG.

  The separation synchronization signal output from the synchronization separation circuit 1 shown in FIG. 1 is supplied to the input terminal 11. Then, the separation synchronization signal is supplied to the addition circuit 13 via the inverter 12. An example of the separation synchronization signal is shown in FIG. FIG. 4 is a diagram illustrating waveforms of signals in the synchronization signal detection circuit 3. 4A shows line (scanning line) numbers, and is in a pair relationship with the separation synchronization signal of FIG. 4B. Moreover, in FIG. 4, (a)-(k) has shown two types by the upper side and the lower side. This is because the NTSC signal has an interlaced scanning 1 frame period (525 lines) of 2 field periods, and the waveform of the synchronization signal differs depending on the interlaced scanning.

  The adder circuit 13 adds the separation synchronization signal (1 bit) from the inverter 12 and the output signal (10 bits) from the latch 15, and outputs an addition result signal indicating the addition result to the selector 14. The output signal from the latch 15 will be described later.

  The selector 14 outputs the addition result signal input from the addition circuit 13 to the latch 15. When the pseudo H pulse is supplied from the pseudo H counter 19, the selector 14 outputs a reset signal (“0” shown in FIG. 2) for resetting the addition result to zero to the latch 15.

  The latch 15 outputs a signal increased by 1 according to the clock supplied from the clock generation circuit 18 when the separation synchronization signal is “0” (Low level). This output signal is reset to zero when a reset signal is input from the selector 14. Therefore, the output signal from the latch 15 is an addition result signal indicating the addition result obtained by counting and accumulating the number of times that the separation synchronization signal is “0” within the pseudo H pulse period (1H: 1 horizontal period). This addition result is a value immediately before being reset to zero by the pseudo H pulse. The output signal from the latch 15 is output to the adder circuit 13 and also to the H comparator circuit 16 and the V comparator circuit 17, respectively.

  The adding circuit 13, the selector 14, and the latch 15 described above correspond to the adding unit 301 shown in FIG.

  The H comparison circuit 16 receives the output signal from the latch 15. Here, the H comparison circuit 16 holds a value indicating an addition result obtained by counting and accumulating the number of times that the separation synchronization signal is “0” within the pseudo H pulse period. As described above, this value is a value immediately before being reset to zero by the pseudo H pulse. Next, the H comparison circuit 16 compares the held value with a predetermined range. This range is a range corresponding to a 4.7 μs width which is a pulse width of the horizontal synchronization signal (range of 50 to 100, horizontal synchronization detection range). Next, the H comparison circuit 16 detects whether or not the value held as a result of the comparison is within the horizontal synchronization detection range. Next, the H comparison circuit 16 sends a signal (horizontal synchronization detection result ((d) shown in FIG. 2)) according to whether or not the held value is within the horizontal synchronization detection range to the delay circuit 20 and the OR gate. 22 is output. In normal horizontal synchronization, the stored value is in the vicinity of 67. Therefore, since the held value falls within the range of 50 to 100, the H comparison circuit 16 outputs “1” (an example of the detection result of horizontal synchronization) as the detection of the horizontal synchronization signal. Also, as shown in FIG. 5B, when the composite sync signal input has a small amplitude and horizontal blanking is occurring, the held value is near 152. Therefore, since the held value falls outside the range of 50 to 100, the H comparison circuit 16 outputs “0” (an example of the horizontal synchronization detection result) as a result of not detecting the horizontal synchronization signal. The waveform of the horizontal synchronization detection result ((d) shown in FIG. 2) is shown in (d) of FIG.

  The H comparison circuit 16 described above corresponds to the horizontal synchronization detection unit 302 shown in FIG.

  The V comparison circuit 17 receives the output signal from the latch 15. Here, the V comparison circuit 17 holds a value indicating an addition result obtained by counting and accumulating the number of times that the separation synchronization signal is “0” within the pseudo H pulse period. As described above, this value is a value immediately before being reset to zero by the pseudo H pulse. Next, the V comparison circuit 17 compares the held value with a predetermined range. This range is a range (range of 756 to 796, vertical synchronization detection range) corresponding to the pulse width of the vertical synchronization signal of 63.556 μs−9.4 μs. Next, the V comparison circuit 17 sends a signal (vertical synchronization detection result ((g) shown in FIG. 2)) according to whether or not the held value is within the vertical synchronization detection range to the AND gate 21. Output. If the held value is within the range of 756 to 796, the V comparison circuit 17 outputs “1” (an example of the detection result of the vertical synchronization) to the AND gate 21 as the detection of the vertical synchronization signal. . If the held value is outside the range of 756 to 796, the V comparison circuit 17 sets “0” (an example of the vertical synchronization detection result) to the AND gate 21 as not detecting the vertical synchronization signal. Output. The waveform of the vertical synchronization detection result ((g) shown in FIG. 2) is shown in (g) of FIG.

  The V comparison circuit 17 described above corresponds to the vertical synchronization detection means 303 shown in FIG.

  The delay circuit 20 receives a signal (horizontal synchronization detection result) from the H comparison circuit 16. The delay circuit 20 delays the input signal by 3H (3 times one horizontal period) and outputs the delayed signal to the AND gate 21 as a delay signal. Since the detection result of the horizontal synchronization in the H comparison circuit 16 and the detection result of the vertical synchronization in the V comparison circuit 17 are detected with a time lag, the delay circuit 20 determines the detection result of the horizontal synchronization in the H comparison circuit 16. Delay. Thereby, the input timing to the AND gate 21 of the detection result of the horizontal synchronization in the H comparison circuit 16 and the detection result of the vertical synchronization in the V comparison circuit 17 can be matched.

  An AND gate (logical product circuit) 21 receives a delay signal from the delay circuit 20 and a signal (vertical synchronization detection result) from the V comparison circuit 17. The AND gate 21 performs a logical operation (logical product) based on the two input signals, and outputs a signal indicating the result of the logical operation (logical product result) to the OR gate 22.

  The OR gate (logical sum circuit) 22 receives a signal (horizontal synchronization detection result) from the H comparison circuit 16 and a signal (logical product result) from the AND gate 21. The OR gate 22 performs a logical operation (logical sum) based on the two input signals, and outputs a signal indicating the result of the logical operation (logical sum result) to the output terminal 23. This signal ((k) shown in FIG. 2) is a signal (video detection signal) indicating the presence or absence of a video signal as a video detection result, and is output via the output terminal 23. This signal is “1” when there is a video signal and “0” when there is no video signal. The waveform of this signal ((k) shown in FIG. 2) is shown in (k) of FIG.

  The delay circuit 20, the AND gate 21, and the OR gate 22 described above correspond to the video detection signal output unit 304 shown in FIG.

  In a pulse width detection circuit that checks the interval from a predetermined pulse change point to the next pulse change point, it is erroneously detected that there is a video signal due to the influence of short-time noise mixing. However, the synchronization signal detection circuit 3 cumulatively adds the number (ratio) of “0” (Low level) in the 1H (one horizontal cycle) period instead of the continuous pulse width as described above. Therefore, it is difficult to be affected by short-time noise mixing as shown in FIG. 5C, so that the erroneous detection can be prevented.

  The synchronization signal detection circuit 3 uses not only the detection result of the vertical synchronization in the V comparison circuit 17 but also the detection result of the horizontal synchronization in the H comparison circuit 16 when detecting the vertical synchronization signal. For example, the synchronization signal detection circuit 3 detects “with video signal” when the detection result of horizontal synchronization is “with horizontal synchronization signal” and the detection result of vertical synchronization is “with vertical synchronization signal”. By doing so, it is possible to prevent erroneous detection of “there is a vertical synchronization signal” when the amplitude of the input composite synchronization signal decreases and a video signal component appears in the separated synchronization signal.

  In the description so far, NTSC analog signals have been described as examples. However, PAL (Phase Alternation by Line) signals can be easily implemented by changing some parameters. Further, the detection of the video signal by the retriggerable multivibrator shown in FIG. 6 and the detection of the video signal by the synchronization signal detection circuit 3 shown in FIG. 2 can be used in combination.

  In the above description, it has been described that the clock generated by the clock generation circuit 18 shown in FIG. 2 is not synchronized with the composite synchronization signal. However, it is obvious that the clock can be used as it is even if it is synchronized.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.
The composite synchronization signal includes a horizontal synchronization pulse, an equalization pulse, and a vertical synchronization pulse. In the synchronization signal detection circuit 3 shown in FIG. 2 described above, “no video signal” is detected at the boundary of the horizontal synchronization pulse, equalization pulse, and vertical synchronization pulse. “No video signal” means that it is temporarily “0” as shown in FIG. Therefore, the signal output from the output terminal 23 ((k) in FIG. 2 and (k) in FIG. 4) is output with 1H (one horizontal period) “0” (no video signal) mixed. Therefore, the video detection circuit of the present embodiment changes the configuration of the subsequent stage of the H comparison circuit 16 and the V comparison circuit 17 in the synchronization signal detection circuit 3 shown in FIG. That is, a subsequent circuit (another example of the video detection signal output unit 304 shown in FIG. 1) different from that described in the first embodiment is provided in the subsequent stage of the H comparison circuit 16 and the V comparison circuit 17. Configure. In the subsequent circuit, “1” (with a horizontal synchronizing signal) is extended and used.

  The subsequent circuit will be described with reference to FIGS. FIG. 3 is a diagram illustrating an example of the configuration of the subsequent circuit. The subsequent circuit shown in FIG. 3 is provided on the right side of the broken line portion shown in FIG. FIG. 4 is a diagram showing waveforms of signals in the subsequent circuit shown in FIG.

  The output (d) of the H comparison circuit 16 is supplied to the input terminal 31. Further, the output (g) of the V comparison circuit 17 is supplied to the input terminal 32. The latch 33 and the OR gate 34 extend “1” (with a horizontal synchronizing signal), which is the output (d) of the H comparison circuit 16, by 1H. The output (e) of the OR gate 34 is output to the output terminal 42 via the OR gate 37. The output (e) of the OR gate 34 is delayed by 2H or 3H in the latches 38, 39, and 40, and is generated as a delayed signal. The AND gate 36 receives the output (g) of the V comparison circuit 17 and the signal (f) from the latch 39, and outputs “1” to the OR gate 37 when both are “1”. The AND gate 41 receives the signal (i) from the latch 35 and the signal (h) from the latch 40, and outputs an AND output of both to the OR gate 37. The output of the OR gate 37 is the final output of the video detection circuit, and “1” indicates “video signal present”.

  As described above, the video detection circuit of the present embodiment employs the succeeding circuit shown in FIG. 3 in the synchronization signal detection circuit 3 shown in FIG. With this configuration, “1” (with video signal) can be extended and used, and it can be prevented that “no video signal” is detected at the boundary between the horizontal synchronization pulse, equalization pulse, and vertical synchronization pulse.

[Third Embodiment]
Next, a third embodiment of the present invention will be described.
The video detection circuit of this embodiment has a configuration in which a synchronous reproduction circuit is added to the configuration shown in FIG. With this configuration, the clock source of the synchronous recovery circuit can be used. The description of the synchronization separation circuit and the synchronization signal detection circuit has been described in the first embodiment and the second embodiment, and will be omitted.

  The synchronization separation circuit outputs a separation synchronization signal to the synchronization signal detection circuit and the synchronization reproduction circuit. When a normal separation / synchronization signal is supplied from the synchronization separation circuit, the synchronized playback circuit uses a clock, various pulses (horizontal period pulse, vertical period pulse, etc.) and black burst necessary for video processing synchronized with the separation synchronization signal. (Black video signal + synchronization signal) is generated. In addition, since the synchronous reproduction circuit has an oscillator, the transmitter outputs a free-run signal even if the separation synchronization signal is not supplied from the synchronization separation circuit.

  As described above, by providing the video detection circuit with the synchronous reproduction circuit, the following applications can be considered. For example, when the synchronization signal detection circuit sends out an alarm to the synchronization regeneration circuit when the supplied separated synchronization signal is not normal, the synchronization regeneration circuit can be made free-run. In addition, a clock generated in a PLL (Phase-Locked Loop) circuit of the synchronous reproduction circuit can be used in the synchronous signal detection circuit.

  Even if the synchronous reproduction circuit is not synchronized with the input video signal, if the frequency difference from the input signal is limited, the detection range of the H comparison circuit and the V comparison circuit in the synchronization signal detection circuit is set appropriately. do it. If the clock source of the synchronous recovery circuit is a crystal oscillator, the frequency change range is very narrow, so that even if it is not locked to the input, the horizontal synchronization detection range 50 to 100 and the vertical synchronization detection range in the synchronization signal detection circuit 756 to 796 may be left as they are.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described.
In the configuration shown in FIG. 1, the video detection circuit of the present embodiment has a configuration in which an analog video signal switcher (analog video signal switching function) is provided in the synchronization separation circuit. This analog video signal switcher switches the video signal input to the sync separator circuit. For example, when the analog video signal switcher switches between a bright video signal and a dark video signal, the synchronization tip potential in the input video signal may be discontinuous. Under this influence, it is conceivable that the separation synchronization signal output from the synchronization separation circuit is temporarily disturbed. If there is a temporary disturbance of the separation synchronization signal, the synchronization signal detection circuit temporarily detects “no video signal” in spite of the input video signal. Therefore, “0” (no video signal) is output from the output terminal of the synchronization signal detection circuit. Therefore, in the video detection circuit of the present embodiment, an additional circuit for extending “1” (with video signal) corresponds to the output of the synchronization signal detection circuit. This additional circuit is added after the output terminal of the synchronization signal detection circuit. Since this additional circuit is the same as the subsequent circuit described in the second embodiment, description thereof is omitted here. With this additional circuit, there is an input video signal even during a temporary period in which the separation synchronization signal is disturbed, and “1” (video signal present) can be output.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described.
The video detection circuit according to the present embodiment includes a second H comparison circuit having a horizontal synchronization detection range of 0 to 49 and a potential for lowering the input potential of the synchronization separation circuit in the synchronization separation circuit described in the fourth embodiment. It is the structure which added the control circuit. In this configuration, first, the second H comparison circuit detects that the synchronization tip potential of the input video signal has risen due to the switching of the analog video signal switch. Then, the input potential of the synchronization separation circuit is lowered by the potential control circuit. As a result, it is possible to realize synchronous separation that is quick in response to fluctuations in the input video signal.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described.
The video detection circuit of the present embodiment has a configuration in which a third H comparison circuit having a horizontal synchronization detection range of 100 to 754 is added to the synchronization signal detection circuit in the configuration shown in FIG. The third H comparison circuit is supplied with the output signal of the latch 15 shown in FIG. The output signal of the latch 15 is the signal described in the first embodiment. When the third H comparison circuit detects that the output signal of the latch 15 is within the horizontal synchronization detection range, it is assumed that the video signal portion above the synchronization signal is separated as synchronization. A control signal is output. This control signal is a signal for controlling the comparator voltage in the synchronization separation circuit to be lowered. As a result, normal synchronization separation can be realized even if the amplitude of the input composite synchronization signal decreases.

  As mentioned above, although each embodiment of this invention was described, it is not limited to said each embodiment, A various deformation | transformation is possible in the range which does not deviate from the summary.

  The present invention can also be applied to the presence / absence detection of an input signal of a device having a synchronous reproduction circuit.

It is a block diagram which shows the structure of the image | video detection circuit which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the synchronizing signal detection circuit which concerns on one Embodiment of this invention. It is a block diagram which shows the structural example of the back | latter stage of the H comparison circuit and V comparison circuit of the video detection circuit which concerns on one Embodiment of this invention. It is a figure which shows the waveform of each signal in the image | video detection circuit which concerns on one Embodiment of this invention, respectively. It is a figure which shows each example of the waveform of the composite video signal input into the video detection circuit which concerns on one Embodiment of this invention. It is a flowchart which shows the flow of the image | video detection method (program) which concerns on one Embodiment of this invention. It is a block diagram which shows the minimum structure of the synchronizing signal detection circuit and video detection circuit which concern on one Embodiment of this invention. It is a block diagram which shows the structure of the image | video detection circuit relevant to this invention.

Explanation of symbols

1 Input terminal 2 Sync separation circuit (SYNC_SEP)
3 Sync signal detection circuit (SYNC_DET)
4 Output terminal 11 Input terminal 12 Inverter 13 Adder circuit 14 Selector 15 Latch 16 H comparison circuit 17 V comparison circuit 18 Clock generation circuit 19 Pseudo H counter 20 Delay circuit 21 AND gate 22 OR gate 23 Output terminal 31 Input terminal 32 Input terminal 33 Latch 34 OR gate 35 Latch 36 AND gate 37 OR gate 38 Latch 39 Latch 40 Latch 41 AND gate 42 Output terminal 43 Input terminal 51 Input terminal 52 Sync separation circuit (SYNC_SEP)
53 retriggerable multivibrator 54 output terminal 301 adding means 302 horizontal synchronization detecting means 303 vertical synchronization detecting means 304 video detection signal output means 305 clock generating means 306 pulse generating means

Claims (19)

A synchronization signal detection circuit that inputs the separated synchronization signal from a synchronization separation circuit that performs synchronization separation of an input composite video signal and outputs a separated synchronization signal,
Adding means for counting and accumulating the number of times of the low level of the separation synchronization signal within one horizontal period;
Horizontal synchronization detection means for detecting whether the addition result by the addition means is within a horizontal synchronization detection range corresponding to a pulse width of a horizontal synchronization signal;
Vertical synchronization detection means for detecting whether the addition result by the addition means is within a vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal;
A synchronization signal detection circuit comprising: A video detection circuit that inputs the separated synchronization signal from a synchronization separation circuit that performs synchronous separation of an input composite video signal and outputs a separated synchronization signal,
Adding means for counting and accumulating the number of times of the low level of the separation synchronization signal within one horizontal period;
Horizontal synchronization detection means for detecting whether the addition result by the addition means is within a horizontal synchronization detection range corresponding to a pulse width of a horizontal synchronization signal;
Vertical synchronization detection means for detecting whether the addition result by the addition means is within a vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal;
Video detection signal output means for performing a logical operation based on the detection result by the horizontal synchronization detection means and the detection result by the vertical synchronization detection means, and outputting a video detection signal indicating the presence or absence of the video signal of the composite video signal;
A video detection circuit comprising: The video detection signal output means includes
When the addition result is within the horizontal synchronization detection range as a result of detection by the horizontal synchronization detection means, and when the addition result is within the vertical synchronization detection range as a result of detection by the vertical synchronization detection means 3. The video detection circuit according to claim 2, wherein the video detection signal indicating that the composite video signal includes a video signal is output. Clock generating means for generating a clock whose frequency and phase are not synchronized with respect to the composite video signal;
The adding means includes
4. The video detection circuit according to claim 2, wherein the number of times of the low level of the separation synchronizing signal is counted and accumulated every time the clock generated by the clock generating means is input. Based on a clock whose frequency and phase are not synchronized with respect to the composite video signal, pulse generating means for generating a pseudo pulse of one horizontal period;
The adding means includes
5. The video detection circuit according to claim 2, wherein the addition result is cleared to zero each time a pseudo pulse generated by the pulse generation unit is input. 6. The adding means includes
6. The video detection circuit according to claim 5, wherein the addition result immediately before the addition result is cleared to zero is output to the horizontal synchronization detection means and the vertical synchronization detection means. The video detection signal output means includes
A delay circuit, an AND circuit, and an OR circuit;
The delay circuit is
The detection result by the horizontal synchronization detection means is delayed three times of one horizontal cycle, and is output to the AND circuit as a delay signal,
The AND circuit is:
Perform a logical product based on the detection result by the vertical synchronization detection means and the delay signal, and output the logical product result to the logical sum circuit,
The OR circuit is
The logical sum is performed based on the detection result by the horizontal synchronization detection means and the result of the logical product, and the logical sum is output as the video detection signal. The video detection circuit described. The video detection signal output means includes
The signal indicating the detection result by the horizontal synchronization detection means is extended by one horizontal period when the addition result is within the horizontal synchronization detection range as a result of detection by the horizontal synchronization detection means. The video detection circuit according to any one of 7 to 7.   9. The video detection circuit according to claim 2, further comprising a synchronization separation circuit that inputs a composite video signal, performs synchronization separation, and outputs a separation synchronization signal. An adding step for counting and accumulating the number of times of the low level of the separation synchronizing signal within one horizontal cycle;
A horizontal synchronization detection step for detecting whether the addition result of the addition step is within a horizontal synchronization detection range corresponding to a pulse width of a horizontal synchronization signal;
A vertical synchronization detection step for detecting whether the addition result of the addition step is within a vertical synchronization detection range corresponding to a pulse width of the vertical synchronization signal;
A synchronization signal detection method comprising:   A video detection signal output step of performing a logical operation based on the detection result of the horizontal synchronization detection step and the detection result of the vertical synchronization detection step and outputting a video detection signal indicating the presence or absence of the video signal of the composite video signal; The synchronization signal detection method according to claim 10, wherein: In the video detection signal output step,
When the addition result is within the horizontal synchronization detection range as a result of detection by the horizontal synchronization detection step, and when the addition result is within the vertical synchronization detection range as a result of detection by the vertical synchronization detection step 12. The synchronous signal detection method according to claim 11, wherein the video detection signal indicating that the composite video signal includes a video signal is output. A clock generation step of generating a clock whose frequency and phase are not synchronized with respect to the composite video signal;
13. The synchronization signal detection method according to claim 10, wherein the addition step is performed every time the clock generated by the clock generation step is input. A pulse generation step of generating a pseudo pulse of one horizontal period based on a clock whose frequency and phase are not synchronized with respect to the composite video signal;
A clear step of clearing the addition result of the addition step to zero each time a pseudo pulse generated by the pulse generation step is input,
The synchronization signal detection method according to claim 10, further comprising: An addition process for counting and accumulating the number of times of the low level of the separation synchronizing signal within one horizontal cycle;
Horizontal synchronization detection processing for detecting whether the addition result by the addition processing is within a horizontal synchronization detection range corresponding to the pulse width of the horizontal synchronization signal;
Vertical synchronization detection processing for detecting whether the addition result by the addition processing is within a vertical synchronization detection range corresponding to the pulse width of the vertical synchronization signal;
A program that causes a computer to execute.   A video detection signal output process for performing a logical operation based on the detection result by the horizontal synchronization detection process and the detection result by the vertical synchronization detection process and outputting a video detection signal indicating the presence or absence of the video signal of the composite video signal is further performed by the computer 16. The program according to claim 15, wherein the program is executed. As the video detection signal output processing,
When the addition result is within the horizontal synchronization detection range as a result of detection by the horizontal synchronization detection process, and when the addition result is within the vertical synchronization detection range as a result of detection by the vertical synchronization detection process 17. The program according to claim 16, causing a computer to execute a process of outputting the video detection signal indicating that the composite video signal includes a video signal. Further causing the computer to execute clock generation processing for generating a clock whose frequency and phase are not synchronized with respect to the composite video signal,
18. The program according to claim 15, wherein the computer executes the addition process every time a clock generated by the clock generation process is input. Based on a clock whose frequency and phase are not synchronized with the composite video signal, a pulse generation process for generating a pseudo pulse of one horizontal period;
Each time a pseudo pulse generated by the pulse generation process is input, a clear process for clearing the addition result by the addition process to zero, and
The program according to claim 15, further causing a computer to execute.

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