JP2005347805A - Vertical synchronizing signal detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical synchronizing signal detection circuit of a digital circuit configuration capable of stably detecting a vertical synchronizing signal regardless of a simple configuration. <P>SOLUTION: The vertical synchronizing signal detection circuit includes: (1) a vertical synchronizing part discrimination means that compares a threshold value, whereby whether or not an amplitude is the amplitude of the vertical synchronizing signal can be discriminated, with an amplitude of a signal to be detected at one or more parts in a horizontal direction at which a vertical synchronizing signal is located in the case of a horizontal scanning line including the vertical synchronizing signal or at which a signal of a synchronizing signal group is not located at all in the case of a horizontal scanning line not including the vertical synchronizing signal in each horizontal scanning line; and (2) a vertical synchronizing signal discrimination means for detecting the vertical synchronizing signal based on the whether or not a pattern of a comparison result of the vertical synchronizing part discrimination means is a prescribed pattern, the pattern being changed every time the signal to be detected on every alternate horizontal scanning line appears. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a vertical synchronization signal detection apparatus, and can be applied to, for example, a case where a vertical synchronization signal is detected from a television signal.

  When a television signal used in analog television broadcasting is displayed on a television receiver or recorded on a VTR tape, or when digitized and subjected to an encoding process typified by MPEG2. In order to determine the horizontal and vertical start timing of the video signal portion, it is necessary to separate or detect the horizontal synchronization signal and the vertical synchronization signal from the television signal.

  Conventionally, as disclosed in Non-Patent Document 1, an analog circuit first separates a composite sync signal from a composite video signal (television signal), and passes the separated composite sync signal through an integration circuit. After that, the vertical synchronization signal is often separated by comparing with a threshold value. The fact that the vertical synchronization signal can be separated is the same as the detection of the vertical synchronization signal.

In addition, with the recent development of digital technology, a method of executing all video signal processing by a digital circuit has become common, but even in that case, by replacing the analog circuit with the digital circuit, In many cases, the vertical synchronization signal is separated and detected by using an integration circuit and a comparator.
Edited by Japan Broadcasting Corporation, “Color TV Reception Technology”, published by Japan Broadcasting Publishers Association (supplemented in December 1990, pages 111-117)

  However, in order to configure a vertical synchronizing signal separation circuit and a vertical synchronizing signal detection circuit with a digital circuit, it is necessary to implement an integration circuit having a long time constant with a multistage digital filter or the like, in other words, a multistage digital filter or the like. A large-scale circuit is required. Also, in the case of a non-standard video signal from a home VTR or an input video signal with a lot of noise and distortion, the integration in the vertical synchronization period is not normal, and a vertical synchronization signal separation circuit or a vertical synchronization signal detection circuit May not work properly.

  Therefore, there has been a demand for a vertical synchronizing signal detection circuit having a digital circuit configuration that operates stably with a simple configuration.

  In order to solve this problem, the present invention provides a vertical synchronization signal detection circuit that detects a vertical synchronization signal from a detected signal that is a digitized video signal or composite synchronization signal. (1) For each horizontal scanning line, The amplitude of the signal to be detected at one or a plurality of positions in the horizontal direction in which the vertical synchronizing signal is positioned in the horizontal scanning line including the synchronizing signal and no synchronizing signal system signal is positioned in the horizontal scanning line not including the vertical synchronizing signal, A vertical synchronization point discriminating means for comparing with a threshold capable of determining whether or not the amplitude of the vertical synchronizing signal is, and (2) the vertical synchronizing point discriminating means which changes every time the detected signal is shifted by one horizontal scanning line. Vertical synchronization determination means for detecting a vertical synchronization signal based on whether or not the pattern of the comparison result is a predetermined pattern.

  According to the vertical synchronizing signal detection circuit of the present invention, the vertical synchronizing signal is based on whether the amplitude of one or a plurality of positions in the vertical and horizontal areas matches the amplitude pattern of one or a plurality of positions in the vertical and horizontal areas including the vertical synchronizing signal. Therefore, the vertical synchronization signal can be detected stably with a simple configuration.

(A) First Embodiment Hereinafter, a first embodiment in which a vertical synchronizing signal detection circuit according to the present invention is applied to a video signal digitizing apparatus that receives an analog video signal and outputs corresponding digital video data will be described. The details will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a video signal digitizing apparatus according to the first embodiment.

  In FIG. 1, a video signal digitizing apparatus 1 according to the first embodiment includes an analog / digital (A / D) converter 2, a clock extractor (CLK extractor) 3, a horizontal counter 4, and a horizontal counter reset circuit. 5, a vertical counter 6, a vertical counter reset circuit 7, and a digital video data generator 8. The horizontal counter 4, the horizontal counter reset circuit 5, and the vertical counter reset circuit 7 constitute a vertical synchronization signal detection circuit.

  In the case of the first embodiment, the vertical direction counter reset circuit 7 includes first and second vertical synchronization line detectors 11 and 21, first and second five-line detection result memories 12 and 22, and first And second vertical synchronization pattern detectors 13 and 23 and a vertical synchronization determination unit 9.

  The clock extractor 3 extracts a digital processing clock from the input analog video signal (analog video input). For example, the clock extractor 3 separates the color burst signal from the input analog video signal, operates a PLL circuit or the like on the separated color burst signal, and is four times the color burst frequency (3.58 MHz). A clock having a frequency (14.3 MHz) is formed.

  The analog / digital converter 2 converts the input analog video signal into a digital signal based on the clock from the clock extractor 3 (signal lines are omitted in FIG. 1).

  The horizontal direction counter 4 is, for example, a cyclic counter that cycles from 0 to 909, which is counted up every time a clock from the clock extractor 3 is given. The count value of the horizontal direction counter 4 represents the position in one horizontal scanning line.

  The horizontal direction counter reset circuit 5 gives a reset command to the horizontal direction counter 4 when the horizontal synchronization signal is detected based on the digital signal from the analog / digital converter 2 and forces the count value of the horizontal direction counter 4. Therefore, the predetermined value is set.

  For example, based on the clock from the clock extractor 3 (the count value of the horizontal direction counter 4 may be used), the vertical direction counter 6 shifts the horizontal scanning line to the next horizontal scanning line. It is a cyclic counter that cycles from 1 to 525, counting up every time. The count value of the vertical direction counter 6 represents the position in the vertical direction.

  As will be described later, the vertical counter reset circuit 7 gives a reset command to the vertical counter 6 when a vertical synchronization signal is detected based on the digital signal from the analog / digital converter 2, and the vertical counter 6 The count value is forcibly set to a predetermined value.

  The digital video data generator 8 includes a digital signal from the analog / digital converter 2, a clock from the clock extractor 3 (signal line is omitted), a count value of the horizontal counter 4, and a vertical counter The digital video data to be output (digital video output) is formed based on the count value of 6.

  Functions of the components of the vertical counter reset circuit 7 will be described with reference to FIG.

  FIG. 2 is an explanatory diagram showing an ideal relationship among a digital signal (video data) from the analog / digital converter 2, a count value of the horizontal direction counter 4, and a count value of the vertical direction counter 6.

  In FIG. 2, the hatched portion is a position where the video data takes a value equal to or lower than the black level for a horizontal synchronizing signal, a vertical synchronizing signal, or the like. In the case of the example of FIG. 2, in the first field, the count value of the vertical direction counter 6 is “4” to “6” and the count value of the horizontal direction counter 4 is “790 to 909” in the first field. 0 to 261 ”and a period in which the count value of the vertical direction counter 6 is“ 4 ”to“ 6 ”and the count value of the horizontal direction counter 4 is“ 340 to 716 ”. In the second field, A period in which the count value of the vertical direction counter 6 is “266” to “268” and the count value of the horizontal direction counter 4 is “340 to 716”, and the count value of the vertical direction counter 6 is “267” to “269” And the count value of the horizontal counter 4 is “790 to 909, 0 to 261”.

  Here, when attention is paid to the horizontal position where the count value of the horizontal direction counter 4 is “197 to 199”, the horizontal position value falls below the black level because of the horizontal scanning line including the vertical synchronization signal. (The horizontal scanning lines whose count values of the vertical direction counter 6 are “4” to “6” and “267” to “269”), the values of these horizontal positions in other horizontal scanning lines are lower than the black level. Takes a value for a large level.

  When attention is paid to the horizontal position where the count value of the horizontal counter 4 is “647 to 649”, the horizontal position value is equal to or lower than the black level because the horizontal scanning line (including the vertical synchronization signal) The count values of the vertical direction counter 6 are only “4” to “6” and “266” to “268” horizontal scanning lines), and in the other horizontal scanning lines, these horizontal position values are larger than the black level. Takes a value related to the level.

  In the first embodiment, the vertical synchronization timing is detected by utilizing the relationship between the count value of the horizontal counter 4 and the value of the digital signal (video data) from the analog / digital converter 2 (see FIG. In other words, the vertical synchronization signal is detected).

  The first vertical synchronization line detector 11 in the vertical counter reset circuit 7 is configured to detect the value of the digital signal (video data) when the count value of the horizontal counter 4 is “197”, “198”, and “199”. Compared with the threshold value, the logic “1” is taken in the case where the value of the digital signal (video data) is equal to or less than the threshold value together with the three comparison results, and even one of the three comparison results When the value of the digital signal (video data) is larger than the threshold value, a signal that takes logic “0” is output.

  The second vertical synchronization line detector 21 executes the same processing as that of the first vertical synchronization line detector 11 when the count values of the horizontal direction counter 4 are “647”, “648”, and “649”. Is.

  The first 5-line detection result memory 12 is, for example, a 5-bit FIFO memory, and holds the output bits from the first vertical synchronization line detector 11 for five consecutive horizontal scanning lines (5 bits). Is.

  The second 5-line detection result memory 22 is also a 5-bit FIFO memory, for example, and holds the output bits from the second vertical synchronization line detector 21 for five consecutive horizontal scanning lines (5 bits). Is.

  The first vertical synchronization pattern detector 13 detects that the 5 bits of the first 5-line detection result memory 12 are “01110”. When the 5 bits of the first 5-line detection result memory 12 take “01110”, the count value of the vertical counter 6 is “7” and the count value of the horizontal counter 6 is “7”. 199 ”or the timing when the count value of the vertical counter 6 is“ 270 ”and the count value of the horizontal counter 6 becomes“ 199 ”(here, expressed as no processing delay) doing).

  The second vertical synchronization pattern detector 23 detects that the 5 bits of the second 5-line detection result memory 22 are “01110” or “11100”. When the 5 bits of the second 5-line detection result memory 22 take “01110”, the count value of the vertical counter 6 is “7” and the count value of the horizontal counter 6 is “7”. 649 ”or the timing when the count value of the vertical counter 6 is“ 269 ”and the count value of the horizontal counter 6 is“ 649 ”(here, expressed as no processing delay) doing). When the 5 bits of the second 5-line detection result memory 22 is “11100”, the count value of the vertical counter 6 is “8” and the count value of the horizontal counter 6 is referred to using FIG. Or the timing when the count value of the vertical direction counter 6 becomes “270” and the count value of the horizontal direction counter 6 becomes “649” (in this case, there is no processing delay). Expressed as).

  The vertical synchronization determination unit 9 forms a reset command for the vertical direction counter 6 based on the detection results of the first and second vertical synchronization pattern detectors 13 and 23.

  (1) The detection output of the first vertical synchronization pattern detector 13 indicates that the content of the first 5-line detection result memory 12 is “01110”, and the detection of the second vertical synchronization pattern detector 23 When the output indicates that the content of the second 5-line detection result memory 22 is “01110”, a reset command for setting “7” to the vertical counter 6 is output.

  (2) The detection output of the first vertical synchronization pattern detector 13 indicates that the content of the first 5-line detection result memory 12 is “01110”, and the detection of the second vertical synchronization pattern detector 23 is performed. When the output indicates that the content of the second 5-line detection result memory 22 is “11100”, a reset command for setting “270” to the vertical counter 6 is output.

  For example, assume that the signal source of the input analog video signal is switched and an analog video signal that is not synchronized with the immediately preceding vertical synchronization signal is input.

  Even in such a case, a color burst signal is superimposed for each horizontal scanning line (not necessarily all lines), and a horizontal synchronization signal is inserted for each horizontal scanning line. The clock from the clock extractor 3 is quickly stabilized, and the horizontal counter 4 is also quickly synchronized.

  Immediately after the signal source of the analog video signal is switched, the count value of the vertical direction counter 6 is not correct, but the horizontal direction counter 4 is quickly synchronized, so the count value of the horizontal direction counter 4 is correct. It has become a thing.

  Even after the signal source is switched, when the horizontal scanning line including the vertical synchronizing signal is reached, the first and second vertical synchronizing line detectors 11 and 21 have the count value of the horizontal direction counter 4 of “199” or “649”. The logic “1” is output at the timing. The three horizontal scanning lines including the vertical synchronizing signal are finished and become the next horizontal scanning line, and at the timing when the count value of the horizontal direction counter 4 is “199” or “649”, the first and second vertical scanning lines are used. The synchronous line detectors 11 and 21 output a logic “0”.

  As a result, the 5 bits stored in the first 5-line detection result memory 12 become “01110”, and the 5 bits stored in the second 5-line detection result memory 22 become “01110” or “11100”. The timing that becomes. Based on the detection results of the first and second vertical synchronization pattern detectors 13 and 23, the vertical synchronization determiner 9 determines that the 5 bits of the first 5-line detection result memory 12 is “01110” and the second 5-line detection result. When the 5 bits of the memory 22 are recognized as “01110”, a reset command is issued to the vertical direction counter 6 to set the count value to “7”, and the 5 bits of the first 5-line detection result memory 12 is “ When 5 bits of the second 5-line detection result memory 22 are recognized as “11100” at “01110”, a reset command is issued to the vertical counter 6 to set the count value to “270”.

  In response to this reset command, the vertical counter 6 is reset, and vertical synchronization is established for the analog video signal whose signal source has been switched.

  As described above, according to the vertical synchronizing signal detection circuit of the first embodiment, the determination is made near the center of the vertical synchronizing signal, and the pattern detection is performed with six values per horizontal scanning line of each field. Since the determination is performed, it is possible to detect the vertical synchronization signal with high accuracy and few malfunctions as compared with the conventional method in which the falling edge of the vertical synchronization is detected by the integration circuit.

(B) Second Embodiment Next, a vertical synchronization signal detection circuit according to a second embodiment of the present invention will be described focusing on differences from the first embodiment.

  FIG. 3 is a block diagram showing a configuration of the video signal digitizing apparatus according to the second embodiment. The same reference numerals are given to the same and corresponding parts as those in FIG. 1 according to the first embodiment. Show.

  As apparent from the comparison between FIG. 3 and FIG. 1, in the case of the second embodiment, the first and second vertical synchronization pattern sub-detectors 14 and 24 are further provided. The reset timing of the vertical direction counter 6 is determined based on the detection outputs of the second vertical synchronization pattern detectors 13 and 23 and the first and second vertical synchronization pattern sub-detectors 14 and 24.

  In the second embodiment, a vertical synchronization signal can be detected even when an input analog video signal is a non-standard signal. In the case of the first embodiment, the vertical synchronization signal can be detected with high accuracy even if noise or distortion is mixed in the input analog video signal. However, since the detection conditions are severe, the VTR is paused, fast forwarded, rewinded, etc. There is a possibility that the vertical synchronization signal cannot be detected for the generated non-standard signal, and the second embodiment has been made in consideration of this point.

  The first vertical synchronization pattern sub-detector 14 detects that 5 bits of the first 5-line detection result memory 12 are “* 111 *” (* may be 0 or 1). When the 5 bits of the first 5-line detection result memory 12 take “* 111 *”, the count value of the vertical direction counter 6 is “7” and the count value of the horizontal direction counter 6 according to FIG. Is the timing when the count value of the vertical direction counter 6 is “270” and the count value of the horizontal direction counter 6 becomes “199” (here, the processing is the processing In the case of a non-standard signal, the timing may be shifted up and down by several horizontal scanning lines due to noise.

  The detection condition “* 111 *” by the first vertical synchronization pattern sub-detector 14 is compared with the detection condition “01110” by the first vertical synchronization pattern detector 13 in three consecutive lines having a vertical synchronization signal (vertical The count value of the direction counter 6 is easy to detect “4” to “6” or “267” to “269”).

  Similarly, the second vertical synchronization pattern sub-detector 24 detects that the 5 bits of the second 5-line detection result memory 22 are “* 111 *” (* may be 0 or 1). is there.

  In the case of the second embodiment, the vertical synchronization determination unit 9 includes the detection outputs of the first and second vertical synchronization pattern detectors 13 and 23 and the first and second vertical synchronization pattern sub-detectors 14 and 24. Therefore, the following determination is made as to whether or not to issue a reset command to the vertical direction counter 6.

  (1) The detection output of the first vertical synchronization pattern detector 13 indicates that the content of the first 5-line detection result memory 12 is “01110”, and the detection of the second vertical synchronization pattern detector 23 When the output indicates that the contents of the second 5-line detection result memory 22 is “01110”, the contents of the detection outputs of the first and second vertical synchronization pattern sub-detectors 14 and 24 are considered. First, a reset command for setting “7” to the vertical direction counter 6 is output.

  (2) The detection output of the first vertical synchronization pattern detector 13 indicates that the content of the first 5-line detection result memory 12 is “01110”, and the detection of the second vertical synchronization pattern detector 23 When the output indicates that the content of the second 5-line detection result memory 22 is “11100”, the output is related to the contents of the detection outputs of the first and second vertical synchronization pattern sub-detectors 14 and 24. First, a reset command for setting “270” to the vertical direction counter 6 is output.

  The reset determination conditions (1) and (2) described above are the same as those in the first embodiment. Only when the reset determination condition of (1) and (2) is not satisfied, it is confirmed whether or not the reset determination condition of (3) is satisfied.

  (3) The detection output of the first vertical synchronization pattern sub-detector 14 indicates that the content of the first 5-line detection result memory 12 is “* 111 *”, and the second vertical synchronization pattern sub-detection When the detection output of the detector 24 indicates that the content of the second 5-line detection result memory 22 is “* 111 *”, the detection of the first and second vertical synchronization pattern detectors 13 and 23 Regardless of the contents of the output, a reset command for setting “7” to the vertical direction counter 6 is output.

  Since an abnormal vertical synchronization waveform due to a non-standard signal appears almost one field after it is determined that the reset determination condition of (3) is satisfied, a reset command is issued when the reset determination condition of (3) is satisfied. Is issued, the vertical synchronization determination unit 9 does not perform the reset by the pattern matching thereafter, for example, during 500 horizontal scanning lines.

  According to the second embodiment, in addition to the effect of the first embodiment, there is an effect that the vertical synchronization detection can be satisfactorily executed even for a non-standard video signal such as a VTR paused or fast-forwarded. Can do.

(C) Other Embodiments In each of the above embodiments, the level of video data at three locations (for example, “197” to “199”) continuous in the horizontal direction is targeted for detection of the vertical synchronization signal portion. However, the number may be one, two, or four or more.

  In each of the above embodiments, pattern matching is performed for a total of five lines including one line not including the vertical synchronization signal above and below the number of consecutive lines including the vertical synchronization signal (3 lines). The number of lines not including the vertical synchronization signal may be zero or more than two lines, the number of lines may be different between the upper side and the lower side, and not all lines including the vertical synchronization signal may be targeted. .

  In the second embodiment, the pattern matching for the non-standard signal targets only continuous lines including the vertical synchronization signal, but may include the line not including the vertical synchronization signal. Some lines including the synchronization signal may not be subjected to pattern matching. In short, it is only necessary that the detection condition for vertical synchronization is looser than the main detection condition.

  According to the present invention, the vertical synchronization signal is determined depending on whether the arrangement (pattern) of the video signal levels at a plurality of locations in the vertical and horizontal (horizontal and vertical) predetermined areas matches the arrangement in the predetermined area including the vertical synchronization signal. If it is detected, the method for determining the coincidence is not limited to those in the above embodiments.

  In each of the above-described embodiments, an analog video signal is inputted and converted into a digital signal to perform vertical synchronization detection. From the beginning, the present invention is also applied to a device to which a digital video signal is inputted. The invention can be applied. The input signal used for vertical synchronization detection is not limited to a video signal, and may be a composite synchronization signal.

  Note that if it is desired to separate and extract a signal including only the vertical synchronization signal, for example, when the count values of the vertical direction counter and the horizontal direction counter in each of the above embodiments are a predetermined combination, a logic “0” is taken. A circuit that generates a signal that takes logic “1” at other times may be provided.

  In the case of the second embodiment, it may be possible to select whether or not to use the determination condition (3) intended for the non-standard signal, and instead of the determination conditions (1) and (2), the determination may be made. The selection of applying only condition (3) may be made possible.

  In each of the above embodiments, the composite video signal represented by NTSC has been described. However, the technical idea of the present invention is also applicable to vertical synchronization detection using a PAL or SECAM system signal, or a component signal in which a luminance signal and a color difference signal are separated. The technical idea of the present invention can also be applied to vertical synchronization detection using a monochrome signal or a non-interlace signal.

1 is a block diagram illustrating a configuration of a video signal digitizing apparatus including a vertical synchronization signal detection circuit according to a first embodiment. It is explanatory drawing which shows the ideal relationship between the digital signal from the analog / digital converter of 1st Embodiment, the count value of a horizontal direction counter, and the count value of a vertical direction counter. It is a block diagram which shows the structure of the video signal digitizing apparatus containing the vertical synchronizing signal detection circuit of 2nd Embodiment.

Explanation of symbols

2 ... Analog / digital (A / D) converter, 3 ... Clock extractor (CLK extractor), 4 ... Horizontal direction counter, 5 ... Horizontal direction counter reset circuit, 6 ... Vertical direction counter, 7 ... Vertical direction counter reset circuit , 9... Vertical synchronization determiner, 11, 21... Vertical synchronization line detector, 12, 22... 5 line detection result memory, 13, 23... Vertical synchronization pattern detector, 14, 24.

Claims (3)

In a vertical synchronizing signal detection circuit for detecting a vertical synchronizing signal from a detected signal consisting of a digitized video signal or a composite synchronizing signal,
For each horizontal scanning line, one or a plurality of positions in the horizontal direction where a vertical synchronizing signal is located in a horizontal scanning line including a vertical synchronizing signal and no synchronizing signal system signal is located in a horizontal scanning line not including a vertical synchronizing signal. Vertical synchronization point discriminating means for comparing the amplitude of the detected signal with a threshold value that can determine whether the amplitude of the detected signal is the amplitude of the vertical synchronization signal;
Vertical synchronization determination means for detecting a vertical synchronization signal based on whether the pattern of the comparison result of the vertical synchronization position discriminating means is a predetermined pattern, which changes every time the detected signal deviates by one horizontal scanning line. A vertical synchronization signal detection circuit characterized by the above.   2. The vertical synchronization signal detection circuit according to claim 1, wherein the vertical synchronization determination means detects a vertical synchronization signal based on a pattern of comparison results for a plurality of horizontal scanning lines. The vertical synchronization determination means uses a predetermined pattern for detecting a vertical synchronization signal for a standard signal in which the vertical synchronization signal portion is stable, and a possibility that the vertical synchronization signal portion is not stable. 3. The vertical synchronization signal detection circuit according to claim 1, wherein the vertical synchronization signal detection circuit is separately provided for a standard signal.

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