JP2001333293A - Video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video display device equipped with a PLL circuit capable of supplying stable clocks even to the signal of a video system having a horizontal synchronizing signal inserted with an equivalent pulse or slit pulse or to the signal of a video system by which the horizontal synchronizing signal is eliminated during a vertical fly-back period, without special sequence control. SOLUTION: While using an equivalent pulse mask circuit 19 for masking the equivalent pulse and the slit pulse and a phase comparator 19 capable of stopping the operation of phase comparison during a vertical synchronizing period, the PLL circuit capable of supplying stable clocks even to irregular horizontal synchronizing signals inputted during the vertical fly-back period is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device which generates a clock by a line lock system and performs signal processing using the clock (International Patent Classification H04N 5/06).
It is about.

[0002]

2. Description of the Related Art Conventionally, a PLL circuit malfunctions under the influence of an equivalent pulse cutting pulse of a composite synchronizing signal or a composite synchronizing signal superimposed on a video, and a countermeasure such as a top curl at the top of a video signal display is taken as an equivalent measure. A method of masking a pulse or a cutting pulse (a method of not capturing an equivalent pulse or a cutting pulse on the reference pulse input terminal side of a phase comparator constituting a PLL circuit) has been adopted (see Japanese Patent Application Laid-Open No. 11-75084). . This will be described below with reference to the drawings.

[0003] FIG. 7 shows a P pulse generator configured to mask an equivalent pulse and a cutting pulse so as not to capture the pulse on the reference pulse input terminal side of the phase comparator.
FIG. 4 is a block diagram showing one embodiment of an LL circuit.

This PLL circuit includes a phase comparator 101 having two input terminals for comparing the phase of an input signal with the phase of a feedback pulse. The phase comparator 101 inputs a horizontal synchronizing input signal (hereinafter, referred to as an HREF signal) to one input terminal, and inputs a feedback pulse (hereinafter, referred to as an HFEED signal) to the other input terminal. The phase difference is compared, and a PFD signal is output as a phase comparison error.

The output signal P of the phase comparator 101 is
The FD signal is applied to a control input of a voltage controlled oscillator (VCO) 103 via a low pass filter (LPF) 102. The oscillation output of the VCO 103 is
And the count value is calculated by the decoder circuit 10.
Give 5 The counter 104 and the decoder circuit 105
This is for counting the oscillation output of C0103 and setting the cycle of the HREF signal which is a horizontal synchronization input signal.
Moreover, the decoder circuit 105 resets the counter 104 at a timing when the count value of the counter 4 becomes a predetermined value corresponding to horizontal synchronization. That is, the counter 104 operates in the horizontal cycle, and the decoder circuit 105 outputs the HFEED signal in the horizontal cycle.

[0006] The HFEED signal of the horizontal cycle is supplied to one input terminal of a phase comparator 101, and the phase of the HFEED signal is compared with the horizontal synchronization input signal HREF. As a result, the PFD signal output as an error voltage from the phase comparator 101 is applied to the VCO 103 through the LPF 102,
By controlling the oscillation of 103, automatic frequency control of the horizontal synchronizing signal is performed.

Accordingly, the PLL circuit varies the oscillation frequency of the VCO 103 so as to reduce the phase difference between the HREF signal, which is the horizontal synchronization input signal, and the HFEED signal having the horizontal period, and the HFEED signal is changed to the horizontal synchronization input signal (HREF).
Signal). In this state, the PLL circuit is locked, and stable phase control can be performed.

The phase comparator 10 in such a PLL circuit
1, the composite sync signal HV from the vertical sync separation circuit 107
Selection pulse SE obtained by separating the vertical synchronization component from S
HREF from the selector 106 controlled according to L
HVS through a signal or a mask circuit 108 described later
A signal is selected and provided. That is, the circuit is configured such that the HREF signal supplied to the phase comparator 101 is selected during the vertical synchronization period, and the HVS is input during the other periods.

The mask circuit 108 is controlled by a mask pulse decoder 109. Mask pulse decoder 109
Is 1 in the horizontal scanning period based on the count value of the counter 104.
The decoder includes a decoder that creates a set pulse and a reset pulse set at the positions of / 4 and ／, and a latch that latches the output of each decoder and outputs a mask pulse. That is, the mask pulse decoder 109 outputs a pulse (hereinafter, referred to as an HHW signal) having a width of １ ／ to ／ of one cycle of the horizontal synchronization frequency. The mask circuit 108 receives the HHW signal, receives an HVS signal from the outside, and outputs an equivalent pulse of a period of 1/4 to 3/4 of one cycle of the horizontal synchronization frequency of the HVS signal.
Mask the cutting pulse.

[0010]

However, in the above configuration, when a composite synchronizing signal of a type in which horizontal synchronization is lost during the vertical synchronizing period is input, the PLL cannot operate normally, and the display screen cannot be displayed. A defect (top curl) may occur at the upper part, and may further affect the entire system.

Even when there is no problem with the horizontal synchronization frequency in the vertical synchronization period, the mask pulse can be operated with the intended setting only when the clock from which the counter operates is operating normally. Due to such a configuration, the mask pulse is output differently from the intended one depending on the timing, which may similarly cause a problem in the system. In order to avoid this, usually, when turning on the power, the mask function is released, and while the top curl occurs, wait until the clock becomes stable to some extent, and then activate the mask function. A method of performing sequence control is employed.

FIG. 5 shows an output waveform of the phase comparator when a top curl problem actually occurs. The normal operation is that the output of the phase comparator converges before entering the screen display area, but the output of the phase comparator does not converge completely even in the video display period because the stability of the PLL is disturbed during the vertical flyback period. In such a case, the image in the period during which the convergence has not been completed is also disturbed.

The present invention has been made to solve the above problems,
P for generating a digital signal processing clock for a multi-scan compatible video display device that supports various types of video signals
In an LL circuit (phase locked loop circuit), a function of stopping a phase comparison in an irregular period with respect to a horizontal synchronization signal input at an irregular frequency, a function of masking an irregular pulse, and a method of vertically setting a masking period. By having a circuit that can be set with the rate and horizontal rate, it is possible to perform horizontal and vertical retrace periods without using special sequence control. It is an object of the present invention to provide a video display device provided with a PLL circuit capable of supplying a stable clock even to a video signal in which a synchronization signal is lost.

[0014]

In order to solve the above-mentioned problems, a video display device according to the present invention provides a digital signal processing clock generation in a multi-scan compatible video display device corresponding to various types of video signals. In a PLL circuit (phase locked loop circuit) to perform, a function of stopping a phase comparison in an irregular period for a horizontal synchronization signal input at an irregular frequency, a function of masking an irregular pulse, and With a function that can be set with the rate and the horizontal rate, it is possible to perform horizontal synchronization with a video system signal with a horizontal synchronization signal with an equivalent pulse or a cutting pulse inserted or a vertical blanking period without special sequence control It is characterized by having a PLL circuit capable of supplying a stable clock even to a signal of a video system in which a signal disappears.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image display device according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a multi-scan compatible image display apparatus corresponding to various types of image signals according to an embodiment of the present invention.

The input terminal 11 receives a composite synchronizing signal or a composite synchronizing signal superimposed on a video signal.

The synchronizing separation circuit 12 converts a composite synchronizing signal input from the input terminal 11 or a composite synchronizing signal superimposed on a video signal into a horizontal synchronizing signal (hereinafter referred to as HD signal) and a vertical synchronizing signal (hereinafter referred to as VD signal). ) Are extracted. In this embodiment, both the HD signal and the VD signal are output with positive polarity.

The HD signal output from the sync separation circuit 12 is input to an equivalent pulse mask circuit 19. The equivalent pulse mask circuit 12 masks periods other than the normal pulse period by a mask signal output from the mask pulse generation circuit 18 via a second AND gate 30 described later.
The mask function of the signal output from the mask pulse generation circuit 18 in the equivalent pulse mask circuit 19 can be turned on / off by a mask circuit control signal input from the input terminal 22.

Further, V output from the synchronization separation circuit 12
The D signal is input to the first AND gate 24. The other input of the first AND gate 24 is connected to the phase comparator 13
A phase comparator control signal for determining whether or not the phase comparison function is controlled by the VD signal is input via the input terminal 23.

The phase comparator 13 has two input terminals,
One of them is HR output from the equivalent pulse mask circuit 19.
An EF signal is input, and an HFEED signal having the same cycle as an HD signal output from a first counter 16 described later is input to the other side. The phase comparator 13 has an ENB terminal capable of on / off control of the phase comparison operation, and the control is performed by the output of the first AND gate 24.

The phase comparator 13 outputs the HREF signal and the HFEE
The phase difference error of the D signal is output as a PFD signal. PF
The D signal is input to the voltage controlled oscillator VCO 15 via the LPF 14, and the VCO 13 performs an oscillation output according to the control voltage. The oscillation output is supplied from the output terminal 20 to each circuit in the system as a system clock.

The first counter 16 counts the clock from the oscillation output of the VCO 13 and supplies the count value to the mask pulse generation circuit 18 and various pulse generation circuits at the subsequent stage. The first counter 16 also has a function of generating a pulse HREFF signal having the same cycle as the horizontal synchronization HD from the count value.

The mask pulse generating circuit 18 outputs a pulse which can mask an equivalent pulse and a cutting pulse included in the HD signal which is a horizontal synchronizing signal from the count value of the first counter 16 from the input terminal 26. The pulse width is set by the pulse width setting signal, and is supplied to the equivalent pulse mask circuit 19 via the second AND gate 30. The output from the mask period setting pulse generation circuit 29 is connected to the other terminal of the second AND gate 30.

The second counter 28 counts the HD signal output from the sync separation circuit 12. The second counter 28 is reset by a VD signal similarly output from the synchronization separation circuit 12. Second counter 28
Is input to the mask period setting pulse generation circuit 29 to generate a pulse having an arbitrary width set from the input terminal 27.

Further, the counter value output from the counter 16 is supplied to various pulse generating circuits 25 to generate pulses necessary for an external block, and to supply them to each block via an output terminal 21.

FIG. 2 shows a composite synchronizing signal assumed to be inputted from the input terminal 11. Each signal indicates a horizontal synchronization signal in a vertical synchronization period.

The VD signal represents a vertical synchronizing signal. (A) is a signal without an equivalent pulse and a cut pulse (the period is constant when the falling edge of the pulse is observed), and (B) has an equivalent pulse on the front porch and the back porch of the vertical synchronization pulse, but has a vertical synchronization period (C) is a signal in which all pulses of the equivalent pulse, the cutting pulse, and the horizontal synchronization pulse are present (the horizontal period is irregular as in 2). ).

FIG. 3 shows the signal waveform of the operation of the phase comparator 13. The signal described at OUT is output based on the phase difference between the pulses input to the two input terminals A and B. However, the OUT terminal can be controlled to high impedance by a signal input to the ENB terminal.

FIG. 4 shows an internal circuit of the equivalent pulse mask circuit 19, wherein the AND gate 41 and the N
An AND gate 42 is provided.

FIG. 6 shows signal waveforms indicating the operation of the circuit shown in FIG. When the mask pulse input from the mask pulse generation circuit 18 is input as shown in FIG. 6 with respect to the sync separation horizontal output having the equivalent pulse, the masked horizontal sync signal output to the phase comparator 13 is at the lower stage. The waveform is as shown. However, when the ENB terminal is at “L”, the NAND gate output is fixed at “H”, and the signal output to the phase comparator 13 is not masked, and the HD output of the sync separation circuit 12 is supplied as it is.

If the mask period setting pulse is set to a period sufficiently including the vertical synchronizing signal as shown on the right side of FIG. 5, the equivalent pulse is extracted only during this period. In other words, the mask pulse is generated by the clock which is generated based on the stable horizontal synchronizing signal at point A in the figure, and a stable PLL operation can be obtained without performing special sequence control.

The setting of the mask period is based on the input vertical,
Since the horizontal synchronizing signal is created simply, the fluctuation occurs due to the influence of an equivalent pulse or the like. However, there is no problem if the vertical synchronizing signal is set to include the vertical synchronizing signal sufficiently.

[0034]

As described above, the synchronizing separation means for separating the horizontal synchronizing signal and the vertical synchronizing signal superimposed on the video signal, the means for masking the equivalent pulse and notch superimposed on the horizontal synchronizing signal, Means for comparing the phases of a horizontal synchronizing signal output from the separating means and a feedback pulse output from a mask pulse generating means described later, and outputting the phase difference as a voltage value, and means for stopping the function of this phase comparison Means for selecting whether to stop the phase comparison with the separated vertical synchronization signal or arbitrarily, means for smoothing the result of converting the phase difference into a voltage value, and changing the oscillation frequency according to the voltage value. A voltage-controlled oscillator, and counting means for counting the oscillation output of the voltage-controlled oscillator,
By providing a mask pulse generating means capable of generating a pulse (feedback pulse) of an arbitrary width from the count result, a video signal having a horizontal synchronizing signal in which an equivalent pulse or a cutting pulse is inserted in a vertical retrace period, Even for signals of the video system in which the horizontal sync signal is lost during the vertical retrace period, special masking by setting the equivalent pulse mask, stopping the phase comparison during the vertical sync period, and setting the mask period at the vertical rate can be performed. It is possible to provide a video display device including a PLL circuit that can supply a stable clock without having sequence control.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a video display device according to the present invention.

FIG. 2 is a diagram showing a composite synchronization signal corresponding to the video display device.

FIG. 3 is an input / output signal waveform diagram of a phase comparator 13 in the video display device.

FIG. 4 is a block diagram of an equivalent pulse mask circuit 19 in the image display device.

FIG. 5 is a diagram showing a phase comparator output waveform when the PLL operation is unstable.

FIG. 6 is an operation waveform diagram of an equivalent pulse mask circuit 19 in the video display device.

FIG. 7 is a block diagram showing an example of a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Composite synchronizing signal input terminal 12 Synchronization separation circuit 13 Phase comparator 14 LPF 15 VCO 16 First counter 17 PLL circuit 18 Mask pulse generation circuit 19 Equivalent pulse mask circuit 20 System clock output terminal 21 Various pulse output terminals 22 Mask circuit control Signal input terminal 23 Phase comparison control signal input terminal 24 First AND gate 25 Various pulse generation circuits 26 Mask pulse width setting signal input terminal 27 Mask period setting signal input terminal 28 Second counter 29 Mask period setting pulse generation circuit 30 Two AND gates 41 AND gate 42 NAND gate 101 Phase comparator 102 LPF 103 VCO 104 Counter 105 Decoder circuit 106 Selector 107 Vertical sync separation circuit 108 Mask circuit 109 Mask pulse decoder

Claims (2)

[Claims] 1. A multi-scan compatible video display device that supports video signals of various types, a synchronization separating unit that separates a horizontal sync signal and a vertical sync signal superimposed on the video signal, and a superimposed signal that is superimposed on the horizontal sync signal. A means for masking an equivalent pulse or a notch, and a phase of a horizontal synchronization signal output from the synchronization separation means and a feedback pulse output from a first counter described later are compared, and the phase difference is output as a voltage value. Means, means for stopping the function of the phase comparison, means for selecting whether to stop the phase comparison with the separated vertical synchronization signal or arbitrarily, and smoothing the phase difference converted into a voltage value. A voltage-controlled oscillator whose oscillation frequency changes according to the voltage value; first counting means for counting the oscillation output of the voltage-controlled oscillator; A second counter for measuring the number of horizontal synchronizing signals of the input signal which is reset in the vertical cycle of the input signal and a mask pulse generating means capable of generating a pulse of an arbitrary width from the result of And a second AND gate for ANDing the pulse output from the mask period setting pulse generation circuit and the output pulse of the mask pulse generation circuit. Video display device. 2. A PLL circuit (phase-locked loop circuit) for generating a digital signal processing clock in a multi-scan compatible video display device corresponding to various types of video signals, the horizontal circuit being input at an irregular frequency. The function to stop the phase comparison during the irregular period, the function to mask the irregular pulse, and the function to set the mask period without the need for special sequence control for the synchronization signal enables the equivalent pulse and the cut pulse. A video circuit having a PLL circuit capable of supplying a stable clock to a video system signal having a horizontal synchronization signal into which a horizontal synchronization signal is inserted or a video system signal having no horizontal synchronization signal during a vertical blanking period. Display device.