JP2009111333A5 - - Google Patents

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Publication number
JP2009111333A5
JP2009111333A5 JP2008133712A JP2008133712A JP2009111333A5 JP 2009111333 A5 JP2009111333 A5 JP 2009111333A5 JP 2008133712 A JP2008133712 A JP 2008133712A JP 2008133712 A JP2008133712 A JP 2008133712A JP 2009111333 A5 JP2009111333 A5 JP 2009111333A5
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JP
Japan
Prior art keywords
signal wiring
semiconductor device
wiring
dummy
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008133712A
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Japanese (ja)
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JP2009111333A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2008133712A priority Critical patent/JP2009111333A/en
Priority claimed from JP2008133712A external-priority patent/JP2009111333A/en
Priority to US12/207,790 priority patent/US8084859B2/en
Publication of JP2009111333A publication Critical patent/JP2009111333A/en
Publication of JP2009111333A5 publication Critical patent/JP2009111333A5/ja
Pending legal-status Critical Current

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Claims (11)

半導体基板と、
前記半導体基板上に形成された絶縁膜と、
前記絶縁膜中に形成された信号配線及びダミー配線と、
前記絶縁膜上に形成された複数の外部端子とを備え、
前記半導体基板平面と平行な平面で、隣接する前記外部端子の中心を結ぶ線上と前記半導体基板の端部との間の領域を信号配線禁止領域と想定し、
前記信号配線及び前記ダミー配線は前記信号配線禁止領域に配置されることを特徴とする半導体装置。
A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
Signal wiring and dummy wiring formed in the insulating film;
A plurality of external terminals formed on the insulating film,
Assuming a region between the end of the semiconductor substrate on the line connecting the centers of the adjacent external terminals in a plane parallel to the semiconductor substrate plane as a signal wiring prohibited region,
The semiconductor device according to claim 1, wherein the signal wiring and the dummy wiring are arranged in the signal wiring prohibited area .
前記信号配線及び前記ダミー配線は前記信号配線禁止領域において、
前記半導体基板の端部から前記半導体基板平面と平行な平面で前記外部端子の中心に垂線を引き、前記垂線を中心に前記外部端子の中心から140°の扇角を持った範囲と、前記外部端子の中心を中心に前記外部端子端までの最短の長さの5分の4を半径とした円弧と前記外部端子の中心を中心に前記外部端子端までの最長の長さの5分の6を半径とした円弧とで囲まれた範囲とが重なる領域に形成されることを特徴とする請求項1に記載の半導体装置。
The signal wiring and the dummy wiring are in the signal wiring prohibited area,
A perpendicular line is drawn from the end of the semiconductor substrate to the center of the external terminal in a plane parallel to the semiconductor substrate plane, and a range having a fan angle of 140 ° from the center of the external terminal around the perpendicular, and the external It said about the center of the terminal external terminal to end the shortest of the longest length 5 minutes 4 the radius of the the arc up to the external terminal ends around the center of the external terminals of the length of 5 minutes 6 The semiconductor device according to claim 1, wherein the semiconductor device is formed in a region overlapping with a range surrounded by an arc having a radius of.
前記ダミー配線が、前記信号配線と2μm以上の隙間を開け、前記信号配線の周囲を連続的に囲っている事を特徴とする請求項1または請求項2のいずれか1項に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the dummy wiring opens a gap of 2 μm or more from the signal wiring and continuously surrounds the periphery of the signal wiring. 4. . 前記ダミー配線が、前記信号配線の幅寸法以上の隙間を開け、前記信号配線に平行して1または複数本配置される事を特徴とする請求項1または請求項2のいずれか1項に記載の半導体装置。 3. The one or more dummy wirings according to claim 1, wherein one or a plurality of the dummy wirings are arranged in parallel with the signal wiring with a gap larger than the width of the signal wiring. semiconductor device. 前記ダミー配線が、前記信号配線と2μm以上の隙間を開け、前記信号配線に平行して1または複数本配置される事を特徴とする請求項1または請求項2のいずれか1項に記載の半導体装置。 3. The dummy wiring according to claim 1, wherein one or a plurality of the dummy wirings are arranged in parallel to the signal wiring with a gap of 2 μm or more between the dummy wirings . 4. Semiconductor device. 前記信号配線の線幅を前記信号配線の厚みの5倍以上の幅にすることを特徴とする請求項1から請求項5のいずれか1項に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein a line width of the signal wiring is set to be not less than five times a thickness of the signal wiring . 前記信号配線の線幅を10μm以上にすることを特徴とする請求項1から請求項5のいずれか1項に記載の半導体装置。 The semiconductor device according to claim 1, wherein a line width of the signal wiring is 10 μm or more . 前記外部端子は円形形状のバンプであることを特徴とする請求項1から請求項7のいずれか1項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the external terminal is a bump having a circular shape . 前記バンプの下層にポストを備えることを特徴とする請求項8に記載の半導体装置。 The semiconductor device according to claim 8 , further comprising a post under the bump . 前記バンプの下層にアンダーバンプメタル膜を備えることを特徴とする請求項8に記載の半導体装置。 The semiconductor device according to claim 8, further comprising an under bump metal film under the bump . 前記信号配線およびダミー配線は、Alを含んだ材料であり、厚さは1.5μm以上であることを特徴とする請求項1から請求項10のいずれか1項に記載の半導体装置。 11. The semiconductor device according to claim 1, wherein the signal wiring and the dummy wiring are made of a material containing Al and have a thickness of 1.5 μm or more .
JP2008133712A 2007-10-12 2008-05-22 Semiconductor device Pending JP2009111333A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008133712A JP2009111333A (en) 2007-10-12 2008-05-22 Semiconductor device
US12/207,790 US8084859B2 (en) 2007-10-12 2008-09-10 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007265973 2007-10-12
JP2008133712A JP2009111333A (en) 2007-10-12 2008-05-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2009111333A JP2009111333A (en) 2009-05-21
JP2009111333A5 true JP2009111333A5 (en) 2011-06-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008133712A Pending JP2009111333A (en) 2007-10-12 2008-05-22 Semiconductor device

Country Status (1)

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JP (1) JP2009111333A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227926B2 (en) 2009-10-23 2012-07-24 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US8299632B2 (en) 2009-10-23 2012-10-30 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US10141202B2 (en) * 2013-05-20 2018-11-27 Qualcomm Incorporated Semiconductor device comprising mold for top side and sidewall protection

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0727966B2 (en) * 1986-07-04 1995-03-29 日立化成工業株式会社 Semiconductor device
JP2919488B2 (en) * 1989-07-05 1999-07-12 株式会社日立製作所 Semiconductor integrated circuit device
JP3173045B2 (en) * 1991-07-09 2001-06-04 ヤマハ株式会社 Semiconductor device
JP2988075B2 (en) * 1991-10-19 1999-12-06 日本電気株式会社 Semiconductor device
JP2003068734A (en) * 2001-08-23 2003-03-07 Seiko Epson Corp Semiconductor device and method of manufacturing the same
JP3961335B2 (en) * 2002-04-19 2007-08-22 シャープ株式会社 Semiconductor integrated circuit device
JP2004273591A (en) * 2003-03-06 2004-09-30 Seiko Epson Corp Semiconductor device and its fabricating process
JP2005050963A (en) * 2003-07-31 2005-02-24 Seiko Epson Corp Semiconductor device, electronic device, electronic apparatus and manufacturing method of semiconductor device
JP4072523B2 (en) * 2004-07-15 2008-04-09 日本電気株式会社 Semiconductor device
JP2006066505A (en) * 2004-08-25 2006-03-09 Fujikura Ltd Semiconductor device and electronic device equipped with it

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