JP2009111333A5 - - Google Patents
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- Publication number
- JP2009111333A5 JP2009111333A5 JP2008133712A JP2008133712A JP2009111333A5 JP 2009111333 A5 JP2009111333 A5 JP 2009111333A5 JP 2008133712 A JP2008133712 A JP 2008133712A JP 2008133712 A JP2008133712 A JP 2008133712A JP 2009111333 A5 JP2009111333 A5 JP 2009111333A5
- Authority
- JP
- Japan
- Prior art keywords
- signal wiring
- semiconductor device
- wiring
- dummy
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Claims (11)
前記半導体基板上に形成された絶縁膜と、
前記絶縁膜中に形成された信号配線及びダミー配線と、
前記絶縁膜上に形成された複数の外部端子とを備え、
前記半導体基板平面と平行な平面で、隣接する前記外部端子の中心を結ぶ線上と前記半導体基板の端部との間の領域を信号配線禁止領域と想定し、
前記信号配線及び前記ダミー配線は前記信号配線禁止領域に配置されることを特徴とする半導体装置。 A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
Signal wiring and dummy wiring formed in the insulating film;
A plurality of external terminals formed on the insulating film,
Assuming a region between the end of the semiconductor substrate on the line connecting the centers of the adjacent external terminals in a plane parallel to the semiconductor substrate plane as a signal wiring prohibited region,
The semiconductor device according to claim 1, wherein the signal wiring and the dummy wiring are arranged in the signal wiring prohibited area .
前記半導体基板の端部から前記半導体基板平面と平行な平面で前記外部端子の中心に垂線を引き、前記垂線を中心に前記外部端子の中心から140°の扇角を持った範囲と、前記外部端子の中心を中心に前記外部端子端までの最短の長さの5分の4を半径とした円弧と前記外部端子の中心を中心に前記外部端子端までの最長の長さの5分の6を半径とした円弧とで囲まれた範囲とが重なる領域に形成されることを特徴とする請求項1に記載の半導体装置。 The signal wiring and the dummy wiring are in the signal wiring prohibited area,
A perpendicular line is drawn from the end of the semiconductor substrate to the center of the external terminal in a plane parallel to the semiconductor substrate plane, and a range having a fan angle of 140 ° from the center of the external terminal around the perpendicular, and the external It said about the center of the terminal external terminal to end the shortest of the longest length 5 minutes 4 the radius of the the arc up to the external terminal ends around the center of the external terminals of the length of 5 minutes 6 The semiconductor device according to claim 1, wherein the semiconductor device is formed in a region overlapping with a range surrounded by an arc having a radius of.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008133712A JP2009111333A (en) | 2007-10-12 | 2008-05-22 | Semiconductor device |
US12/207,790 US8084859B2 (en) | 2007-10-12 | 2008-09-10 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007265973 | 2007-10-12 | ||
JP2008133712A JP2009111333A (en) | 2007-10-12 | 2008-05-22 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009111333A JP2009111333A (en) | 2009-05-21 |
JP2009111333A5 true JP2009111333A5 (en) | 2011-06-23 |
Family
ID=40779469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008133712A Pending JP2009111333A (en) | 2007-10-12 | 2008-05-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2009111333A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8227926B2 (en) | 2009-10-23 | 2012-07-24 | Ati Technologies Ulc | Routing layer for mitigating stress in a semiconductor die |
US8299632B2 (en) | 2009-10-23 | 2012-10-30 | Ati Technologies Ulc | Routing layer for mitigating stress in a semiconductor die |
US10141202B2 (en) * | 2013-05-20 | 2018-11-27 | Qualcomm Incorporated | Semiconductor device comprising mold for top side and sidewall protection |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0727966B2 (en) * | 1986-07-04 | 1995-03-29 | 日立化成工業株式会社 | Semiconductor device |
JP2919488B2 (en) * | 1989-07-05 | 1999-07-12 | 株式会社日立製作所 | Semiconductor integrated circuit device |
JP3173045B2 (en) * | 1991-07-09 | 2001-06-04 | ヤマハ株式会社 | Semiconductor device |
JP2988075B2 (en) * | 1991-10-19 | 1999-12-06 | 日本電気株式会社 | Semiconductor device |
JP2003068734A (en) * | 2001-08-23 | 2003-03-07 | Seiko Epson Corp | Semiconductor device and method of manufacturing the same |
JP3961335B2 (en) * | 2002-04-19 | 2007-08-22 | シャープ株式会社 | Semiconductor integrated circuit device |
JP2004273591A (en) * | 2003-03-06 | 2004-09-30 | Seiko Epson Corp | Semiconductor device and its fabricating process |
JP2005050963A (en) * | 2003-07-31 | 2005-02-24 | Seiko Epson Corp | Semiconductor device, electronic device, electronic apparatus and manufacturing method of semiconductor device |
JP4072523B2 (en) * | 2004-07-15 | 2008-04-09 | 日本電気株式会社 | Semiconductor device |
JP2006066505A (en) * | 2004-08-25 | 2006-03-09 | Fujikura Ltd | Semiconductor device and electronic device equipped with it |
-
2008
- 2008-05-22 JP JP2008133712A patent/JP2009111333A/en active Pending
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