JP2009076499A - Substrate having lead, semiconductor package, and method of manufacturing substrate having lead - Google Patents

Substrate having lead, semiconductor package, and method of manufacturing substrate having lead Download PDF

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JP2009076499A
JP2009076499A JP2007241510A JP2007241510A JP2009076499A JP 2009076499 A JP2009076499 A JP 2009076499A JP 2007241510 A JP2007241510 A JP 2007241510A JP 2007241510 A JP2007241510 A JP 2007241510A JP 2009076499 A JP2009076499 A JP 2009076499A
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metallized
substrate
lead
gap
metallized portion
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Bunro Yamamoto
文朗 山本
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Toshiba Corp
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Toshiba Corp
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<P>PROBLEM TO BE SOLVED: To provide a substrate having a lead, a semiconductor package and a method of manufacturing the substrate having a lead, capable of improving junction strength of the lead while maintaining electric characteristics in a wide band. <P>SOLUTION: The substrate having a lead has: a base substrate 11 on which a rear metallizing section 26 is formed; and the lead 30 that has a junction section 31 joined to the rear metallizing section 26 and an extension section 32 extended from the junction section 31 to separate from the rear metallizing section 26, has a step section 34 as a space formation section for forming a gap between the junction section 31 and the rear metallizing section 26, and is joined to the rear metallizing section 26 by silver solder 20 as a jointing material arranged in the gap. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は例えば高周波半導体パッケージに用いられるリード付基板、半導体パッケージ、及びリード付基板の製造方法に関し、特に、リードの接合強度を向上するものに関する。   The present invention relates to a substrate with a lead used in, for example, a high-frequency semiconductor package, a semiconductor package, and a method for manufacturing the substrate with a lead, and particularly relates to a method for improving the bonding strength of a lead.

高周波半導体パッケージの伝送線路方式として、マイクロストリップ線路が知られている。この伝送線路方式において、金属箔のリードが用いられるものがある(例えば、特許文献1参照)。例えば、図10及び図11に示すように、金属のリードはセラミック材からなる基板の表面に形成されたメタライズ部に銀ロウ付けにより接合される。高周波半導体パッケージを薄型化するにはセラミック板厚を薄く構成することが求められるが、所望のインピーダンスを得るにあたり、表面のメタライズ幅は基板の厚さに応じて決定されるので、基板を薄型にすると、表面のメタライズ部の幅Wやリードの幅を狭く設定することになる。このため、銀ロウとリードとの接合部位の面積が小さくなり、所望の接合強度を維持するのが困難となる。したがって、図11に示すように上方への引張力Fが発生した際等に、リードが接合部位の端部側から剥離するなどの不都が生じる場合がある。   A microstrip line is known as a transmission line system for a high-frequency semiconductor package. Some of these transmission line systems use metal foil leads (see, for example, Patent Document 1). For example, as shown in FIGS. 10 and 11, a metal lead is joined to a metallized portion formed on the surface of a ceramic substrate by silver brazing. In order to reduce the thickness of a high-frequency semiconductor package, it is necessary to make the ceramic plate thin. However, in order to obtain a desired impedance, the metallization width of the surface is determined according to the thickness of the substrate. Then, the width W of the metallized portion on the surface and the width of the lead are set narrow. For this reason, the area of the joint portion between the silver solder and the lead is reduced, and it becomes difficult to maintain a desired joint strength. Therefore, when the upward tensile force F is generated as shown in FIG. 11, there may be a disadvantage that the lead is peeled off from the end portion side of the joining portion.

これに鑑みて、図12及び図13に示すように、セラミックの基板を多層構造に構成し、表面メタライズ部が形成されるセラミック板に切欠きを設け、この切欠きの側面にメタライズ部を形成し、切欠き部分に銀ロウを溜め、接合部位の端部にメニスカスを形成することで、接合強度を向上させる技術が提供されている。
特開2003−51575号公報
In view of this, as shown in FIGS. 12 and 13, the ceramic substrate is formed in a multilayer structure, a notch is provided in the ceramic plate on which the surface metallized part is formed, and the metallized part is formed on the side surface of the notch. However, a technique for improving the bonding strength is provided by storing silver brazing in the notch and forming a meniscus at the end of the bonding site.
JP 2003-51575 A

しかしながら、上記の技術では、次のような問題があった。すなわち、上記の構造では、側面のメタライズ部が表面のメタライズ部に導通して連続形成されることとなるため、電気的には、表面のメタライズ部にスタブが延出形成された場合と同様の影響が生じ、電気的特性が劣化する。特に高周波帯域においては、この影響が顕著となる。   However, the above technique has the following problems. In other words, in the above structure, the metallized portion on the side surface is electrically connected to the metallized portion on the surface and is continuously formed. Therefore, electrically, the same as when the stub is extended and formed on the metallized portion on the surface. An effect occurs, and electrical characteristics deteriorate. In particular, this effect becomes significant in the high frequency band.

そこで、本発明は、広い帯域における電気的特性を維持しつつリードの接合強度を向上することができるリード付基板、半導体パッケージ、及びリード付基板の製造方法を提供することを目的とする。   Accordingly, an object of the present invention is to provide a leaded substrate, a semiconductor package, and a method for manufacturing the leaded substrate that can improve the bonding strength of the leads while maintaining the electrical characteristics in a wide band.

本発明の一形態にかかるリード付基板は、所定領域がメタライズされたメタライズ部を有する基板と、前記メタライズ部に接合される接合部と前記接合部から延出し前記メタライズ部と離間する延出部とを備えるとともに、前記接合部に前記メタライズ部との間に隙間を形成する隙間形成部を有し、前記隙間に配置された接合材により前記メタライズ部に接合されるリードと、を備えたことを特徴とする。   A substrate with leads according to an aspect of the present invention includes a substrate having a metallized portion in which a predetermined region is metallized, a bonded portion bonded to the metalized portion, an extended portion extending from the bonded portion and spaced apart from the metalized portion. And a lead that is joined to the metallized portion by a joining material disposed in the gap, the gap forming portion forming a gap between the jointed portion and the metallized portion. It is characterized by.

本発明の一形態にかかるリード付基板は、前記隙間形成部は、前記基板の主面方向と交差する方向に延びる段差面を有し、前記段差面は前記メタライズ部の端縁よりも内側に配置され、前記リードが前記メタライズ部に接合された接合状態において、前記接合材により前記メタライズ部の端縁と前記段差面との間にメニスカスが形成されることを特徴とする。   In the leaded substrate according to one aspect of the present invention, the gap forming portion has a step surface extending in a direction intersecting with a main surface direction of the substrate, and the step surface is located inside an edge of the metallized portion. A meniscus is formed between the edge of the metallized portion and the step surface by the bonding material in a bonded state in which the leads are bonded to the metallized portion.

本発明の一形態にかかるリード付基板は、前記リードは、前記隙間形成部を挟んで一方側の厚みが、他方側の厚みよりも大きく構成されたことを特徴とする。   The substrate with leads according to an aspect of the present invention is characterized in that the leads are configured such that the thickness on one side is larger than the thickness on the other side across the gap forming portion.

本発明の一形態にかかるリード付基板は、前記リードの前記メタライズ部に接合される面に前記隙間形成部としての切欠部が形成されたことを特徴とする
本発明の一形態にかかる半導体パッケージは、一方の主面上にメタライズされた第1メタライズ部が形成された基板と、前記基板の一方の主面に接合された枠状のフレームと、前記フレームの内側において、前記基板の一方の主面上に配置された半導体装置と、前記フレーム上に接合され、前記フレームの内側に形成される中空部を気密封止する蓋部材と、前記基板の他方の主面上において、前記基板を貫くビアホールを介して前記第1メタライズ部に接続されてメタライズされた第2メタライズ部と、前記基板の他方の主面に接合された金属板と、を備え、前記第2メタライズ部に接合される接合部と前記第2メタライズ部から離間して前記接合部から延出する延出部とを備えるとともに、前記接合部に前記第2メタライズ部との間に隙間を形成する隙間形成部を有し、前記隙間に配置された接合材により前記第2メタライズ部に接合されるリードと、を備えたことを特徴とする。
A substrate with leads according to an embodiment of the present invention is characterized in that a notch portion as the gap forming portion is formed on a surface of the lead to be joined to the metallized portion. Includes a substrate on which a first metallized portion metallized on one main surface is formed, a frame-like frame bonded to one main surface of the substrate, and one of the substrates on the inner side of the frame. A semiconductor device disposed on a main surface; a lid member that is bonded onto the frame and hermetically seals a hollow portion formed inside the frame; and A second metallized portion metallized by being connected to the first metallized portion through a via hole penetrating; and a metal plate joined to the other main surface of the substrate; and joined to the second metallized portion And a gap forming portion that forms a gap between the joint portion and the second metallized portion, and an extension portion that is spaced apart from the second metallized portion and extends from the joint portion. And a lead joined to the second metallized portion by a joining material disposed in the gap.

本発明の一形態にかかるリード付基板の製造方法は、基板の所定領域がメタライズされたメタライズ部に、接合材を配置する工程と、前記メタライズ部に接合される接合部と前記メタライズ部から離間して延出する延出部とを備えるとともに前記接合部に前記メタライズ部との間に隙間を形成する隙間形成部を有するリードを、前記隙間形成部が前記メタライズ部の端縁よりも内側に位置するように、前記接合材上に配置する工程と、前記接合材を、前記隙間に配置された状態で、熱処理により前記接合材を溶融及び固化させ、前記リードと前記メタライズ部とを接合する工程と、を備えたことを特徴とする。   According to one embodiment of the present invention, there is provided a method of manufacturing a substrate with leads, the step of disposing a bonding material in a metallized portion where a predetermined region of the substrate is metallized, and a distance between the bonded portion bonded to the metallized portion and the metallized portion. And a lead having a gap forming portion that forms a gap between the joint portion and the metallized portion, and the gap forming portion is located inside the edge of the metalized portion. A step of disposing the bonding material on the bonding material, and the bonding material being melted and solidified by heat treatment in a state where the bonding material is disposed in the gap, thereby bonding the lead and the metallized portion. And a process.

本発明によれば、広い帯域における電気的特性を維持しつつリードの接合強度を向上することができる。   According to the present invention, the bonding strength of a lead can be improved while maintaining electrical characteristics in a wide band.

以下に本発明の第1実施形態にかかるリード付基板、半導体パッケージ、及びリード付基板の製造方法について、図1乃至図7を参照して説明する。なお、各図において適宜構成を拡大・縮小・省略して概略的に示している。図中矢印X、Y、及びZはそれぞれ直交する3方向を示している。矢印Zは上下方向に沿い、表面側(他方の主面側)を指す。   A method of manufacturing a substrate with leads, a semiconductor package, and a substrate with leads according to the first embodiment of the present invention will be described below with reference to FIGS. In each figure, the configuration is schematically shown by appropriately enlarging, reducing, or omitting it. In the figure, arrows X, Y, and Z indicate three orthogonal directions. An arrow Z points along the vertical direction and points to the surface side (the other main surface side).

図1乃至図4に示すように、高周波半導体パッケージ1は、ベース基板11と、ベース基板11の表面(他方側の主面)側に接合されたフレーム13と、フレーム13の内側に配置された半導体装置14と、フレーム13の上にはんだで接合され、フレーム13の内側部分の中空部15を減圧状態で気密封止する蓋部材16(図3及び図4にのみ図示)と、ベース基板11の裏面(一方側の主面)側に接合された金属板17とを備えて構成されている。高周波半導体パッケージ1の伝送方式はマイクロストリップラインである。   As shown in FIG. 1 to FIG. 4, the high-frequency semiconductor package 1 is disposed inside a base substrate 11, a frame 13 bonded to the surface (the main surface on the other side) of the base substrate 11, and the frame 13. A semiconductor device 14, a lid member 16 (shown only in FIGS. 3 and 4) that is joined to the frame 13 with solder and hermetically seals the hollow portion 15 in the inner portion of the frame 13 in a reduced pressure state, and the base substrate 11 And a metal plate 17 joined to the back surface (one main surface) side. The transmission system of the high-frequency semiconductor package 1 is a microstrip line.

ベース基板11は、例えばアルミナ(AL)からなり、厚さt1が例えば0.2mm〜0.3mm程度の矩形状に構成されている。 The base substrate 11 is made of alumina (AL 2 O 3 ), for example, and has a rectangular shape with a thickness t1 of about 0.2 mm to 0.3 mm, for example.

ベース基板11の表面の周縁近傍には金属材からなるフレーム13が銀ロウ20で接合されている。ベース基板11の表面であってフレーム13の内側には半導体装置14が実装されている。   A frame 13 made of a metal material is joined with a silver solder 20 near the periphery of the surface of the base substrate 11. A semiconductor device 14 is mounted on the surface of the base substrate 11 and inside the frame 13.

ベース基板11の表面21には、例えばW焼結体からなり、半導体装置14に接続される所定の配線パターンを構成する表面メタライズ部22が形成されている。表面メタライズ部22の線幅W1は、特性インピーダンスやベース基板11の誘電率などに応じて決定され、例えばここでは0.3mm程度に構成されている。ベース基板11の周縁近傍における表面メタライズ部22の端部位置には、ベース基板11をその表裏に渡って貫通するビアホール23が形成されている。   On the surface 21 of the base substrate 11, a surface metallized portion 22 made of, for example, a W sintered body and constituting a predetermined wiring pattern connected to the semiconductor device 14 is formed. The line width W1 of the surface metallized portion 22 is determined according to the characteristic impedance, the dielectric constant of the base substrate 11, and the like, and is configured to be, for example, about 0.3 mm here. A via hole 23 penetrating the base substrate 11 across its front and back is formed at the end position of the surface metallized portion 22 in the vicinity of the periphery of the base substrate 11.

ベース基板11の裏面側は金属板17に覆われている。金属板17は、例えばCuW、CuMo、FeNiCo等からなり、その厚さt2は例えば0.2mm〜0.25mm程度に構成され、ベース基板11の裏面に例えばAgCu共晶からなる銀ロウ20により接合されている。金属板17の周縁は、ベース基板11のビアホール23付近に対応する所定箇所に複数の切欠部25を有する矩形状に構成されている。したがって、ベース基板11のうち、切欠部25に対応する周縁部分は露出している。   The back side of the base substrate 11 is covered with a metal plate 17. The metal plate 17 is made of, for example, CuW, CuMo, FeNiCo, or the like, and has a thickness t2 of, for example, about 0.2 mm to 0.25 mm. The metal plate 17 is joined to the back surface of the base substrate 11 by, for example, silver solder 20 made of AgCu eutectic. Has been. The peripheral edge of the metal plate 17 is configured in a rectangular shape having a plurality of notches 25 at predetermined locations corresponding to the vicinity of the via holes 23 of the base substrate 11. Therefore, the peripheral edge portion of the base substrate 11 corresponding to the notch 25 is exposed.

ベース基板11の裏面の露出部分には、ビアホール23の裏面側の端部からベース基板の端縁に至る所定の配線パターンを構成する裏面メタライズ部26が形成されている。裏面メタライズ部26は、表面メタライズ部22と同様に、W焼結体からなるとともにその線幅W1が0.3mm程度に構成されている。裏面メタライズ部26の先端部分近傍にリード30が銀ロウ20により接合されている。   On the exposed portion of the back surface of the base substrate 11, a back surface metallized portion 26 that forms a predetermined wiring pattern from the end portion on the back surface side of the via hole 23 to the edge of the base substrate is formed. Similar to the front surface metallized portion 22, the back surface metallized portion 26 is made of a W sintered body and has a line width W1 of about 0.3 mm. Leads 30 are joined by silver solder 20 near the tip of the back metallized portion 26.

次に、リード30の接合構造について、図5乃至図7を参照して説明する。なお、図5乃至図7においては裏面が上方に位置し、表面が下方に位置するように示す。   Next, the bonding structure of the lead 30 will be described with reference to FIGS. In FIGS. 5 to 7, the rear surface is located on the upper side and the front surface is located on the lower side.

リード30は、裏面メタライズ部26に接合される接合部31と裏面メタライズ部26から離間して延出する延出部32とを備えるとともに、接合部31の端部に段差部34を有している。   The lead 30 includes a bonding portion 31 bonded to the back surface metallized portion 26 and an extending portion 32 extending away from the back surface metallized portion 26, and has a stepped portion 34 at the end of the bonding portion 31. Yes.

リード30は、例えばFeNiCo合金からなる断面正方形の棒状部材の長手方向における一端側がハーフエッチングで除去されることにより、厚みの大きい厚部35と、厚みの小さい薄部36とを、隙間形成部としての段差部34を介して一体に有する細長部材からなる。細長部材の線幅W2は0.2mm程度であり、厚部35、段差部34及び薄部36において一様である。この細長部材の段差部34及び薄部36が図6及び図7に示すように湾曲されてリード30が形成されている。段差部34のコーナー部分は滑らかな曲面38を構成している。   The lead 30 is formed, for example, by removing one end in the longitudinal direction of a rod-shaped member having a square cross section made of FeNiCo alloy by half etching, so that the thick portion 35 having a large thickness and the thin portion 36 having a small thickness serve as a gap forming portion. It consists of an elongate member which has integrally through the level | step difference part 34 of this. The line width W2 of the elongated member is about 0.2 mm, and is uniform in the thick portion 35, the step portion 34, and the thin portion 36. The step portion 34 and the thin portion 36 of the elongated member are curved as shown in FIGS. 6 and 7 to form the lead 30. The corner portion of the step portion 34 constitutes a smooth curved surface 38.

厚部35の厚さt3は0.2mm程度に構成されている。厚部35はX方向に延びるとともにその表面側が、銀ロウ20により裏面メタライズ部26に接合されている。   The thickness t3 of the thick portion 35 is configured to be about 0.2 mm. The thick portion 35 extends in the X direction, and the front surface side is joined to the back metallized portion 26 by the silver solder 20.

薄部36の厚さt4はt3の1/2の0.1mm程度に構成されている。段差部34により、薄部36は、Z方向において裏面メタライズ部26から所定距離d1だけ離間している。薄部36の、段差部34近傍の端部、すなわち基端部側は、銀ロウ20により、裏面メタライズ部26に接合され、接合部31を構成する。   The thickness t4 of the thin portion 36 is configured to be about 0.1 mm which is 1/2 of t3. Due to the stepped portion 34, the thin portion 36 is separated from the back surface metallized portion 26 by a predetermined distance d1 in the Z direction. An end portion of the thin portion 36 in the vicinity of the stepped portion 34, that is, a base end portion side is joined to the back metallized portion 26 by the silver brazing 20 to constitute a joined portion 31.

薄部36の先端側は、湾曲され、裏面メタライズ部26から裏面側に離間して、X方向またはY方向を含む面方向に延び、延出部32を構成している。この延出部32の先端が実装基板(不図示)に接続されることにより高周波半導体パッケージ1が実装される。   The distal end side of the thin portion 36 is curved, is spaced apart from the back surface metallized portion 26 toward the back surface side, extends in the surface direction including the X direction or the Y direction, and constitutes an extending portion 32. The tip of the extending portion 32 is connected to a mounting substrate (not shown), whereby the high frequency semiconductor package 1 is mounted.

リード30は、段差部34に形成されるZ方向に延びる段差面34aの端縁が、Y方向においてベース基板11の端縁11a及び裏面メタライズ部26の端縁26aからd2で示す所定距離、内側に位置するように配置されている。d2は、例えば0.2mm程度である。   The lead 30 has an end edge of a step surface 34a formed in the step portion 34 extending in the Z direction at a predetermined distance indicated by d2 from the end edge 11a of the base substrate 11 and the end edge 26a of the back surface metallization portion 26 in the Y direction. It is arranged to be located in. For example, d2 is about 0.2 mm.

したがって、リード30は、Z方向において裏面メタライズ部と離間しつつX方向及びY方向を含む面方向において裏面メタライズ部26を覆うオーバーラップ部42を有するとともに、リード30と裏面メタライズ部26及びベース基板11との間にはZ方向にd1、面方向d2の寸法を有する隙間43が形成される。   Accordingly, the lead 30 has an overlap portion 42 that covers the back surface metallized portion 26 in a plane direction including the X direction and the Y direction while being separated from the back surface metallized portion in the Z direction, and the lead 30, the back surface metalized portion 26, and the base substrate. 11 is formed with a gap 43 having dimensions of d1 in the Z direction and d2 in the surface direction.

本実施形態におけるリード30と裏面メタライズ部26との接合工程では、まず、印刷法などにより裏面メタライズ部26上に銀ロウ20が配置され、さらにこの銀ロウ20の上にリード30の接合部31が配置される。このとき、段差面34aの表面側の端縁、すなわち図中下端部分が、裏面メタライズ部26の端縁26aよりも所定距離d1内側に配置される。この状態で、加熱、冷却等の熱処理により、銀ロウ20が溶融及び固化し、銀ロウ20によりリード30と裏面メタライズ部26とが接合される。このとき、銀ロウ20の一部が隙間43に溜まり、裏面メタライズ部26の端縁26aとリード30の段差部34のコーナー部分の表面側、すなわち段差面34aの裏面側部分、との間にメニスカス45が形成される。   In the bonding process between the lead 30 and the back surface metallized portion 26 in the present embodiment, first, the silver solder 20 is disposed on the back surface metallized portion 26 by a printing method or the like, and the joint portion 31 of the lead 30 is further disposed on the silver solder 20. Is placed. At this time, the edge on the front surface side of the step surface 34 a, that is, the lower end portion in the drawing, is disposed inside the predetermined distance d 1 with respect to the edge 26 a of the back surface metallized portion 26. In this state, the silver solder 20 is melted and solidified by heat treatment such as heating and cooling, and the lead 30 and the back metallized portion 26 are joined by the silver solder 20. At this time, a part of the silver solder 20 is accumulated in the gap 43, and between the edge 26a of the back surface metallized portion 26 and the surface side of the corner portion of the step portion 34 of the lead 30, that is, the back surface side portion of the step surface 34a. A meniscus 45 is formed.

本実施形態にかかるリード付基板、半導体パッケージ、及びリード付基板の製造方法は以下に掲げる効果を奏する。すなわち、リード30に段差部34を設けるとともに、裏面メタライズ部26及びベース基板11の端部から所定距離d2だけオフセットさせたため、銀ロウ20が溜まる隙間43が形成され、接合の際に銀ロウ20により大きいメニスカス45が形成されるため、接合強度を向上させることができる。また、リード30側に段差部34を設けたため、裏面メタライズ部26自体の長さを維持し、電気的な影響を回避することができる。リード30側に段差を設ける構成としたため、複数層の基板を用いて基板側に段差を設けると比べて製造容易である。さらに、延出部32全体を薄く構成したので曲げに強く、固いメッキを施した場合にも高い強度を確保できる。   The substrate with leads, the semiconductor package, and the method for manufacturing the substrate with leads according to the present embodiment have the following effects. That is, the step 30 is provided in the lead 30 and is offset by a predetermined distance d2 from the back metallized portion 26 and the end of the base substrate 11, so that a gap 43 in which the silver solder 20 accumulates is formed, and the silver solder 20 is joined at the time of joining. Since a larger meniscus 45 is formed, the bonding strength can be improved. Further, since the step portion 34 is provided on the lead 30 side, the length of the back surface metallized portion 26 itself can be maintained, and an electrical influence can be avoided. Since a step is provided on the lead 30 side, manufacturing is easier than using a multi-layer substrate and providing a step on the substrate side. Further, since the entire extending portion 32 is made thin, it is strong against bending, and high strength can be secured even when hard plating is applied.

なお、本発明は上記実施形態そのままに限定されるものではない。例えば上記実施形態では隙間形成部として段差部34を設け、リードの一端側の延出部32全体を薄く構成したが、図8に示すようにリード30の一部に切欠きを設け、この切欠き部分に裏面メタライズ部26と離間する隙間を構成してもよい。また、上記実施形態では、ハーフエッチングによりリードに段差部34を形成したが、プレス工程等により形成してもよい。また、図9に示すように段差部34のコーナー部分が滑らかな曲面でない場合にも適用可能である。裏面メタライズ部26にリード30が接合される場合について例示したが、これに限られるものではなく、表面メタライズ部22にも適用することが可能である。   In addition, this invention is not limited to the said embodiment as it is. For example, in the above embodiment, the stepped portion 34 is provided as the gap forming portion and the entire extending portion 32 on one end side of the lead is thinly formed. However, as shown in FIG. You may comprise the clearance gap spaced apart from the back surface metallization part 26 in a notch part. Moreover, in the said embodiment, although the level | step-difference part 34 was formed in the lead by half etching, you may form by a press process etc. Further, the present invention is also applicable to the case where the corner portion of the step portion 34 is not a smooth curved surface as shown in FIG. Although the case where the lead 30 is bonded to the back surface metallized portion 26 is illustrated, the present invention is not limited to this, and the present invention can also be applied to the front surface metalized portion 22.

この他、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。   In addition, in the implementation stage, the constituent elements can be modified and embodied without departing from the spirit of the invention. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

本発明の一実施形態にかかる高周波半導体パッケージを示す平面図。The top view which shows the high frequency semiconductor package concerning one Embodiment of this invention. 同高周波半導体パッケージの底面図。The bottom view of the high frequency semiconductor package. 同高周波半導体パッケージの正面図。The front view of the high frequency semiconductor package. 同高周波半導体パッケージの側面図。The side view of the high frequency semiconductor package. 図2のA部分を拡大して示す斜視図。The perspective view which expands and shows the A section of FIG. 図4のB部分を拡大して示す側面図。The side view which expands and shows the B section of FIG. 本発明の一実施形態にかかるリードの構成を示す斜視図。The perspective view which shows the structure of the lead | read | reed concerning one Embodiment of this invention. 他の実施形態にかかる接合部を示す側面図。The side view which shows the junction part concerning other embodiment. 他の実施形態にかかる接合部を示す側面図。The side view which shows the junction part concerning other embodiment. 接合部の一例を示す斜視図。The perspective view which shows an example of a junction part. 接合部の一例を示す側面図。The side view which shows an example of a junction part. 接合部の一例を示す斜視図。The perspective view which shows an example of a junction part. 接合部の一例を示す側面図。The side view which shows an example of a junction part.

符号の説明Explanation of symbols

1…高周波半導体パッケージ、11…ベース基板、11a…端縁、13…フレーム、14…半導体装置、15…中空部、16…蓋部材、17…金属板、20…銀ロウ、21…表面、22…表面メタライズ部部(第1メタライズ部)、23…ビアホール、25…切欠部、26…裏面メタライズ部(第2メタライズ部)、26a…端縁、30…リード、31…接合部、32…延出部、34…段差部、34a…段差面、35…厚部、36…薄部、38…曲面、42…オーバーラップ部、43…隙間、45…メニスカス。   DESCRIPTION OF SYMBOLS 1 ... High frequency semiconductor package, 11 ... Base substrate, 11a ... Edge, 13 ... Frame, 14 ... Semiconductor device, 15 ... Hollow part, 16 ... Lid member, 17 ... Metal plate, 20 ... Silver brazing, 21 ... Surface, 22 ... front surface metallized part (first metallized part), 23 ... via hole, 25 ... notch part, 26 ... back metallized part (second metallized part), 26a ... edge, 30 ... lead, 31 ... joint part, 32 ... extension Protruding part 34 ... Step part 34a ... Step surface 35 ... Thick part 36 ... Thin part 38 ... Curved surface 42 ... Overlap part 43 ... Gap 45 ... Menicus

Claims (6)

所定領域がメタライズされたメタライズ部を有する基板と、
前記メタライズ部に接合される接合部と前記接合部から延出し前記メタライズ部と離間する延出部とを備えるとともに、前記接合部に前記メタライズ部との間に隙間を形成する隙間形成部を有し、前記隙間に配置された接合材により前記メタライズ部に接合されるリードと、を備えたことを特徴とするリード付基板。
A substrate having a metallized portion in which a predetermined region is metallized;
A joining portion joined to the metallized portion and an extending portion extending from the joining portion and spaced apart from the metallized portion; and a gap forming portion for forming a gap between the metallized portion and the joining portion. And a lead bonded to the metallized portion by a bonding material disposed in the gap.
前記隙間形成部は、前記基板の主面方向と交差する方向に延びる段差面を有し、
前記段差面は前記メタライズ部の端縁よりも内側に配置され、
前記リードが前記メタライズ部に接合された接合状態において、前記接合材により前記メタライズ部の端縁と前記段差面との間にメニスカスが形成されることを特徴とする請求項1記載のリード付基板。
The gap forming portion has a step surface extending in a direction intersecting with the main surface direction of the substrate,
The step surface is disposed inside the edge of the metallized portion,
2. The substrate with leads according to claim 1, wherein a meniscus is formed between an edge of the metallized portion and the stepped surface by the bonding material in a bonded state in which the lead is bonded to the metallized portion. .
前記リードは、前記隙間形成部を挟んで一方側の厚みが、他方側の厚みよりも大きく構成されたことを特徴とする請求項1または2に記載のリード付基板。   3. The substrate with leads according to claim 1, wherein the lead is configured such that a thickness on one side is larger than a thickness on the other side across the gap forming portion. 前記リードの前記メタライズ部に接合される面に前記隙間形成部としての切欠部が形成されたことを特徴とする請求項1または2に記載のリード付基板。   The substrate with leads according to claim 1, wherein a notch portion as the gap forming portion is formed on a surface of the lead to be joined to the metallized portion. 一方の主面上にメタライズされた第1メタライズ部が形成された基板と、
前記基板の一方の主面に接合された枠状のフレームと、
前記フレームの内側において、前記基板の一方の主面上に配置された半導体装置と、
前記フレーム上に接合され、前記フレームの内側に形成される中空部を気密封止する蓋部材と、
前記基板の他方の主面上において、前記基板を貫くビアホールを介して前記第1メタライズ部に接続されてメタライズされた第2メタライズ部と、
前記基板の他方の主面に接合された金属板と、
を備え、
前記第2メタライズ部に接合される接合部と前記第2メタライズ部から離間して前記接合部から延出する延出部とを備えるとともに、前記接合部に前記第2メタライズ部との間に隙間を形成する隙間形成部を有し、前記隙間に配置された接合材により前記第2メタライズ部に接合されるリードと、
を備えたことを特徴とする半導体パッケージ。
A substrate on which a first metallized portion metallized on one main surface is formed;
A frame-like frame joined to one main surface of the substrate;
A semiconductor device disposed on one main surface of the substrate inside the frame; and
A lid member that is bonded onto the frame and hermetically seals a hollow portion formed inside the frame;
A second metallized portion metallized on the other main surface of the substrate connected to the first metallized portion via a via hole penetrating the substrate;
A metal plate joined to the other principal surface of the substrate;
With
A bonding portion bonded to the second metallized portion and an extending portion extending from the bonding portion apart from the second metallized portion; and a gap between the bonding portion and the second metallized portion. A lead that is bonded to the second metallized portion by a bonding material disposed in the gap,
A semiconductor package comprising:
基板の所定領域がメタライズされたメタライズ部に、接合材を配置する工程と、
前記メタライズ部に接合される接合部と前記メタライズ部から離間して延出する延出部とを備えるとともに前記接合部に前記メタライズ部との間に隙間を形成する隙間形成部を有するリードを、前記隙間形成部が前記メタライズ部の端縁よりも内側に位置するように、前記接合材上に配置する工程と、
前記接合材を、前記隙間に配置された状態で、熱処理により前記接合材を溶融及び固化させ、前記リードと前記メタライズ部とを接合する工程と、
を備えたことを特徴とするリード付基板の製造方法。
Placing the bonding material on the metallized portion where the predetermined region of the substrate is metallized;
A lead having a gap forming portion for forming a gap between the joint portion and the metallized portion, the joint portion being joined to the metallized portion and an extending portion extending away from the metallized portion. A step of disposing on the bonding material such that the gap forming portion is located inside the edge of the metallized portion;
A step of melting and solidifying the bonding material by heat treatment in a state where the bonding material is disposed in the gap, and bonding the lead and the metallized portion;
A method for manufacturing a substrate with leads, comprising:
JP2007241510A 2007-09-18 2007-09-18 Substrate having lead, semiconductor package, and method of manufacturing substrate having lead Pending JP2009076499A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248777A (en) * 2011-05-31 2012-12-13 Kyocera Corp Package for housing element and semiconductor module including the same
JP2014179432A (en) * 2013-03-14 2014-09-25 Kyocera Corp Package for mounting electronic component and electronic device using the same
JP2015195237A (en) * 2014-03-31 2015-11-05 住友電工デバイス・イノベーション株式会社 Package for mounting electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248777A (en) * 2011-05-31 2012-12-13 Kyocera Corp Package for housing element and semiconductor module including the same
JP2014179432A (en) * 2013-03-14 2014-09-25 Kyocera Corp Package for mounting electronic component and electronic device using the same
JP2015195237A (en) * 2014-03-31 2015-11-05 住友電工デバイス・イノベーション株式会社 Package for mounting electronic component

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