JP2009070356A5 - - Google Patents

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Publication number
JP2009070356A5
JP2009070356A5 JP2007269577A JP2007269577A JP2009070356A5 JP 2009070356 A5 JP2009070356 A5 JP 2009070356A5 JP 2007269577 A JP2007269577 A JP 2007269577A JP 2007269577 A JP2007269577 A JP 2007269577A JP 2009070356 A5 JP2009070356 A5 JP 2009070356A5
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JP
Japan
Prior art keywords
bits
check
check bits
bit
code
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JP2007269577A
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English (en)
Japanese (ja)
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JP4960829B2 (ja
JP2009070356A (ja
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Priority claimed from US11/855,070 external-priority patent/US7962837B2/en
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JP2007269577A 2007-09-13 2007-10-16 エラー訂正方法およびエラー訂正回路 Active JP4960829B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/855,070 US7962837B2 (en) 2007-09-13 2007-09-13 Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix
US11/855,070 2007-09-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012067151A Division JP5485323B2 (ja) 2007-09-13 2012-03-23 エラー訂正回路

Publications (3)

Publication Number Publication Date
JP2009070356A JP2009070356A (ja) 2009-04-02
JP2009070356A5 true JP2009070356A5 (fr) 2011-04-14
JP4960829B2 JP4960829B2 (ja) 2012-06-27

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ID=40455887

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JP2007269577A Active JP4960829B2 (ja) 2007-09-13 2007-10-16 エラー訂正方法およびエラー訂正回路
JP2012067151A Active JP5485323B2 (ja) 2007-09-13 2012-03-23 エラー訂正回路

Family Applications After (1)

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JP2012067151A Active JP5485323B2 (ja) 2007-09-13 2012-03-23 エラー訂正回路

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US (3) US7962837B2 (fr)
JP (2) JP4960829B2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7962837B2 (en) * 2007-09-13 2011-06-14 United Memories, Inc. Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix
US8327223B2 (en) * 2009-02-05 2012-12-04 Infineon Technologies Ag System and method for constructing multi-write error correcting code
KR101772008B1 (ko) * 2011-03-03 2017-09-05 삼성전자주식회사 통신 및 방송시스템에서 송수신 방법 및 장치
US8612842B2 (en) 2011-05-25 2013-12-17 Infineon Technologies Ag Apparatus for generating a checksum
US20130007563A1 (en) * 2011-07-01 2013-01-03 Samsung Electronics Co., Ltd. Semiconductor memory device having error correction function and memory system including the same
US8996950B2 (en) * 2012-02-23 2015-03-31 Sandisk Technologies Inc. Erasure correction using single error detection parity
US9513987B2 (en) 2014-11-07 2016-12-06 International Business Machines Corporation Using error correcting codes for parity purposes
US9787329B2 (en) 2015-10-15 2017-10-10 Apple Inc. Efficient coding with single-error correction and double-error detection capabilities
KR102717146B1 (ko) 2018-11-19 2024-10-15 삼성전자주식회사 반도체 메모리 장치 및 이를 구비하는 메모리 시스템
CN109714132B (zh) * 2019-01-23 2021-04-20 中国电子科技集团公司第二十八研究所 一种用于复杂电磁环境下的多链路抗干扰实时传输方法
KR102266056B1 (ko) * 2019-06-04 2021-06-17 주식회사 한글과컴퓨터 블록체인을 기반으로 문서 정보의 관리를 가능하게 하는 문서 정보 관리 장치 및 그 동작 방법
US11422888B2 (en) * 2020-10-14 2022-08-23 Western Digital Technologies, Inc. Data integrity check for writing data in memory
CN114203250B (zh) * 2021-12-14 2022-06-24 北京得瑞领新科技有限公司 固态存储器的数据存储方法、数据读取方法及固态存储器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623155A (en) * 1969-12-24 1971-11-23 Ibm Optimum apparatus and method for check bit generation and error detection, location and correction
US3825893A (en) * 1973-05-29 1974-07-23 Ibm Modular distributed error detection and correction apparatus and method
US4072853A (en) * 1976-09-29 1978-02-07 Honeywell Information Systems Inc. Apparatus and method for storing parity encoded data from a plurality of input/output sources
US4334309A (en) * 1980-06-30 1982-06-08 International Business Machines Corporation Error correcting code system
US4388684A (en) * 1981-03-27 1983-06-14 Honeywell Information Systems Inc. Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources
JPH0760394B2 (ja) * 1986-12-18 1995-06-28 株式会社日立製作所 誤り訂正・検出方式
JPH04290144A (ja) * 1991-03-19 1992-10-14 Hitachi Ltd メモリ拡張方式
JP3515616B2 (ja) * 1994-09-20 2004-04-05 株式会社トキメック 誤り訂正装置
JP4413091B2 (ja) * 2004-06-29 2010-02-10 株式会社ルネサステクノロジ 半導体装置
DE102005022107B9 (de) * 2005-05-12 2016-04-07 Infineon Technologies Ag Vorrichtung und Verfahren zum Bestimmen einer Position eines Bitfehlers in einer Bitfolge
FR2891419A1 (fr) * 2005-09-23 2007-03-30 St Microelectronics Sa Decodage d'une pluralite de flux d'informations codees selon un algorithme de codage par blocs.
US7853854B2 (en) * 2005-11-15 2010-12-14 Stmicroelectronics Sa Iterative decoding of a frame of data encoded using a block coding algorithm
US7962837B2 (en) * 2007-09-13 2011-06-14 United Memories, Inc. Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix

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