JP2009059814A - Manufacturing method of multilayer printed board - Google Patents

Manufacturing method of multilayer printed board Download PDF

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Publication number
JP2009059814A
JP2009059814A JP2007224596A JP2007224596A JP2009059814A JP 2009059814 A JP2009059814 A JP 2009059814A JP 2007224596 A JP2007224596 A JP 2007224596A JP 2007224596 A JP2007224596 A JP 2007224596A JP 2009059814 A JP2009059814 A JP 2009059814A
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Japan
Prior art keywords
sintered body
circuit pattern
via hole
multilayer printed
sintered
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JP2007224596A
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Japanese (ja)
Inventor
Yoshihiko Shiraishi
芳彦 白石
Koji Kondo
宏司 近藤
Yoshitaro Yazaki
芳太郎 矢崎
Atsusuke Sakaida
敦資 坂井田
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Denso Corp
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Denso Corp
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Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2007224596A priority Critical patent/JP2009059814A/en
Priority to TW097130661A priority patent/TW200930197A/en
Priority to KR1020080081655A priority patent/KR20090023130A/en
Priority to US12/230,219 priority patent/US20090057265A1/en
Priority to CNA2008102142887A priority patent/CN101378634A/en
Priority to DE102008045003A priority patent/DE102008045003A1/en
Publication of JP2009059814A publication Critical patent/JP2009059814A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0263Details about a collection of particles
    • H05K2201/0272Mixed conductive particles, i.e. using different conductive particles, e.g. differing in shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0388Other aspects of conductors
    • H05K2201/0394Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a low-cost multilayer printed board of high quality in which a power supply defect due to insufficient charging of conductive paste and a short-circuit defect due to a spill of conductive paste can be eliminated. <P>SOLUTION: The manufacturing method of the multilayer printed board as a first embodiment of the present invention includes an etching stage of etching a thin metal layer 2 formed on a surface of a resin film 1 to form circuit patterns 3; a via-hole forming state of boring the resin film 1 from the surface on the opposite side from the circuit pattern 3 to form a plurality of via holes 4 reaching the circuit pattern 3; a sintered body arranging stage of arranging sintered bodies 5 one by one in the respective via-holes 4; a sintered body fixing stage of bringing the respective sintered bodies 5 arranged in the sintered body arranging stage into contact with the circuit patterns 3 forming bottom portions of the via-holes 4 and fixing them; and a substrate connecting stage of stacking a fourth circuit pattern film 40 formed in the sintered body fixing stage to form electric interlayer connections of the circuit patterns 3 disposed in multiple layers through the sintered bodies 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、絶縁性基材に形成されたビアホールに設けた導電性物質により複数の回路パターン層の層間接続を行なう多層プリント基板の製造方法に関する。   The present invention relates to a method for manufacturing a multilayer printed circuit board in which a plurality of circuit pattern layers are connected with each other by a conductive material provided in a via hole formed in an insulating base material.

従来の多層プリント基板の製造方法として、樹脂フィルムに形成されたビアホール内に、金属粒子と有機溶剤とにバインダーとなる樹脂成分を添加した導電ペーストを充填し、このビアホール内に充填された導電ペーストにより、複数の回路パターン層の層間接続を行なう製造方法が知られている(例えば、特許文献1参照)。   As a conventional multilayer printed circuit board manufacturing method, a conductive paste in which a resin component as a binder is added to metal particles and an organic solvent is filled in a via hole formed in a resin film, and the conductive paste is filled in the via hole. Thus, a manufacturing method for performing interlayer connection of a plurality of circuit pattern layers is known (see, for example, Patent Document 1).

このような製造方法においては、導電ペーストをビアホールに充填するときに、導電ペーストをビアホール以外の樹脂フィルムの表面に付着させないために、ビアホールの導電ペースト充填入口側となる樹脂フィルムの表面に保護フィルムを貼着し、ビアホール内に導電ペーストを充填して有機溶剤を乾燥した後、樹脂フィルムから保護フィルムを剥離する。
特開2001−24323号公報
In such a manufacturing method, when filling the conductive paste into the via hole, the protective film is not applied to the surface of the resin film other than the via hole so as to adhere the conductive paste to the surface of the resin film other than the via hole. Is attached, the conductive paste is filled in the via hole, the organic solvent is dried, and then the protective film is peeled off from the resin film.
JP 2001-24323 A

しかしながら上記従来技術では、保護フィルムを剥離する時に、導電ペーストの崩壊や導電ペーストの樹脂フィルム上への落下が起こり、通電性能低下や短絡不良の不具合が生じる。例えば、層間接続部分の通電性等の信頼性を向上するために金属含有率が極めて高い導電ペーストを採用した場合には、この問題は顕著となる。   However, in the above prior art, when the protective film is peeled off, the conductive paste is collapsed or the conductive paste is dropped onto the resin film, resulting in problems such as deterioration of energization performance and short circuit failure. For example, this problem becomes significant when a conductive paste having a very high metal content is employed in order to improve the reliability such as the conductivity of the interlayer connection portion.

本発明は上記点に鑑みてなされたものであり、その目的は、導電ペーストの充填不足による通電不良や導電ペーストこぼれによる短絡不良を解消できる多層プリント基板の製造方法を提供することにある。   The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a multilayer printed circuit board which can eliminate a current-carrying failure due to insufficient filling of the conductive paste and a short-circuit failure due to spilling of the conductive paste.

本発明は上記目的を達成するため以下の技術的手段を採用する。多層プリント基板の製造方法に係る第1の発明は、絶縁性基材(1)の表面に回路パターン(3)を形成する回路パターン形成工程と、絶縁性基材(1)に回路パターン(3)と反対側の表面から穴あけして回路パターン(3)に達するビアホール(4)を複数個形成するビアホール形成工程と、各ビアホール(4)に、導電性粒子の集合体を焼結により固結させて形成した焼結体(5)を1個ずつ配置する焼結体配置工程と、焼結体配置工程において配置された焼結体(5)のそれぞれをビアホール(4)内に固定する焼結体固定工程と、焼結体固定工程で得られたプリント基板(40)を積層して多層に配置された回路パターン(3)を焼結体(5)を介して電気的に層間接続する基板接続工程と、を備えることを特徴とする。   The present invention employs the following technical means to achieve the above object. A first invention relating to a method for manufacturing a multilayer printed circuit board includes a circuit pattern forming step of forming a circuit pattern (3) on the surface of an insulating base (1), and a circuit pattern (3 on the insulating base (1). ) And a via hole forming step of forming a plurality of via holes (4) reaching the circuit pattern (3) by drilling from the surface opposite to the surface, and consolidating the aggregate of conductive particles in each via hole (4) by sintering The sintered body arranging step of arranging the sintered bodies (5) formed one by one, and the sintering for fixing each of the sintered bodies (5) arranged in the sintered body arranging step in the via hole (4) The printed circuit board (40) obtained in the bonded body fixing step and the sintered body fixing step is laminated to electrically connect the circuit patterns (3) arranged in multiple layers via the sintered body (5). And a substrate connecting step.

この発明によれば、導電ペーストをビアホールに充填することなくプリント基板の電気的な層間接続を可能にしたので、導電ペースト充填のために必要となる保護フィルムが不要になり製造工程を簡単化できるとともに、従来の保護フィルムを剥がす時に起こり得る導電ペーストの抜けやこぼれを防止することができる。したがって、導電ペーストの充填不足による通電不良や導電ペーストこぼれによる短絡不良を解消し、プリント基板接続の信頼性が高い多層プリント基板の製造方法を提供することができる。また、保護フィルムを不要にできることにより製造工程を簡単化し、低コストかつ高品質である多層プリント基板の製造方法を提供できる。   According to the present invention, since the electrical interlayer connection of the printed circuit board can be performed without filling the conductive paste into the via hole, the protective film necessary for filling the conductive paste is not necessary, and the manufacturing process can be simplified. At the same time, it is possible to prevent the conductive paste from coming off or spilling, which may occur when the conventional protective film is peeled off. Accordingly, it is possible to provide a method for manufacturing a multilayer printed board with high reliability in connection with the printed board, which eliminates the failure of energization due to insufficient filling of the conductive paste and the short-circuit failure caused by spilling of the conductive paste. In addition, since the protective film can be eliminated, the manufacturing process can be simplified, and a method for manufacturing a multilayer printed circuit board having low cost and high quality can be provided.

また、第2の発明は、絶縁性基材(1)の表面に回路パターン(3A)を形成する回路パターン形成工程と、絶縁性基材(1)に回路パターン(3A)と反対側の表面から穴あけして回路パターン(3A)に達するビアホール(4)を複数個形成するビアホール形成工程と、導電性粒子の集合体を焼結によって固結することでビアホール(4)内から外部に突出しない大きさに形成した焼結体(5A)を各ビアホール(4)内に1個ずつ配置する焼結体配置工程と、焼結体配置工程において作成された回路パターンフィルム(30A)を積層し加熱しながらプレスすることにより、隣接する回路パターンフィルム(30A)における回路パターン(3A)と焼結体(5A)とをビアホール(4)内で接触させて多層に配置された回路パターン(3A)を電気的に層間接続する基板接続工程と、を備えることを特徴とする。   Moreover, 2nd invention is a circuit pattern formation process which forms a circuit pattern (3A) in the surface of an insulating base material (1), and the surface on the opposite side to a circuit pattern (3A) in an insulating base material (1). A via hole forming step for forming a plurality of via holes (4) reaching the circuit pattern (3A) by drilling from the inside, and by consolidating the aggregate of conductive particles by sintering, the via hole (4) does not protrude to the outside The sintered body (5A) formed in the size is placed in each via hole (4) one by one, and the circuit pattern film (30A) created in the sintered body placement process is laminated and heated. The circuit pattern (3A) and the sintered body (5A) in the adjacent circuit pattern film (30A) are brought into contact with each other in the via hole (4) by pressing while the circuit pattern is arranged in multiple layers. 3A) and the substrate connection step of electrically interconnecting the, characterized in that it comprises a.

この発明によれば、上記第1の発明による作用効果を有するとともに、さらにビアホールから外部に突出しない大きさに形成した焼結体を各ビアホールに1個ずつ配置することにより、焼結体をビアホール内に固定する工程と多層プリント基板を電気的に層間接続する工程とを同時に行うことができるので、製造工程をさらに簡単化して、より高い生産性を備えた多層プリント基板の製造方法を提供することができる。   According to this invention, the sintered body having the function and effect of the first invention and having a size that does not protrude to the outside from the via hole is disposed in each via hole. Since the step of fixing inside and the step of electrically connecting the multilayer printed circuit boards can be performed at the same time, the manufacturing process is further simplified, and a method for manufacturing a multilayer printed circuit board with higher productivity is provided. be able to.

上記導電性粒子は銀粒子と錫粒子を含んでいることが好ましく、さらに導電性粒子に対する錫粒子の含有比率は、20〜80重量%の範囲であることが好ましい。この発明によれば、銀粒子と錫粒子の含有により、酸化性が比較的低く、焼結処理を行いやすい導電性粒子を提供することができる。   The conductive particles preferably contain silver particles and tin particles, and the content ratio of the tin particles to the conductive particles is preferably in the range of 20 to 80% by weight. According to this invention, the inclusion of silver particles and tin particles can provide conductive particles that are relatively low in oxidizability and that can be easily sintered.

さらに導電性粒子に対する錫粒子の含有比率を20〜80重量%の範囲としたことにより、焼結体の接合界面における合金層を適切な状態に確保でき、通電性と接合性のバランスがよく信頼性の高い焼結体を提供することができる。   Furthermore, by setting the content ratio of the tin particles to the conductive particles in the range of 20 to 80% by weight, the alloy layer at the bonded interface of the sintered body can be ensured in an appropriate state, and the balance between the conductivity and the bondability is reliable. A highly sintered body can be provided.

また上記焼結体(5、5A)は、銀粉末と錫粉末を含有する導電性粒子を溶剤と混ぜ合わせて製造したペースト(70)を、メタルマスク(80)を用いて所定形状に成形してから高温加熱することにより焼結処理し、さらに炭化物を処理する洗浄を施すことによって製造されることが好ましい。   In addition, the sintered body (5, 5A) is obtained by forming a paste (70) produced by mixing conductive particles containing silver powder and tin powder with a solvent into a predetermined shape using a metal mask (80). Then, it is preferably manufactured by performing a sintering treatment by heating at a high temperature and further performing a washing treatment for carbide.

この発明によれば、メタルマスクを用いてペーストの型取りを行って焼結体を製造することにより、回路パターンとの通電性および接合性の観点から、適切な形状および大きさの焼結体を量産することができる。   According to the present invention, a sintered body having an appropriate shape and size can be obtained from the viewpoint of electrical conductivity and bonding with a circuit pattern by producing a sintered body by molding a paste using a metal mask. Can be mass-produced.

なお、上記各手段に付した括弧内の符号は、後述する実施形態記載の具体的手段との対応関係の一例を示す。   In addition, the code | symbol in the parenthesis attached | subjected to each said means shows an example of a correspondence with the specific means of embodiment description later mentioned.

(第1実施形態)
多層プリント基板の製造方法の一例である第1実施形態について図1〜図4を用いて説明する。図1(a)〜(e)は第1実施形態における多層プリント基板の製造工程の概略を示す工程別断面図である。
(First embodiment)
1st Embodiment which is an example of the manufacturing method of a multilayer printed circuit board is described using FIGS. 1-4. FIGS. 1A to 1E are cross-sectional views showing the outline of the manufacturing process of the multilayer printed board in the first embodiment.

まず、図1(a)に示すように、絶縁性基材である樹脂フィルム1の片側表面に導体である金属層2を貼着して形成されたフィルムを用意する。樹脂フィルム1は、例えば、ポリエーテルエーテルケトン樹脂65〜35重量%とポリエーテルイミド樹脂35〜65重量%とからなる厚さ25〜75μmの熱可塑性樹脂フィルムである。金属層2は例えば厚さ18μmの銅箔により形成されている。   First, as shown to Fig.1 (a), the film formed by affixing the metal layer 2 which is a conductor on the one side surface of the resin film 1 which is an insulating base material is prepared. The resin film 1 is, for example, a thermoplastic resin film having a thickness of 25 to 75 μm composed of 65 to 35% by weight of polyetheretherketone resin and 35 to 65% by weight of polyetherimide resin. The metal layer 2 is formed of, for example, a copper foil having a thickness of 18 μm.

次に、導体により構成される回路パターンを樹脂フィルム1の表面に形成する回路パターン形成工程を実施する。回路パターン形成工程は、エッチング、印刷、蒸着、めっき等により行うことができるが、本実施形態では図1(b)に示すように、図1(a)のフィルムに対して金属層2側からエッチングによりパターン形成して片面に第1の回路パターンフィルム10を作成するエッチング工程により行う。   Next, the circuit pattern formation process which forms the circuit pattern comprised with a conductor on the surface of the resin film 1 is implemented. The circuit pattern forming step can be performed by etching, printing, vapor deposition, plating, etc. In this embodiment, as shown in FIG. 1B, the film of FIG. This is performed by an etching process in which a pattern is formed by etching to form the first circuit pattern film 10 on one side.

次に、図1(c)に示すように、金属層2が設けられていない樹脂フィルム1側から炭酸ガスレーザを照射することにより、樹脂フィルム1に回路パターン2を底面とする有底のビアホール4を複数個形成し、第2の回路パターンフィルム20を作成する(ビアホール形成工程)。各ビアホール4の開口径は、後述の焼結体配置工程で配置される1個の焼結体5がビアホール内に収まるような大きさである。つまり、ビアホール4の開口寸法が球体状、円柱体状、直方体状もしくは立方体状に形成されている焼結体5の最大径となる部分よりも大きいということである。   Next, as shown in FIG.1 (c), the bottomed via-hole 4 which makes the circuit pattern 2 the bottom face to the resin film 1 by irradiating a carbon dioxide laser from the resin film 1 side in which the metal layer 2 is not provided. Are formed to form a second circuit pattern film 20 (via hole forming step). The opening diameter of each via hole 4 is such a size that one sintered body 5 arranged in the sintered body arranging step described later can be accommodated in the via hole. In other words, the opening size of the via hole 4 is larger than the portion having the maximum diameter of the sintered body 5 formed in a spherical shape, a cylindrical shape, a rectangular parallelepiped shape or a cubic shape.

ビアホール4の底面となる回路パターン3の部位は、後述の基板接続工程における多層の回路パターン3の層間接続時に電極となる部位である。ビアホール4の形成においては、炭酸ガスレーザの出力と照射時間等を適切に調整することにより、回路パターン3に穴を開けないようにしている。   The part of the circuit pattern 3 that becomes the bottom surface of the via hole 4 is a part that becomes an electrode when the multilayer circuit pattern 3 is connected between the layers in the substrate connection process described later. In forming the via hole 4, the circuit pattern 3 is prevented from being perforated by appropriately adjusting the output of the carbon dioxide gas laser and the irradiation time.

また、ビアホール4の形成には、炭酸ガスレーザ以外にエキシマレーザ等が使用可能である。レーザ以外のドリル加工等によるビアホール形成方法も可能であるが、レーザビームによる穴あけ加工では微細な径で穴あけでき、回路パターン3に過度の損傷を与えないようにすることができる。   In addition to the carbon dioxide laser, an excimer laser or the like can be used for forming the via hole 4. A via hole forming method by drilling other than laser or the like is also possible, but drilling with a laser beam can make a hole with a fine diameter so that the circuit pattern 3 is not excessively damaged.

次に、図1(d)に示すように、予め焼結処理により導電性粒子の集合体から生成した焼結体5を各ビアホール4に1個ずつ配置し、第3の回路パターンフィルム30を作成する(焼結体配置工程)。この工程で配置された状態の焼結体5は、ビアホール4の開口縁部の表面と同じ高さ、あるいはわずかに突出していることが好ましく、またビアホール4内においてビアホール4の内面と焼結体5の外面との間には、隙間が形成されていることが好ましい。これは、後の焼結体固定工程において焼結体5を変形させた場合に上記隙間を埋めるように焼結体5の変形量を逃がすことができるからである。   Next, as shown in FIG. 1 (d), one sintered body 5 previously generated from an aggregate of conductive particles by a sintering process is disposed in each via hole 4, and the third circuit pattern film 30 is formed. Create (sintered body arrangement step). The sintered body 5 in the state of being arranged in this step preferably has the same height as the surface of the opening edge of the via hole 4 or slightly protrudes, and the inner surface of the via hole 4 and the sintered body in the via hole 4 A gap is preferably formed between the outer surface 5 and the outer surface 5. This is because the deformation amount of the sintered body 5 can be released so as to fill the gap when the sintered body 5 is deformed in the subsequent sintered body fixing step.

焼結体5は、予め、数種の導電性物質の粉末の集合体を加圧条件下で所定の形状や所定の大きさに成形し、融点以下の温度で加熱して粉体粒子間に結合力を生じさせて固体化(固結)して作成する。ビアホール4内に配置された各焼結体5は後述の基板接続工程において多層プリント基板の層間を電気的に接続する層間接続部材6となる。   The sintered body 5 is formed by previously forming an aggregate of powders of several kinds of conductive substances into a predetermined shape and a predetermined size under pressure, and heating at a temperature below the melting point between the powder particles. It is created by solidifying (consolidating) by generating a binding force. Each sintered body 5 arranged in the via hole 4 serves as an interlayer connection member 6 for electrically connecting the layers of the multilayer printed board in a substrate connection process described later.

本実施形態では上記導電性粒子は銀(Ag)粒子と錫(Sn)粒子とからなる。そして、導電性粒子全体に対する錫粒子の含有率は20〜80重量%の範囲であり、さらに好ましくは30〜50重量%の範囲である。これは、上記錫粒子の含有率が20重量%未満であったり80重量%を超える値であったりすると、焼結体の接合界面における合金層が薄くなるため通電性と接合性のバランスが好ましくなく高い信頼性が得られないからである。そして、上記錫粒子の含有率が30〜50重量%の範囲である場合には、錫粒子と銀粒子との焼結物として、通電性と接合性のバランスがより優れたものになる。   In the present embodiment, the conductive particles are composed of silver (Ag) particles and tin (Sn) particles. And the content rate of the tin particle with respect to the whole electroconductive particle is the range of 20-80 weight%, More preferably, it is the range of 30-50 weight%. This is because when the content of the tin particles is less than 20% by weight or more than 80% by weight, the alloy layer at the joining interface of the sintered body becomes thin, so that the balance between the electrical conductivity and the joining property is preferable. This is because high reliability cannot be obtained. And when the content rate of the said tin particle is the range of 30 to 50 weight%, as a sintered compact of a tin particle and a silver particle, the balance of electroconductivity and bondability will be more excellent.

焼結体5を球体状に形成する場合の処理工程は、上記錫粒子と銀粒子との混合物を高温で溶融し、これを回転するディスク上に所定の粒子径となるように噴霧して遠心力によって分散させて成形するものである。そしてこのように成形された球体を所定温度まで冷却すると、AgSnとAg・Sn固溶体とで構成される球体状の焼結体(ボール状の焼結体)を製造することができる。 When the sintered body 5 is formed into a spherical shape, the mixture of the tin particles and silver particles is melted at a high temperature, sprayed on the rotating disk to a predetermined particle diameter, and centrifuged. It is formed by being dispersed by force. When the cooling thus shaped spheres to a to a predetermined temperature, it is possible to produce spherical sintered bodies composed of the Ag 3 Sn and Ag · Sn solid solution (ball-shaped sintered body).

本実施形態の焼結体5の1個の大きさは、その最も寸法の大きい部位の長さ(焼結体が球体状のときは直径の長さ)が樹脂フィルム1(絶縁性基材1)の厚さtに対してt〜1.4tの範囲であるものを使用することができ、さらにはt〜1.3tの範囲であるものを使用することが好ましい。このような大きさの焼結体5を使用することにより、錫粒子と銀粒子との焼結物として適切な通電性および接合性が得られるからである。例えば、厚さ75μmの樹脂フィルム1、厚さ18μmの銅箔(回路パターン)に対して、球体状の焼結体5は直径90μmのものを目指しており、実際には製造上のばらつきにより上記範囲を満たすものを使用する。   One size of the sintered body 5 of the present embodiment is such that the length of the portion with the largest dimension (the length of the diameter when the sintered body is spherical) is the resin film 1 (insulating base material 1). ) In the range of t to 1.4 t with respect to the thickness t, and more preferably in the range of t to 1.3 t. This is because by using the sintered body 5 having such a size, it is possible to obtain appropriate electrical conductivity and bondability as a sintered product of tin particles and silver particles. For example, with respect to a resin film 1 having a thickness of 75 μm and a copper foil (circuit pattern) having a thickness of 18 μm, the spherical sintered body 5 is aimed to have a diameter of 90 μm. Use one that meets the range.

図2(a)および(b)は多層プリント基板の製造工程における焼結体配置工程の手順を示した概略図である。この焼結体配置工程は、図2(a)に示すようにメタルマスク63を用いた焼結体設定装置によって行われる。   FIGS. 2A and 2B are schematic views showing the procedure of the sintered body arranging step in the manufacturing process of the multilayer printed board. This sintered body arranging step is performed by a sintered body setting device using a metal mask 63 as shown in FIG.

この焼結体設定装置は、所定位置および所定形状の貫通孔64を複数個備えたメタルマスク63と、回転部6および回転部6から垂下するカーテン部62を備えた回転移動体60とによって焼結体5を1個ずつ各ビアホール4に導くものである。複数個の貫通孔64は、焼結体5が落下可能な大きさで形成されており、第2の回路パターンフィルム20に形成されたすべてのビアホール4に対応するようにメタルマスク63に設けられている。   This sintered body setting apparatus is baked by a metal mask 63 having a plurality of through holes 64 having a predetermined position and a predetermined shape, and a rotary moving body 60 having a rotating portion 6 and a curtain portion 62 depending from the rotating portion 6. One ligated body 5 is led to each via hole 4 one by one. The plurality of through holes 64 are formed in such a size that the sintered body 5 can be dropped, and are provided in the metal mask 63 so as to correspond to all the via holes 4 formed in the second circuit pattern film 20. ing.

まず、すべてのビアホール4が貫通孔64に対応するようにメタルマスク63に対して第2の回路パターンフィルム20を設置する。そして、メタルマスク63の表面上にビアホール4の個数よりも多い個数の焼結体5を置き、回転部6を回転させながら貫通孔64に向かって移動させるように焼結体設定装置を作動させると、回転部6が移動するにつれて焼結体5が回転移動するカーテン部62によって順次貫通孔64に導かれるようになる。貫通孔64に案内された焼結体5は貫通孔64から1個ずつ落下してビアホール4に納まることとなり、各ビアホール4に焼結体5が1個ずつ配置された第3の回路パターンフィルム30が完成する(以上、図2(a)および(b)参照)。   First, the second circuit pattern film 20 is placed on the metal mask 63 so that all the via holes 4 correspond to the through holes 64. Then, a larger number of sintered bodies 5 than the number of via holes 4 are placed on the surface of the metal mask 63, and the sintered body setting device is operated so as to move toward the through hole 64 while rotating the rotating portion 6. Then, as the rotating part 6 moves, the sintered body 5 is sequentially guided to the through hole 64 by the curtain part 62 that rotates. The sintered bodies 5 guided to the through holes 64 fall one by one from the through holes 64 and are accommodated in the via holes 4, and a third circuit pattern film in which one sintered body 5 is arranged in each via hole 4. 30 is completed (see FIGS. 2A and 2B).

また、メタルマスクを使用せず回路パターンフィルム20上でビアホール4に焼結体5を配置し、フィルム上に残存した余分な焼結体5をスキージにより回収することにより焼結体設定をすることもできる。   Further, the sintered body 5 is arranged by arranging the sintered body 5 in the via hole 4 on the circuit pattern film 20 without using a metal mask, and collecting the excess sintered body 5 remaining on the film with a squeegee. You can also.

次に、図1(e)に示すように、焼結体5をビアホール4内で変形させて層間接続部材6を形成してビアホール4内に固定し、第4の回路パターンフィルム40を作成する(焼結体固定工程)。   Next, as shown in FIG. 1 (e), the sintered body 5 is deformed in the via hole 4 to form an interlayer connection member 6 and fixed in the via hole 4 to form a fourth circuit pattern film 40. (Sintered body fixing step).

焼結体固定工程において焼結体5を固定する方法としては、焼結体5を加圧することにより焼結体5を変形させて固定する方法、焼結体5とビアホール4の内面との間に溶剤を塗布することにより表面張力を利用して固定する方法、超音波振動をかけることにより銀粒子の表面から錫粒子の拡散を起こさせて固定する方法、所定温度に加熱することにより銀粒子の表面から錫粒子を溶融させて固定する方法等がある。なお、ここでいう固定とは外力を受けても動かないような強固な固定力だけでなく、後の基板接続工程を首尾よく行える程度の固定力であることも含んでいる。   As a method of fixing the sintered body 5 in the sintered body fixing step, a method of deforming and fixing the sintered body 5 by pressurizing the sintered body 5, and between the sintered body 5 and the inner surface of the via hole 4 are used. A method of fixing by applying surface tension by applying a solvent to the surface, a method of fixing by causing diffusion of tin particles from the surface of silver particles by applying ultrasonic vibration, and silver particles by heating to a predetermined temperature There is a method in which tin particles are melted and fixed from the surface. The term “fixing” as used herein includes not only a strong fixing force that does not move even when an external force is applied, but also a fixing force that allows a subsequent substrate connection process to be performed successfully.

また、層間接続部材6は、例えば、ロール部材50を一方側から他方側へ徐々に回転移動させながら、第3の回路パターンフィルム30の表面に圧縮荷重をかけるロールプレス加工を施すことによって焼結体5をビアホール4の内面形状に沿うように変形させることで形成することもできる(図3参照)。   Further, the interlayer connection member 6 is sintered, for example, by performing a roll press process that applies a compressive load to the surface of the third circuit pattern film 30 while gradually rotating the roll member 50 from one side to the other side. It can also be formed by deforming the body 5 so as to follow the inner shape of the via hole 4 (see FIG. 3).

次に、多層に配置された複数の回路パターンフィルムの回路パターン3を電気的に層間接続する基板接続工程を説明する。この基板接続工程では、まず、複数枚の第4の回路パターンフィルム40(本実施形態では2枚)と、最上面に位置する第1の回路パターンフィルム10とを積層する。そして、下方側の2枚の第4の回路パターンフィルム40と上方側の第1の回路パターンフィルム10の両方とも、回路パターン3が設けられた側の面を下側にして積層し、隣接する回路パターンフィルムそれぞれの回路パターン3と層間接続部材6とを対向させた状態で、これら多層プリント基板の上下両面を真空加熱プレス機により加熱しながら加圧する。例えば、250〜350℃の雰囲気温度下で1〜10MPaの圧力で10〜20分間加圧する。   Next, a substrate connecting process for electrically connecting the circuit patterns 3 of a plurality of circuit pattern films arranged in multiple layers will be described. In this substrate connection step, first, a plurality of fourth circuit pattern films 40 (two in this embodiment) and the first circuit pattern film 10 positioned on the uppermost surface are laminated. Then, both the two lower fourth circuit pattern films 40 and the upper first circuit pattern film 10 are laminated with the surface on which the circuit pattern 3 is provided facing down, and are adjacent to each other. With the circuit pattern 3 of each circuit pattern film and the interlayer connection member 6 facing each other, the upper and lower surfaces of these multilayer printed boards are pressed while being heated by a vacuum heating press. For example, pressurization is performed for 10 to 20 minutes at a pressure of 1 to 10 MPa under an atmospheric temperature of 250 to 350 ° C.

この基板接続工程により、複数枚の第4の回路パターンフィルム40および第1の回路パターンフィルム10の相互が熱融着して一体化するとともに、ビアホール4内の層間接続部材6を介して隣接する回路パターンフィルムの回路パターン3間が電気的に層間接続された多層プリント基板100が得られることになる(図4参照)。図4は本実施形態の多層プリント基板の製造工程において多層に配置された複数の回路パターンフィルムを電気的に層間接続した状態を示す概略的断面図である。   By this substrate connection step, the plurality of fourth circuit pattern films 40 and the first circuit pattern film 10 are heat-fused and integrated with each other, and are adjacent to each other through the interlayer connection member 6 in the via hole 4. A multilayer printed circuit board 100 in which the circuit patterns 3 of the circuit pattern film are electrically connected to each other is obtained (see FIG. 4). FIG. 4 is a schematic cross-sectional view showing a state in which a plurality of circuit pattern films arranged in multiple layers are electrically connected to each other in the manufacturing process of the multilayer printed board according to the present embodiment.

この状態でビアホール4内の層間接続部材6は、一定の力で加圧されているため、ビアホール4の底部を構成している回路パターン3の面に圧接されている。この圧接状態により、層間接続部材6中のSn成分と回路パターン3を構成する銅箔のCu成分とが相互に固相拡散し、層間接続部材6と回路パターン3との界面に固相拡散層を形成するので、多層に並べられた回路パターンを電気的に接続することができる。   In this state, the interlayer connection member 6 in the via hole 4 is pressed with a constant force, so that it is pressed against the surface of the circuit pattern 3 constituting the bottom of the via hole 4. Due to this pressure contact state, the Sn component in the interlayer connection member 6 and the Cu component of the copper foil constituting the circuit pattern 3 are mutually solid-phase diffused, and a solid-phase diffusion layer is formed at the interface between the interlayer connection member 6 and the circuit pattern 3. Therefore, circuit patterns arranged in multiple layers can be electrically connected.

以上のように本実施形態の多層プリント基板100の製造方法は、樹脂フィルム1の表面に形成された薄い金属層2にエッチングを施すことにより回路パターン3を形成するエッチング工程と、樹脂フィルム1に回路パターン3と反対側の表面から穴あけして回路パターン3に達するビアホール4を複数個形成するビアホール形成工程と、各ビアホール4に、導電性粒子の焼結により固結させて形成した焼結体5を1個ずつ配置する焼結体配置工程と、焼結体配置工程において配置された焼結体5のそれぞれをビアホール4の底部をなす回路パターン3に密着させるように固定する焼結体固定工程と、焼結体固定工程で作成した第4の回路パターンフィルム40を積層して、焼結体5を介して多層に配置された回路パターン3を電気的に層間接続する基板接続工程と、を備えている。   As described above, the manufacturing method of the multilayer printed circuit board 100 according to the present embodiment includes an etching process for forming the circuit pattern 3 by etching the thin metal layer 2 formed on the surface of the resin film 1, and the resin film 1. A via hole forming step of forming a plurality of via holes 4 reaching the circuit pattern 3 by drilling from the surface opposite to the circuit pattern 3, and a sintered body formed by consolidating each via hole 4 by sintering conductive particles Sintered body fixing step for fixing each of the sintered bodies 5 arranged in the sintered body arranging step to be in close contact with the circuit pattern 3 forming the bottom of the via hole 4 The fourth circuit pattern film 40 created in the process and the sintered body fixing process is laminated, and the circuit patterns 3 arranged in multiple layers via the sintered body 5 are electrically connected to each other. Includes a board connecting step of continued, the.

この製造方法によれば、所定の大きさに形成された1個の焼結体5をビアホール4内に配置することにより、導電性物質をビアホール4内に安定した姿勢で固定することができ、通電性に支障をきたすような導電性物質のビアホール4内での欠損および崩壊やビアホール4からのこぼれを解消することができる。したがって、導電ペーストを用いることなくプリント基板の電気的な層間接続を可能にできるので、導電ペースト充填のために必要となる保護フィルムが不要になり製造工程を簡単化できるとともに、従来問題となっていた、保護フィルムを剥がす時に起こり得る導電ペーストの抜けやこぼれを防止することができる。   According to this manufacturing method, by disposing one sintered body 5 having a predetermined size in the via hole 4, the conductive material can be fixed in the via hole 4 in a stable posture. It is possible to eliminate the loss and collapse of the conductive material in the via hole 4 and the spillage from the via hole 4 that hinder the conductivity. Therefore, since it is possible to connect the electrical layers of the printed circuit board without using the conductive paste, a protective film necessary for filling the conductive paste is not necessary, and the manufacturing process can be simplified and has been a problem in the past. In addition, it is possible to prevent the conductive paste from dropping or spilling, which may occur when the protective film is peeled off.

(第2実施形態)
第2実施形態では多層プリント基板の製造工程の他の例を説明する。本実施形態で説明する多層プリント基板100Aの製造工程は、第1実施形態で説明した製造工程に対して、焼結体固定工程がなく、ビアホール形成工程、焼結体配置工程および基板接続工程が異なった内容となっている。その他の工程については第1実施形態で説明した工程と同様であり、その説明は省略する。
(Second Embodiment)
2nd Embodiment demonstrates the other example of the manufacturing process of a multilayer printed circuit board. The manufacturing process of the multilayer printed circuit board 100A described in the present embodiment has no sintered body fixing process as compared to the manufacturing process described in the first embodiment, and includes a via hole forming process, a sintered body arranging process, and a board connecting process. The contents are different. Other steps are the same as those described in the first embodiment, and a description thereof will be omitted.

多層プリント基板100Aの製造工程におけるビアホール形成工程では、ビアホール4の開口の直径を、後の基板接続工程の層間接続において隣接することになる回路パターンフィルムの回路パターン3Aがビアホール4内に入り込むことができる大きさに形成するものである。   In the via hole forming step in the manufacturing process of the multilayer printed circuit board 100A, the circuit pattern 3A of the circuit pattern film that is adjacent to the diameter of the opening of the via hole 4 in the interlayer connection in the subsequent substrate connecting step may enter the via hole 4. It is formed in a size that can be made.

次に、焼結体配置工程では、第1実施形態と同様の構成要素を備える導電性粒子を焼結処理によってビアホール4内から外部に突出しない大きさに成形した焼結体5Aを使用するものであり、このように形成した焼結体5Aを各ビアホール4内に1個ずつ配置して第3の回路パターンフィルム30Aを作成する工程である。   Next, in the sintered body arrangement step, a sintered body 5A is used in which conductive particles having the same components as those in the first embodiment are formed into a size that does not protrude from the inside of the via hole 4 by a sintering process. In this step, the sintered body 5A thus formed is arranged one by one in each via hole 4 to form the third circuit pattern film 30A.

つまり、ビアホール4内に配置された状態の焼結体5Aの頂面の高さは、ビアホール4の開口縁部の表面よりも所定距離分下方に位置することになる。そしてこの所定距離分は、後の基板接続工程において接触することになる回路パターン3Aの厚さと同等もしくはこれよりも小さくなるように設定されている。焼結体5Aは大きさこそ異なるが同様の形状であり、第1実施形態の焼結体5と同様な方法で製造するものとする。   That is, the height of the top surface of the sintered body 5 </ b> A disposed in the via hole 4 is positioned below the surface of the opening edge of the via hole 4 by a predetermined distance. The predetermined distance is set to be equal to or smaller than the thickness of the circuit pattern 3A to be contacted in the subsequent substrate connection process. The sintered body 5A is different in size but has the same shape, and is manufactured by the same method as the sintered body 5 of the first embodiment.

そして、焼結体配置工程に続いて図5に示す基板接続工程を行う。本実施形態の多層プリント基板100Aの製造工程において、図5(a)は複数の回路パターンフィルムを多層となるように配置した状態を示す概略的断面図であり、図5(b)は多層に配置した複数の回路パターンフィルムを電気的に層間接続した状態を示す概略的断面図である。   And the board | substrate connection process shown in FIG. 5 is performed following a sintered compact arrangement | positioning process. In the manufacturing process of the multilayer printed circuit board 100A of the present embodiment, FIG. 5A is a schematic cross-sectional view showing a state in which a plurality of circuit pattern films are arranged in a multilayer, and FIG. It is a schematic sectional drawing which shows the state which carried out the interlayer connection of the some circuit pattern film arrange | positioned.

この基板接続工程では、まず、複数枚の第3の回路パターンフィルム30A、30B(本実施形態では3枚)と、最上面に位置する第1の回路パターンフィルム10Aとを積層する。そして、下方側の3枚の第3の回路パターンフィルム30A、30Bと上方側の第1の回路パターンフィルム10Aをともに回路パターン3Aが設けられた側の面を下側にして積層し、隣接する回路パターンフィルムそれぞれの回路パターン3Aが下方のビアホール4内に入り込むようにすべての回路パターンフィルムを重ね合わせる。   In this substrate connecting step, first, a plurality of third circuit pattern films 30A and 30B (three in this embodiment) and the first circuit pattern film 10A positioned on the uppermost surface are laminated. Then, the third circuit pattern films 30A and 30B on the lower side and the first circuit pattern film 10A on the upper side are laminated with the surface on which the circuit pattern 3A is provided on the lower side, and adjacent to each other. All the circuit pattern films are overlaid so that the circuit pattern 3A of each circuit pattern film enters the lower via hole 4.

このとき、回路パターンフィルム30Aの回路パターン3Aは下方で重ね合わされる回路パターンフィルムに形成されたビアホール4内で焼結体5Aに接触した状態にある。そして、これら多層プリント基板の上下両面を真空加熱プレス機により加熱しながら加圧する。例えば、250〜350℃の雰囲気温度下で1〜10MPaの圧力で10〜20分間加圧する。   At this time, the circuit pattern 3A of the circuit pattern film 30A is in contact with the sintered body 5A in the via hole 4 formed in the circuit pattern film superimposed below. Then, the upper and lower surfaces of these multilayer printed boards are pressurized while being heated by a vacuum heating press. For example, pressurization is performed for 10 to 20 minutes at a pressure of 1 to 10 MPa under an atmospheric temperature of 250 to 350 ° C.

この基板接続工程により、複数枚の第3の回路パターンフィルム30Aおよび第1の回路パターンフィルム10Aの相互が熱融着して一体化するとともに、ビアホール4内の焼結体5Aを介して隣接する回路パターンフィルムの回路パターン3、3A間が電気的に層間接続された多層プリント基板100Aが得られることになる(以上、図5(a)、(b)参照)。   By this substrate connection step, the plurality of third circuit pattern films 30A and the first circuit pattern film 10A are integrated by thermal fusion and are adjacent to each other via the sintered body 5A in the via hole 4. A multilayer printed board 100A in which the circuit patterns 3 and 3A of the circuit pattern film are electrically connected to each other is obtained (see FIGS. 5A and 5B).

この状態でビアホール4内の焼結体5Aは、一定の力で加圧されているため、ビアホール4の底部を構成している回路パターン3、3Aの面に圧接されている。この圧接状態により、焼結体5A中のSn成分と回路パターン3、3Aを構成する銅箔のCu成分とが相互に固相拡散し、焼結体5Aと回路パターン3、3Aとの界面に固相拡散層を形成するので、多層に並べられた回路パターンを電気的に接続することができる。   In this state, the sintered body 5 </ b> A in the via hole 4 is pressed with a constant force, and is in pressure contact with the surfaces of the circuit patterns 3 and 3 </ b> A constituting the bottom of the via hole 4. Due to this pressure contact state, the Sn component in the sintered body 5A and the Cu component of the copper foil constituting the circuit patterns 3 and 3A are solid-phase diffused to each other at the interface between the sintered body 5A and the circuit patterns 3 and 3A. Since the solid phase diffusion layer is formed, the circuit patterns arranged in multiple layers can be electrically connected.

以上のように本実施形態の多層プリント基板100Aの製造方法は、絶縁フィルム1の表面に形成された薄い金属層2にエッチングを施すことにより回路パターン3Aを形成するエッチング工程と、絶縁フィルム1に回路パターン3Aと反対側の表面から穴あけして回路パターン3Aに達するビアホール4を複数個形成するビアホール形成工程と、導電性粒子の集合体を焼結によって固結することでビアホール4から外部に突出しない大きさに形成した焼結体5Aを各ビアホール4に1個ずつ配置する焼結体配置工程と、焼結体配置工程において作成された回路パターンフィルム30Aを積層し、隣接する回路パターンフィルム30Aについて回路パターン3Aをビアホール4内で焼結体5Aに接触させた状態で加熱プレスすることにより、多層に配置された回路パターン3Aを電気的に層間接続する基板接続工程と、を備えるものである。   As described above, the manufacturing method of the multilayer printed circuit board 100A according to the present embodiment includes the etching step of forming the circuit pattern 3A by etching the thin metal layer 2 formed on the surface of the insulating film 1, and the insulating film 1. A via hole forming step of forming a plurality of via holes 4 which are drilled from the surface opposite to the circuit pattern 3A and reach the circuit pattern 3A, and a set of conductive particles is solidified by sintering, and protrudes from the via hole 4 to the outside. The sintered body disposing step of disposing one sintered body 5A having a size not to be placed in each via hole 4 and the circuit pattern film 30A created in the sintered body disposing step are laminated, and the adjacent circuit pattern film 30A is laminated. By heating and pressing the circuit pattern 3A in contact with the sintered body 5A in the via hole 4, A substrate connecting step of electrically interconnecting a circuit pattern 3A arranged in layers, those comprising a.

この製造方法によれば、第1実施形態の製造方法と同様の作用効果に加え、焼結体5Aをビアホール4内に固定する工程と多層のプリント基板を電気的に層間接続する工程とを同時に行うことができるので、製造工程をさらに簡単化してさらに生産性を向上させることができる。   According to this manufacturing method, in addition to the same effects as those of the manufacturing method of the first embodiment, the step of fixing the sintered body 5A in the via hole 4 and the step of electrically connecting the multilayer printed circuit board to each other at the same time are performed simultaneously. Therefore, the manufacturing process can be further simplified and the productivity can be further improved.

(第3実施形態)
第3実施形態では焼結体の製造方法の一例について図6にしたがって説明する。本実施形態で説明する方法によって製造される焼結体は、本発明に係る多層プリント基板の製造方法に適用することができる。図6(a)〜(d)は本実施形態における焼結体の製造工程を示す工程別概略図である。
(Third embodiment)
In 3rd Embodiment, an example of the manufacturing method of a sintered compact is demonstrated according to FIG. The sintered body manufactured by the method described in the present embodiment can be applied to the method for manufacturing a multilayer printed board according to the present invention. 6 (a) to 6 (d) are schematic views by process showing the manufacturing process of the sintered body in the present embodiment.

焼結処理される前の導電性粒子の集合体は、分散剤としてのAg(銀)粉末とSn(錫)粉末とに溶剤を加えて混練することによってペースト状にして作成される。例えば、銀粉末は平均粒径1μm、比表面積1.2m/gの銀粒子からなり、錫粉末は平均粒径5μm、比表面積0.5m/gの錫粒子からなり、溶剤としてはテルピネオールを使用する。分散剤等の樹脂成分は金属粒子全体の形状を保持するバインダー成分としても機能する。また、導電性粒子全体に対する錫粒子の含有率は第1実施形態と同様にすることが好ましいが、本実施形態では銀粒子と錫粒子の含有率の比を65:35とする。 The aggregate of conductive particles before the sintering treatment is made into a paste by adding a solvent to Ag (silver) powder and Sn (tin) powder as a dispersant and kneading them. For example, silver powder is composed of silver particles having an average particle diameter of 1 μm and specific surface area of 1.2 m 2 / g, tin powder is composed of tin particles having an average particle diameter of 5 μm and specific surface area of 0.5 m 2 / g, and the solvent is terpineol. Is used. A resin component such as a dispersant also functions as a binder component that maintains the shape of the entire metal particle. Moreover, it is preferable to make the content rate of the tin particle with respect to the whole electroconductive particle the same as 1st Embodiment, However In this embodiment, the ratio of the content rate of a silver particle and a tin particle shall be 65:35.

このように生産された導電性粒子の集合体(導電ペースト70)は所定形状の貫通孔81(例えば、貫通孔の深さ50μm、内径φ100μm)が複数個形成されたメタルマスク80を用いたペースト印刷により当該所定形状に成形される。具体的には、上記構成比率を満たす錫粒子71、銀粒子73および溶剤72からなる所定量の導電ペースト70を、離型性を有する基板82(例えばフッ素樹脂基板)に載置したメタルマスク80の表面に置き、刷毛83等によってメタルマスク80の全体に行き渡らせると、導電ペースト70はメタルマスク80の貫通孔81に印刷充填される(図6(a)参照)。   The aggregate of conductive particles (conductive paste 70) produced in this way is a paste using a metal mask 80 in which a plurality of through holes 81 having a predetermined shape (for example, through holes having a depth of 50 μm and an inner diameter of φ100 μm) are formed. The predetermined shape is formed by printing. Specifically, a metal mask 80 in which a predetermined amount of conductive paste 70 composed of tin particles 71, silver particles 73 and solvent 72 satisfying the above-described composition ratio is placed on a substrate 82 (for example, a fluororesin substrate) having releasability. The conductive paste 70 is printed and filled in the through holes 81 of the metal mask 80 (see FIG. 6A).

そして、メタルマスク80を基板82から鉛直上方に持ち上げると、基板82上には貫通孔81の内面形状に等しい側面形状と、メタルマスク80の厚さとほぼ同等の高さ寸法とを有する円盤形状に成形された導電ペースト70が複数個残ることになる(図6(b)参照)。   When the metal mask 80 is lifted vertically upward from the substrate 82, the substrate 82 has a disk shape having a side surface shape equal to the inner surface shape of the through hole 81 and a height dimension substantially equal to the thickness of the metal mask 80. A plurality of molded conductive pastes 70 remain (see FIG. 6B).

続いて、図6(c)に示すように、この円盤形状に成形された導電ペースト70を雰囲気温度260℃で高温加熱して焼結処理を実施すると、安定した姿勢の焼結体74が得られる。この高温加熱は、一般的なリフロー炉、ベーパーリフロー炉、雰囲気焼成炉、ボックス炉等により行うことができる。また加熱雰囲気は、錫成分の酸化防止のため還元雰囲気であることが好ましい。   Subsequently, as shown in FIG. 6 (c), when the conductive paste 70 formed into a disk shape is heated at an atmospheric temperature of 260 ° C. to perform a sintering process, a sintered body 74 having a stable posture is obtained. It is done. This high temperature heating can be performed by a general reflow furnace, a vapor reflow furnace, an atmosphere firing furnace, a box furnace, or the like. The heating atmosphere is preferably a reducing atmosphere to prevent oxidation of the tin component.

この焼結処理において導電ペースト70は、溶剤であるテルピネオールが蒸発乾燥し、錫粒子と銀粒子とが混合された状態にある。上記加熱温度によって融点が232℃である錫粒子は融解し、銀粒子の外周を覆うように付着するようになる。そして、この状態で加熱を継続すると、融解した錫は銀粒子の表面から拡散を始め、錫と銀との焼結体が生成される。   In this sintering process, the conductive paste 70 is in a state where terpineol as a solvent is evaporated and dried, and tin particles and silver particles are mixed. The tin particles having a melting point of 232 ° C. are melted by the heating temperature, and adhere to cover the outer periphery of the silver particles. When heating is continued in this state, the molten tin starts to diffuse from the surface of the silver particles, and a sintered body of tin and silver is generated.

次に、図6(d)に示すように、複数個の焼結体74を容器に入れて洗浄液83で洗浄して、焼結体74に対して炭化物を除去する洗浄処理を施す。そして洗浄処理された焼結体74を乾燥すると焼結体配置工程に使用できる焼結体5、5Aが得られる。   Next, as shown in FIG. 6 (d), a plurality of sintered bodies 74 are put in a container and washed with a cleaning solution 83, and the sintered body 74 is subjected to a cleaning process for removing carbides. When the washed sintered body 74 is dried, sintered bodies 5 and 5A that can be used in the sintered body arranging step are obtained.

以上のように、銀粉末と錫粉末を含有する導電性粒子を溶剤と混ぜ合わせて製造した導電性ペースト70を、メタルマスク80を用いて所定形状に成形してから高温加熱することにより焼結処理し、さらに炭化物を処理する洗浄を施すことによって焼結体5、5Aを製造する。   As described above, the conductive paste 70 produced by mixing conductive particles containing silver powder and tin powder with a solvent is molded into a predetermined shape using a metal mask 80 and then sintered at a high temperature. Sintered bodies 5 and 5A are manufactured by performing cleaning and further cleaning to treat carbide.

この焼結体の製造方法によれば、メタルマスク80を用いてペーストの型取りを行って焼結体を製造するので、層間接続される回路パターンとの通電性および接合性の観点から、信頼性の高い焼結体5、5Aを量産することができる。
(その他の実施形態)
以上、本発明の好ましい実施形態について説明したが、本発明は上述した実施形態に何ら制限されることなく、本発明の主旨を逸脱しない範囲において種々変形して実施することが可能である。 例えば、上記実施形態では、樹脂フィルム2としてポリエーテルエーテルケトン樹脂65〜35重量%とポリエーテルイミド樹脂35〜65重量%とからなる樹脂フィルムを用いたが、これに限定するものではなく、ポリエーテルエーテルケトン樹脂とポリエーテルイミド樹脂に非導電性フィラを充填したフィルムであってもよいし、ポリエーテルエーテルケトン(PEEK)もしくはポリエーテルイミド(PEI)を使用することもできる。
According to this method of manufacturing a sintered body, since the sintered body is manufactured by performing paste molding using the metal mask 80, it is reliable from the viewpoint of electrical conductivity and bondability with the circuit pattern connected between the layers. High-performance sintered bodies 5 and 5A can be mass-produced.
(Other embodiments)
The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, a resin film composed of 65 to 35% by weight of polyetheretherketone resin and 35 to 65% by weight of polyetherimide resin is used as the resin film 2, but the present invention is not limited to this. A film in which a non-conductive filler is filled in an ether ether ketone resin and a polyether imide resin may be used, or polyether ether ketone (PEEK) or polyether imide (PEI) may be used.

また、上記実施形態では、多層プリント基板100、100Aは3層または4層のプリント基板であるが、多層の回路パターン層を構成するものであれば、その層数が上記層数に限定されるものではない。   In the above-described embodiment, the multilayer printed circuit boards 100 and 100A are three-layer or four-layer printed circuit boards, but the number of layers is limited to the number of layers as long as the multilayer circuit pattern layer is configured. It is not a thing.

(a)〜(e)は第1実施形態における多層プリント基板の製造工程の概略を示す工程別断面図である。(A)-(e) is sectional drawing according to process which shows the outline of the manufacturing process of the multilayer printed circuit board in 1st Embodiment. (a)および(b)は多層プリント基板の製造工程における焼結体配置工程の手順を示した概略図である。(A) And (b) is the schematic which showed the procedure of the sintered compact arrangement | positioning process in the manufacturing process of a multilayer printed circuit board. ビアホールに配置された焼結体をローラで加圧する様子を示した概略図である。It is the schematic which showed a mode that the sintered compact arrange | positioned at the via hole was pressurized with a roller. 第1実施形態の多層プリント基板の製造工程において、多層に配置された複数の回路パターンフィルムを電気的に層間接続した状態を示す概略的断面図である。In the manufacturing process of the multilayer printed circuit board of a 1st embodiment, it is a schematic sectional view showing the state where a plurality of circuit pattern films arranged in multiple layers were electrically interlayer-connected. 第2実施形態の多層プリント基板の製造工程において、(a)は複数の回路パターンフィルムを多層となるように配置した状態を示す概略的断面図であり、(b)は多層に配置した複数の回路パターンフィルムを電気的に層間接続した状態を示す概略的断面図である。In the manufacturing process of the multilayer printed circuit board according to the second embodiment, (a) is a schematic cross-sectional view showing a state in which a plurality of circuit pattern films are arranged in a multilayer, and (b) is a plurality of arrangements in multiple layers. It is a schematic sectional drawing which shows the state which carried out the interlayer connection of the circuit pattern film electrically. (a)〜(d)は第3実施形態における焼結体の製造工程を示す工程別概略図である。(A)-(d) is the schematic according to process which shows the manufacturing process of the sintered compact in 3rd Embodiment.

符号の説明Explanation of symbols

1…樹脂フィルム(絶縁性基材)
2…金属層(導体)
3、3A…回路パターン
4…ビアホール
5、5A…焼結体
30A…第3の回路パターンフィルム
40…第4の回路パターンフィルム(プリント基板)
70…ペースト
80…メタルマスク
1 ... Resin film (insulating substrate)
2 ... Metal layer (conductor)
3, 3A ... circuit pattern 4 ... via hole 5, 5A ... sintered body 30A ... third circuit pattern film 40 ... fourth circuit pattern film (printed circuit board)
70 ... Paste 80 ... Metal mask

Claims (5)

絶縁性基材(1)の表面に回路パターン(3)を形成する回路パターン形成工程と、
前記絶縁性基材(1)に前記回路パターン(3)と反対側の表面から穴あけして前記回路パターン(3)に達するビアホール(4)を複数個形成するビアホール形成工程と、
前記各ビアホール(4)に、導電性粒子の集合体を焼結により固結させて形成した焼結体(5)を1個ずつ配置する焼結体配置工程と、
前記焼結体配置工程において配置された前記焼結体(5)のそれぞれを前記ビアホール(4)内に固定する焼結体固定工程と、
前記焼結体固定工程で得られたプリント基板(40)を積層して多層に配置された前記回路パターン(3)を前記焼結体(5)を介して電気的に層間接続する基板接続工程と、
を備えることを特徴とする多層プリント基板の製造方法。
A circuit pattern forming step of forming a circuit pattern (3) on the surface of the insulating substrate (1);
A via hole forming step of forming a plurality of via holes (4) reaching the circuit pattern (3) by drilling the insulating base material (1) from the surface opposite to the circuit pattern (3);
In each via hole (4), a sintered body disposing step of disposing one sintered body (5) formed by consolidating an aggregate of conductive particles by sintering;
A sintered body fixing step of fixing each of the sintered bodies (5) arranged in the sintered body arrangement step in the via hole (4);
A substrate connecting step of electrically connecting the circuit patterns (3) arranged in multiple layers by stacking the printed circuit boards (40) obtained in the sintered body fixing step via the sintered body (5) When,
A method for producing a multilayer printed circuit board, comprising:
絶縁性基材(1)の表面に回路パターン(3A)を形成する回路パターン形成工程と、
前記絶縁性基材(1)に前記回路パターン(3A)と反対側の表面から穴あけして前記回路パターン(3A)に達するビアホール(4)を複数個形成するビアホール形成工程と、
導電性粒子の集合体を焼結によって固結することで前記ビアホール(4)内から外部に突出しない大きさに形成した焼結体(5A)を前記各ビアホール(4)内に1個ずつ配置する焼結体配置工程と、
前記焼結体配置工程において作成された回路パターンフィルム(30A)を積層し加熱しながらプレスすることにより、隣接する前記回路パターンフィルム(30A)における前記回路パターン(3A)と前記焼結体(5A)とを前記ビアホール(4)内で接触させて多層に配置された前記回路パターン(3A)を電気的に層間接続する基板接続工程と、
を備えることを特徴とする多層プリント基板の製造方法。
A circuit pattern forming step of forming a circuit pattern (3A) on the surface of the insulating substrate (1);
A via hole forming step of forming a plurality of via holes (4) reaching the circuit pattern (3A) by drilling the insulating base material (1) from the surface opposite to the circuit pattern (3A);
One sintered body (5A) formed in a size not protruding outside from the via hole (4) by consolidating an aggregate of conductive particles by sintering is disposed one by one in each via hole (4). A sintered body arranging step,
The circuit pattern film (30A) prepared in the sintered body arrangement step is laminated and pressed while being heated, whereby the circuit pattern (3A) and the sintered body (5A) in the adjacent circuit pattern film (30A). ) In the via hole (4) to electrically connect the circuit patterns (3A) arranged in multiple layers,
A method for producing a multilayer printed circuit board, comprising:
前記導電性粒子は銀粒子と錫粒子を含んでいることを特徴とする請求項1または2に記載の多層プリント基板の製造方法。   The method for producing a multilayer printed board according to claim 1, wherein the conductive particles include silver particles and tin particles. 前記導電性粒子に対する前記錫粒子の含有比率は、20〜80重量%の範囲であることを特徴とする請求項3に記載の多層プリント基板の製造方法。   The method for producing a multilayer printed circuit board according to claim 3, wherein the content ratio of the tin particles to the conductive particles is in the range of 20 to 80% by weight. 前記焼結体(5、5A)は、銀粉末と錫粉末を含有する前記導電性粒子を溶剤と混ぜ合わせて製造したペースト(70)を、メタルマスク(80)を用いて所定形状に成形してから高温加熱することにより焼結処理し、
さらに炭化物を処理する洗浄を施すことによって製造されることを特徴とする請求項1から4のいずれか一項に記載の多層プリント基板の製造方法。
The sintered body (5, 5A) is formed by molding a paste (70) produced by mixing the conductive particles containing silver powder and tin powder with a solvent into a predetermined shape using a metal mask (80). And then sintering by heating at high temperature,
Furthermore, it manufactures by giving the washing | cleaning which processes a carbide | carbonized_material, The manufacturing method of the multilayer printed circuit board as described in any one of Claim 1 to 4 characterized by the above-mentioned.
JP2007224596A 2007-08-30 2007-08-30 Manufacturing method of multilayer printed board Pending JP2009059814A (en)

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JP2007224596A JP2009059814A (en) 2007-08-30 2007-08-30 Manufacturing method of multilayer printed board
TW097130661A TW200930197A (en) 2007-08-30 2008-08-12 Method of manufacturing multilayer printed circuit board
KR1020080081655A KR20090023130A (en) 2007-08-30 2008-08-21 Method of manufacturing multilayer printed circuit board
US12/230,219 US20090057265A1 (en) 2007-08-30 2008-08-26 Method of manufacturing multilayer printed circuit board
CNA2008102142887A CN101378634A (en) 2007-08-30 2008-08-29 Method of manufacturing multilayer printed circuit board
DE102008045003A DE102008045003A1 (en) 2007-08-30 2008-08-29 Method for producing a multilayer printed circuit board

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JP2011018728A (en) * 2009-07-08 2011-01-27 Fujikura Ltd Laminated wiring board, and method of manufacturing the same
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JP2013123031A (en) * 2011-11-07 2013-06-20 Denso Corp Conductive material and semiconductor device
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DE102013208387A1 (en) * 2013-05-07 2014-11-13 Robert Bosch Gmbh Silver composite sintered pastes for low temperature sintered joints
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JP2011018727A (en) * 2009-07-08 2011-01-27 Fujikura Ltd Circuit wiring board, and method of manufacturing the same
JP2011018728A (en) * 2009-07-08 2011-01-27 Fujikura Ltd Laminated wiring board, and method of manufacturing the same
CN103796418A (en) * 2012-10-31 2014-05-14 重庆方正高密电子有限公司 Circuit board and manufacturing method thereof

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