TW200930197A - Method of manufacturing multilayer printed circuit board - Google Patents

Method of manufacturing multilayer printed circuit board Download PDF

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Publication number
TW200930197A
TW200930197A TW097130661A TW97130661A TW200930197A TW 200930197 A TW200930197 A TW 200930197A TW 097130661 A TW097130661 A TW 097130661A TW 97130661 A TW97130661 A TW 97130661A TW 200930197 A TW200930197 A TW 200930197A
Authority
TW
Taiwan
Prior art keywords
via holes
majority
sintered body
sintered bodies
sintered
Prior art date
Application number
TW097130661A
Other languages
Chinese (zh)
Inventor
Yoshihiko Shiraishi
Kouji Kondo
Yoshitarou Yazaki
Atusi Sakaida
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of TW200930197A publication Critical patent/TW200930197A/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0263Details about a collection of particles
    • H05K2201/0272Mixed conductive particles, i.e. using different conductive particles, e.g. differing in shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0388Other aspects of conductors
    • H05K2201/0394Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

In a method of manufacturing a multilayer printed circuit board (100, 100A), a plurality of insulating substrates (1) each having a first surface and a second surface is prepared. A circuit pattern (3) is formed on each of the first surfaces of the insulating substrates (1). A plurality of via holes (4) is provide so as to extend through respective ones of the insulating substrates (1) from a side of the second surfaces in such a manner that the via holes (4) reach corresponding ones of the circuit patterns (3, 3A). Ones of a plurality of sintered bodies (5, 5A) made of conductive particles (71, 73) is inserted into corresponding ones of the via holes (4) and is fixed in the via holes (4). The insulating substrates (1) are stacked so that the circuit patterns (3, 3A) are electrically coupled through the sintered bodies (5, 5A).

Description

200930197 • 九、發明說明 【發明所屬之技術領域】 本發明關係於製造多層印刷電路板的方法。 【先前技術】 • 在傳統製造多層印刷電路板的方法中,設在多數樹脂 • 膜中之導孔係被塡入以導電膏。導電膏包含金屬粒子、有 f) 機溶劑、及樹脂作爲黏合劑。各個樹脂膜具有電路圖案層 。樹脂膜係被堆疊及多層電路圖案係經由導電膏加以電耦 合,例如於對應於日本公開 200-243 23的美國專利第 . 6,8 89,43 3 號所述。 在該製造方法中,當導電膏被塡入導孔時,一保護膜 被附接至該樹脂膜的表面。藉以,導電膏係被防止附接至 除了導孔外的該樹脂膜表面。在乾燥導電膏中之有機溶劑 後,保護膜被由樹脂膜移除。 〇 然而,當保護膜被移除時,導電膏可能破裂或落在樹 脂膜上。因此,可以發生導電異常或短路異常。更明確地 - 說,當使用高金屬含量率的導電膏,以改良連接部導電率 > 時,上述缺點變得更明顯。 【發明內容】 針對上述問題,本發明的目的係提供一多層印刷電路 板的製造方法,其可以防止由於不足導電膏的導電異常或 由於落下導電膏造成之短路異常。 -5- 200930197 * 依據製造多層印刷電路板的第一態樣的方法,多數絕 緣基材’各絕緣基材具有第一面與第二面。一電路圖案被 形成在多數絕緣基材的各個第一面,以形成多數電路圖案 。多數導孔被設置,以由第二面的一側延伸穿過多數絕緣 基材,使得多數導孔到達對應多數電路圖案。多數燒結體 * 被插入多數對應導孔,其中的多數燒結體係藉由燒結多數 * 聚結導電粒子加以形成。多數燒結體被固定於多數導孔中 Q 。多數絕緣基材被堆疊及多數電路圖案經由多數燒結體被 電耦合。 在本製造方法中,電路圖案可以電耦合,而不必將導 . 電膏塡入導孔中。因此,並不需要塡入導電膏所用之保護 膜,藉以簡化製程。再者,可以防止可能發生於保護膜移 除時的導電膏落下或噴濺。 依據製造多層印刷電路板的方法的第二態樣,備製有 各具有第一面與第二面的多數絕緣基材。一電路圖案被形 Ο 成在多數絕緣基材的各個第一面上,以形成多數電路圖案 。多數導通被設置以延伸由該等第二面的一側穿過個別多 - 數絕緣基材,使得多數導通到達對應的多數電路圖案。多 _ 數燒結體被插入多數對應的導孔中,其中多數燒結體係藉 由燒結多數聚結導電粒子加以形成,及多數燒結體具有較 多數導孔的深度爲少之高度。多數絕緣基材係被堆疊,使 得多數電路圖案係被固定至多數對應導孔。堆疊絕緣基材 係於加熱時被壓合,使得多數電路圖案與對應多數在對應 導孔中之燒結體接觸,及多數電路圖案與多數燒結體作電 -6- 200930197 耦合。 在現今製造方法中,可以取得類似依據第一態樣之製 造方法的作用。另外,因爲用以將燒結體固定至導孔中之 程序係在多數電路圖案被電耦合的同時被執行,所以,可 以簡化製程。 • 【實施方式】 ❹ 本發明之其他目的及優點將由配合附圖參考較佳實施 例的詳細說明加以迅速了解。 . (第一實施例) 依據第一實施例製造多層印刷電路板的方法將參考圖 1 A至圖4加以描述。 首先,如圖1A所示,一導電金屬層2係附接至絕緣 樹脂膜1的第一面,該樹脂膜係作爲一絕緣基材。該樹脂 Φ 膜1係爲熱塑型樹脂膜,其具有於約25微米至約75微米 間之厚度。例如,樹脂膜1由約65至約35重量%間的聚 - 醚醚酮樹脂及於3 5至約65重量%的聚醚醯亞胺加以構成 。金屬層2係由銅作成並具有例如約18微米的厚度. 然後,執行一電路圖案形成製程,用以在樹脂膜1的 第一表面上形成電路圖案3。例如,電路圖案形成製程可 以藉由蝕刻、印刷、沈積或電鍍加以執行。在本實施例中 ,電路圖案3係由蝕刻製程加以形成。在蝕刻製程中,金 屬層2係由樹脂膜1的第一面側蝕刻,如圖1B所示。藉 200930197 ' 以,形成第一電路圖案膜10。 再者,如圖1 c所示’一導孔設置程序係藉由自樹脂 膜1的第二面側照射碳氣體雷射加以執行。藉以,多數導 孔4係被設置,以延伸穿過樹脂膜1及電路圖案3變成導 孔4的底部。因此’形成第二圖案膜20。導孔4的開口直 ' 徑係被決定’以使得燒結體5之一可以插入燒結體插入程 • 序中之對應導孔4。因此’開口直徑大於燒結體5的最大 〇 尺寸。燒結體5可以例如具有球形、柱形、矩固體形、或 立方體形。 當電路圖案3被電耦合於電路圖案耦合程序中時,位 . 於導孔4的底部之的電路圖案3的部份作動爲電極。當設 置導孔4時’碳氣體雷射的輸出功率及照射時間係被控制 ,使得孔並不延伸於電路圖案3中。 替代碳氣體雷射,例如,可以使用準分子雷射,用以 設置導孔4。導孔設置程序也可以藉由使用鑽頭加以執行 〇 。藉由使用雷射束,導孔4可以作成很小,可以防止對電 路圖案3造成過量的損害。 - 再者,在燒結體插入程序中,多數燒結體5係被插入 _ 對應導孔4中,如圖1D所示。因此,形成第三電路圖案 膜3 0。燒結體5係藉由燒結聚結導電粒子加以形成。燒結 體5可以例如具有與導孔4的開口端相同的高度。或者, 燒結體5可以略微由導孔4的開口端突出。各個導孔4被 設置以在導孔4的內面與燒結體5的外面間形成一餘隙。 在此時,當燒結體5在燒結體固定程序中被變形時,變形 -8 - 200930197 量可以嵌入餘隙中。 爲了形成燒結體5 ’聚結體係由受壓狀態下的幾種導 電粒子形成’以具有預定形狀與預定大小。然後’聚結體 在熔點下的一溫度被加熱。藉以,導電粒子間有黏結力及 聚結體被固化。插入於導孔4中之燒結體5變成在電路圖 、 案耦合程序中之耦合件6。 ^ 在本實施例中,導電粒子包含銀(Ag)粒子及錫(Sn ❹ )粒子。整個導電粒子的錫含量係由約20至約80重量% 的範圍內。在實驗時,當錫含量係在由約30至約50重量 %的範圍內。當錫含量係低於約20重量%或當錫含量係高 . 於約80重量%時,設在聚結體黏結界面間之合金層變成錫 。因此,於相當於錫含量範圍由約20%至約8 0%時,於導 電特性與鍵結特性間之價變得更差。當錫含量範圍由約3 0 至約5 0重量%時,於導電特性與鍵結特性間之價被改良。 在形成燒結體5的程序中,以具有球形時,錫粒子與 〇 銀粒子的混合體被加熱於高溫。受加熱的混合體被噴灑於 旋轉碟片上並爲離心力所分散,以具有預定粒子大小。然 - 後,混合體的球體被冷卻至一預定溫度。藉此,形成包含 . 有Ag3Sn及Ag · Sn固態溶液的球型燒結體5。 當樹脂膜1的厚度被表示爲厚度T時,各個燒結體5 的最大尺寸爲範圍T至1.4T。在實驗時,當各個燒結體5 的最大尺寸爲範圍T至1.3T時,可以取得優點結果。在 當各個燒結體5具有球型時,最大尺寸爲直徑。當燒結體 5具有範圍由T至1.4T的最大尺寸時,導電特性及黏結特 200930197 ' 性係適用作爲一燒結體,其係由錫粒子及銀粒子作成。例 如,當樹脂膜1具有75微米的厚度及由銅膜作成之電路 圖案3具有1 8微米的厚度時,燒結體5係被形成以具有 90微米的直徑。在此時,即使燒結體5具有生產變動,燒 結體5的直徑係在範圍由T至1.4T的範圍內。 ' 現將參考圖2 A及2 B描述燒結體插入程序。燒結體插 * 入程序係例如藉由使用一插入設備加以執行。 ❹ 插入設備包含一金屬遮罩63,及一旋轉移動體60。 金屬遮罩63具有多數貫孔64。旋轉移動體60包含旋轉件 61及簾幕件62,其由旋轉件61懸垂下來。插入設備逐一 , 將燒結體5引入導孔4。貫孔64的直徑係被設置,使得燒 結體5的直徑可以落下通過對應貫孔64。貫孔64延伸穿 過金屬遮罩63,以對應於導孔4延伸穿過第二圖案膜20 〇 首先,第二圖案膜20係被相對於金屬遮罩63定位, 〇 使得導孔4分別對應於貫孔6 4。然後,超出導孔4數量的 燒結體5係被安置在金屬遮罩63的表面上。旋轉移動體 - 60在旋轉旋轉件61的同時,也被移動向貫孔64。燒結體 _ 5被旋轉時移動的簾幕件62所引入貫孔64中。引入穿過 貫孔64的燒結體5逐一落下穿過貫孔64並固定在導孔4 中。藉以形成其中安置有燒結體5在導孔4中之第三電路 圖案膜30。 或者,燒結體5也可以安排在第二電路圖案膜2〇的 導孔4中’而不使用金屬遮罩63,及剩餘在第二電路圖案 -10- 200930197 ' 膜20的表面上的過量燒結體5係藉由使用一 T型刮刀加 以移除。 然後,在燒結體固定程序中,燒結體5係在導孔4內 變形,如圖1Ε所示。藉此,形成耦接件6並固定於導孔 4內。因此,形成第四電路圖案膜40。 ' 燒結體固定程序可以使用各種方法加以執行。例如, * 燒結體5可以藉由加壓,以變形固定於導孔4內。燒結體 〇 5也可以藉由使用施加於燒結體5與導孔4的內表面間之 溶劑以表面張力加以固定。錫粒子也可以藉由施加一超音 波振動由銀粒子的表面分散,或者,也可以以預定溫度加 . 熱,而由銀粒子表面熔化。應注意的是,”固定”表示燒結 _ 體5具有足夠固定力量,以即使施加外力下,仍能防止移 動。結果,可以成功地執行電路圖案耦合程序,而使燒結 體5不會落在定位外。 耦接件6也可以藉由滾壓加以形成。在此時,如圖3 © 所示,藉由於旋轉的同時,移動滾子50由一側到另一側 ,而將一壓力施加至第三電路圖案膜30。藉此,燒結體5 係被變形,以配合導孔4的內部形狀。 . 再者,在電路圖案耦接程序中,由多數電路圖案膜作 成之電路圖案3係被電耦接。首先,第一電路圖案膜1〇 係被安置在例如兩個第四電路圖案膜40的多數上。第― 電路圖案膜10及兩個第四電路圖案膜40係被堆疊,使得 各個形成有電路圖案3的第一面被安排在下側及電路圖案 3朝向鄰接電路圖案膜的耦接件6。然後,於加熱的同時 -11 - 200930197 ,藉由使用真空加熱加壓設備,施加一壓力至第一電路圖 案膜10的上面及最下第四電路圖案膜40的下面。例如, 真空加熱加壓係被執行於範圍由約250°C至約3 50 °C間的 一溫度中,在範圍由IMPa至約lOMPa的壓力下,持續由 約10分至約20分的範圍內的時間。 ' 藉此,兩個第四圖案膜40及第一電路圖案膜10係被 - 熱密封並被作成一體。結果,形成如圖4所示之多層印刷 0 電路板100。在多層印刷電路板100中,鄰近電路圖案膜 的電路圖案3係透過在導孔4中之耦接件6被電耦接。 在導孔4中之耦接件6係加壓焊至位於導孔4底部的 . 電路圖案3的表面。因此,在耦接件6中之錫成份及在電 路圖案3之銅成份係互相固相擴散,及在耦接件6與電路 圖案3間設有一固相擴散層。因此,多層電路圖案3可以 電耦接。 如上所述,多層印刷電路板1 00的製造方法包含蝕刻 〇 製程、導孔設置製程、燒結體插入製程、燒結體固定製程 、及電路圖案耦合製程。在蝕刻製程中,電路圖案3係藉 . 由鈾刻附接在樹脂膜1的第一面的金屬層2加以形成。在 _ 導孔設置製程中,導孔4被設由第二面側設置於樹脂膜1 中,以到達電路圖案3。在燒結體插入製程中,多數由導 電粒子作成之燒結體5係被插入對應導孔4中。在燒結體 固定製程中,燒結體5係被固定在導孔4中,以附接至位 在導孔4的底部的電路圖案3表面。藉以,形成第四電路 圖案膜40。在電路圖案耦接製程中,堆疊多數第四電路圖 -12- 200930197 ' 案膜40,及多層電路圖案3係經由由燒結體5作成之耦接 件6所電耦接。 在本製程方法中,各個具有預定大小的燒結體5係被 安置在導孔4中。因此,導電物質可以穩固地固定於導孔 4中。因此,可以限制導孔4中之導電物質的不足及導電 ' 物質的破裂。另外,可以限制導電物質自導孔4的噴濺。 - 因爲電路圖案3可以電耦接,而不必將導電膏塡入導孔4 〇 中,也不需要塡入導電膏所用之保護膜。因此,可以簡化 製程。再者,也可以防止當保護膜被移除時,可能發生之 導電膏落下或導電膏噴濺。 (第二實施例) 現將描述依據本發明第二實施例之多層印刷電路板 100 A的製造方法。在本製造方法中,導孔設置製程、燒 結體插入製程、及電路圖案耦接製程係與第一實施例所述 © 者不同。另外,於第一實施例中所述之燒結體固定製程在 本製造方法中並不需要。其他製程係與第一實施例中所述 - 之製程類似。因此,其他製程的說明將被省略。 . 在本導孔設置製程中,導孔4係被設置以具有此一開 口直徑,其中,鄰接電路膜的電路圖案3A可以在電路圖 案耦接程序中被固定於導孔4中。 在燒結體插入製程中,具有類似於燒結體5的成份的 多數燒結體5A係被插入對應導孔4中。因此,形成第三 電路圖案膜30A。燒結體5A係具有較導孔4的深度爲低 -13- 200930197 ' 之高度。因此,燒結體5 A並不會由導孔4的開 出樹脂膜1之外側。 即,安置在導孔4中之各個燒結體5的上面 面)係定位在對應導孔4的開口端旁的表面下一 。該預定距離係小於或等於電路圖案3A的厚度 ' 5A的尺寸係與在第一實施例中之燒結體5的不 • ,燒結體5A可以以類似於燒結體5的方式加以充 φ 在燒結體插入製程後,如圖5A及5B所示, 圖案耦接製程。200930197 • IX. Description of the Invention [Technical Field of the Invention] The present invention relates to a method of manufacturing a multilayer printed circuit board. [Prior Art] • In the conventional method of manufacturing a multilayer printed circuit board, the via holes provided in most of the resin films are infiltrated with a conductive paste. The conductive paste contains metal particles, f) an organic solvent, and a resin as a binder. Each of the resin films has a circuit pattern layer. The resin film is stacked and the multilayer circuit pattern is electrically coupled via a conductive paste, for example, as described in U.S. Patent No. 6,8,89,43, to the Japanese Patent Publication No. Hei. In the manufacturing method, a protective film is attached to the surface of the resin film when the conductive paste is drawn into the via hole. Thereby, the conductive paste is prevented from being attached to the surface of the resin film except for the via holes. After drying the organic solvent in the conductive paste, the protective film is removed by the resin film. 〇 However, when the protective film is removed, the conductive paste may rupture or land on the resin film. Therefore, a conductive abnormality or a short circuit abnormality can occur. More specifically, it is said that the above disadvantage becomes more apparent when a high metal content conductive paste is used to improve the junction conductivity >. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a method of manufacturing a multilayer printed circuit board which can prevent a short circuit abnormality due to insufficient conductive abnormality of the conductive paste or dropping of the conductive paste. -5- 200930197 * According to the method of manufacturing the first aspect of the multilayer printed circuit board, the majority of the insulating substrate 'each insulating substrate has the first side and the second side. A circuit pattern is formed on each of the first faces of the plurality of insulating substrates to form a plurality of circuit patterns. A plurality of vias are provided to extend through a plurality of insulating substrates from one side of the second side such that a plurality of vias reach a corresponding majority of the circuit pattern. Most of the sintered bodies * are inserted into a plurality of corresponding via holes, and most of the sintered systems are formed by sintering a plurality of * coalesced conductive particles. Most of the sintered bodies are fixed in a plurality of via holes Q. Most of the insulating substrates are stacked and most of the circuit patterns are electrically coupled via a plurality of sintered bodies. In the present manufacturing method, the circuit pattern can be electrically coupled without having to push the conductive paste into the via hole. Therefore, it is not necessary to break into the protective film used for the conductive paste, thereby simplifying the process. Further, it is possible to prevent the conductive paste which may occur when the protective film is removed from falling or splashing. According to a second aspect of the method of manufacturing a multilayer printed circuit board, a plurality of insulating substrates each having a first side and a second side are prepared. A circuit pattern is formed on each of the first faces of the plurality of insulating substrates to form a plurality of circuit patterns. A plurality of turns are provided to extend from one side of the second faces through the individual multi-number insulating substrate such that a majority of the conduction reaches a corresponding majority of the circuit pattern. The plurality of sintered bodies are inserted into a plurality of corresponding via holes, and most of the sintered systems are formed by sintering a plurality of coalesced conductive particles, and most of the sintered bodies have a height with a smaller number of via holes. Most of the insulating substrates are stacked such that most of the circuit pattern is fixed to a plurality of corresponding via holes. The stacked insulating substrate is pressed while being heated such that a plurality of circuit patterns are in contact with a corresponding plurality of sintered bodies in the corresponding via holes, and a plurality of circuit patterns are coupled to a plurality of sintered bodies for electricity -6-200930197. In the present manufacturing method, it is possible to obtain a function similar to the manufacturing method according to the first aspect. In addition, since the program for fixing the sintered body to the via hole is performed while most of the circuit patterns are electrically coupled, the process can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the present invention will be readily understood from the following detailed description of the preferred embodiments. (First Embodiment) A method of manufacturing a multilayer printed circuit board according to the first embodiment will be described with reference to Figs. 1A to 4. First, as shown in Fig. 1A, a conductive metal layer 2 is attached to the first face of the insulating resin film 1, and the resin film serves as an insulating substrate. The resin Φ film 1 is a thermoplastic resin film having a thickness of between about 25 μm and about 75 μm. For example, the resin film 1 is composed of from about 65 to about 35 wt% of a polyether ether ketone resin and from 35 to about 65 wt% of a polyether quinone. The metal layer 2 is made of copper and has a thickness of, for example, about 18 μm. Then, a circuit pattern forming process for forming the circuit pattern 3 on the first surface of the resin film 1 is performed. For example, the circuit patterning process can be performed by etching, printing, depositing or plating. In the present embodiment, the circuit pattern 3 is formed by an etching process. In the etching process, the metal layer 2 is etched from the first face side of the resin film 1, as shown in Fig. 1B. The first circuit pattern film 10 is formed by 200930197'. Further, a guide hole setting procedure as shown in Fig. 1c is performed by irradiating a carbon gas laser from the second surface side of the resin film 1. Therefore, a plurality of via holes 4 are provided to extend through the resin film 1 and the circuit pattern 3 to become the bottom of the via hole 4. Therefore, the second pattern film 20 is formed. The opening of the guide hole 4 is determined to be such that one of the sintered bodies 5 can be inserted into the corresponding guide hole 4 in the sintered body insertion process. Therefore, the opening diameter is larger than the maximum 〇 size of the sintered body 5. The sintered body 5 may have, for example, a spherical shape, a cylindrical shape, a rectangular solid shape, or a cubic shape. When the circuit pattern 3 is electrically coupled in the circuit pattern coupling process, a portion of the circuit pattern 3 located at the bottom of the via 4 acts as an electrode. When the pilot holes 4 are provided, the output power and the irradiation time of the carbon gas laser are controlled so that the holes do not extend in the circuit pattern 3. Instead of a carbon gas laser, for example, an excimer laser can be used to provide the via hole 4. The pilot hole setting procedure can also be performed by using a drill bit. By using the laser beam, the via hole 4 can be made small to prevent excessive damage to the circuit pattern 3. Further, in the sintered body insertion process, most of the sintered body 5 is inserted into the corresponding guide hole 4 as shown in Fig. 1D. Therefore, the third circuit pattern film 30 is formed. The sintered body 5 is formed by sintering agglomerated conductive particles. The sintered body 5 can have, for example, the same height as the open end of the guide hole 4. Alternatively, the sintered body 5 may protrude slightly from the open end of the guide hole 4. Each of the guide holes 4 is provided to form a clearance between the inner face of the guide hole 4 and the outer face of the sintered body 5. At this time, when the sintered body 5 is deformed in the sintered body fixing process, the amount of deformation -8 - 200930197 can be embedded in the clearance. In order to form a sintered body, the 5' coalescing system is formed by several kinds of conductive particles in a pressurized state to have a predetermined shape and a predetermined size. The 'agglomerate' is then heated at a temperature below the melting point. Therefore, there is adhesion between the conductive particles and the agglomerates are solidified. The sintered body 5 inserted in the guide hole 4 becomes the coupling member 6 in the circuit diagram coupling case. In the present embodiment, the conductive particles contain silver (Ag) particles and tin (Sn ❹ ) particles. The tin content of the entire conductive particles is in the range of from about 20 to about 80% by weight. In the experiment, the tin content was in the range of from about 30 to about 50% by weight. When the tin content is less than about 20% by weight or when the tin content is high. At about 80% by weight, the alloy layer disposed between the agglomerate bonding interfaces becomes tin. Therefore, when the tin content is in the range of from about 20% to about 80%, the price between the conductive property and the bonding property becomes worse. When the tin content ranges from about 30 to about 50% by weight, the price between the conductive properties and the bonding characteristics is improved. In the process of forming the sintered body 5, when it has a spherical shape, the mixture of the tin particles and the silver particles is heated at a high temperature. The heated mixture is sprayed onto a rotating disc and dispersed by centrifugal force to have a predetermined particle size. After - the sphere of the mixture is cooled to a predetermined temperature. Thereby, a spherical sintered body 5 containing a solid solution of Ag3Sn and Ag·Sn was formed. When the thickness of the resin film 1 is expressed as the thickness T, the maximum size of each of the sintered bodies 5 is in the range of T to 1.4T. In the experiment, when the maximum size of each sintered body 5 is in the range of T to 1.3T, advantageous results can be obtained. When each sintered body 5 has a spherical shape, the largest dimension is a diameter. When the sintered body 5 has a maximum size ranging from T to 1.4T, the conductive property and the adhesion characteristic are applied as a sintered body which is made of tin particles and silver particles. For example, when the resin film 1 has a thickness of 75 μm and the circuit pattern 3 made of a copper film has a thickness of 18 μm, the sintered body 5 is formed to have a diameter of 90 μm. At this time, even if the sintered body 5 has a production variation, the diameter of the sintered body 5 is in the range of from T to 1.4T. The sintered body insertion procedure will now be described with reference to Figs. 2A and 2B. The sintered body insertion process is performed, for example, by using an insertion device.插入 The insertion device includes a metal mask 63 and a rotating moving body 60. The metal mask 63 has a plurality of through holes 64. The rotary moving body 60 includes a rotary member 61 and a curtain member 62 which are suspended by the rotary member 61. The sintered body 5 is introduced into the guide holes 4 one by one by inserting the devices. The diameter of the through hole 64 is set such that the diameter of the sintered body 5 can fall through the corresponding through hole 64. The through hole 64 extends through the metal mask 63 to extend through the second pattern film 20 corresponding to the guide hole 4. First, the second pattern film 20 is positioned relative to the metal mask 63, so that the guide holes 4 correspond to each other. Through the hole 6 4 . Then, the sintered body 5 exceeding the number of the guide holes 4 is placed on the surface of the metal mask 63. The rotary moving body - 60 is also moved to the through hole 64 while rotating the rotary member 61. The curtain member 62, which is moved when the sintered body _5 is rotated, is introduced into the through hole 64. The sintered bodies 5 introduced through the through holes 64 are dropped one by one through the through holes 64 and fixed in the guide holes 4. Thereby, a third circuit pattern film 30 in which the sintered body 5 is placed in the via hole 4 is formed. Alternatively, the sintered body 5 may be arranged in the via hole 4 of the second circuit pattern film 2' without using the metal mask 63, and excessive sintering remaining on the surface of the second circuit pattern-10-200930197' film 20. Body 5 is removed by using a T-blade. Then, in the sintered body fixing process, the sintered body 5 is deformed in the guide hole 4 as shown in Fig. 1A. Thereby, the coupling member 6 is formed and fixed in the guide hole 4. Thus, the fourth circuit pattern film 40 is formed. The sintered body fixing procedure can be performed using various methods. For example, the sintered body 5 can be fixed in the guide hole 4 by deformation by pressurization. The sintered body 〇 5 can also be fixed by surface tension by using a solvent applied between the sintered body 5 and the inner surface of the pilot hole 4. The tin particles may also be dispersed from the surface of the silver particles by applying an ultrasonic vibration, or may be heated at a predetermined temperature to be melted by the surface of the silver particles. It should be noted that "fixed" means that the sintered body 5 has a sufficient fixing force to prevent movement even when an external force is applied. As a result, the circuit pattern coupling procedure can be successfully performed without causing the sintered body 5 to fall outside the positioning. The coupling member 6 can also be formed by rolling. At this time, as shown in FIG. 3 ©, a pressure is applied to the third circuit pattern film 30 by moving the roller 50 from one side to the other side while rotating. Thereby, the sintered body 5 is deformed to match the inner shape of the guide hole 4. Further, in the circuit pattern coupling program, the circuit pattern 3 made of a plurality of circuit pattern films is electrically coupled. First, the first circuit pattern film 1 is placed on, for example, a majority of the two fourth circuit pattern films 40. The first - circuit pattern film 10 and the two fourth circuit pattern films 40 are stacked such that the first faces each formed with the circuit pattern 3 are arranged on the lower side and the circuit pattern 3 faces the coupling member 6 adjacent to the circuit pattern film. Then, while heating, -11 - 200930197, a pressure is applied to the upper surface of the first circuit pattern film 10 and the lowermost fourth circuit pattern film 40 by using a vacuum heating and pressing device. For example, the vacuum heating pressurization is carried out at a temperature ranging from about 250 ° C to about 35 ° C, in a range from about 10 ° to about 20 minutes at a pressure ranging from IMPa to about 10 MPa. Time inside. Thereby, the two fourth pattern films 40 and the first circuit pattern film 10 are heat sealed and integrated. As a result, a multilayer printed 0 circuit board 100 as shown in FIG. 4 is formed. In the multilayer printed circuit board 100, the circuit pattern 3 adjacent to the circuit pattern film is electrically coupled through the coupling member 6 in the via hole 4. The coupling member 6 in the guide hole 4 is pressure-welded to the surface of the circuit pattern 3 at the bottom of the guide hole 4. Therefore, the tin component in the coupling member 6 and the copper component in the circuit pattern 3 are solid-phase diffused with each other, and a solid phase diffusion layer is provided between the coupling member 6 and the circuit pattern 3. Therefore, the multilayer circuit pattern 3 can be electrically coupled. As described above, the manufacturing method of the multilayer printed circuit board 100 includes an etching process, a via hole setting process, a sintered body insertion process, a sintered body fixing process, and a circuit pattern coupling process. In the etching process, the circuit pattern 3 is formed by a metal layer 2 which is attached to the first surface of the resin film 1 by uranium. In the _ via hole setting process, the via hole 4 is provided in the resin film 1 from the second surface side to reach the circuit pattern 3. In the sintered body insertion process, a plurality of sintered bodies 5 made of conductive particles are inserted into the corresponding via holes 4. In the sintered body fixing process, the sintered body 5 is fixed in the guide hole 4 to be attached to the surface of the circuit pattern 3 located at the bottom of the via hole 4. Thereby, the fourth circuit pattern film 40 is formed. In the circuit pattern coupling process, a plurality of fourth circuit diagrams -12-200930197', the multilayer film pattern 3, and the multilayer circuit pattern 3 are electrically coupled via a coupling member 6 made of the sintered body 5. In the present process, each sintered body 5 having a predetermined size is placed in the pilot hole 4. Therefore, the conductive material can be firmly fixed in the guide hole 4. Therefore, the shortage of the conductive material in the via hole 4 and the cracking of the conductive material can be restricted. In addition, the sputtering of the conductive material from the conductive holes 4 can be restricted. - Since the circuit pattern 3 can be electrically coupled without having to insert the conductive paste into the via hole 4, it is not necessary to break into the protective film used for the conductive paste. Therefore, the process can be simplified. Further, it is also possible to prevent the conductive paste from falling or the conductive paste from splashing when the protective film is removed. (Second Embodiment) A method of manufacturing the multilayer printed circuit board 100 A according to the second embodiment of the present invention will now be described. In the manufacturing method, the via hole setting process, the sintered body insertion process, and the circuit pattern coupling process are different from those described in the first embodiment. Further, the sintered body fixing process described in the first embodiment is not required in the present manufacturing method. Other processes are similar to those described in the first embodiment. Therefore, the description of other processes will be omitted. In the present via hole setting process, the via hole 4 is provided to have such an opening diameter, wherein the circuit pattern 3A adjacent to the circuit film can be fixed in the via hole 4 in the circuit pattern coupling program. In the sintered body insertion process, a plurality of sintered bodies 5A having a composition similar to that of the sintered body 5 are inserted into the corresponding via holes 4. Thus, the third circuit pattern film 30A is formed. The sintered body 5A has a height lower than that of the guide holes 4 from -13 to 200930197 '. Therefore, the sintered body 5 A is not opened by the outer side of the resin film 1 by the via hole 4. That is, the upper surface of each of the sintered bodies 5 disposed in the guide holes 4 is positioned next to the surface beside the open end of the corresponding guide holes 4. The predetermined distance is less than or equal to the thickness '5A of the circuit pattern 3A' and the size of the sintered body 5 in the first embodiment, and the sintered body 5A can be filled in a manner similar to the sintered body 5 in the sintered body. After the insertion process, as shown in FIGS. 5A and 5B, the pattern is coupled to the process.

首先,電路圖案膜10A係安置在多數三個第 . 案膜30A及30B之上。例如,第三圖案膜30B 於圖1C所示之第三圖案膜第三電路圖案膜30的 3。第一電路圖案膜10A及第三電路圖案膜30A, 被堆疊,使得其上形成有電路圖案3或3A的各 係被安排在下側及各個電路圖案3 A係被固定於 Ο 電路圖案3A下的導孔4中。 第三電路圖案膜30A的各個電路圖案3A接 - 中之燒結體5。第一電路圖案膜10A的上面及第 30B的下面係藉由使用一真空加熱加壓設備時加 壓。例如,真空加熱加壓係被執行於約250°C至 的溫度,在範圍由約IMPa至約l〇MPa的壓力, 10分至20分的範圍。 藉此,第三圖案膜30A及30B及第一電路圖 係被加熱密封及被整合。結果,多層印刷電路板 口端延伸 (即曝露 預定距離 。燒結體 同。然而 》成。 執行電路 三電路圖 具有類似 電路圖案 S: 30B 係 個第一面 位在每一 觸導孔4 三圖案膜 熱時被加 約 3 5 0 〇C 持續由約 案膜10A 100A 係 -14- 200930197 - 被形成如圖5B所示。在多層印刷電路板1 00 A中,鄰近電 路圖案膜的電路圖案3及3A係被經由在導孔4中之燒結 體5 A而電連接。 因爲安置在導孔4中之燒結體5A係被施加預定壓力 ,所以燒結體5A接觸電路圖案3A的表面。因此,在燒 結體5中之錫成份及電路圖案3及3A的銅成份係被互相 . 固相熔合,及固相熔合層係被設在燒結體5A及電路圖案 φ 3與3A間。因此,多層電路圖案3及3A可以電耦接。 如上所述,多層印刷電路板1 〇〇A的製造方法包含: 蝕刻製程、導孔設置製程、燒結體插入製程、及電路圖案 . 耦接製程。在蝕刻製程中,電路圖案3 A係藉由蝕刻附著 至樹脂膜1的第一面上的金屬層2加以形成。在導孔設置 製程中,導孔4係被設置,以由第二面延伸穿過樹脂膜1 ,以到達電路圖案3A。在燒結體插入製程中,燒結體5A 之一係被插入對應導孔4中,藉此,形成電路圖案膜30A φ 。在此時,各個燒結體5具有此一尺寸,使得各個燒結體 5並不由導孔4突出至外部。在電路圖案耦接製程中,第 . 三電路圖案膜30A被熱加壓,使得電路圖案3A接觸導孔 4中之燒結體5A。藉此,多層電路圖案3係被電耦接。 在本製造方法中,可以取得類似於第一實施例的效果 。另外,因爲用以固定於導孔4中之燒結體5A的製程係 被執行於多層電路圖案3A被電耦接的同時,所以製程可 以簡化。 -15- 200930197 ' (第三實施例) 依據本發明第三實施例的燒結體的製造方法將參考圖 6A至6D加以描述。爲本製造方法所製造之燒結體可以被 使用於依據第一及第二實施例的多層印刷電路板的製造方 法。 _ 首先,錫粒子71及銀粒子73係被加入至溶劑72中 並被混合以形成導電膏70。例如,銀粒子73具有約1微 〇 米的平均粒子大小及約1.2m2/g的比表面積。錫粒子71具 有約燒結體5微米的平均粒子大小及約〇.5m2/g的比表面 積。溶劑72例如包含松油醇。包含溶劑72的樹脂成份作 - 爲用以固持整個導電粒子形狀的黏結劑。整個導電粒子的 錫含量可以類似於第一實施例之錫含量。例如,銀粒子73 對錫粒子7 1的含量比約6 5 : 3 5。 包含導電粒子聚結之導電膏7〇係被形成以具有預定 形狀,以藉由以金屬遮罩80而膏印刷。金屬遮罩80具有 © 多數具有預定形狀的貫孔81。例如,各個貫孔81具有約 5〇微米的深度及約多層印刷電路板1〇〇微米的內徑。金屬 - 遮罩80係被安置在具有釋放特性的基材82上。例如,基 材82係由氟樹脂作成。包含錫粒子71、銀粒子73及溶劑 72的預定量之導電膏70係被設在金屬遮罩8〇的表面上。 然後,導電膏70係藉由使用刷子83而噴在金屬遮罩8〇 的整個表面上。藉此’導電膏70被塡入金屬遮罩80的貫 孔8 1中,如圖6 A所示。 當金屬遮罩80被抬舉於垂直方向時,具有碟形的多 -16- 200930197 • 數導電膏7〇係被殘留在基材82上,如圖6B所示。各碟 片具有與貫孔81的內徑大致相同的側形及與金屬遮罩80 的厚度大致相同的高度。 再者’如圖6C所示,碟片形導電膏70係被燒結於約 260°C的溫度。藉此,形成燒結體74。熱處理可以藉由使 _ 用一通用迴焊爐、蒸氣迴焊爐、焙燒氣氛爐或箱型爐加以 - 執行。熱處理可以執行一還原氣氛中,用以防止錫成份的 ❹ 氧化。 當導電膏70被燒結時,包含松油醇的溶劑72係被蒸 發並乾燥,及錫粒子71及銀粒子73係被混合。錫粒子71 . 的熔點約23 2 °C。因此,當加熱溫度變成260°C時,錫粒 子71被熔化並附接至銀粒子73的表面。當熱處理被保持 於上述狀態時,熔化錫被由銀粒子的表面擴散。藉此,形 成由錫及銀作成之燒結體74。 再者,如圖6D所示,燒結體74係被以清潔劑83加 Φ 以清洗,以移除碳化物。被清洗的燒結體74係被乾燥, 藉以提供了用於燒結體插入製程的燒結體5及5A。 . 如上所述,包含錫粒子71、銀粒子73及溶劑72的導 電膏70係被形成爲預定形狀並被熱處理所燒結。然後, 燒結體74被清洗以移除碳化物,藉以提供用於燒結體插 入製程的燒結體5及5A。 在本製造方法中,燒結體5及5A係使用金屬遮罩80 作出形狀。因此’燒結體5及5A可以以高度準確度加以 大量生產,及改良多層印刷電路板100及100A的導電特 200930197 性及黏結特性。 (其他實施例) 雖然本發明已經整個以較佳實施例參考附圖加以描述 ,但應了解的各種改變及修改可以爲熟習於本技藝者所了 ' 解。 - 在上述第一與第二實施例中,樹脂膜1係由約65至 φ 約35重量%間之聚醚醚酮樹脂及於約35至65重量%的聚 醚醯亞胺樹脂所構成。樹脂膜1也可以包含聚醚醚酮樹脂 、聚醚醯亞胺樹脂、及非導電塡料。或者,樹脂膜1也可 . 以包含聚醚醚酮(PEEK)或聚醚醯亞胺(PEI)。 依據第一實施例之多層印刷電路板1〇〇具有三層及依 據第二實施例之多層印刷電路板100A具有四層。多層電 路板的數量並不限於上述例子,只要多層印刷電路板1 00 及100A各具有多層電路圖案即可。 【圖式簡單說明】 - 圖1A至1E爲依據本發明第一實施例之多層印刷電路 _ 板的例示製程的剖面圖; 圖2A及2B爲顯示例示燒結體插入程序的圖表; 圖3爲例示燒結體固定程序圖; 圖4爲例示電路圖案耦合程序圖; 圖5A及5B爲依據第二實施例之例示電路圖案耦合程 序的示意圖;及 -18- 200930197 ' 圖6A至6D爲依據第三實施例之燒結體的例示製程 的示意圖。 【主要元件符號說明】 1 :絕緣樹脂膜 — 2 :導電金屬層 - 3 :電路圖案 ❹ 4 :導孔 5 : 燒結體 6 : 耦接件 10 : 第一電路圖案膜 20 : 第二圖案膜 30 : 第三電路圖案膜 40 : 第四電路圖案膜 60 : 旋轉移動體 61 : 旋轉件 62 : 簾幕件 63 : 金屬遮罩 64 : 貫孔 50 : 滾子 3 A :電路圖案 5 A :燒結體 1 0A :第一電路圖案膜 30A :第三電路圖案膜 -19- 200930197 • 30B:第三電路圖案膜 70 :導電膏 7 1 :錫粒子 72 :溶劑 7 3 :銀粒子 _ 74 :燒結體 - 80 :金屬遮罩 ^ 8 1 :貫孔 82 :基材 8 3 :刷子 -20First, the circuit pattern film 10A is placed over most of the three film films 30A and 30B. For example, the third pattern film 30B is 3 of the third pattern film third circuit pattern film 30 shown in Fig. 1C. The first circuit pattern film 10A and the third circuit pattern film 30A are stacked such that the respective lines on which the circuit patterns 3 or 3A are formed are arranged on the lower side and the respective circuit patterns 3 A are fixed under the 电路 circuit pattern 3A. In the guide hole 4. The respective circuit patterns 3A of the third circuit pattern film 30A are connected to the sintered body 5 in the middle. The upper surface of the first circuit pattern film 10A and the lower surface of the 30B are pressed by using a vacuum heating and pressurizing device. For example, the vacuum heating pressurization is carried out at a temperature of from about 250 ° C to a range of from about 1 MPa to about 10 MPa, in the range of from 10 minutes to 20 minutes. Thereby, the third pattern films 30A and 30B and the first circuit pattern are heat sealed and integrated. As a result, the end of the multilayer printed circuit board is extended (i.e., exposed to a predetermined distance. The sintered body is the same. However). The circuit of the execution circuit has a similar circuit pattern S: 30B is a first facet in each of the contact holes 4 When heat is added, about 305 〇C is continuously formed by the film 10A 100A series-14-200930197 - as shown in Fig. 5B. In the multilayer printed circuit board 100 A, the circuit pattern 3 adjacent to the circuit pattern film and 3A is electrically connected via the sintered body 5 A in the guide hole 4. Since the sintered body 5A placed in the guide hole 4 is applied with a predetermined pressure, the sintered body 5A contacts the surface of the circuit pattern 3A. The tin component in the body 5 and the copper component of the circuit patterns 3 and 3A are mutually solid-phase fused, and the solid phase fusion layer is provided between the sintered body 5A and the circuit patterns φ 3 and 3A. Therefore, the multilayer circuit pattern 3 And 3A can be electrically coupled. As described above, the manufacturing method of the multilayer printed circuit board 1 〇〇A includes: an etching process, a via hole setting process, a sintered body insertion process, and a circuit pattern. A coupling process. In the etching process, Circuit pattern 3 A It is formed by etching a metal layer 2 attached to the first surface of the resin film 1. In the via hole setting process, the via hole 4 is provided to extend through the resin film 1 from the second surface to reach the circuit pattern 3A. In the sintered body insertion process, one of the sintered bodies 5A is inserted into the corresponding via hole 4, whereby the circuit pattern film 30A φ is formed. At this time, each of the sintered bodies 5 has such a size that each sintered body 5 is not protruded to the outside by the via hole 4. In the circuit pattern coupling process, the third circuit pattern film 30A is thermally pressed so that the circuit pattern 3A contacts the sintered body 5A in the via hole 4. Thereby, the multilayer circuit pattern 3 is electrically coupled. In the present manufacturing method, effects similar to those of the first embodiment can be obtained. In addition, since the process for fixing the sintered body 5A in the via hole 4 is performed on the multilayer circuit pattern 3A At the same time as the electrical coupling, the process can be simplified. -15- 200930197 ' (Third embodiment) A method of manufacturing a sintered body according to a third embodiment of the present invention will be described with reference to Figs. 6A to 6D. Sintered body can be A method of manufacturing a multilayer printed circuit board according to the first and second embodiments. First, tin particles 71 and silver particles 73 are added to a solvent 72 and mixed to form a conductive paste 70. For example, silver particles 73 It has an average particle size of about 1 micrometer and a specific surface area of about 1.2 m 2 /g. The tin particles 71 have an average particle size of about 5 μm of the sintered body and a specific surface area of about 0.5 m 2 /g. The solvent 72 contains, for example, pine oil. The alcohol component of the solvent 72 is used as a binder for holding the entire shape of the conductive particles. The tin content of the entire conductive particles may be similar to the tin content of the first embodiment. For example, the content of silver particles 73 to tin particles 71 is about 6 5 : 3 5 . A conductive paste 7 containing conductive particles agglomerated is formed to have a predetermined shape to be paste-printed by a metal mask 80. The metal mask 80 has a plurality of through holes 81 having a predetermined shape. For example, each of the through holes 81 has a depth of about 5 Å and an inner diameter of about 1 〇〇 of the multilayer printed circuit board. The metal-mask 80 is placed on a substrate 82 having release characteristics. For example, the base material 82 is made of a fluororesin. A predetermined amount of the conductive paste 70 containing the tin particles 71, the silver particles 73, and the solvent 72 is provided on the surface of the metal mask 8A. Then, the conductive paste 70 is sprayed on the entire surface of the metal mask 8 by using the brush 83. Thereby, the conductive paste 70 is immersed in the through hole 81 of the metal mask 80 as shown in Fig. 6A. When the metal mask 80 is lifted in the vertical direction, a plurality of conductive pastes 7 having a dish shape are left on the substrate 82 as shown in Fig. 6B. Each of the discs has a side shape substantially the same as the inner diameter of the through hole 81 and a height substantially the same as the thickness of the metal mask 80. Further, as shown in Fig. 6C, the disk-shaped conductive paste 70 is sintered at a temperature of about 260 °C. Thereby, the sintered body 74 is formed. The heat treatment can be carried out by using a general reflow furnace, a steam reflow furnace, a roasting atmosphere furnace or a box furnace. The heat treatment can be carried out in a reducing atmosphere to prevent oxidation of the tin component. When the conductive paste 70 is sintered, the solvent 72 containing terpineol is evaporated and dried, and the tin particles 71 and the silver particles 73 are mixed. The melting point of tin particles 71 . is about 23 2 °C. Therefore, when the heating temperature becomes 260 ° C, the tin particles 71 are melted and attached to the surface of the silver particles 73. When the heat treatment is maintained in the above state, the molten tin is diffused from the surface of the silver particles. Thereby, a sintered body 74 made of tin and silver is formed. Further, as shown in Fig. 6D, the sintered body 74 is pulverized with a cleaning agent 83 to remove carbides. The sintered body 74 to be cleaned is dried to provide sintered bodies 5 and 5A for the sintered body insertion process. As described above, the conductive paste 70 containing the tin particles 71, the silver particles 73, and the solvent 72 is formed into a predetermined shape and sintered by heat treatment. Then, the sintered body 74 is washed to remove carbides, thereby providing the sintered bodies 5 and 5A for the sintered body insertion process. In the present manufacturing method, the sintered bodies 5 and 5A are formed in a shape using a metal mask 80. Therefore, the sintered bodies 5 and 5A can be mass-produced with high accuracy, and the conductive characteristics and bonding characteristics of the multilayer printed circuit boards 100 and 100A are improved. (Other Embodiments) While the present invention has been described in detail with reference to the preferred embodiments thereof, it is understood that various modifications and changes may be made by those skilled in the art. - In the above first and second embodiments, the resin film 1 is composed of a polyetheretherketone resin of about 65 to φ of about 35% by weight and a polyetheretherimide resin of about 35 to 65 wt%. The resin film 1 may also contain a polyetheretherketone resin, a polyetherimide resin, and a non-conductive pigment. Alternatively, the resin film 1 may also contain polyetheretherketone (PEEK) or polyetherimide (PEI). The multilayer printed circuit board 1 of the first embodiment has three layers and the multilayer printed circuit board 100A according to the second embodiment has four layers. The number of the multilayer circuit boards is not limited to the above example as long as the multilayer printed circuit boards 100 and 100A each have a multilayer circuit pattern. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1E are cross-sectional views showing an exemplary process of a multilayer printed circuit board according to a first embodiment of the present invention; FIGS. 2A and 2B are diagrams showing an exemplary sintered body insertion procedure; FIG. 3 is an illustration. FIG. 4 is a schematic diagram showing a circuit pattern coupling procedure; FIG. 5A and FIG. 5B are schematic diagrams showing an exemplary circuit pattern coupling procedure according to the second embodiment; and -18-200930197'. FIGS. 6A to 6D are diagrams according to a third embodiment. A schematic of an exemplary process for a sintered body of the example. [Main component symbol description] 1 : Insulating resin film - 2 : Conductive metal layer - 3 : Circuit pattern ❹ 4 : Conductor 5 : Sintered body 6 : Coupling member 10 : First circuit pattern film 20 : Second pattern film 30 : Third circuit pattern film 40 : Fourth circuit pattern film 60 : Rotating moving body 61 : Rotating member 62 : Curtain member 63 : Metal mask 64 : Through hole 50 : Roller 3 A : Circuit pattern 5 A : Sintered body 1 0A : First circuit pattern film 30A : Third circuit pattern film -19- 200930197 • 30B: Third circuit pattern film 70 : Conductive paste 7 1 : Tin particles 72 : Solvent 7 3 : Silver particles _ 74 : Sintered body - 80: metal mask ^ 8 1 : through hole 82: substrate 8 3 : brush -20

Claims (1)

200930197 十、申請專利範園 1.—種製造多層印刷電路板(100、100A)的方法, 包含: 備製多數絕緣基材(丨),各絕緣基材具有第一面與 第二面; 在該多數絕緣基材(1)的各個第一面上’形成電路 . 圖案(3、3A),以形成該多數電路圖案(3、3A); Q 設置多數導孔(4) ’以由該第二面的一側延伸穿過 多數絕緣基材(1)的個別絕緣基材,使得該多數導孔(4 )到達該多數電路圖案(3、3A)的對應電路圖案; . 將多數燒結體(5、5A)插入多數導孔(4)的對應導 孔中,該多數燒結體(5、5A)係藉由燒結多數聚結導電 粒子(71、73 )加以形成; 將多數燒結體(5、5 A )固定於該多數導孔(4 )中; 及 〇 堆疊該多數絕緣基材(1)並透過多數燒結體(5、5A )電路至該多數電路圖案(3、3A)。 . 2 ·如申請專利範圍第1項所述之方法,其中: 該導電粒子(71、73 )包含銀粒子(73 )及錫粒子( 71 ) ° 3 .如申請專利範圍第2項所述之方法,其中: 該整個導電粒子(71、73 )的錫含量的範圍係由約2〇 至約8 0重量%。 4.如申請專利範圍第3項所述之方法,其中: -21 - 200930197 _ 該整個導電粒子(71、73)的該錫含量的範圍係由約 30至約50重量%。 5 ·如申請專利範圍第1項所述之方法,其中: 該各個多數燒結體(5)的最大尺寸與該各個多數絕 緣基材(1 )的厚度的比率係在範圍由約1至約1.4間。 6.如申請專利範圍第5項所述之方法,其中: • 該各個多數燒結體(5)的最大尺寸與該各個多數絕 Ο 緣基材(1)的厚度的比率係在範圍由約1至約1.3間。 7 ·如申請專利範圍第1項所述之方法,其中: 當該多數燒結體(5)被固定至該多數導孔(4)時, - 該各個多數燒結體(5)係被變形。 . 8.如申請專利範圍第7項所述之方法,其中: 當該多數燒結體(5)的多數燒結體被插入該多數導 孔(4)的對應導孔時,該多數燒結體(5)的多數燒結體 與該多數導孔(4 )的對應導孔間具有一餘隙;及 ® 當該多數燒結體(5)被固定至該多數導孔(4)時, 該多數燒結體(5)的該變形量嵌入該餘隙中。 - 9.如申請專利範圍第丨至8項中任一項所述之方法, . 其中該多數燒結體(5)的製造方法包含: 混合包含銀粒子(73 )及錫粒子(7 1 )的該導電粒子 (71、73)與一溶劑(72),以提供一膏(70); 藉由使用一遮罩(80),將該膏(70)形成爲預定形 狀; 燒結該膏(70 );及 -22- 200930197 • 清洗該被燒結膏(74),用以移除碳化物。 1〇.—種製造多層印刷電路板(100A)的方法,包含 備製多數絕緣基材(1),各基材具有第一面與第二 面; ' 在該多數絕緣基材(1)的各個該第一面上,形成一 • 電路圖案(3A),以形成多數電路圖案(3A); 〇 設置多數導孔(4),由該第二面的一側延伸穿過該 多數絕緣基材(1)的個別絕緣基材,使得該多數導孔(4 )到達該多數電路圖案(3A)的對應電路圖案; 、 將多數燒結體(5A)插入多數導孔(4)的對應導孔 _ ’該多數燒結體(5A)係藉由燒結多數導電粒子(71、73 )的聚結加以形成,該多數燒結體(5 A )具有小於該多數 導孔(4 )深度的高度; 堆疊該多數絕緣基材(1),使得該多數電路圖案( © 3A)的多數電路圖案被固定至該多數導孔(4)的對應導 孔中;及 - 在加熱時,加壓該堆疊的絕緣基材(1 ),使得該多 數電路圖案(3A)與在該對應導孔(4)中之多數燒結體 (5A)的對應燒結體接觸,以及,多數電路圖案(3A) 係透過多數燒結體(5、5 A )加以電耦接。 1 1 ·如申請專利範圍第1 〇項所述之方法,其中: 該導電粒子(Ή、73 )包含銀粒子(π )及錫粒子( 7 1) 〇 -23- 200930197 ' 1 2 ·如申請專利範圍第1 1項所述之方法,其中: 該整個導電粒子(71、73)的錫含量係在範圍由 至約80重量%內。 1 3 ·如申請專利範圍第1 2項所述之方法,其中: 該整個導電粒子(71、73)的錫含量係在範圍由 至約50重量%內。 • 1 4 ·如申請專利範圍第i 〇項所述之方法,其中: 〇 當該多數燒結體(5A)之多數燒結體被插入該多 孔(4)的對應導孔時,該多數燒結體(5A)的多數 體的曝露面係定位在離開該多數導孔(4)的對應導 , 開口端一預定距離;及 ^ 該預定距離係小於等於該多數電路圖案(3A)的 〇 1 5 ·如申請專利範圍第1 〇至丨4項中任一項所述 法’其中該多數燒結體(5A)的製造方法包含: © 混合包括有銀粒子(73)及錫粒子(71)的該導 子(71、73 )與溶劑(72 ),以提供一膏(70 ); - 藉由使用一遮罩(80 ),以將該膏形成爲預定形 燒結該膏(7〇 );及 清洗該燒結膏(74 ),用以移除碳化物。 約20 約30 數導 燒結 孔的 厚度 之方 電粒 狀; -24-200930197 X. Application for Patent Park 1. A method for manufacturing a multilayer printed circuit board (100, 100A), comprising: preparing a plurality of insulating substrates (丨), each insulating substrate having a first side and a second side; Each of the first surfaces of the plurality of insulating substrates (1) 'forms a circuit. Pattern (3, 3A) to form the majority of the circuit patterns (3, 3A); Q sets a plurality of via holes (4)' by the first One side of the two sides extends through the individual insulating substrates of the plurality of insulating substrates (1) such that the plurality of vias (4) reach corresponding circuit patterns of the plurality of circuit patterns (3, 3A); 5, 5A) inserted into the corresponding via holes of the plurality of via holes (4), the majority of the sintered bodies (5, 5A) are formed by sintering a plurality of coalesced conductive particles (71, 73); a plurality of sintered bodies (5, 5 A ) is fixed in the plurality of via holes (4); and the plurality of insulating substrates (1) are stacked and passed through a plurality of sintered body (5, 5A) circuits to the plurality of circuit patterns (3, 3A). 2. The method of claim 1, wherein: the conductive particles (71, 73) comprise silver particles (73) and tin particles (71) ° 3 as described in claim 2 The method wherein: the tin content of the entire conductive particles (71, 73) ranges from about 2 Torr to about 80% by weight. 4. The method of claim 3, wherein: -21 - 200930197 _ the tin content of the entire conductive particle (71, 73) ranges from about 30 to about 50% by weight. 5. The method of claim 1, wherein: the ratio of the maximum size of each of the plurality of sintered bodies (5) to the thickness of each of the plurality of insulating substrates (1) is in the range of from about 1 to about 1.4. between. 6. The method of claim 5, wherein: • a ratio of a maximum size of each of the plurality of sintered bodies (5) to a thickness of each of the plurality of insulating substrates (1) is in a range of about 1 To about 1.3. 7. The method of claim 1, wherein: when the plurality of sintered bodies (5) are fixed to the plurality of via holes (4), the plurality of sintered bodies (5) are deformed. 8. The method according to claim 7, wherein: when a plurality of sintered bodies of the plurality of sintered bodies (5) are inserted into corresponding guide holes of the plurality of via holes (4), the plurality of sintered bodies (5) a plurality of sintered bodies having a clearance between the corresponding via holes of the plurality of via holes (4); and a majority of the sintered bodies when the plurality of sintered bodies (5) are fixed to the plurality of via holes (4) The amount of deformation of 5) is embedded in the clearance. 9. The method according to any one of the preceding claims, wherein the method of manufacturing the majority of the sintered body (5) comprises: mixing the silver particles (73) and the tin particles (71) The conductive particles (71, 73) and a solvent (72) to provide a paste (70); the paste (70) is formed into a predetermined shape by using a mask (80); sintering the paste (70) ; and -22- 200930197 • Clean the sintered paste (74) to remove carbides. 1 . A method of manufacturing a multilayer printed circuit board (100A) comprising preparing a plurality of insulating substrates (1) each having a first side and a second side; 'in the majority of the insulating substrate (1) Each of the first faces forms a circuit pattern (3A) to form a plurality of circuit patterns (3A); a plurality of via holes (4) are disposed, and one side of the second surface extends through the plurality of insulating substrates The individual insulating substrates of (1) are such that the plurality of via holes (4) reach the corresponding circuit patterns of the plurality of circuit patterns (3A); and the plurality of sintered bodies (5A) are inserted into the corresponding via holes of the plurality of via holes (4)_ 'The majority of the sintered body (5A) is formed by sintering a plurality of conductive particles (71, 73) having a height smaller than the depth of the plurality of via holes (4); stacking the majority An insulating substrate (1) such that a plurality of circuit patterns of the plurality of circuit patterns (© 3A) are fixed to corresponding via holes of the plurality of via holes (4); and - when heated, pressurizing the stacked insulating substrate (1) such that the majority of the circuit pattern (3A) is in the corresponding via hole (4) A plurality of sintered bodies (5A) are in contact with corresponding sintered bodies, and a plurality of circuit patterns (3A) are electrically coupled through a plurality of sintered bodies (5, 5 A ). The method according to the first aspect of the invention, wherein: the conductive particles (Ή, 73) comprise silver particles (π) and tin particles (7 1) 〇-23- 200930197 ' 1 2 · If applied The method of claim 11, wherein: the tin content of the entire conductive particles (71, 73) is in the range of from about 80% by weight. The method of claim 12, wherein: the tin content of the entire conductive particles (71, 73) is in the range of from about 50% by weight. The method of claim i, wherein: ???When a majority of the sintered body of the majority of the sintered body (5A) is inserted into the corresponding via hole of the porous (4), the majority of the sintered body ( The exposed surface of the majority of the body of 5A) is positioned at a corresponding guide away from the plurality of vias (4), the open end being a predetermined distance; and the predetermined distance is less than or equal to the majority of the circuit pattern (3A). The method of any one of claims 1 to 4 wherein the method of manufacturing the majority of the sintered body (5A) comprises: © mixing the derivative including silver particles (73) and tin particles (71) (71, 73) and a solvent (72) to provide a paste (70); - sintering the paste (7〇) by using a mask (80) to form the paste into a predetermined shape; and cleaning the sintering Paste (74) to remove carbides. Approximately 20 to about 30. The thickness of the sintered hole is in the shape of an electric grain; -24-
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