JP2009049379A - 半導体メモリ素子の誘電体膜形成方法 - Google Patents

半導体メモリ素子の誘電体膜形成方法 Download PDF

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JP2009049379A
JP2009049379A JP2008175137A JP2008175137A JP2009049379A JP 2009049379 A JP2009049379 A JP 2009049379A JP 2008175137 A JP2008175137 A JP 2008175137A JP 2008175137 A JP2008175137 A JP 2008175137A JP 2009049379 A JP2009049379 A JP 2009049379A
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film
forming
semiconductor memory
memory device
dielectric film
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Jae Mun Kim
在 文 金
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

【課題】本発明は、フローティングゲート及びコントロールゲートの間に形成する誘電体膜を第１の絶縁膜、第２の絶縁膜及び第３の絶縁膜の積層構造で形成するが、第２の絶縁膜を高誘電体膜で形成して半導体素子の電気的特性を向上させ、第２の絶縁膜にプラズマ処理工程を行って第２の絶縁膜の表面を均一にすると共に、第２の絶縁膜の結晶化を抑制し、半導体メモリ素子の漏洩電流の発生を防止することができる半導体メモリ素子の誘電体膜形成方法を提供することを可能にすることを目的としている。
【解決手段】 半導体基板上に高誘電体膜を形成する段階と、高誘電体膜を結晶化しないながら膜質を均一にするプラズマ処理工程を行う段階とを含む構成としたことを特徴とする。
【選択図】 図１

Description

本発明は、半導体メモリ素子の誘電体膜形成方法に関するものであり、特に、半導体メモリ素子の電気的特性を向上させることができる半導体メモリ素子の誘電体膜形成方法に関するものである。
半導体メモリ素子の中で、フラッシュメモリ素子を例として説明すれば、次の通りである。一般に、フラッシュメモリ素子は、半導体基板上にトンネル絶縁膜、フローティングゲート、誘電体膜及びコントロールゲートが積層された構造で形成される。トンネル絶縁膜と誘電体膜は、フローティングゲートを隔離することは役割をする。さらに具体的に説明すれば、トンネル絶縁膜は半導体基板とフローティングゲートとの間で電子のトンネリング(tunneling)を調節し、誘電体膜はフローティングゲートとコントロールゲートとの間でカップリング(coupling)を調節する役割をする。
このうち、誘電体膜は、第１の絶縁膜、第２の絶縁膜及び第３の絶縁膜が順に積層された構造で形成される。第1及び第３の絶縁膜は酸化膜で形成し、第２の絶縁膜は窒化膜で形成するが、窒化膜で形成した後に窒化膜の膜質を均一にするために熱処理工程を行う。しかし、熱処理工程時、高温により窒化膜が結晶化されやすく、トンネル絶縁膜に熱的欠陷が発生しやすい。また、窒化膜が結晶化されれば、半導体メモリ素子に漏洩電流が発生しやすいため、電気的特性の低下を誘発することができる。
本発明が解決しようとする課題は、フローティングゲート及びコントロールゲートの間に形成する誘電体膜を第１の絶縁膜、第２の絶縁膜及び第３の絶縁膜の積層構造で形成するが、第２の絶縁膜を高誘電体膜で形成して半導体素子の電気的特性を向上させ、第２の絶縁膜にプラズマ処理工程を行って第２の絶縁膜の表面を均一にすると共に、第２の絶縁膜の結晶化を抑制し、半導体メモリ素子の漏洩電流の発生を防止することができる。
本発明の一実施例による半導体メモリ素子の誘電体膜形成方法は、半導体基板上に高誘電体膜を形成する。高誘電体膜を結晶化しないながら膜質を均一にするプラズマ処理工程を行う段階を含む半導体メモリ素子の誘電体膜形成方法で構成される。
本発明の他の実施例による半導体メモリ素子の誘電体膜形成方法は、トンネル絶縁膜、第１の導電膜及び素子分離膜が形成された半導体基板が提供される。第１の導電膜及び素子分離膜上に第１の絶縁膜を形成する。第１の絶縁膜上に第２の絶縁膜を形成する。第２の絶縁膜の膜質を均一にする先処理工程を行う。第２の絶縁膜上に第３の絶縁膜を形成する段階を含む半導体メモリ素子の誘電体膜形成方法で構成される。
第３の絶縁膜上に第２の導電膜を形成する段階をさらに含み、第２の絶縁膜は高誘電体膜(high-k)で形成する。高誘電体膜は２０Å〜１５０Åの厚さで形成し、原子層蒸着法（ＡＬＤ）で形成する。
原子層蒸着法（ＡＬＤ）は２００℃〜６００℃の温度を加えて行い、ソースガス注入工程、パージ工程及び反応ガス注入工程を単位サイクルとし、単位サイクルを繰り返して形成する。
反応ガスは、Ｏ２、Ｈ２Ｏ及びＯ３のいずれか一つまたはこれらを混合して注入し、高誘電体膜はソースガスの種類によりＡｌ２Ｏ３、ＨｆＯ２、ＺｒＯ２、ＳｉＯＮ、Ｌａ２Ｏ３、Ｙ２Ｏ３、ＴｉＯ２、ＣｅＯ２、Ｎ２Ｏ３、Ｔａ２Ｏ５、ＢａＴｉＯ３、ＳｒＴｉＯ３、ＢＳＴまたはＰＺＴのいずれか一つで形成するか、またはこれらの二つ以上を積層して形成する。
先処理工程はプラズマ処理工程(Plasma treatment)で行い、プラズマ処理工程はラジカル(radical)を用いたプラズマ酸化工程(Plasma Oxidation)で行う。
プラズマ酸化工程はＡｒガスとＯ２ガスを混合したガスを用い、混合したガスにＨ２ガスをさらに混合して行う。
プラズマ酸化工程は、０．０１Torr〜１０Torrの圧力で１ｋＷ〜５ｋＷのパワー(power)を加え、３００℃〜６００℃の温度を加えて行う。
第１及び第２の絶縁膜は２０Å〜５０Åの厚さの酸化膜で形成し、酸化膜は６００℃〜９００℃の温度を加えて低圧化学的気相蒸着法（ＬＰ−ＣＶＤ）で形成する。
酸化膜は、ＳｉＣｌ２Ｈ２及びＮ２Ｏ２ガスを反応させてＤＣＳ−ＨＴＯ(DiChloroSilane High Temperature Oxide)膜で形成する。
本発明のまた他の実施例による半導体メモリ素子の誘電体膜形成方法は、第１の絶縁膜が形成された半導体基板が提供される。第１の絶縁膜上に高誘電体物質で第２の絶縁膜を形成する。第２の絶縁膜上に第３の絶縁膜を形成する段階を含む半導体メモリ素子の誘電体膜形成方法で構成される。
第３の絶縁膜を形成する前に、第２の絶縁膜の表面を均一にするプラズマ処理工程を行う段階をさらに含む。
本発明は、半導体メモリ素子の誘電体膜を形成するにおいて、誘電体膜で第１の絶縁膜、第２の絶縁膜及び第３の絶縁膜を形成するが、第1及び第３の絶縁膜は酸化膜で形成し、第２の絶縁膜は高誘電体膜で形成することにより誘電率を高めることができ、破壊電圧(breakdown voltage)を高めることができ、フラットバンド電圧(flatband voltage)の移動を防止することができる。また、充電容量の増加とセル(cell)間の干渉(interference)現象を減少させることができる。
そして、高誘電体膜が形成された半導体基板にプラズマ処理工程を行うことにより、高誘電体膜の結晶化を防止しながら膜質が均一にすることができ、これにより漏洩電流の発生を抑制することができ、トンネル絶縁膜の熱的欠陷を防止することができるため、半導体メモリ素子の信頼度を向上させることができる。
添付した図面を参照し、本発明の好ましい実施例を説明する。しかし、本発明は、以下に開示される実施例により限定されるものではなく、互いに異なる多様な形態で具現されることができ、単に、本実施例は本発明の開示が完全であるようにし、通常の知識を有する者に発明の範疇を完全に知らせるために提供されるものである。
図１及び図２は、本発明による半導体メモリ素子の誘電体膜形成方法を説明するための断面図である。
図１（ａ）を参照すれば、半導体基板100の上部にトンネル絶縁膜102及びフローティングゲート用第１の導電膜104を順に形成する。トンネル絶縁膜102は、酸化膜で形成することが望ましく、第１の導電膜104はポリシリコン膜で形成することが好ましい。
図面には示されていないが、トレンチを形成した後、トレンチ内に素子分離膜(図示せず)を形成する。本図面は、素子分離膜と平行な断面を示したため、素子分離膜が示されていない(以下、‘図示せず’と記載する)に留意しなければならない。素子分離膜(図示せず)を形成する方法を具体例として説明すれば、第１の導電膜104の上部に素子分離マスクパターン(図示せず)を形成し、素子分離マスクパターン(図示せず)に沿ってエッチング工程を行って第１の導電膜104及びトンネル絶縁膜102をパターニングし、露出した半導体基板100をエッチングしてトレンチ(図示せず)を形成する。トレンチ(図示せず)の内部に素子分離膜(図示せず)を形成し、素子分離マスクパターン(図示せず)を除去する。次いで、素子分離膜(図示せず)のＥＦＨ(effective field oxide height)を調節する。
図１（ｂ）を参照すれば、第１の導電膜104及び前記素子分離膜の上部に誘電体膜用第１の絶縁膜106を形成する。第１の絶縁膜106は、酸化膜で形成することができる。具体的に説明すれば、酸化膜は低圧化学的気相蒸着法(low pressure chemical vapor deposition; ＬＰ−ＣＶＤ)を用いて形成することができる。低圧化学的気相蒸着法（ＬＰ−ＣＶＤ）は、６００℃〜９００℃の温度を加えて形成することができ、ＳｉＣｌ２Ｈ２及びＮ２Ｏ２ガスを反応させてＤＣＳ−ＨＴＯ(DiChloroSilane High Temperature Oxide)膜の第１の絶縁膜106を形成することができる。この時、第１の絶縁膜106は、２０Å〜５０Åの厚さで形成することができる。
図１（ｃ）を参照すれば、第１の絶縁膜106の上部に誘電体膜用第２の絶縁膜108を形成する。第２の絶縁膜108は、高誘電体物質からなる高誘電体(high-k)膜で２０Å〜１５０Åの厚さで形成することが望ましく、原子層蒸着法(atomic layer deposition; ＡＬＤ)で形成することが好ましい。高誘電体膜は、誘電定数が３．９よりも大きい膜(layer)であり、漏洩電流の発生を抑制するのに容易である。
原子層蒸着法（ＡＬＤ）は、ソースガスと反応ガスを注入して行うが、ソースガスと反応ガスは同時に注入せずにそれぞれ注入し、その間にパージ(purge)工程を行い、吸着及び脱着反応を用いる。このようなソースガス注入工程、パージ工程及び反応ガス注入工程を単位サイクル(cycle)とし、単位サイクルを繰り返して第２の絶縁膜108を形成することができる。
具体的には、原子層蒸着法（ＡＬＤ）工程は、２００℃〜６００℃の温度を加えて行うことができるが、反応ガス注入工程時の反応ガスは、Ｏ２、Ｈ２Ｏ及びＯ３のいずれか一つまたは混合して用いることができ、ソースガスの種類により多様な種類の高誘電体膜を形成することができる。例えば、高誘電体膜は、Ａｌ２Ｏ３、ＨｆＯ２、ＺｒＯ２、ＳｉＯＮ、Ｌａ２Ｏ３、Ｙ２Ｏ３、ＴｉＯ２、ＣｅＯ２、Ｎ２Ｏ３、Ｔａ２Ｏ５、ＢａＴｉＯ３、ＳｒＴｉＯ３、ＢＳＴまたはＰＺＴのいずれか一つで形成することができ、これらの二つ以上を積層して形成することもできる。
高誘電体膜は、一般的な窒化膜より膜質が優れるだけでなく、ステップカバレッジ(step coverage)特性も優れるため、高誘電体膜で第２の絶縁膜108を形成することにより、破壊電圧(breakdown voltage)を上昇させることができる。また、高誘電体膜により、フラットバンド電圧(flatband voltage)の変動を抑制することができ、充電容量の増加とセル(cell)間の干渉(interference)現象を減少させることができる。
そして、高誘電体膜を形成する工程時、上述したように、２００℃〜６００℃の低い温度で形成することができ、トンネル絶縁膜102の熱による損傷を防止することができるため、半導体素子の信頼度を改善することができる。
次いで、第２の絶縁膜108を形成した後、第２の絶縁膜108の膜質を均一にするための先処理(post treatment)工程を行う。一般には、誘電体膜形成工程時に窒化膜を形成した後に先処理工程で熱処理工程を行って膜質を均一にするが、本発明では、熱処理工程の代わりにプラズマ処理工程を行う。本発明において、プラズマ処理工程時にも熱を加えるものの、一般的な熱処理工程よりも低い温度(例えば、３００℃〜６００℃の温度)で行うため、第２の絶縁膜108の結晶化を抑制することができる。
プラズマ処理工程は、ＡｒガスとＯ２ガスを混合したガスを用い、Ｈ２ガスを混合することもできる。プラズマ処理工程は、ラジカル(radical)を用いたプラズマ酸化工程(Plasma Oxidation)で行うことが好ましい。ラジカルを用いたプラズマ酸化工程は、０．０１Torr〜１０Torrの圧力下で１ｋＷ〜５ｋＷのパワー(power)を加えて行うことができる。
このように、３００℃〜６００℃の低い温度でプラズマ処理工程を行う場合、高誘電体膜は非晶質薄膜の特性を維持することができる。また、後続工程で行う熱処理工程時、７００℃〜１０００℃の高温で熱処理工程が行なわれても、低い温度で行ったプラズマ処理工程により高誘電体膜の結晶化が不十分に進行されることにより、結晶粒境界通路(grain boundary path)を減少させて漏洩電流(leakage current)の発生を抑制させることができる。
図２（ａ）を参照すれば、第２の絶縁膜108の上部に誘電体膜用第３の絶縁膜110を形成する。具体的に説明すれば、第３の絶縁膜110は、低圧化学的気相蒸着法（ＬＰ−ＣＶＤ）を用いて酸化膜で形成することができる。低圧化学的気相蒸着法（ＬＰ−ＣＶＤ）は、６００℃〜９００℃の温度を加えて形成することができ、ＳｉＣｌ２Ｈ２及びＮ２Ｏ２ガスを反応させてＤＣＳ−ＨＴＯ(DiChloroSilane High Temperature Oxide)膜の第３の絶縁膜110を形成することができる。この時、第３の絶縁膜110は、２０Å〜５０Åの厚さで形成することができる。
これにより、上述した第１の絶縁膜106、第２の絶縁膜108及び第３の絶縁膜110は誘電体膜111となる。
図２（ｂ）を参照すれば、誘電体膜111の上部にコントロールゲート用第２の導電膜112を形成する。即ち、第３の絶縁膜110上に第２の導電膜112を形成する。第２の導電膜112は、ポリシリコン膜で形成することができ、ポリシリコン膜及び金属膜を積層して形成することもできる。
上述した技術により、第２の絶縁膜108で高誘電体膜を形成し、高誘電体膜にプラズマ処理工程を行うことにより。高誘電体膜の結晶化を防止することができるため、漏洩電流(leakage current)特性及び電荷保持(charge retention)特性を向上させることができ、熱的欠陷(thermal budget)によるトンネル絶縁膜102の信頼性の低下を防止することができる。
上記で説明した本発明の技術的思想は、好ましい実施例により具体的に記述されたが、上記の実施例はその説明のためのものであり、その制限のためのものではないことに注意しなければならない。また、本発明は、本発明の技術分野の通常の専門家であれば、本発明の技術的思想の範囲内で多様な実施例が可能であることを理解することができるものである。
本発明の活用例として、半導体メモリ素子の誘電体膜形成方法に適用出来、特に、半導体メモリ素子の電気的特性を向上させることができる半導体メモリ素子の誘電体膜形成方法に適用出来る。
本発明による半導体メモリ素子の誘電体膜形成方法を説明するための断面図である。 本発明による半導体メモリ素子の誘電体膜形成方法を説明するための断面図である。
符号の説明
100…半導体基板
102…トンネル絶縁膜
104…第１の導電膜
106…第１の絶縁膜
108…第２の絶縁膜
110…第３の絶縁膜
111…誘電体膜
112…第２の導電膜

Claims (20)

  1. 半導体基板上に高誘電体膜を形成する段階と、
    前記高誘電体膜が結晶化されない温度で前記高誘電体膜の膜質を均一にするプラズマ処理工程を行う段階と、
    を含むことを特徴とする半導体メモリ素子の誘電体膜形成方法。
  2. トンネル絶縁膜、第１の導電膜及び素子分離膜が形成された半導体基板が提供される段階と、
    前記第１の導電膜及び素子分離膜上に第１の絶縁膜を形成する段階と、
    前記第１の絶縁膜上に第２の絶縁膜を形成する段階と、
    前記第２の絶縁膜の膜質を均一にする先処理工程を行う段階と、
    前記第２の絶縁膜上に第３の絶縁膜を形成する段階と、
    を含むことを特徴とする半導体メモリ素子の誘電体膜形成方法。
  3. 前記第３の絶縁膜上に第２の導電膜を形成する段階をさらに含むことを特徴とする請求項２に記載の半導体メモリ素子の誘電体膜形成方法。
  4. 前記第２の絶縁膜を高誘電体膜(high-k)で形成することを特徴とする請求項２に記載の半導体メモリ素子の誘電体膜形成方法。
  5. 前記高誘電体膜は、２０Å〜１５０Åの厚さで形成することを特徴とする請求項１または請求項４に記載の半導体メモリ素子の誘電体膜形成方法。
  6. 前記高誘電体膜は、原子層蒸着法（ＡＬＤ）で形成することを特徴とする請求項１または請求項４に記載の半導体メモリ素子の誘電体膜形成方法。
  7. 前記原子層蒸着法（ＡＬＤ）は、２００℃〜６００℃の温度を加えて行うことを特徴とする請求項６に記載の半導体メモリ素子の誘電体膜形成方法。
  8. 前記原子層蒸着法（ＡＬＤ）は、ソースガス注入工程、パージ工程及び反応ガス注入工程を単位サイクルとし、前記単位サイクルを繰り返して形成することを特徴とする請求項６に記載の半導体メモリ素子の誘電体膜形成方法。
  9. 前記反応ガス注入工程時、反応ガスは、Ｏ２、Ｈ２Ｏ及びＯ３のいずれか一つまたはこれらを混合して注入することを特徴とする請求項８に記載の半導体メモリ素子の誘電体膜形成方法。
  10. 前記高誘電体膜は、ソースガスの種類により、Ａｌ２Ｏ３、ＨｆＯ２、ＺｒＯ２、ＳｉＯＮ、Ｌａ２Ｏ３、Ｙ２Ｏ３、ＴｉＯ２、ＣｅＯ２、Ｎ２Ｏ３、Ｔａ２Ｏ５、ＢａＴｉＯ３、ＳｒＴｉＯ３、ＢＳＴまたはＰＺＴのいずれか一つで形成するか、またはこれらの二つ以上を積層して形成することを特徴とする請求項１または請求項４に記載の半導体メモリ素子の誘電体膜形成方法。
  11. 前記先処理工程は、プラズマ処理工程(Plasma treatment)で行うことを特徴とする請求項２に記載の半導体メモリ素子の誘電体膜形成方法。
  12. 前記プラズマ処理工程は、ラジカル(radical)を用いたプラズマ酸化工程(Plasma Oxidation)で行うことを特徴とする請求項１１に記載の半導体メモリ素子の誘電体膜形成方法。
  13. 前記プラズマ酸化工程は、ＡｒガスとＯ２ガスを混合したガスを用いることを特徴とする請求項１２に記載の半導体メモリ素子の誘電体膜形成方法。
  14. 前記混合したガスにＨ２ガスをさらに混合して行うことを特徴とする請求項１３に記載の半導体メモリ素子の誘電体膜形成方法。
  15. 前記プラズマ酸化工程は、０．０１Torr〜１０Torrの圧力で１ｋＷ〜５ｋＷのパワー(power)を加え、３００℃〜６００℃の温度を加えて行うことを特徴とする請求項１２に記載の半導体メモリ素子の誘電体膜形成方法。
  16. 前記第１及び第２の絶縁膜は、２０Å〜５０Åの厚さの酸化膜で形成することを特徴とする請求項２に記載の半導体メモリ素子の誘電体膜形成方法。
  17. 前記酸化膜は、６００℃〜９００℃の温度を加えて低圧化学的気相蒸着法（ＬＰ−ＣＶＤ）で形成することを特徴とする請求項１６に記載の半導体メモリ素子の誘電体膜形成方法。
  18. 前記酸化膜は、ＳｉＣｌ２Ｈ２及びＮ２Ｏ２ガスを反応させてＤＣＳ−ＨＴＯ(DiChloroSilane High Temperature Oxide)膜で形成することを特徴とする請求項１６に記載の半導体メモリ素子の誘電体膜形成方法。
  19. 第１の絶縁膜が形成された半導体基板が提供される段階と、
    前記第１の絶縁膜上に高誘電体物質で第２の絶縁膜を形成する段階と、
    前記第２の絶縁膜上に第３の絶縁膜を形成する段階と、
    を含むことを特徴とする半導体メモリ素子の誘電体膜形成方法。
  20. 前記第３の絶縁膜を形成する前に、前記第２の絶縁膜の表面を均一にするプラズマ処理工程を行う段階をさらに含むことを特徴とする請求項１９に記載の半導体メモリ素子の誘電体膜形成方法。
JP2008175137A 2007-08-20 2008-07-04 半導体メモリ素子の誘電体膜形成方法 Pending JP2009049379A (ja)

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