JP2008536305A - フォトレジストマスクを用いたエッチング - Google Patents
フォトレジストマスクを用いたエッチング Download PDFInfo
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- JP2008536305A JP2008536305A JP2008504073A JP2008504073A JP2008536305A JP 2008536305 A JP2008536305 A JP 2008536305A JP 2008504073 A JP2008504073 A JP 2008504073A JP 2008504073 A JP2008504073 A JP 2008504073A JP 2008536305 A JP2008536305 A JP 2008536305A
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- 229920002120 photoresistant polymer Polymers 0.000 title claims abstract description 60
- 238000005530 etching Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000003085 diluting agent Substances 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims 1
- 239000003701 inert diluent Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 description 33
- 239000000463 material Substances 0.000 description 25
- 239000010410 layer Substances 0.000 description 24
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 238000003860 storage Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】基板の上の誘電体層をエッチングするための方法が提供されている。フォトレジストマスクが、誘電体層の上に形成される。基板は、プラズマ処理チャンバ内に配置される。NF3を含むエッチャントガスが、プラズマチャンバに供給される。NF3ガスから、プラズマが生成される。誘電体層は、NF3ガスから生成されたプラズマによってフォトレジストマスクを通してエッチングされる。
【選択図】図1
Description
本発明を容易に理解できるように、工程104で準備された誘電体層220を備える基板210の断面図を図2Aに示した。本発明の好ましい実施形態の一例では、基板210は、シリコンウエハであり、誘電体層220は、有機ケイ酸塩ガラス、すなわち、酸化ケイ素系の低誘電率材料である。好ましい実施形態では、誘電体層220の上に、ARC層が配置される。ARC層は、下部反射防止膜(BARC)224であることが好ましい。フォトレジストマスク228が、誘電体層220の上に形成される(工程108)。フォトレジストマスク228は、193nm用のフォトレジストであることが好ましい。マスクは、400nm以下の厚さを有することが好ましい。ビアのパターニングでは、約400nmのマスク厚を用いる。トレンチのパターニングでは、約200nmのマスク厚を用いる。マスクは、200nm以下の厚さを有することが、さらに好ましい。基板210は、プラズマ処理チャンバ内に配置される(工程112)。
Claims (14)
- 基板の上の誘電体層をエッチングするための方法であって、
前記誘電体層の上にフォトレジストマスクを形成する工程と、
プラズマ処理チャンバ内に前記基板を配置する工程と、
NF3を含むエッチャントガスを前記プラズマチャンバ内に供給する工程と、
前記NF3ガスからプラズマを生成する工程と、
前記NF3ガスから生成された前記プラズマによって前記フォトレジストマスクを通して前記誘電体層をエッチングする工程と、を備える、方法。 - 請求項1に記載の方法であって、前記エッチャントガスは、本質的に、フッ化炭素およびフッ化炭化水素を含まない、方法。
- 請求項1ないし2のいずれかに記載の方法であって、前記誘電体層は、低誘電体層である、方法。
- 請求項1ないし3のいずれかに記載の方法であって、前記誘電体層は、酸化ケイ素系の誘電体層である、方法。
- 請求項4に記載の方法であって、前記酸化ケイ素系の誘電体層は、有機ケイ酸塩ガラスである、方法。
- 請求項1ないし5のいずれかに記載の方法であって、前記フォトレジストマスクを形成する工程は、400nm以下の厚さの前記フォトレジストマスクを形成する、方法。
- 請求項1ないし5のいずれかに記載の方法であって、前記フォトレジストマスクを形成する工程は、200nm以下の厚さの前記フォトレジストマスクを形成する、方法。
- 請求項1ないし7のいずれかに記載の方法であって、前記エッチャントガスは、本質的にNF3と不活性希釈剤からなる、方法。
- 請求項1ないし8のいずれかに記載の方法によって製造された半導体素子。
- 基板の上の誘電体層をエッチングするための方法であって、
前記誘電体層の上に、400nm以下の厚さのフォトレジストマスクを形成する工程と、
プラズマ処理チャンバ内に前記基板を配置する工程と、
本質的にNF3と希釈剤からなるエッチャントガスを前記プラズマチャンバ内に供給する工程と、
前記NF3ガスからプラズマを生成する工程と、
前記NF3ガスから生成された前記プラズマによって前記フォトレジストマスクを通して前記誘電体層をエッチングする工程と、を備える、方法。 - 請求項10に記載の方法であって、前記誘電体層は、低誘電体層である、方法。
- 請求項10ないし11のいずれかに記載の方法であって、前記誘電体層は、酸化ケイ素系の誘電体層である、方法。
- 請求項10に記載の方法であって、前記誘電体層は、有機ケイ酸塩ガラスである、方法。
- 基板によって支持されると共にフォトレジストマスクによって覆われたエッチング層に形状を形成するための装置であって、
プラズマ処理チャンバであって、
プラズマ処理チャンバ容器を形成するチャンバ壁と、
前記プラズマ処理チャンバ容器内で基板を支持するための基板支持と、
前記プラズマ処理チャンバ容器内の圧力を調整するための圧力調整手段と、
前記プラズマ処理チャンバ容器に電力を供給してプラズマを維持するための少なくとも1つの電極と、
前記プラズマ処理チャンバ容器にガスを供給するためのガス流入口と、
前記プラズマ処理チャンバ容器からガスを排出するためのガス流出口と、を備える、プラズマ処理チャンバと、
前記ガス流入口と流体接続されたNF3源を備えるガス源と、
前記ガス源と、前記少なくとも1つの電極とに、制御可能に接続された制御部であって、
少なくとも1つのプロセッサと、
コンピュータ読み取り可能な媒体と、を備える、制御部と、
を備え、
前記コンピュータ読み取り可能な媒体は、
前記NF3源からNF3ガスを前記プラズマ処理チャンバに供給するためのコンピュータ読み取り可能なコードと、
前記NF3ガスからプラズマを生成するためのコンピュータ読み取り可能なコードと、
前記NF3ガスからの前記プラズマによって前記エッチング層のエッチングを引き起こすようなプラズマ条件を与えるためのコンピュータ読み取り可能なコードと、を備える、装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/094,559 US7442649B2 (en) | 2005-03-29 | 2005-03-29 | Etch with photoresist mask |
PCT/US2006/008306 WO2006104655A2 (en) | 2005-03-29 | 2006-03-07 | Etch with photoresist mask |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008536305A true JP2008536305A (ja) | 2008-09-04 |
Family
ID=36917335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008504073A Pending JP2008536305A (ja) | 2005-03-29 | 2006-03-07 | フォトレジストマスクを用いたエッチング |
Country Status (6)
Country | Link |
---|---|
US (1) | US7442649B2 (ja) |
JP (1) | JP2008536305A (ja) |
KR (1) | KR101252878B1 (ja) |
CN (1) | CN101151719A (ja) |
TW (1) | TWI393997B (ja) |
WO (1) | WO2006104655A2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8887026B2 (en) * | 2009-04-14 | 2014-11-11 | Ben Gurion University Of The Negev | Efficient detection of errors in associative memory |
US8871650B2 (en) * | 2011-10-28 | 2014-10-28 | Applied Materials, Inc. | Post etch treatment (PET) of a low-K dielectric film |
US20140127901A1 (en) * | 2012-11-08 | 2014-05-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-k damage free integration scheme for copper interconnects |
KR20140000076A (ko) * | 2012-06-22 | 2014-01-02 | 삼성전기주식회사 | 터치패널 |
US10197908B2 (en) * | 2016-06-21 | 2019-02-05 | Lam Research Corporation | Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework |
US10572697B2 (en) | 2018-04-06 | 2020-02-25 | Lam Research Corporation | Method of etch model calibration using optical scatterometry |
KR20200131342A (ko) | 2018-04-10 | 2020-11-23 | 램 리써치 코포레이션 | 레지스트 및 에칭 모델링 |
WO2019200015A1 (en) | 2018-04-10 | 2019-10-17 | Lam Research Corporation | Optical metrology in machine learning to characterize features |
US10977405B2 (en) | 2019-01-29 | 2021-04-13 | Lam Research Corporation | Fill process optimization using feature scale modeling |
US11915933B2 (en) * | 2020-09-18 | 2024-02-27 | Changxin Memory Technologies, Inc. | Manufacturing method of semiconductor structure |
Citations (5)
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JPH0360121A (ja) * | 1989-07-28 | 1991-03-15 | Sony Corp | ドライエッチング方法 |
JP2001237228A (ja) * | 2000-02-24 | 2001-08-31 | Canon Sales Co Inc | 基板処理方法および基板処理装置ならびにデバイス製造方法 |
WO2003107410A2 (en) * | 2002-06-14 | 2003-12-24 | Lam Research Corporation | Process for etching dielectric films with improved resist and/or etch profile characteristics |
JP2005072518A (ja) * | 2003-08-28 | 2005-03-17 | Hitachi Ltd | 半導体装置の製造方法およびその装置 |
JP2005079191A (ja) * | 2003-08-28 | 2005-03-24 | Ulvac Japan Ltd | 層間絶縁膜のドライエッチング方法 |
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US4892753A (en) * | 1986-12-19 | 1990-01-09 | Applied Materials, Inc. | Process for PECVD of silicon oxide using TEOS decomposition |
US4793897A (en) * | 1987-03-20 | 1988-12-27 | Applied Materials, Inc. | Selective thin film etch process |
GB2219434A (en) * | 1988-06-06 | 1989-12-06 | Philips Nv | A method of forming a contact in a semiconductor device |
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US7001833B2 (en) * | 2002-09-27 | 2006-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming openings in low-k dielectric layers |
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US7256134B2 (en) * | 2003-08-01 | 2007-08-14 | Applied Materials, Inc. | Selective etching of carbon-doped low-k dielectrics |
-
2005
- 2005-03-29 US US11/094,559 patent/US7442649B2/en not_active Expired - Fee Related
-
2006
- 2006-03-07 JP JP2008504073A patent/JP2008536305A/ja active Pending
- 2006-03-07 KR KR1020077025010A patent/KR101252878B1/ko not_active IP Right Cessation
- 2006-03-07 CN CNA2006800102507A patent/CN101151719A/zh active Pending
- 2006-03-07 WO PCT/US2006/008306 patent/WO2006104655A2/en active Application Filing
- 2006-03-13 TW TW095108472A patent/TWI393997B/zh not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0360121A (ja) * | 1989-07-28 | 1991-03-15 | Sony Corp | ドライエッチング方法 |
JP2001237228A (ja) * | 2000-02-24 | 2001-08-31 | Canon Sales Co Inc | 基板処理方法および基板処理装置ならびにデバイス製造方法 |
WO2003107410A2 (en) * | 2002-06-14 | 2003-12-24 | Lam Research Corporation | Process for etching dielectric films with improved resist and/or etch profile characteristics |
JP2005072518A (ja) * | 2003-08-28 | 2005-03-17 | Hitachi Ltd | 半導体装置の製造方法およびその装置 |
JP2005079191A (ja) * | 2003-08-28 | 2005-03-24 | Ulvac Japan Ltd | 層間絶縁膜のドライエッチング方法 |
Also Published As
Publication number | Publication date |
---|---|
TW200643611A (en) | 2006-12-16 |
WO2006104655A3 (en) | 2007-02-01 |
KR20080013874A (ko) | 2008-02-13 |
TWI393997B (zh) | 2013-04-21 |
CN101151719A (zh) | 2008-03-26 |
US20060223327A1 (en) | 2006-10-05 |
KR101252878B1 (ko) | 2013-04-09 |
US7442649B2 (en) | 2008-10-28 |
WO2006104655A2 (en) | 2006-10-05 |
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